General Description
The MAX5949A/MAX5949B are hot-swap controllers that
allow a circuit card to be safely hot plugged into a live
backplane. The MAX5949A/MAX5949B operate from
-20V to -80V and are well-suited for -48V power systems.
These devices are pin and function compatible with the
LT4250 and pin compatible with the LT1640.
The MAX5949A/MAX5949B provide a controlled turn-on
to circuit cards preventing glitches on the power-supply
rail and damage to board connectors and components.
The MAX5949A/MAX5949B provide undervoltage, over-
voltage, and overcurrent protection. These devices
ensure the input voltage is stable and within tolerance
before applying power to the load.
Both the MAX5949A and MAX5949B protect a system
against overcurrent and short-circuit conditions by turn-
ing off the external MOSFET in the event of a fault con-
dition. The MAX5949A/MAX5949B also provide
protection against input voltage steps. During an input
voltage step, the MAX5949A/MAX5949B limit the cur-
rent drawn by the load to a safe level without turning off
power to the load.
Both devices feature an open-drain power-good status
output (PWRGD for the MAX5949A or PWRGD for the
MAX5949B) that can be used to enable downstream
converters.
The MAX5949A/MAX5949B are available in an 8-pin SO
package. Both devices are specified for the extended
-40°C to +85°C temperature range.
Applications
Telecom Line Cards
Network Switches/Routers
Central-Office Line Cards
Server Line Cards
Base-Station Line Cards
Central-Office Switching
-48V Distributed Power Systems
Negative Power-Supply Controls
Features
oAllow Safe Board Insertion and Removal
from a Live -48V Backplane
oPin and Function Compatible with LT4250L
(MAX5949A)
oPin Compatible with LT1640L (MAX5949A)
oPin and Function Compatible with LT4250H
(MAX5949B)
oPin Compatible with LT1640H (MAX5949B)
oCircuit-Breaker Immunity to Input Voltage Steps
and Current Spikes
oWithstand -100V Input Transients with No
External Components
oProgrammable Inrush and Short-Circuit Current
Limits
oOperate from -20V to -80V
oProgrammable Overvoltage Protection
oProgrammable Undervoltage Lockout
oPower Up into a Shorted Load
oPower-Good Control Output
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
________________________________________________________________
Maxim Integrated Products
1
GATE
SENSEVEE
1
+
2
8
7
VDD
DRAINOV
UV
PWRGD
(PWRGD)
SO
TOP VIEW
3
4
6
5
MAX5949A
MAX5949B
( ) FOR MAX5949B.
Pin Configuration
Ordering Information
19-3494; Rev 1; 8/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX5949AESA+ -40°C to +85°C 8 SO
MAX5949BESA+ -40°C to +85°C 8 SO
Typical Operating Circuit and Selector Guide appear at end
of data sheet.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VEE = 0V, VDD = 48V, TA= -40°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.) (Notes 2, 5)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages are referenced to VEE, unless otherwise noted.)
Supply Voltage (VDD - VEE ) .................................-0.3V to +100V
PWRGD, PWRGD .................................................-0.3V to +100V
DRAIN (Note 1)........................................................-2V to +100V
PWRGD to DRAIN .............................................… -0.3V to +95V
PWRGD to VDD........................................................-95V to +85V
SENSE (Internally Clamped) .................................-0.3V to +1.0V
GATE (Internally Clamped) ....................................-0.3V to +18V
UV and OV..............................................................-0.3V to +60V
Current Through SENSE ...................................................±40mA
Current into GATE...........................................................±300mA
Current into DRAIN .........................................-100mA to +20mA
Current into Any Other Pin................................................±20mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SO (derate 5.9mW/°C above +70°C)..................471mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Operating Input Voltage Range VDD 20 80 V
Supply Current IDD (Note 3) 0.7 2 mA
GATE DRIVE AND CLAMPING CIRCUITS
GATE Pin Pullup Current IPU Gate drive on, VGATE = VEE -30 -45 -60 µA
GATE Pin Pulldown Current IPD Gate drive off, VGATE = 2V, TA = +25°C 24 50 70 mA
External Gate Drive ∆VGATE VGATE - VEE, 20V ≤ VDD ≤ 80V 10 13.5 18 V
GATE to VEE Clamp Voltage VGSCLMP VGATE - VEE, IGS = 30mA 15 16.4 18 V
CIRCUIT BREAKER
Current-Limit Trip Voltage VCL VCL = VSENSE - VEE 40 50 60 mV
SENSE Input Bias Current ISENSE VSENSE = 50mV 0 -0.2 -2 µA
UNDERVOLTAGE LOCKOUT
Internal Undervoltage-Lockout
Voltage High VUVLOH VDD increasing 13.8 15.4 17.0 V
Internal Undervoltage-Lockout
Voltage Low VUVLOL VDD decreasing 11.8 13.4 15.0 V
UV PIN
UV High Threshold VUVH UV voltage increasing 1.240 1.255 1.270 V
UV Low Threshold VUVL UV voltage decreasing 1.105 1.125 1.145 V
UV Hysteresis VUVHY 130 mV
UV Input Bias Current IINUV VUV = VEE 0-0.5µA
OV PIN
OV High Threshold VOVH OV voltage increasing 1.235 1.255 1.275 V
OV Low Threshold VOVL OV voltage decreasing 1.210 1.235 1.255 V
OV Hysteresis VOVHY 20 mV
OV Input Bias Current IINOV VOV = VEE 0-0.5µA
Note 1: Test condition per Figure 1. DRAIN current must be limited to the specified 100mA maximum.
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VEE = 0V, VDD = 48V, TA= -40°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.) (Notes 2, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWRGD OUTPUT SIGNAL REFERENCED TO DRAIN
DRAIN Input Bias Current IDRAIN VDRAIN = 48V 10 80 250 µA
D RAIN Thr eshol d for P ow er - G ood VDL VDRAIN - VEE threshold for power-good
condition, DRAIN decreasing 1.1 1.4 2.0 V
GATE High Threshold VGH ∆VGATE - VGATE threshold for power-good
condition, ∆VGATE - VGATE decreasing 1.0 1.4 2.0 V
PWRGD, PWRGD Output
Leakage IOH
PWRGD (MAX5949A) = 80V, VDRAIN = 48V,
PWRGD (MAX5949B) = 80V, VDRAIN = 0V 10 µA
PWRGD Output Low Voltage VOL V PWRGD - VEE; VDRAIN - VEE < VDL,
ISINK = 5mA (MAX5949A) 0.11 0.4 V
PWRGD Output Low Voltage VOL VPWRGD - VDRAIN; VDRAIN = 5V,
ISINK = 1mA (MAX5949B) 0.11 0.4 V
AC PARAMETERS
OV High to GATE Low tPHLOV Figures 2a, 3 0.5 µs
UV Low to GATE Low tPHLUV Figures 2a, 4 0.4 µs
OV Low to GATE High tPLHOV Figures 2a, 3 4 µs
UV High to GATE High tPLHVL Figures 2a, 4 5.5 µs
SENSE High to GATE Low tPHLSENSE Figures 2a, 5a 1 3 µs
Current Limit to GATE Low tPHLCB Figures 2b, 5b 350 500 650 µs
MAX5949A, Figures 2a, 6a 1.8DRAIN Low to PWRGD Low
DRAIN Low to (PWRGD - DRAIN)
High
tPHLDL
MAX5949B, Figures 2a, 6a 3.4
µs
MAX5949A, Figures 2a, 6b 1.6
GATE High to PWRGD Low
GATE High to (PWRGD - DRAIN)
High
tPHLGH
MAX5949B, Figures 2a, 6b 2.5
µs
TURN-OFF
Latch-Off Period tOFF (Note 4) 51 64 78 ms
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE,
unless otherwise specified.
Note 3: Current into VDD with UV = 3V, OV = DRAIN = PWRGD = SENSE = VEE, GATE = open.
Note 4: Minimum duration of GATE pulldown following a circuit-breaker fault. The circuit breaker can be reset during this time by
toggling UV low, but the GATE pulldown does not release until tOFF has elapsed.
Note 5: Limits are 100% tested at TA= +25°C and +85°C. Limits at -40°C are guaranteed by design.
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD = 48V, VEE = 0V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5949 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
80604020
100
200
300
400
500
600
700
800
900
0
0100
TA = +85°CTA = +25°C
TA = -40°C
GATE VOLTAGE vs. SUPPLY VOLTAGE
MAX5949 toc02
SUPPLY VOLTAGE (V)
GATE VOLTAGE (V)
80604020
9
10
11
12
13
14
15
8
0100
TA = +85°C
TA = -45°CTA = +25°C
CURRENT-LIMIT TRIP VOLTAGE
vs. TEMPERATURE
MAX5949 toc03
TEMPERATURE (°C)
TRIP VOLTAGE (mV)
603510-15
47
48
49
50
51
52
53
46
-40 85
GATE PULLUP CURRENT
vs. TEMPERATURE
MAX5949 toc04
TEMPERATURE (°C)
GATE PULLUP CURRENT (µA)
603510-15
43.2
43.4
43.6
43.8
44.0
44.2
44.4
44.6
44.8
45.0
43.0
-40 85
VGATE = 0V
GATE PULLDOWN CURRENT
vs. TEMPERATURE
MAX5949 toc05
TEMPERATURE (°C)
GATE PULLDOWN CURRENT (mA)
603510-15
30
35
40
45
50
55
60
65
70
25
-40 85
VGATE = 2V
PWRGD OUTPUT LOW VOLTAGE
vs. TEMPERATURE (MAX5949A)
MAX5920 toc06
TEMPERATURE (°C)
PWRGD OUTPUT LOW VOLTAGE (mV)
603510-15
5
10
15
20
25
30
35
40
45
50
0
-40 85
IOUT = 1mA
PWRGD OUTPUT IMPEDANCE
vs. TEMPERATURE (MAX5949B)
MAX5949 toc07
TEMPERATURE (°C)
OUTPUT IMPEDANCE (GΩ)
7525 500-25
10
100
1000
10,000
1
-50 100
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
_______________________________________________________________________________________ 5
Test Circuits
2V
100mA MAX
MAX5949_
PWRGD/PWRGD
OV
UV
VEE
VDD
DRAIN
GATE
TEST VOLTAGE
SENSE
Figure 1. -2V DRAIN Voltage Test Circuit
VS
R
5kΩ
VOV
VUV
V+
5V
VSENSE
VDRAIN
48V
MAX5949A
MAX5949B
PWRGD/PWRGD
OV
UV
VEE
VDD
DRAIN
GATE
SENSE
Figure 2a. Test Circuit 1
VS
VUV
48V
MAX5949A
MAX5949B
PWRGD/PWRGD
OV
UV
VEE
VDD
DRAIN
GATE
SENSE
N
IRF530
VS20V
10kΩ
10Ω
0.1µF
10Ω
Figure 2b. Test Circuit 2
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
6 _______________________________________________________________________________________
Timing Diagrams
1.255V
OV
tPHLOV
0V
2V
1V
1.235V
1V
tPLHOV
GATE
Figure 3. OV to GATE Timing
tPHLUV
1.125V
1V 1V
1.255V
tPLHUV
UV
0V
2V
GATE
Figure 4. UV to GATE Timing
60mV
1V
100mV
GATE
SENSE
VEE
tPHLSENSE
Figure 5a. SENSE to GATE Timing
tPHLCB
50mV
UV
GATE
SENSE
1V1V
Figure 5b. Active Current-Limit Threshold
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
_______________________________________________________________________________________ 7
Timing Diagrams (continued)
DRAIN
PWRGD
VPWRGD - VDRAIN = 0V
PWRGD
DRAIN
VEE
VEE
VEE
tPHLDL
1V
1.4V
1.4V
tPHLDL
1V
Figure 6a. DRAIN to PWRGD/PWRGD Timing
∆VGATE - VGATE = 0V
GATE
PWRGD
VEE
VEE
∆VGATE - VGATE = 0V
GATE
PWRGD
VPWRGD - VDRAIN = 0V
1.4V
1.4V
1V
1V
tPHLGH
tPHLGH
Figure 6b. GATE to PWRGD/PWRGD Timing
LOGIC
GATE
DRIVER
500µs
DELAY
UVLO VCC AND
REFERENCE
GENERATOR
REF
VCC
REF
VDL
VEE
VGH
∆VGATE
50mV
VDD
UV
OV
VEE SENSE GATE DRAIN
PWRGD
PWRGD
MAX5949A
MAX5949B
OUTPUT DRIVE
Block Diagram
MAX5949A/MAX5949B
Detailed Description
The MAX5949A/MAX5949B are integrated hot-swap
controllers for -48V power systems. They allow circuit
boards to be safely hot plugged into a live backplane
without causing a glitch on the power-supply rail. When
circuit boards are inserted into a live backplane without
hot-swap control, the bypass capacitors at the input of
the board’s power module or switching power supply
can draw large inrush currents as they charge. The
inrush currents can cause glitches on the system
power-supply rail and damage components on the
board.
The MAX5949A/MAX5949B provide a controlled turn-on
to circuit cards, preventing glitches on the power-supply
rail and damage to board connectors and components.
Both the MAX5949A and MAX5949B provide undervolt-
age, overvoltage, and overcurrent protection. The
MAX5949A/MAX5949B ensure the input voltage is sta-
ble and within tolerance before applying power to the
load. The devices also provide protection against input
voltage steps. During an input voltage step, the
MAX5949A/MAX5949B limit the current drawn by the
load to a safe level without turning off power to the load.
-48V Hot-Swap Controllers
with External RSENSE
8 _______________________________________________________________________________________
Pin Description
PIN
MAX5949A MAX5949B NAME FUNCTION
1—PWRGD
Power-Good Signal Output. PWRGD is an active-low open-drain status output referenced
to VEE. PWRGD is latched low when VDRAIN - VEE ≤ VDL and VGATE > (∆VGATE - VGH),
indicating a power-good condition. PWRGD is open drain otherwise.
— 1 PWRGD
Power-Good Signal Output. PWRGD is an active-high open-drain status output referenced
to DRAIN. PWRGD latches in a high-impedance state when VDRAIN - VEE ≤ VDL and
VGATE > (∆VGATE - VGH), indicating a power-good condition. PWRGD is pulled low to
DRAIN otherwise.
22OV
Input Pin for Overvoltage Detection. OV is referenced to VEE. When OV is pulled above the
VOVH voltage, the GATE pin is immediately pulled low. The GATE pin remains low until the
OV pin voltage reduces to VOVL.
33UV
Input Pin for Undervoltage Detection. UV is referenced to VEE. When UV is pulled above the
VUVH voltage, the GATE is enabled. When UV is pulled below VUVL, GATE is pulled low.
UV is also used to reset the circuit breaker after a fault condition. To reset the circuit
breaker, pull UV below VUVL. The reset command can be issued immediately after a fault
condition; however, the device does not restart until a tOFF delay time has elapsed after
the fault.
44V
EE Device Negative Power-Supply Input. Connect to the negative power-supply rail.
5 5 SENSE
Current-Sense Voltage Input. Connect to an external sense resistor and the external
MOSFET source. The voltage drop across the external sense resistor is monitored to detect
overcurrent or short-circuit fault conditions. Connect SENSE to VEE to disable the current-
limiting feature.
6 6 GATE Gate-Drive Output. Connect to the gate of the external n-channel MOSFET.
7 7 DRAIN Output-Voltage Sense Input. Connect to the output-voltage node (drain of the external
n-channel MOSFET).
88V
DD Positive Power-Supply Rail Input. This is the power ground in the negative-supply voltage
system. Connect to the higher potential of the power-supply inputs.
Board Insertion
Figure 7a shows a typical hot-swap circuit for -48V sys-
tems. When the circuit board first makes contact with
the backplane, the DRAIN to GATE capacitance (Cgd)
of Q1 pulls up the GATE voltage to roughly IVEE x Cgd /
(Cgd + Cgs)I. The MAX5949_ features an internal
dynamic clamp between GATE and VEE to keep the
gate-to-source voltage of Q1 low during hot insertion,
preventing Q1 from passing an uncontrolled current to
the load. For most applications, the internal dynamic
clamp between GATE and VEE of the MAX5949A/
MAX5949B eliminates the need for an external gate-to-
source capacitor C1. Resistor R3 limits the current into
the clamp circuitry during card insertion.
Power-Supply Ramping
The MAX5949_ can reside either on the backplane or
the removable circuit board (Figure 7a). Power is deliv-
ered to the load by placing an external n-channel
MOSFET pass transistor in the power-supply path.
After the circuit board is inserted into the backplane
and the supply voltage at VEE is stable and within the
undervoltage and overvoltage tolerance, the MAX5949_
turn on Q1. The MAX5949_ gradually turn on the exter-
nal MOSFET by charging the gate of Q1 with a 45µA
current source.
Capacitor C2 provides a feedback signal to accurately
limit the inrush current. The value of C2can be
calculated:
where CLis the total load capacitance, C3 + C4, and
IPU is the MAX5949_ gate pullup current.
Figure 7b shows the inrush current waveform. The cur-
rent through C2 controls the GATE voltage. At the end
of the DRAIN ramp, the GATE voltage is charged to its
final value. The GATE-to-SENSE clamp limits the maxi-
mum VGS to about 18V under any condition.
Board Removal
If the card is removed from a live backplane, the output
capacitor on the card may not be immediately dis-
charged. While the output capacitor is discharging, the
MAX5949_ continues to operate as if the input supply
were still connected because the output capacitor tem-
porarily supplies operating current to the IC. If the cir-
cuit is connected as in Figure 7a, the voltage at the UV
pin falls below the VUVL, and the MAX5949_ turns off
the external MOSFET. If R4 in the circuit is connected
directly to the -48V return, the external MOSFET
remains on until the capacitor is discharged sufficiently
to drop the UV pin voltage to VUVL.
CIxC
I
PU L
INRUSH
2=
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
_______________________________________________________________________________________ 9
VEE SENSE GATE DRAIN
VDD
OV
UV
PWRGD
MAX5949B
-48V RTN
-48V
R4
549kΩ
1%
R5
6.49kΩ
1%
R6
10kΩ
1%
R1
0.02Ω
5%
R3
1kΩ
5%
R2
10Ω
5%
C1**
470nF
25V
Q1
IRF530
C2
15nF
100V
GATE IN
VICOR
VI-J3D-CY
VIN+
VIN-
C4
100µF
100V
C3
0.1µF
100V
C5
100µF
10V
*
10nF
-48V RTN
(SHORT PIN)
*DIODES INC. SMAT70A.
**OPTIONAL.
Figure 7a. Inrush Control Circuitry
MAX5949A/MAX5949B
In either case, when the MOSFET is turned off, the out-
put capacitor continues to discharge by the IC supply
current, IDD. The IDD flows into the IC at the VDD termi-
nal, out at the VEE terminal, and back to the capacitor
through the external MOSFET’s substrate diode. There
is also a parallel current path between the VEE and
DRAIN terminals through multiple internal ESD-protec-
tion diodes. Protection circuits built into the IC allow the
DRAIN terminal voltage to drop below that of the VEE
terminal so long as the allowed absolute-maximum
DRAIN terminal current (-100mA) is not exceeded. As
IDD is only 2mA maximum, this limiting current will not
even be approached.
Current Limit and Electronic
Circuit Breaker
The MAX5949_ provides current-limiting and circuit-
breaker features that protect against excessive load cur-
rent and short-circuit conditions. The load current is
monitored by sensing the voltage across an external
sense resistor connected between VEE and SENSE.
If the voltage between VEE and SENSE reaches the cur-
rent-limit trip voltage (VCL), the MAX5949_ pulls down
the GATE pin and regulates the current through the
external MOSFET so VSENSE - VEE < VCL. If the current
drawn by the load drops below VCL / RSENSE limit, the
GATE pin voltage rises again. However, if the load cur-
rent is at the regulation limit of VCL / RSENSE for a period
of tPHLCB, the electronic circuit breaker trips, causing the
MAX5949A/MAX5949B to turn off the external MOSFET.
After an overcurrent fault condition, the circuit breaker
is reset by pulling the UV pin low and then pulling UV
high or by cycling power to the MAX5949A/MAX5949B.
Unless power is cycled to the MAX5949A/MAX5949B,
the device waits until tOFF has elapsed before turning
on the gate of the external FET.
Overcurrent Fault Integrator
The MAX5949_ features an overcurrent fault integrator.
When an overcurrent condition exists, an internal digital
counter increments its count. When the counter reaches
500µs (the maximum current-limit duration) for the
MAX5949_, an overcurrent fault is generated. If the
overcurrent fault does not last 500µs, then the counter
begins decrementing at a rate 128 (maximum current-
limit duty cycle) times slower than the counter was
incrementing. Repeated overcurrent conditions will gen-
erate a fault if duty cycle of the overcurrent condition is
greater than 1/128.
Load-Current Regulation
The MAX5949_ accomplishes load-current regulation by
pulling current from the GATE pin whenever VSENSE - VEE
> VCL (see the
Typical Operating Characteristics
). This
decreases the gate-to-source voltage of the external
MOSFET, thereby reducing the load current. When
VSENSE - VEE < VCL, the MAX5949A/MAX5949B pull the
GATE pin high by a 45µA (IPU) current.
Driving into a Shorted Load
In the event of a permanent short-circuit condition, the
MAX5949_ limits the current drawn by the load to VCL /
RSENSE for a period of tPHLCB, after which the circuit
breaker trips. Once the circuit breaker trips, the GATE
of the external FET is pulled low by 50mA (IPD) turning
off power to the load.
Immunity to Input Voltage Steps
The MAX5949_ guards against input voltage steps on the
input supply. A rapid increase in the input supply voltage
(VDD - VEE increasing) causes a current step equal to I =
CL x∆VIN / ∆T. If the load current exceeds VCL / RSENSE
during an input voltage step, the MAX5949A/MAX5949B
current limit activates, pulling down the gate voltage and
limiting the load current to VCL / RSENSE. The DRAIN
voltage (VDRAIN) then slews at a slower rate than the
input voltage. As the drain voltage starts to slew down,
the drain-to-gate feedback capacitor C2 pushes back on
the gate, reducing the gate-to-source voltage (VGS) and
the current through the external MOSFET. Once the input
supply reaches its final value, the DRAIN slew rate (and
therefore the inrush current) is limited by the capacitor
C2 just as it is limited in the startup condition. To ensure
correct operation, RSENSE must be chosen to provide a
current limit larger than the sum of the load current and
the dynamic current into the load capacitance in the
slewing mode.
If the load current plus the capacitive charging current is
-48V Hot-Swap Controllers
with External RSENSE
10 ______________________________________________________________________________________
GATE - VEE
10V/div
VEE
50V/div
DRAIN
50V/div
INRUSH
CURRENT
1A/div
4ms/div
CONTACT
BOUNCE
Figure 7b. Input Inrush Current
below the current limit, the circuit breaker does not trip.
For C2 values less than 10nF, a positive voltage step on
the input supply can result in Q1 turning off momentarily,
which can shut down the output. By adding an additional
resistor and diode, Q1 remains on during the voltage
step. This is shown as D1 and R7 in Figure 10. The pur-
pose of D1 is to shunt current around R7 when the power
pins first make contact and allow C1 to hold the GATE
low. The value of R7 should be sized to generate an
R7 x C1 time constant of 33µs.
Undervoltage and Overvoltage
Protection
The UV and OV pins can be used to detect undervoltage
and overvoltage conditions. The UV and OV pins are
internally connected to analog comparators with 130mV
(UV) and 20mV (OV) of hysteresis. When the UV voltage
falls below its threshold or the OV voltage rises above its
threshold, the GATE pin is immediately pulled low. The
GATE pin is held low until UV goes high and OV is low,
indicating that the input supply voltage is within specifica-
tion. The MAX5949_ includes an internal lockout (UVLO)
that keeps the external MOSFET off until the input supply
voltage exceeds 15.4V, regardless of the UV input.
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
______________________________________________________________________________________ 11
GATE - VEE
10V/div
ID (Q1)
5A/div
DRAIN
50V/div
1ms/div
Figure 8. Short-Circuit Protection Waveform
DRAIN
20V/div
ID (Q1)
5A/div
VEE
20V/div
400µs/div
Figure 9. Voltage Step on Input Supply
VEE SENSE GATE DRAIN
VDD
OV
UV
PWRGD
MAX5949A
-48V RTN
-48V
R4
549kΩ
1%
R5
6.49kΩ
1%
R6
10kΩ
1%
R1
0.02Ω
5%
R3
1kΩ
5%
R2
10Ω
5%
C1
150nF
25V
Q1
IRF530
C2
3.3nF
100V
*
-48V RTN
(SHORT PIN)
R7
220Ω
5%
D1
BAT85
C4
22µF
100V
C3
0.1µF
100V
*DIODES INC. SMAT70A.
Figure 10. Circuit for Input Steps with Small C1
MAX5949A/MAX5949B
The UV pin is also used to reset the circuit breaker after
a fault condition has occurred. The UV pin can be pulled
below VUVL to reset the circuit breaker.
Figure 12 shows how to program the undervoltage and
overvoltage trip thresholds using three resistors. With R4
= 549kΩ, R5 = 6.49kΩ, and R6 = 10kΩ, the undervoltage
threshold is set to 38.5V (with a 43V release from under-
voltage), and the overvoltage is set to 71V. The resistor-
divider also increases the hysteresis of the overvoltage
and overvoltage lockout, to 4.5V and 1.1V at the input
supply, respectively.
PWRGD
/PWRGD Output
The PWRGD (PWRGD) output can be used directly to
enable a power module after hot insertion. The
MAX5949A (PWRGD) can be used to enable modules
with an active-low enable input (Figure 14), while the
MAX5949B (PWRGD) is used to enable modules with
an active-high enable input (Figure 13).
The PWRGD signal is referenced to the DRAIN termi-
nal, which is the negative supply of the power module.
The PWRGD signal is referenced to VEE.
-48V Hot-Swap Controllers
with External RSENSE
12 ______________________________________________________________________________________
GATE
2V/div
NODE2
50V/div
1s/div
VEE SENSE GATE DRAIN
VDD
OV
UV
PWRGD
MAX5949A
-48V RTN
-48V RTN
(SHORT PIN)
*
-48V
*DIODES INC. SMAT70A.
R4
549kΩ
1%
R8
510kΩ
5%
R5
10kΩ
1%
R6
549kΩ
1%
R7
1MΩ
5%
R9
6.49kΩ
1%
R1
0.02Ω
5%
R3
1kΩ
5%
R2
10Ω
5%
C1
470nF
25V
C4
1µF
100V
N
Q1
IRF530
D1
1N4148
Q2
2N2222
Q3
ZVN3310
C2
15nF
100V
C3
100µF
100V
NODE2
Figure 11. Automatic Restart After Current Fault
VEE
VDD
OV
UV
MAX5949A
MAX5949B
-48V RTN
-48V
VUV = 1.255 R4 + R5 + R6
R5 + R6
R4
R5
R6
-48V RTN
(SHORT PIN)
3
2
4
8
VOV = 1.255 R4 + R5 + R6
R6
Figure 12. Undervoltage and Overvoltage Sensing
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
______________________________________________________________________________________ 13
PWRGD
GATE
I1
VEE
VGH
VDL
∆VGATE
-48V
R1
R2
C1
Q1
R3 C2
MAX5949B
VIN+
VIN-
C3
NQ2
Q3
N
VOUT+
VOUT-
ON/OFF
ACTIVE-HIGH
ENABLE MODULE
DRAIN
GATESENSEVEE
VDD
R4
R5
R6
*
*DIODES INC. SMAT70A.
-48V RTN
-48V RTN
(SHORT PIN)
UV
OV
Figure 13. Active-High Enable Module
PWRGD
VEE
VGH
GATE
VDL
∆VGATE
-48V
R1
R2
C1
Q1
R3 C2
MAX5949A
VIN+
VIN-
C3
VOUT+
VOUT-
ON/OFF
ACTIVE-LOW
ENABLE MODULE
DRAIN
GATESENSEVEE
VDD
R4
R5
R6
*
*DIODES INC. SMAT70A.
-48V RTN
-48V RTN
(SHORT PIN)
UV
OV
NQ2
Figure 14. Active-Low Enable Module
MAX5949A/MAX5949B
When the DRAIN voltage of the MAX5949A is high with
respect to VEE or the GATE voltage is low, the internal
pulldown MOSFET Q2 is off and the PWRGD pin is in a
high-impedance state (Figure 14). The PWRGD pin is
pulled high by the module’s internal pullup current
source, turning the module off. When the DRAIN volt-
age drops below VDL and the GATE voltage is greater
than ∆VGATE - VGH, Q2 turns on and the PWRGD pin
pulls low, enabling the module.
The PWRGD signal can also be used to turn on an LED
or optoisolator to indicate that the power is good
(Figure 15) (see the
Component Selection Procedure
section).
When the DRAIN voltage of the MAX5949B is high with
respect to VEE (Figure 13) or the GATE voltage is low, the
internal MOSFET Q3 is turned off so that I1 and the inter-
nal MOSFET Q2 clamp the PWRGD pin to the DRAIN pin.
MOSFET Q2 sinks the module’s pullup current, and the
module turns off.
When the DRAIN voltage drops below VDL and the
GATE voltage is greater than ∆VGATE - VGH, MOSFET
Q3 turns on, shorting I1 to VEE and turning Q2 off. The
pullup current in the module pulls the PWRGD pin high,
enabling the module.
GATE Pin Voltage Regulation
The GATE pin goes high when the following startup con-
ditions are met: the UV pin is high, the OV pin is low, the
supply voltage is above VUVLOH, and (VSENSE - VEE) is
less than 50mV. The gate is pulled up with a 45µA current
source and is regulated at 13.5V above VEE. The
MAX5949A/MAX5949B include an internal clamp that
ensures the GATE voltage of the external MOSFET never
exceeds 18V. During a fast-rising VDD, the clamp also
keeps the GATE and SENSE potentials as close as possi-
ble to prevent the FET from accidentally turning on. When
a fault condition is detected, the GATE pin is pulled low
with a 50mA current.
Applications Information
Sense Resistor
The circuit-breaker current-limit threshold is set to 50mV
(typically). Select a sense resistor that causes a drop
equal to or above the current-limit threshold at a current
level above the maximum normal operating current.
Typically, set the overload current to 1.5 to 2.0 times the
nominal load current plus the load-capacitance charging
current during startup. Choose the sense-resistor power
rating to be greater than (VCL)2/ RSENSE.
-48V Hot-Swap Controllers
with External RSENSE
14 ______________________________________________________________________________________
VEE SENSE GATE DRAIN
VDD
OV
UV
PWRGD
MAX5949A
-48V RTN
-48V
R4
549kΩ
1%
R5
6.49kΩ
1%
R6
10kΩ
1%
R1
0.02Ω
5%
R3
1kΩ
5%
R2
10Ω
5%
C1**
470nF
25V
Q1
IRF530
C2
15nF
100V
*
-48V RTN
(SHORT PIN)
C3
100µF
100V
*DIODES INC. SMAT70A.
**OPTIONAL.
PWRGD
MOC207
R7**
51kΩ
5%
Figure 15. Using PWRGD to Drive an Optoisolator
Component Selection Procedure
• Determine load capacitance:
CL= C2 + C3 + module input capacitance
• Determine load current, ILOAD.
• Select circuit-breaker current; for example:
ICB = 2 x ILOAD
• Calculate RSENSE:
Realize that ICB varies ±20% due to trip-voltage
tolerance.
• Set allowable inrush current:
• Determine value of C2:
• Calculate value of C1:
• Determine value of R3:
• Set R2 = 10Ω.
• If an optocoupler is utilized as in Figure 15, deter-
mine the LED series resistor:
Although the suggested optocoupler is not specified for
operation below 5mA, its performance is adequate for
36V temporary low-line voltage where LED current
would then be ≈2.2mA to 3.7mA. If R7 is set as high as
51kΩ, optocoupler operation should be verified over
the expected temperature and input voltage range to
ensure suitable operation when LED current ≈0.9mA for
48V input and ≈0.7mA for 36V input.
If input transients are expected to momentarily raise the
input voltage to >100V, select an input transient-volt-
age-suppression diode (TVS) to limit maximum voltage
on the MAX5949 to less than 100V. A suitable device is
the Diodes Inc. SMAT70A telecom-specific TVS.
Select Q1 to meet supply voltage, load current, efficien-
cy, and Q1 package power-dissipation requirements:
BVDSS ≥100V
ID(ON) ≥3x I
LOAD
DPAK, D2PAK, or TO-220AB
The lowest practical RDS(ON), within budget constraints
and with values from 14mΩto 540mΩ, are available at
100V breakdown.
Ensure that the temperature rise of Q1 junction is not
excessive at normal load current for the package select-
ed. Ensure that ICB current during voltage transients
does not exceed allowable transient-safe operating-area
limitations. This is determined from the SOA and tran-
sient-thermal-resistance curves in the Q1 manufacturer’s
data sheet.
Example 1:
ILOAD = 2.5A, efficiency = 98%, then VDS = 0.96V is
acceptable, or RDS(ON) ≤384mΩat operating temper-
ature is acceptable. An IRL520NS 100V NMOS with
RDS(ON) ≤180mΩand ID(ON) = 10A is available in
D2PAK. (A Vishay Siliconix SUD40N10-25 100V NMOS
with RDS(ON) ≤25mΩand ID(ON) = 40A is available in
DPAK, but may be more costly because of a larger die
size.)
Using the IRL520NS, VDS ≤0.625V even at +80°C so
efficiency ≥98.6% at 80°C. PD≤1.56W and junction
temperature rise above case temperature would be 5°C
due to the package θJC = 3.1°C/W thermal resistance.
Of course, using the SUD40N10-25 would yield an effi-
ciency greater than 99.8% to compensate for the
increased cost.
RVV
mA I mA
IN NOMINAL
LED
72
35
()
=≤≤
−
Rs
Ctypically k3 150
21≤µ ( )Ω
CCCx
VV
V
gd IN MAX GS TH
GS TH
12=+ ⎛
⎝
⎜⎞
⎠
⎟
−
()
() ()
()
CAxC
I
L
INRUSH
245
=µ
Ix
mV
RIor
II xI
INRUSH SENSE LOAD
INRUSH LOAD CB MIN
≤
+≤
−08 40
08
.
.()
RmV
I
SENSE CB
=50
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
______________________________________________________________________________________ 15
MAX5949A/MAX5949B
If ICB is set to twice ILOAD, or 5A, VDS momentarily dou-
bles to ≤1.25V. If COUT = 4000µF, transient-line input
voltage is ∆36V, and the 5A charging-current pulse is:
Entering the data sheet transient-thermal-resistance
curves at 1ms provides a θJC = 0.9°C/W. PD= 6.25W,
so ∆tJC = 5.6°C. Clearly, this is not a problem.
Example 2:
ILOAD = 10A, efficiency = 98%, allowing VDS = 0.96V
but RDS(ON) ≤96mΩ. An IRF530 in a D2PAK exhibits
RDS(ON) ≤90mΩat +25°C and ≤135mΩat +80°C.
Power dissipation is 9.6W at +25°C or 14.4W at +80°C.
Junction-to-case thermal resistance is 1.9W/°C, so the
junction-temperature rise would be approximately 5°C
above the +25°C case temperature. For higher efficien-
cy, consider IRL540NS with RDS(ON) ≤44mΩ. This
allows η= 99%, PD≤4.4W, and TJC = +4°C (θJC =
1.1°C/W) at +25°C.
Thermal calculations for the transient condition yield
ICB = 20A, VDS = 1.8V, t = 0.5ms, transient θJC =
0.12°C/W, PD= 36W and ∆tJC = 4.3°C.
tFx V
Ams . ==
4000 1 25
51
µ
-48V Hot-Swap Controllers
with External RSENSE
16 ______________________________________________________________________________________
SENSE RESISTOR
HIGH-CURRENT PATH
MAX5949A
MAX5949B
SENSE VEE
Figure 16. Recommended Layout for Kelvin-Sensing Current
Through Sense Resistor
Selector Guide
PART PWRGD POLARITY FAULT MANAGEMENT
MAX5949AESA Active low (PWRGD) Latched
MAX5949BESA Active high (PWRGD) Latched
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
______________________________________________________________________________________ 17
VEE SENSE GATE DRAIN
VDD
OV
UV
PWRGD
MAX5949A
-48V (INPUT1)
-48V (INPUT2)
INPUT1
0.1µF
10V
C1
490nF
25V C3
0.1µF
100V
C4
100µF
100V
C2
15nF
100V
R4
549kΩ
1%
R5
649kΩ
1%
R6
10kΩ
1%
R2
10Ω
5%
R1
0.02Ω
5%
R3
1kΩ
5%
INPUT2
N
LUCENT
JW050A1-E
VIN+
VIN-
-48V RTN
-48V RTN
(SHORT PIN)
BACKPLANE CIRCUIT CARD
Typical Operating Circuit
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
8 SO S8+5 21-0041 90-0096
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 11/04 Initial release —
1 8/11 Updated the Electrical Characteristics and Figure 11. 3, 12
