FEATURES
D18-CHANNEL GAMMA CORRECTION
D2-CHANNEL PROGRAMMABLE VCOM:
100mA IOUT
DON-CHIP OTP MEMORY
D10-BIT RESOLUTION
DRAIL-TO-RAIL OUTPUT
DLOW SUPPLY CURRENT: 900µA/ch
DSUPPLY VOLTAGE: 7V to 18V
DDIGITAL SUPPLY: 2.0V to 5.5V
DINDUSTRY-STANDARD, TWO-WIRE
INTERFACE: 3.4MHz HIGH-SPEED MODE
DHIGH ESD RATING:
4kV HBM, 1kV CDM, 200V MM
DDEMO BOARD AND SOFTWARE AVAILABLE
REFH OUT
7V−18V2V−5.5V
REFLAOLD
SCL
SDA
OUT 1
OUT 18
REFL OUT
OUT 2
OUT 17
VCOM OUT1
VCOM OUT2
DAC Registers 2
Control IF
…
…
18 Output Channels plus
Two VCOM Channels
BUF20820
DAC Registers 1
…
OTP Memory
Digital Analog REFH
Program Command
APPLICATIONS
DREPLACES RESISTOR-BASED GAMMA
SOLUTIONS
DTFT-LCD REFERENCE DRIVERS
DDYNAMIC GAMMA CONTROL
DESCRIPTION
The BUF20820 is a programmable voltage reference
generator designed for gamma correction in TFT-LCD
panels. It provides 18 programmable outputs for gamma
correction and two channels for VCOM adjustment, each
with 10-bit resolution. It offers on-chip One-Time
Programmable (OTP) memory that allows the user to store
the gamma voltages on-chip. This eliminates the need for
an external EEPROM.
This programmability replaces the traditional, time-
consuming process of changing resistor values to optimize
the various gamma voltages and allows designers to
determine the correct gamma voltages for a panel very
quickly. Required voltage changes can also be easily
implemented without hardware changes.
The BUF20820 uses TI’s latest, small-geometry analog
CMOS process, which makes it a very competitive choice
for full production, not just evaluation.
Programming of each output occurs through an industry-
standard, two-wire serial interface. Unlike existing
programmable bu ffers, the BUF20820 offers a high-speed
mode that allows clock speeds up to 3.4MHz.
For lower or higher channel count, please contact your
local sales or marketing representative.
The BUF20820 is available in an HTSSOP-38
PowerPAD package. It is specified from −40°C to +85 °C.
BUF20820 RELATED PRODUCTS
FEATURES PRODUCT
18-Channel Programmable, Two VCOM BUF20800
12-Channel Programmable Buffer, 10-Bit BUF12800
Programmable VCOM with Memory BUF01900
10-Channel Gamma Correction Buffer, Int VCOM,
18V Operating Supply Voltage BUF11704
High-Speed VCOM, 1 and 2 Channels SN10501
Complete LCD DC/DC Solution TPS651xx
BUF20820
SBOS330E − DECEMBER 2005 − REVISED OCTOBER 2008
18-Channel GAMMA VOLTAGE GENERATOR
with Two Programmable VCOM Channels
! !
www.ti.com
Copyright 2005−2008, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
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2
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage, VS +19V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage, VSD +6V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Input Terminals, SCL, SDA, AO, LD:
Voltage −0.5V to +6V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current ±10mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Short Circuit(2) Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature −40°C to +95°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature −65°C to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction Temperature +125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Rating:
Human Body Model (HBM) 4kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged-Device Model (CDM) 1kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine Model (MM) 200V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only , and functional operation of the device at these or any other conditions beyond those specified is
not supported.
(2) Short-circuit to ground.
ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
BUF20820 HTSSOP-38 DCP BUF20820
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
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3
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = −40°C to +85°C.
At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
BUF20820
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG
Gamma Output Swing—High OUT1−9, REFH OUT, Sourcing 10mA, VREFH = 17.8V, Code 1023 17.7 17.8 V
OUT10−18, REFL OUT, Sourcing 10mA, VREFH = 17.8V, Code 1023 17.0 17.2 V
Gamma Output Swing—Low OUT1−9, REFH OUT, Sinking 10mA, VREFL = 0.2V, Code 00 0.6 1.0 V
OUT10−18, REFL OUT, Sinking 10mA, VREFL = 0.2V, Code 00 0.2 0.3 V
VCOM Buffer Output Swing—High VCOM, Sourcing 100mA, VREFH = 17.8V 13 15.5 V
VCOM Buffer Output Swing—Low VCOM, Sinking 100mA, VREFL = 0.2V 1 2.0 V
Output Current See Typical Characteristics Curve
REFH Input Range(1) 4 VSV
REFL Input Range(1) GND VS − 4 V
Integral Nonlinearity INL No Load, VREFH = 17V, VREFL = 1V 0.3 1.5 Bits
Dif ferential Nonlinearity DNL No Load, VREFH = 17V, VREFL = 1V 0.3 1 Bits
Gain Error 0.12 %
Program to Out Delay tD5µs
Output Accuracy No Load, VREFH = 17V, VREFL = 1V ±20 ±50 mV
over Temperature ±25 mV
Input Resistance at VREFH and VREFL RINH 100 MΩ
Load Regulation, All References REG VOUT = VS/2, IOUT = +5mA to −5mA Step 0.5 1.5 mV/mA
40mA, All Channels VOUT = VS/2, ISINKING = 40mA, ISOURCING = 40mA 0.5 1.5 mV/mA
ANALOG POWER SUPPLY
Operating Range(2) VS7 18 V
Total Analog Supply Current ISNo Load 18 28 mA
over Temperature 28 mA
DIGITAL
Logic 1 Input Voltage VIH 0.7 × VSD V
Logic 0 Input Voltage VIL 0.3 × VSD V
Logic 0 Output Voltage VOL ISINK = 3mA 0.15 0.4 V
Input Leakage ±0.01 ±10 µA
Clock Frequency fCLK Standard/Fast Mode 400 kHz
High-Speed Mode 3.4 MHz
DIGITAL POWER SUPPLY
Operating Voltage Range VSD 2.0 5.5 V
Digital Supply Current(3) ISD No-Load, Two-Wire Bus Inactive 25 50 µA
over Temperature 100 µA
TEMPERATURE
Specified Temperature Range −40 +85 °C
Operating Temperature Range Junction Temperature < +125°C −40 +95 °C
Storage Temperature Range −65 +150 °C
Thermal Resistance, HTSSOP-38
Junction-to-Ambient qJA 30 °C/W
Junction-to-Case qJC 15 °C/W
(1) See Applications Information section REFH and REFL Input Range.
(2) Minimum analog supply voltage is 8.5V when programming OTP memory.
(3) See typical characteristic curve, Digital Supply Current vs Two-Wire Bus Activity.
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4
PIN CONFIGURATIONS
Top V iew HTSSOP
(1) NC denotes no connection.
(2) GNDD and GNDA are internally connected and must be at the same voltage potential.
VCOM OUT 2
REFH
NC(1)
NC(1)
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
GNDA(2)
VS
OUT7
OUT8
OUT9
REFH OUT
VSD
SCL
SDA
VCOM OUT 1
REFL
NC(1)
NC(1)
REFL OUT
OUT18
OUT17
OUT16
OUT15
OUT14
GNDA(2)
VS
OUT13
OUT12
OUT11
OUT10
GNDD(2)
LD
AO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
PowerPAD
Lead−Frame
Die Pad
Exposed on
Underside
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TYPICAL CHARACTERISTICS
At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
Figure 1
10
8
6
4
2
0
Analog Supply Current (mA)
ANALOG SUPPLY CURRENT vs TEMPERATURE
−40 −20 0 10040 60 8020
Temperat ure (_C)
VS= 18V
VS= 10V
Figure 2
30
25
20
15
10
5
0
Digital Supply Current (µA)
DIGITAL SUPPLY CURRENT vs TEMPERATURE
−40 −20 0 10040 60 8020
Temperat ure (_C)
VSD =3.3V
VSD =5V
VS= 10V
Output Voltage (5V/div)
FULL−SCALE OUTPUT SWING
Time (1µs/div)
REFH = 17V
REFL = 1V
Code 3FF →000
Code 000 →3FF
Figure 3 Figure 4
18
17
16
15
3
2
1
0
Output Voltage (V)
OUTPUT VOLTAGE vs OUTPUT CURRENT
01020 10040 50 60 70 80 9030
Output Current (mA)
OUT1−9, VCOM1−2 (sinking)
Code = 000h
VREFL =1V,V
REFH =17.8V
RLOAD Connectedto18V
OUT10−18 (sourcing), Code = 3FFh
VREFL =0.2V,V
REFH =17V
RLOAD Connected to GND
OUT10−18 (sinking), Code = 000h
VREFL =0.2V,V
REFH = 17V
RLOAD Connected to 18V
OUT1−9, VCOM1−2 (sourcing)
Code = 3FFh
VREFL =1V,V
REFH = 17.8V
RLOAD Connected to GND
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
INL Error (LSB)
INTEGRAL NONLINEARITY ERROR vs INPUT CODE
0 200 1000400 600 800
Input Code
Figure 5
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
DNL Error (LSB)
DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE
0 200 1000400 600 800
Input Code
Figure 6
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6
APPLICATIONS INFORMATION
The BUF20820 programmable voltage reference allows
fast and easy adjustment of 18 programmable reference
outputs and two channels for VCOM adjustment, each with
10-bit resolution. It allows very simple, time-efficient
adjustment of the gamma reference and VCOM voltages.
The BUF20820 is programmed through a high-speed,
standard, two-wire interface. The BUF20820 features a
double-register structure for each DAC channel to simplify
the implementation of dynamic gamma control. This
design allows pre-loading of register data and rapid
updating of all channels simultaneously.
Buffers 1−9 are able to swing to within 200mV of the
positive supply rail, and to within 0.6V of the negative
supply rail. Buffers 10−18 are able to swing to within 0.8V
of the positive supply rail and to within 200mV of the
negative supply rail.
The BUF20820 can be powered using an analog supply
voltage from 7V to 18V, and a digital supply from 2V to
5.5V. The digital supply must be applied prior to or
simultaneously with the analog supply to avoid excessive
current and power consumption; damage to the device
may occur if it is left connected only to the analog supply
for extended periods of time. Figure 7 shows the power
supply timing requirements.
VSD
GNDD
VS
GND
Digital Supply:
Analog Supply:
t1: 0s minimum delay between Digital Supply and Analog Supply.
t1
Figure 7. Power Supply Timing Requirements
Figure 8 shows the BUF20820 in a typical configuration.
In this configuration, the BUF20820 device address is 74h.
The output of each digital-to-analog converter (DAC) is
immediately updated as soon as data are received in the
corresponding register (LD = 0). For maximum dynamic
range, set VREFH = VS − 0.2V and VREFL = GND + 0.2V.
TWO-WIRE BUS OVERVIEW
The BUF20820 communicates through an industry-
standard, two-wire interface to receive data in slave mode.
This standard uses a two-wire, open-drain interface that
supports multiple devices on a single bus. Bus lines are
driven to a logic low level only. The device that initiates the
communication is called a master, and the devices
controlled by the master are slaves. The master generates
the serial clock on the clock signal line (SCL), controls the
bus access, and generates the START and STOP
conditions.
To address a specific device, the master initiates a START
condition by pulling the data signal line (SDA) from a HIGH
to a LOW logic level while SCL is HIGH. All slaves on the
bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended.
During the 9th clock pulse, the slave being addressed
responds to the master by generating an Acknowledge
and pulling SDA LOW.
Data transfer is then initiated and eight bits of data are sent
followed by an Acknowledge Bit. During data transfer,
SDA must remain stable while SCL is HIGH. Any change
in SDA while SCL is HIGH will be interpreted as a START
or STOP condition.
Once all data have been transferred, the master generates
a STOP condition indicated by pulling SDA from LOW to
HIGH while SCL is HIGH.
The BUF20820 can act only as a slave device; therefore,
it never drives SCL. SCL is only an input for the BUF20820.
Table 1 and Table 2 summarize the address and
command codes, respectively, for the BUF20820.
ADDRESSING THE BUF20820
The address of the BUF20820 is 111010x, where x is the
state of the A0 pin. When the A0 pin is LOW, the device will
acknowledge on address 74h (1110100). If the A0 pin is
HIGH, the device will acknowledge on address 75h
(1110101).
Other valid addresses are possible through a simple mask
change. Contact your TI representative for information.
Table 1. Quick-Reference Table of BUF20820
Addresses
DEVICE/COMPONENT ADDRESS
BUF20820 Address:
A0 pin is LOW
(device will acknowledge on address 74h) 1110100
A0 pin is HIGH
(device will acknowledge on address 75h) 1110101
Table 2. Quick-Reference Table of Command
Codes
COMMAND CODE
General Call Reset Address byte of 00h followed by a data byte
of 06h.
High-Speed Mode 00001xxx, with SCL ≤ 400kHz; where xxx
are bits unique to the Hs-capable master.
This byte is called the Hs master code.
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7
VCOM OUT2
REFH
NC
NC
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
GNDA(3)
VS(4)
OUT7
OUT8
OUT9
REFH OUT
VSD
SCL
SDA
VCOM OUT1
REFL
NC
NC
REFL OUT
OUT18
OUT17
OUT16
OUT15
OUT14
GNDA(3)
VS(4)
OUT13
OUT12
OUT11
OUT10
GNDD(3)
LD
AO
BUF20820
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
VCOM1 VCOM2
VS
VS
VS
(1)
(1)
(1)
(1)
(1)
Timing
Controller
3.3V
NOTES: (1) RC combination optional.
(2) GNDAand GNDDmust be connected together.
(3) Connecting acapacitor to this node is not recommended.
(4) Pins 12 and 27 are VS. The one set of capacitors shown on pin 27 are common to both pins.
100nF1µF
(1)
(1)
(1)
(1)
100nF 10µF
Source
Driver
Source
Driver
VS
(1)
(1)
(1)(1)
(1)
(2) (2)
(1)
(1)
(1)
(1)
(1)
(1)
Source
Driver
Source
Driver
Figure 8. Typical Application Configuration
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8
DATA RATES
The two-wire bus operates in one of three speed modes:
DStandard: allows a clock frequency of up to 100kHz;
DFast: allows a clock frequency of up to 400kHz; and
DHigh-speed mode (or Hs mode): allows a clock
frequency of up to 3.4MHz.
The BUF20820 is fully compatible with all three modes. No
special action is required to use the device in Standard or
Fast modes, but High-speed mode must be activated. To
activate High-speed mode, send a special address byte of
00001xxx, with SCL = 400kHz, following the START
condition; xxx are bits unique to the Hs-capable master,
which can be any value. This byte is called the Hs master
code. (Note that this is different from normal address
bytes—the low bit does not indicate read/write status.) The
BUF20820 will respond to the High-speed command
regardless of the value of these last three bits. The
BUF20820 will not acknowledge this byte; the
communication protocol prohibits acknowledgement of
the Hs master code. On receiving a master code, the
BUF20820 will switch on its Hs mode filters, and
communicate at up to 3.4MHz. Additional high-speed
transfers may be initiated without resending the Hs mode
byte by generating a repeat START without a STOP. The
BUF20820 will switch out of Hs mode with the next STOP
condition.
GENERAL CALL RESET AND POWER-UP
The BUF20820 responds to a General Call Reset, which
is an address byte of 00h (0000 0000) followed by a data
byte of 06h (0000 0110). The BUF20820 acknowledges
both bytes. Upon receiving a General Call Reset, the
BUF20820 performs a full internal reset, as though it had
been powered off and then on. It always acknowledges t h e
General Call address byte of 00h (0000 0000), but does
not acknowledge any General Call data bytes other than
06h (0000 0110).
The BUF20820 automatically performs a reset upon
power-up. As part of the reset, the BUF20820 is configured
for all outputs to change to the programmed OTP memory
values, or to ‘0000’ if the OTP values have not been
programmed.
The BUF20820 resets all outputs to the OTP memory
values (or to ‘0000’ if the OTP values have not been
programmed) when the device address is sent, followed
by a valid DAC address with bits D7 to D5 set to ‘100’. If
these bits are set to ‘010’, only the DAC being addressed
will be reset.
OUTPUT VOLTAGE
Buffer output values are determined by the reference
voltages (VREFH and VREFL) and the decimal value of the
binary input code used to program that buf fer . The value is
calculated using Equation 1:
VOUT +ƪVREFH *VREFL
1024 Decimal Value of Codeƫ)VREFL
The valid voltage ranges for the reference voltages are:
4V vVREFH vVS*0.2V and 0.2V vVREFL vVS*4V
The BUF20820 outputs are capable of a full-scale voltage
output change in typically 5µs—no intermediate steps are
required.
OUTPUT LATCH
Updating the DAC register is not the same as updating the
DAC output voltage, because the BUF20820 features a
double-buffered register structure. There are three
methods for latching transferred data from the storage
registers into the DACs to update the DAC output
voltages.
Method 1 requires externally setting the latch pin (LD)
LOW, LD = LOW, which will update each DAC output
voltage whenever its corresponding register is updated.
Method 2 externally sets LD = HIGH to allow all DAC
output voltages to retain their values during data transfer
and until LD = LOW , which will then simultaneously update
the output voltages of all DACs to the new register values.
Use this method to transfer a future data set in advance to
prepare for a very fast output voltage update.
Method 3 uses software control. LD is maintained HIGH,
and all DACs are updated when the master writes a 1 in bit
15 and a 0 in bit 14 of any DAC register. The update will
occur after receiving the 16-bit data for the
currently-written register.
The General Call Reset and the power-up reset will update
the DAC regardless of the state of the latch pin.
(1)
(2)
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9
ACQUIRE OF OTP MEMORY
A general acquire command will update all registers and
DAC outputs to the values stored in OTP memory.
A single channel acquire command will update only the
register and DAC output of the DAC corresponding to the
DAC address used in the command.
General Acquire Command
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3. Send a DAC address byte. Bits D7−D5 must be s et
to 100. Bits D4−D0 are any valid DAC address.
Only addresses 00000 to 10100 are valid and will
be acknowledged. Table 3 shows the valid
addresses.
4. Send a STOP condition on the bus.
Following this command, all DAC registers and DAC
outputs will change to the OTP memory values.
Table 3. DAC Addresses
DAC ADDRESS
DAC_1 0 0000
DAC_2 0 0001
DAC_3 0 0010
DAC_4 0 0011
DAC_5 0 0100
DAC_6 0 0101
DAC_7 0 0110
DAC_8 0 0111
DAC_9 0 1000
DAC_10 0 1001
DAC_11 0 1010
DAC_12 0 1011
DAC_13 0 1100
DAC_14 0 1101
DAC_15 0 1110
DAC_16 0 1111
DAC_17 1 0000
DAC_18 1 0001
VCOM OUT1 1 0010
VCOM OUT2 1 0011
W rite Disable Bit 1 0100
Single Channel Acquire Command
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3. Send a DAC address byte using the DAC address
corresponding to the DAC output and register to
update with the OTP memory value. Bits D7−D5 must
be set to 010. Bits D4−D0 are the DAC address. Only
DAC addresses 00000 to 10100 are valid and will be
acknowledged. Table 3 shows the valid addresses.
4. Send a STOP condition on the bus.
See Figure 9 for the timing diagrams for the acquire
commands.
READ/WRITE OPERATIONS
Single or multiple read and write operations can be done
in a single communication transaction. Writing to a DAC
register differs from writing to the OTP memory. Bits
D15−D14 o f the most significant byte of data will determine
if data will be written to the DAC register or the OTP
memory. See Figure 10 through Figure 12 for the timing
diagrams and timing requirements for the read/write
commands.
Read/Write: DAC register
The BUF20820 is able to read from a single DAC, or
multiple DACs, or write to the register of a single DAC, or
multiple DACs in a single communication transaction.
DAC addresses begin with 00000, which corresponds to
DAC_1, through 10011, which corresponds to VCOM OUT2.
Write commands are performed by setting the read/write
bit LOW. Setting the read/write bit HIGH will perform a read
transaction.
Writing:
To write to a single DAC register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3. Send a DAC or write disable bit address byte. Bits
D7−D5 must be set to 0. Bits D4−D0 are the DAC
address. Only addresses 00000 to 10100 are valid
and will be acknowledged. Table 3 shows valid
addresses.
4. Send two bytes of data for the specified DAC register.
Begin by sending the most significant byte first (bits
D15−D8, of which only bits D9 and D8 are used, and
bits D15−D14 must not be 01), followed by the least
significant byte (bits D7−D0). For address 10100, only
D0 has meaning. This bit is the write disable bit. The
register is updated after receiving the second byte.
5. Send a STOP condition on the bus.
The BUF20820 will acknowledge each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register will not be updated. Updating the DAC register is
not the same as updating the DAC output voltage. See the
Output Latch section.
The process of updating multiple DAC registers begins the
same as when updating a single register. However,
instead of sending a STOP condition after writing the
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10
addressed register, the master continues to send data for
the next register. The BUF20820 automatically and
sequentially steps through subsequent registers as
additional data is sent. The process continues until all
desired registers have been updated or a STOP condition
is sent.
To write to multiple DAC registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3. Send either the DAC_1 address byte to start at the first
DAC, or send the address byte for whichever DAC will
be the first in the sequence of DACs to be updated.
The BUF20820 will begin with this DAC and step
through subsequent DACs in sequential order.
4. Send the bytes of data; begin by sending the most
significant byte (bits D15−D8, of which only bits D9
and D8 have meaning, and bits D15−D14 must not be
01), followed by the least significant byte (bits D7−D0).
The first two bytes are for the DAC addressed in step
3 above. Its register is automatically updated after
receiving the second byte. The next two bytes are for
the following DAC. That DAC register is updated after
receiving the fourth byte. This process continues until
the registers of all following DACs have been updated.
The last address, 10100, is the address of the write
disable bit and cannot be accessed using this method.
It must be written using the write to a single DAC
register procedure.
5. Send a STOP condition on the bus.
The BUF20820 will acknowledge each byte. To terminate
communication, send a STOP or START condition on the
bus. Only DAC registers that have received both bytes of
data will be updated.
Reading:
Reading a DAC register will return the data stored in the
DAC. This data can differ from the data stored in the DAC
register. See the Output Latch section.
To read the DAC value:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3. Send the DAC address byte. Bits D7−D5 must be set
to 0; Bits D4−D0 are the DAC address. Only DAC
addresses 00000 to 10100 are valid and will be
acknowledged. For address 10100, only D0 has
meaning. This bit is the write disable bit.
4. Send a S TART or STOP/ST ART condition on the bus.
5. Send correct device address and read/write
bit = HIGH. The BUF20820 will acknowledge this
byte.
6. Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15−D8, only bits D9 and D8 have
meaning); the next byte is the least significant byte
(bits D7−D0).
7. Acknowledge after receiving the first byte.
8. Do not acknowledge the second byte to end the read
transaction.
Communication may be terminated by sending a
premature S TOP o r S TART condition on the bus, or by no t
sending the acknowledge.
To Read Multiple DACs:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3. Send either the DAC_1 address byte to start at the first
DAC, or send the address byte for whichever DAC will
be the first in the sequence of DACs to be read. The
BUF20820 will begin with this DAC and step through
subsequent DACs in sequential order.
4. Send a S TART or STOP/ST ART condition on the bus.
5. Send correct device address and read/write
bit = HIGH. The BUF20820 will acknowledge this
byte.
6. Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15−D8, only bits D9 and D8 have
meaning), the next byte is the least significant byte
(bits D7−D0).
7. Acknowledge after receiving each byte of data except
for the last byte. The acknowledge bit of the last byte
should be HIGH to end the read operation.
8. When all desired DACs have been read, send a ST OP
or START condition on the bus.
Communication may be terminated by sending a
premature S TOP o r S TART condition on the bus, or by no t
sending the acknowledge.
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11
Write: OTP Memory for the DAC Register
The BUF20820 is able to write to the OTP memory of a
single DAC, or multiple DACs in a single communication
transaction. DAC addresses begin with 00000 (which
corresponds to DAC_1) through 10011 (which corre-
sponds to VCOM OUT2).
When programming the OTP memory, the analog supply
voltage must be between 8.5V and 18V.
Write commands are performed by setting the read/write
bit LOW.
To write to a single OTP register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3. Send a DAC address byte. Bits D7−D5 must be set to
0. Bits D4−D0 are the DAC address. Only DAC
addresses 00000 to 10100 are valid and will be
acknowledged. See Table 3 for DAC addresses.
4. Send two bytes of data for the OTP register of the
specified DAC. Begin by sending the most significant
byte first (bits D15−D8, of which only bits D9 and D8
are data bits, and bits D15−D14 must be 01), followed
by the least significant byte (bits D7−D0). For address
10100, only D0 has meaning. This bit is the write
disable bit. The register is updated after receiving the
second byte.
5. Send a STOP condition on the bus.
The BUF20820 will acknowledge each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified OTP
register will not be updated. Writing an OTP register will
also update the DAC register and output voltage.
To write to multiple OTP registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3. Send either the DAC_1 address byte to start at the
OTP register of the first DAC, or send the address byte
for whichever DAC will be the first in the sequence t o
be updated. The BUF20820 will begin with the OTP
register of this DAC and step through subsequent
registers in sequential order.
4. Send the bytes of data; begin by sending the most
significant byte (bits D15−D8, of which only bits D9
and D8 have meaning, and bits D15−D14 must be 01),
followed by the least significant byte (bits D7−D0). The
first two bytes are for the OTP register of the DAC
addressed in step 3 above. This OTP register is
automatically updated after receiving the second byte.
The next two bytes are for the OTP register of the
following DAC (bits D15−D14 must again be 01). That
DAC OTP register is updated after receiving the fourth
byte. This process continues until the registers of all
following DAC OTP registers have been updated. The
last address, 10100, is the address of the write disable
bit and cannot be accessed using this method. It must
be written using the write to a single OTP register
procedure.
5. Send a STOP condition on the bus.
The BUF20820 will acknowledge each byte. To terminate
communication, send a STOP or START condition on the
bus. Only DAC registers that have received both bytes of
data will be programmed.
OTP WRITE DISABLE
Writing a ‘1’ in bit D0 of register 10100 disables all future
writes. The state of this bit can be accessed the same as
any other data bit. It is important to set this bit to 1 after the
OTP registers have been programmed to prevent
accidental changes to the OTP registers. Until bit D0 of
register 10100 is set to 1, any OTP register bit can be
changed from 0 to 1; however, once a bit is set to a 1, it
cannot be set back to 0.
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12
SCL
Start Device Address Write Ackn DAC address pointer. D7−D5 must be 100. Ackn Stop
Write OperationGeneral acquire command. P4−P0 must specify any valid DAC addess.
SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn
A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 AcknDevice_out
SCL
Start Device Address Write Ackn DAC address pointer. D7−D5 must be 010. Ackn Stop
Write OperationSingle channel acquire command. P4−P0 must specify any valid DAC addess.
SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn
A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 AcknDevice_out
a) General Acquire b) Single-Channel Acquire
Figure 9. Timing Diagram for Acquire Operation
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13
a. W rite Single DAC b. W rite Multiple DACs
SDA_in A6
Start
Write single DAC register. P4−P0 specify DAC address.
If D15= 0, the DACs are updated on the Latch pin.
If D15 = 1, all DACs are updated when the current DAC register is updated.
The whole DAC register D9−D0
is updated in this moment.
Write Operation
Device Address Write Ackn DAC address pointer. D7−D5 must be 000. Ackn DAC MSbyte. D14 must be 0. Ackn DAC LSbyte Ackn Stop
A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
SCL
Device_out
SCL
SDA_in A6
Start Device Address Write Ackn Ackn Ackn DAC (pointer) LSbyte Ackn DAC (pointer + 1) MSbyte. D14 mustbe 0.DAC (pointer) MSbyte. D14 must be 0.Start DACaddress pointer. D7−D5 must be 000.
Write Operation
Writemultiple DAC registers. P4−P0 specify start DAC address.
A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13
If D15 = 0, theDACs are updated on the Latch pin.
If D15 = 1, all DACs are updated when the current DAC register is updated. The whole DAC register D9−D0
is updated in this moment.
D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn D15 D14 D13
A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn D15 D14 D13Device_out
Thewhole DAC register D9−D0
is updated in this moment.
IfD15=0,theDACsareuploadedontheLatchpin.
If D15 = 1, all the DACs are updated when the current DAC register is updated.
D15 D14 D13
DAC 20 (VCOM OUT2)MSbyte.D14mustbe0. Ackn DAC 20 LSbyte Ackn Stop
D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
Figure 10. Timing Diagram for Write DAC Register
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14
a. Read Single DAC
SCL
SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0
A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0
Device_out
Start Device Address Write Ackn DAC address pointer. D7−D5 must be 000. Ackn Device Address Read Ackn DACMSbyte. D15−D10 have nomeaning. Ackn DACLSbyte. No Ackn StopStart
Read Operation
ReadsingleDAC register. P4−P0specifyDAC address.
SCL
Start Device Address Write Ackn Start DAC address pointer. D7−D5 must be 000. Ackn Device Address Read Ackn DAC (pointer)MSbyte. D15−D10 have no meaning. AcknStart
Read OperationRead multiple DAC registers. P4−P0 specify start DAC address.
SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn
A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4
D15
DAC 20 (VCOM OUT2) MSbyte. D15−D10 have no meaning. Ackn DAC 20 LSbyte. No Ackn Stop
D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 AcknDevice_out
b. Read Multiple DACs
Figure 11. Timing Diagram for Read DAC Register
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15
a) Write Single OTP Register b) Write Multiple OTP Registers
SCL
Start
Write single OTP register. P4−P0 specify DAC address.
Device Address Write Ackn DAC address pointer. D7−D5 must be 000. Ackn DAC (pointer) MSByte. D15−D14must be 01. Ackn DAC (pointer) LSbyte Ackn Stop
Write Operation
SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D0 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2
WriteSupplyActive
WriteSignal Active
D1 D0 Ackn
A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D0 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1
The OTPregister D9−D0 is updated at this moment.
t1:>20
µs before falling edge of clock.
t2: minimum100µs, maximum2ms.
D0 AcknDevice_out
SCL
Start
Write multiple OTP registers. P4−P0 specify start DAC address.
Device Address Write Ackn Start DAC address pointer. D7−D5 must be 000. Ackn DAC(pointer) MSByte. D15−D14 must be 01. Ackn DAC (pointer) LSbyte Ackn DAC (pointer + 1) MSbyte. D15−D14must be 01.
Write Operation
SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D0 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D0 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
D15
D15
D14
D14
D13
D13
Device_out
The OTP register D9−D0 is updated at this moment.
DAC20 (VCOMOUT2) MSbyte. D14−D10 have no meaning. Ackn DAC (pointer) LSbyte Ackn Stop
D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2
WriteSupplyActive
WriteSignal Active
D1 D0 Ackn
D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1
The whole DACregister D9−D0 is updated at this moment.
t1:>20
µs beforefalling edge of clock.
t2: minimum100µs, maximum 2ms.
D0 Ackn
t1t2
WriteSupplyActive
WriteSignal Active
t1t2
t1t2
Figure 12. Timing Diagram for Write OTP Register
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16
REPLACEMENT OF TRADITIONAL GAMMA
BUFFER
Traditional gamma buffers rely on a resistor string (often
using expensive 0.1% resistors) to set the gamma
voltages. During development, the optimization of these
gamma voltages can be time consuming. Programming
these gamma voltages with the BUF20820 can
significantly reduce the time required for gamma voltage
optimization. The final gamma values can be written into
the internal OTP memory to replace a traditional gamma
buffer solution. Figure 13a shows the traditional resistor
string approach; Figure 13b shows the more efficient
alternative method using the BUF20820.
The BUF20820 uses the most advanced high-voltage
CMOS process available today, which allows it to be
competitive with traditional gamma buffers.
Programmability offers the following advantages:
DIt shortens development time significantly.
DIt eliminates manufacturing variance between panels.
DIt allows a single panel to be built for multiple
customers, with loading of customer-dependent
gamma curves during final production. This
significantly lowers inventory cost and risk and
simplifies inventory management.
DIt allows demonstration of various gamma curves to
LCD monitor makers by simply uploading a different
set of gamma values.
DIt provides a simple means of adjusting gamma curves
during final production improve picture quality and
accommodate changes in the panel manufacturing
process or end-customer requirements.
DIt decreases cost and space.
BUFxx704
a) Traditional b) BUF20820 Solution
PC
SDA
SCL
SDA
SCL
Timing
Controller
LCD Panel Electronics
BUF20820
Register
Control Interface
Gamma
References
OUT1
OUT2
OUT17
OUT18
VCOM
VCOM OUT1
VCOM OUT2
Figure 13. Replacement of the Traditional Gamma Buffer
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17
PROGRAMMABLE VCOM
The VCOM channels of the BUF20820 can swing to 2.5V
from the positive supply rail while sourcing 100mA, and to
1V above the negative rail while sinking 100mA (see
Figure 4, typical characteristic Output Voltage vs Output
Current). The gamma and the VCOM values can be
permanently stored in the internal OTP memory. The VCOM
channels can be programmed independently from the
gamma channels. Figure 14 shows the BUF20820 being
used for VCOM voltages.
BUF20820
SDA
SCL
Register
Control Interface
Gamma
References
OUT1
OUT2
OUT17
OUT18
VCOM
VCOM OUT1
VCOM OUT2
Figure 14. BUF20820 Used for Programmable
VCOM
REFH AND REFL INPUT RANGE
Best performance and output swing range of the
BUF20820 are achieved by applying REFH and REFL
voltages that are slightly below the power-supply voltages.
Most specifications have been tested at
REFH = VS− 200mV and REFL = GND + 200mV. The
REFH internal buffer is designed to swing very closely to
VS and the REFL internal buffer to GND. However, there
is a finite limit on how close they can swing before
saturating. To avoid saturation of the internal REFH and
REFL buffers, the REFH voltage should not be greater
than VS −100mV and REFL voltage should not be lower
than GND + 100mV. Figure 15 shows the swing capability
of the REFH and REFL buffers.
The other consideration when trying to maximize the
output swing capability of the gamma buffers is the
limitation in the swing range of output buffers (OUT1−18,
VCOM OUT1, and VCOM OUT2), which depends on the load
current. A typical load in the LCD application is 5−10mA.
For example, if OUT1 is sourcing 10mA, the swing is
typically limited to about VS − 200mV. The same applies to
OUT18, which typically limits at GND + 200mV when
sinking 10mA. An increase in output swing can only be
achieved for much lighter loads. For example, a 3mA load
typically allows the swing to be increased to approximately
VS− 100mV and GND + 100mV.
Connecting REFH directly to VS and REFL directly to GND
does not damage the BUF20820. As discussed above
however, the output stages of the REFH and REFL buf fers
will saturate. This condition is not desirable and can result
in a small error in the measured output voltages of
OUT1−18, V COM OUT1, and VCOM OUT2. As described above,
this method of connecting REFH and REFL does not help
to maximize the output swing capability.
18
17
16
15
3
2
1
0
Output Voltage (V)
0 10 20 10040 50 60 70 80 9030 Output Current (mA)
REFL OUT (sinking), Code = 000h
VREFL =0.2V,V
REFH = 17V
RLOAD Connected to 18V
REFH OUT (sourcing), Code = 3FFh
VREFL =1V,V
REFH =17.8V
RLOAD Connected to GND
Figure 15. Reference Buffer Output Voltage vs
Output Current
CONFIG URATION FO R 20 GAMMA CHANNELS
The VCOM outputs can be used as additional gamma
references in order to achieve two additional gamma
channels (20 total). The VCOM outputs will behave the
same as the OUT1−9 outputs when sourcing or sinking
smaller currents (see the Typical Characteristics,
Figure 4). The VCOM outputs are better able to swing to th e
positive rail than to the negative rail. Therefore, it is better
to use the VCOM outputs for higher reference voltages; see
Figure 16.
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18
CONFIG URATION FO R 22 GAMMA CHANNELS
In addition to the VCOM outputs, the REFH and REFL OUT
outputs can also be used as fixed gamma references. The
output voltage will be set by the REFH and REFL input
voltages, respectively. Therefore, REFH OUT should be
used for the highest voltage gamma reference, and REFL
OUT for the lowest voltage gamma reference. A
22-channel solution can be created by using all 18 outputs,
the two VCOM outputs, and both REFH/L OUT outputs for
gamma references—see Figure 17. However, the REFH
and REFL OUT buffers were designed to only drive light
loads on the order of 5−10mA. Driving capacitive loads is
not recommended with these buffers. In addition, the
REFH and REFL buffers must not be allowed to saturate
from sourcing/sinking too much current from REFH OUT
or REFL OUT. Saturation of the REFH and REFL buffers
results in errors in the voltages of OUT1−18, VCOM OUT1,
and VCOM OUT2. The BUF01900 can be used to provide a
programmable VCOM output.
SDA
SCL
LD A0
AnalogDigital REFH
OUT17
VCOM OUT1
REFL
DAC Registers 2
Control IF
OUT18
OUT1
OUT2
REFH OUT
REFL OUT
DAC Registers 1
OTP Memory
Program Command
14.8V
0.2V
15V
2V−5.5V
15V 0.2V
14.8V
GMA 3
GMA 4
GMA 19
GMA 20
VCOM OUT2
GMA 1
GMA 2
2V
COM Channels plus
18 Gamma Channels
Source
Driver
BUF20820
Figure 16. 20-Gamma Channel Solution—2 VCOM Channels Used as Additional Gamma Channels
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19
SDA
SCL
LD A0
AnalogDigital REFH
OUT 17
REFL
DAC Registers 2
Control IF
OUT 18
OUT 1
OUT 2
REFL OUT
DAC Registers 1
OTP Memory
REFH OUT
17V
0.2V
15V
15V 0.2V VCOM
Output of reference
buffer can be used
for an extra fixed
gamma channel.
14.8V2V−5.5V
GMA 1
GMA 2
GMA 3
GMA 4
GMA 5
GMA 20
GMA 21
GMA 22
(REFH OUT
willbeafixed
voltage.)
Referencebuffer
and VCOM OUT
outputs can be used
for extra gamma channels.
Analog BIAS
8V−18V
Digital
2V−5.5V
SDA
SCL
A0
Control IF
VCOM OUT
VCOM
Buffer
10−Bit
DAC
4xOTP
ROM Switch
Control
Voltage Regulator
Program Command
18 Output Channels
2V
COM Channels plus
Program Command
VCOMOUT2
VCOMOUT1
BUF01900
Panel
Source
Driver
BUF20820
Figure 17. 22-Gamma Channel Solution
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20
DYNAMIC GAMMA CONTROL
Dynamic gamma control is a technique used to improve
the picture quality in LCD TV applications. The brightness
in each picture frame is analyzed and the gamma curves
are adjusted on a frame-by-frame basis. The gamma
curves are typically updated during the short vertical
blanking period in the video signal. Figure 18 shows a
block diagram using the BUF20820 for dynamic gamma
control and VCOM output.
The BUF20820 is ideally suited for rapidly changing the
gamma curves because of its unique topology:
Ddouble register input structure to the DAC;
Dfast serial interface;
Dsimultaneous updating of all DACs by software. See
the Read/Write Operations to write to all registers an d
the Output Latch sections.
The double register input structure saves programming
time by allowing updated DAC values to be pre-loaded
into the first register bank. Storage of this data can occur
while a picture is still being displayed. Because the data
are only stored into the first register bank, the DAC output
values remain unchanged—the display is unaffected.
During the vertical sync period, the DAC outputs (and
therefore, the gamma voltages) can be quickly updated
either by using an additional control line connected to the
LD pin, or through software—writing a ‘1’ in bit 15 of any
DAC register. For the details on the operation o f the double
register input structure, see the Output Latch section.
Example: Update all 18 gamma registers simultaneously
via software.
Step 1: Check if LD pin is placed in HIGH state.
Step 2: Write DAC Registers 1−18 with bit 15 always ‘0’.
Step 3 : Write any DAC register a second time with identi-
cal data. Make sure that bit 15 is ‘1’. All DAC channels will
be updated simultaneously after receiving the last bit of
data. (Note: this step may be eliminated by setting bit 15
of DAC 18 to ‘1’ in the previous step.)
Digital
Picture
Data
Histogram
Gamma
Adjustment
Algorithm
SDA BUF20820
Gamma References
Timing Controller/µController
1 through 18
SCL
Source Driver Source Driver VCOM
Black White
Figure 18. Dynamic Gamma Control
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21
TOTAL TI PANEL SOLUTION
In addition to the BUF20820 programmable voltage
reference, T I o ffers a complete set of ICs for the LCD panel
market, including gamma correction buffers, various
power-supply solutions, and audio power solutions. See
Figure 19 for the total IC solution from TI.
THE BUF20820 IN INDUSTRIAL
APPLICATIONS
The wide supply range, high output current, and very low
cost make the BUF20820 attractive for a range of medium
accuracy industrial applications such as programmable
power supplies, multi-channel data acquisition systems,
data loggers, sensor excitation and linearization,
power-supply generation, and others. Each DAC channel
features 1LSB DNL and INL.
Many systems require dif ferent levels of biasing and power
supply for various components as well as sensor
excitation, control-loop set-points, voltage outputs, current
outputs, and other functions. The BUF20820, with its 20
total programmable DAC channels, provides great
flexibility to the entire system by allowing the designer to
change all these parameters via software.
Figure 20 provides various ideas on how the BUF20820
can be used in applications. A micro-controller with
two-wire serial interface controls the various DACs of the
BUF20820. The BUF20820 can be used for:
Dsensor excitation
Dprogrammable bias/reference voltages
Dvariable power-supplies
Dhigh-current voltage output
D4-20mA output
Dset-point generators for control loops.
NOTE: At power-up, the output voltages of the BUF20820
DACs are configured to the programmed OTP memory
values, o r ( V REFH − VREFL)/2 if the OTP values have not been
programmed.
2.7 V−5 V
3.3 V
nn
26 V
−14 V
15 V
TPA3005D2
TPA3008D2
Audio
Speaker
Driver
Logic and
Timing
Controller
High−Resolution
TFT−LCS Panel
Source Driver
Gamma Correction
BUF20820
VCOM
Gate Driver
TPS651xx
LCD
Supply
Figure 19. TI LCD Solution
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SBOS330E − DECEMBER 2005 − REVISED OCTOBER 2008
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22
Sensor Excitation/Linearization
0.3V to 17V
2V to 16V, 100mA
+18V +5V
Voltage
Output
High Current
Voltage Output
SDA SCL
µC
BUF20820 +5V
+5V
+2.5V Bias
Bias Voltage
Generator
LED Driver
+4.3V +4V
+7.5V
Supply Voltage
Generator
Control Loop
Set Point
Offset
Adjustment
Ref
INA
MDAC
Comparator
Threshold
4−20mA
4−20mA
Generator
Reference
for MDAC
Ref
Figure 20. Industrial Applications for the BUF20820
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SBOS330E − DECEMBER 2005 − REVISED OCTOBER 2008
www.ti.com
23
EVALUATION BOARD AND SOFTWARE
An evaluation board is available for the BUF20820, as
shown in Figure 21. The evaluation board features
easy-to-use software that allows individual channel
voltages to be set. Configurations can be quickly
evaluated to determine optimal codes for a given
application. Contact your local TI representative for more
information regarding the evaluation board.
Figure 21. BUF208x0 Evaluation Board
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SBOS330E − DECEMBER 2005 − REVISED OCTOBER 2008
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24
OUTPUT PROTECTION
The BUF20820 output stages can safely source and sink
the current levels indicated in Figure 4. However,
precautions must be taken in certain situations in order to
prevent the output stages from being damaged by
excessive current flow. The outputs (OUT1-18, VCOM O UT 1
and V COM OUT 2) include ESD protection diodes, as shown
in Figure 22. Normally, these diodes do not conduct and
are passive during typical device operation. Under certain
operating conditions where the diodes may conduct, they
can be subjected to high or even damaging current levels.
These conditions are most likely to occur when a voltage
applied to an output exceeds VS + 0.5V, or drops below
GND − 0.5V.
One common scenario where these conditions can occur
is when the output pin is connected to a sufficiently large
capacitor, and the BUF20820 power-supply source (VS) is
suddenly removed. Removing the power-supply source
allows the capacitor to discharge through the
current-steering diodes. The energy released during the
high current flow period causes the power dissipation
limits of the diode to be exceeded. Protection against this
high current flow may be provided by placing
current-limiting resistors in series with the output, as
shown in Figure 8. Select a resistor value that restricts the
current level to the maximum rating for the particular pin.
VS
OUTX
or
VCOMX
ESD Current
Steering Diodes
BUF20820
Figure 22. Output Pins ESD Protection
Current-Steering Diodes
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SBOS330E − DECEMBER 2005 − REVISED OCTOBER 2008
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25
GENERAL POWERPAD DESIGN
CONSIDERATIONS
The BUF20820 is available in a thermally-enhanced
PowerPAD package. This package is constructed using a
downset leadframe upon which the die is mounted, as
shown in Figure 23(a) and Figure 23(b). This arrangement
results in the lead frame being exposed as a thermal pad
on the underside of the package; see Figure 23(c). This
thermal pad has direct thermal contact with the die; thus,
excellent thermal performance is achieved by providing a
good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a ground plane or other heat-dissipating device.
Soldering the PowerPAD to the printed circuit board
(PCB) is always required, even with applications that
have low power dissipation. This provides the
necessary thermal and mechanical connection between
the lead frame die pad and the PCB.
The PowerPAD must be connected to the most negative
supply voltage on the device, GNDA and GNDD.
1. Prepare the PCB with a top-side etch pattern. There
should be etching for the leads as well as etch for the
thermal pad.
2. Place recommended holes in the area of the thermal
pad. Ideal thermal land size and thermal via patterns
(2x5) for the HTSSOP-38 DCP package can be seen
in the technical brief, PowerPAD Thermally-En-
hanced Package (SLMA002), available for download
at www.ti.com. These holes should be 13 mils
(0.33mm) in diameter. Keep them small, so that solder
wicking through the holes is not a problem during re-
flow.
3. Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the BUF20820
IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can
be larger because they are not in the thermal pad area
to be soldered; thus, wicking is not a problem.
4. Connect all holes to the internal plane that is at the
same voltage potential as the GND pins.
5. When connecting these holes to the internal plane, do
not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the BUF20820
PowerPAD package should make their connection to
the internal plane with a complete connection around
the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals
of the package and the thermal pad area with its eight
holes exposed. The bottom-side solder mask should
cover the holes of the thermal pad area. This masking
prevents solder from being pulled away from the
thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8. With these preparatory steps in place, the BUF20820
IC is simply placed in position and run through the
solder reflow operation as any standard surface-
mount component. This preparation results in a
properly installed part.
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SBOS330E − DECEMBER 2005 − REVISED OCTOBER 2008
www.ti.com
26
DIE
Side View (a)
End V iew (b)
Bottom View (c)
DIE
The thermal pad is electrically isolated from all terminals in the package.
Thermal
Pad
Figure 23. Views of Thermally-Enhanced DCP Package
For a given qJA, the maximum power dissipation is shown
in Figure 24, and is calculated by Equation 3:
PD+ǒTMAX *TA
qJA Ǔ
Where:
PD = maximum power dissipation (W)
TMAX = absolute maximum junction temperature (125°C)
TA = free-ambient air temperature (°C)
qJA = qJC + qCA
qJC = thermal coefficient from junction-to-case (°C/W)
qCA = thermal coefficient from case-to-ambient air (°C/W)
6
5
4
3
2
1
0
Maximum Power Dissipation (W)
−40 −20 0 10040 60 8020
TA, Free−Air Temperature (_C)
Figure 24. Maximum Power Dissipation vs
Free-Air Temperature
(with PowerPAD soldered down)
(3)
PACKAGE OPTION ADDENDUM
www.ti.com 25-Mar-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
BUF20820AIDCPR ACTIVE HTSSOP DCP 38 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR Add to cart
BUF20820AIDCPRE4 ACTIVE HTSSOP DCP 38 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR Add to cart
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BUF20820AIDCPR HTSSOP DCP 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BUF20820AIDCPR HTSSOP DCP 38 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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