256-Position Two-Time Programmable
I2C Digital Potentiometer
AD5170
Rev. 0
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
256-position
TTP (two-time programmable) set-and-forget resistance
setting allows second-chance permanent programming
Unlimited adjustments prior to OTP (one-time
programming) activation
OTP overwrite allows dynamic adjustments with user
defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Fast settling time: tS = 5 µs typ in power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins AD0 and AD1
Single supply 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power, IDD = 6 µA max
Wide operating temperature: –40°C to +125°C
Evaluation board and software are available
Software replaces µC in factory programming applications
APPLICATIONS
Systems calibration
Electronics level setting
Mechanical Trimmers® replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW
The AD5170 is a 256-position, two-time programmable (TTP)
digital potentiometer* that employs fuse link technology to
enable two opportunities at permanently programming the
resistance setting. OTP is a cost-effective alternative to EEMEM
for users who do not need to program the digital potentiometer
setting in memory more than once. This device performs the
same electronic adjustment function as mechanical
potentiometers or variable resistors with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.
FUNCTIONAL BLOCK DIAGRAM
V
DD
G
ND
SDA
SCL
AD0
AD1
W
RDAC
REGISTER
ADDRESS
DECODE
SERIAL INPUT
REGISTER
BA
FUSE
LINKS
12
/
8
04104-0-001
Figure 1
The AD5170 is programmed using a 2-wire, I2C compatible
digital interface. Unlimited adjustments are allowed before
permanently (there are actually two opportunities) setting the
resistance value. During OTP activation, a permanent blow fuse
command freezes the wiper position (analogous to placing
epoxy on a mechanical trimmer).
Unlike traditional OTP digital potentiometers, the AD5170 has
a unique temporary OTP overwrite feature that allows for new
adjustments even after the fuse has been blown. However, the
OTP setting is restored during subsequent power-up conditions.
This feature allows users to treat these digital potentiometers as
volatile potentiometers with a programmable preset.
For applications that program the AD5170 at the factory,
Analog Devices offers device programming software running
on Windows NT®, 2000, and XP® operating systems. This
software effectively replaces any external I2C controllers, thus
enhancing the time-to-market of the user’s systems.
*The terms digital potentiometer, VR, and RDAC are used interchangeably.
AD5170
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Electrical Characteristics—2.5 kΩ ................................................. 3
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4
Timing Characteristics—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions
............................................................................................................. 5
Absolute Maximum Ratings............................................................ 6
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 11
Operation......................................................................................... 12
One-Time Programming (OTP) .............................................. 12
Programming the Variable Resistor and Voltage.................... 12
Programming the Potentiometer Divider............................... 13
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range.......................................... 14
Power-Up Sequence ................................................................... 14
Power Supply Considerations................................................... 14
Layout Considerations............................................................... 15
Evaluation Software/Hardware..................................................... 16
Software Programming ............................................................. 16
I2C Interface .................................................................................... 18
I2C Compatible 2-Wire Serial Bus ........................................... 20
Pin Configuration and Function Descriptions........................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
Revision 0: Initial Version
AD5170
Rev. 0 | Page 3 of 24
ELECTRICAL CHARACTERISTICS—2.5 kΩ
Table 1. VDD = 5 V ± 10% or 3 V ±10%; VA = +VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = No Connect –2 ±0.1 +2 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = No Connect –6 ±0.75 +6 LSB
Nominal Resistor Tolerance3 ∆RAB T
A = 25°C –20 +55 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T VAB = VDD, Wiper = No Connect 35 ppm/°C
RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V 160 200
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to all VRs)
Differential Nonlinearity4 DNL –1.5 ±0.1 +1.5 LSB
Integral Nonlinearity4 INL –2 ±0.6 +2 LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF –10 –2.5 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 2 10 LSB
RESISTOR TERMINALS
Voltage Range5 V
A,VB,VW GND VDD V
Capacitance6 A, B CA, CB f = 1 MHz, Measured to GND,
Code = 0x80
45 pF
Capacitance W CW f = 1 MHz, Measured to GND,
Code = 0x80
60 pF
Shutdown Supply Current7 I
A_SD V
DD = 5.5 V 0.01 1 µA
Common-Mode Leakage ICM V
A = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH V
DD = 5 V 2.4 V
Input Logic Low VIL V
DD = 5 V 0.8 V
Input Logic High VIH V
DD = 3 V 2.1 V
Input Logic Low VIL V
DD = 3 V 0.6 V
Input Current IIL V
IN = 0 V or 5 V ±1 µA
Input Capacitance6 C
IL 5 pF
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
OTP Supply Voltage VDD_OTP T
A = 25°C 6 6.5 V
Supply Current IDD V
IH = 5 V or VIL = 0 V 3.5 6 µA
OTP Supply Current IDD_OTP V
DD_OTP = 6 V, TA = 25°C 100 mA
Power Dissipation8 P
DISS V
IH = 5 V or VIL = 0 V, VDD = 5 V 30 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10%, Code = Midscale ±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS 9
Bandwidth –3 dB BW_2.5K Code = 0x80 4.8 MHz
Total Harmonic Distortion THDW V
A = 1 V rms, VB = 0 V, f = 1 kHz 0.1 %
VW Settling Time tS V
A = 5 V, VB = 0 V, ±1 LSB Error Band 1 µs
Resistor Noise Voltage Density eN_WB R
WB = 1.25 kΩ, RS = 0 3.2 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V.
AD5170
Rev. 0 | Page 4 of 24
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 2. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = No Connect –1 ±0.1 +1 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = No Connect –2.5 ±0.25 +2.5 LSB
Nominal Resistor Tolerance3 ∆RAB T
A = 25°C –20 +20 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T VAB = VDD, Wiper = No Connect 35 ppm/°C
RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V 160 200
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to all VRs)
Differential Nonlinearity4 DNL –1 ±0.1 +1 LSB
Integral Nonlinearity4 INL –1 ±0.3 +1 LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF –2.5 –1 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 1 2.5 LSB
RESISTOR TERMINALS
Voltage Range5 VA,VB,VW GND VDD V
Capacitance6 A, B CA, CB f = 1 MHz, Measured to GND, Code = 0x80 45 pF
Capacitance6 W CW f = 1 MHz, Measured to GND, Code = 0x80 60 pF
Shutdown Supply Current7 I
A_SD V
DD = 5.5 V 0.01 1 µA
Common-Mode Leakage ICM V
A = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH V
DD = 5 V 2.4 V
Input Logic Low VIL V
DD = 5 V 0.8 V
Input Logic High VIH V
DD = 3 V 2.1 V
Input Logic Low VIL V
DD = 3 V 0.6 V
Input Current IIL V
IN = 0 V or 5 V ±1 µA
Input Capacitance6 C
IL 5 pF
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
OTP Supply Voltage8 V
DD_OTP 6 6.5 V
Supply Current IDD V
IH = 5 V or VIL = 0 V 3.5 6 µA
OTP Supply Current9 I
DD_OTP 100 mA
Power Dissipation10 P
DISS V
IH = 5 V or VIL = 0 V, VDD = 5 V 30 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10%, Code = Midscale ±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS11
Bandwidth –3 dB BW RAB = 10 kΩ, Code = 0x80 600 kHz
R
AB = 50 kΩ, Code = 0x80 100 kHz
R
AB = 100 kΩ, Code = 0x80 40 kHz
Total Harmonic Distortion THDW V
A =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ 0.1 %
VW Settling Time
(10 kΩ/50 kΩ/100 kΩ)
tS V
A = 5 V, VB = 0 V, ±1 LSB Error Band 2 µs
Resistor Noise Voltage Density eN_WB R
WB = 5 kΩ, RS = 0 9 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 Different from operating power supply, power supply OTP is used one time only.
9 Different from operating current, supply current for OTP lasts approximately 400 ms for one time only.
10 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
11 All dynamic characteristics use VDD = 5 V.
AD5170
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 3. VDD = 5 V ± 10% or 3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted
Parameter Symbol Conditions Min Typ Max Unit
I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications Apply to All Parts)
SCL Clock Frequency fSCL 400 kHz
tBUF Bus Free Time between STOP and START t1 1.3 µs
tHD;STA Hold Time (Repeated START) t2After this period, the first clock
pulse is generated.
0.6 µs
tLOW Low Period of SCL Clock t3 1.3 µs
tHIGH High Period of SCL Clock t4 0.6 µs
tSU;STA Setup Time for Repeated START Condition t5 0.6 µs
tHD;DAT Data Hold Time2t6 0.9 µs
tSU;DAT Data Setup Time t7 100 ns
tF Fall Time of Both SDA and SCL Signals t8 300 ns
tR Rise Time of Both SDA and SCL Signals t9 300 ns
tSU;STO Setup Time for STOP Condition t10 0.6 µs
1 See timing diagrams for locations of measured values
2 The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
AD5170
Rev. 0 | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25°C, unless otherwise noted
Parameter Value
VDD to GND –0.3 V to +7 V
VA, VB, VW to GND VDD
Terminal Current, Ax–Bx, Ax–Wx, Bx–Wx1
Pulsed ±20 mA
Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance2 θJA: MSOP-10 230°C/W
1 Maximum terminal current is bound by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5170
Rev. 0 | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-0-002
V
DD
= 5.5V
T
A
= 25°C
R
AB
= 10k
V
DD
= 2.7V
Figure 2. R-INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-0-003
TA = 25°C
RAB = 10k
VDD = 2.7V
VDD = 5.5V
Figure 3. R-DNL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE INL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-0-004
RAB = 10k
VDD = 2.7V
TA = –40°C, +25°C, +85°C, +125°C
VDD = 5.5V
TA = –40°C, +25°C, +85°C, +125°C
Figure 4. INL vs. Code vs. Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-0-005
VDD = 2.7V; TA = –40°C, +25°C, +85°C, +125°C
RAB = 10k
Figure 5. DNL vs. Code vs. Temperature
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
POTENTIOMETER MODE INL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-0-006
TA = 25°C
RAB = 10k
VDD = 2.7V
VDD = 5.5V
Figure 6. INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-0-007
T
A
= 25°C
R
AB
= 10k
V
DD
= 2.7V
V
DD
= 5.5V
Figure 7. DNL vs. Code vs. Supply Voltages
AD5170
Rev. 0 | Page 8 of 24
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-0-008
R
AB
= 10k
V
DD
= 2.7V
T
A
= –40°C, +25°C, +85°C, +125°C
V
DD
= 5.5V
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 8. R-INL vs. Code vs. Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-0-009
V
DD
= 2.7V, 5.5V; T
A
= –40°C, +25°C, +85°C, +125°C
R
AB
= 10k
Figure 9. R-DNL vs. Code vs. Temperature
–2.0
–1.5
–1.0
–0.5
0
0.5
FSE, FULL-SCALE ERROR (LSB)
1.0
1.5
2.0
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04104-0-010
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10k
V
DD
= 2.7V, V
A
= 2.7V
Figure 10. Full-Scale Error vs. Temperature
0
0.75
1.50
2.25
3.00
3.75
4.50
ZSE, ZERO-SCALE ERROR (LSB)
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04104-0-011
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10k
V
DD
= 2.7V, V
A
= 2.7V
Figure 11. Zero-Scale Error vs. Temperature
I
DD
, SUPPLY CURRENT (µA)
0.1
1
10
–40 –7 26 59 92 125
TEMPERATURE (°C)
04104-0-012
V
DD
= 5V
V
DD
= 3V
Figure 12. Supply Current vs. Temperature
–20
0
20
40
60
80
100
120
RHEOSTAT MODE TEMPCO (ppm/°C)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-0-013
R
AB
= 10k
V
DD
= 2.7V
T
A
= –40°C TO +85°C, –40°C TO +125°C
V
DD
= 5.5V
T
A
= –40°C TO +85°C, –40°C TO +125°C
Figure 13. Rheostat Mode Tempco ∆RWB/∆T vs. Code
AD5170
Rev. 0 | Page 9 of 24
–30
–20
–10
0
10
20
POTENTIOMETER MODE TEMPCO (ppm/°C)
30
40
50
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-0-014
R
AB
= 10k
V
DD
= 2.7V
T
A
= –40°C TO +85°C, –40°C TO +125°C
V
DD
= 5.5V
T
A
= –40°C TO +85°C, –40°C TO +125°C
Figure 14. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
10k 1M100k 10M
04104-0-015
0x80
0x40
0x20
0x10
0x08
0x04
0x010x02
Figure 15. Gain vs. Frequency vs. Code, RAB = 2.5 k
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04104-0-016
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 16. Gain vs. Frequency vs. Code, RAB = 10 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04104-0-017
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 17. Gain vs. Frequency vs. Code, RAB = 50 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04104-0-018
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 18. Gain vs. Frequency vs. Code, RAB = 100 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
10k1k 100k 1M 10M
04104-0-019
100k
60kHz 50k
120kHz 10k
570kHz
2.5k
2.2MHz
Figure 19. –3 dB Bandwidth @ Code = 0x80
AD5170
Rev. 0 | Page 10 of 24
I
DD
, SUPPLY CURRENT (mA)
0.01
1
0.1
10
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIGITAL INPUT VOLTAGE (V)
04104-0-020
T
A
= 25°C
V
DD
= 2.7V
V
DD
= 5.5V
Figure 20. IDD vs. Input Voltage
04104-0-021
SCL
V
W
Figure 21. Digital Feedthrough
04104-0-025
V
W
Figure 22. Midscale Glitch, Code 0x80 to 0x7F
04104-0-023
SCL
V
W
Figure 23. Large Signal Settling Time
AD5170
Rev. 0 | Page 11 of 24
TEST CIRCUITS
Figure 24 to Figure 29 illustrate the test circuits that define the
test conditions used in the product specification tables.
04104-0-026
V
MS
AW
B
DUT
V+
V+ = V
DD
1LSB = V+/2
N
Figure 24. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
04104-0-027
NO CONNECT
IW
V
MS
AW
B
DUT
Figure 25. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
04104-0-028
V
MS2
V
MS1
V
W
AW
B
DUT
I
W
= V
DD
/R
NOMINAL
R
W
= [V
MS1
– V
MS2
]/I
W
Figure 26. Test Circuit for Wiper Resistance
04104-0-029
V
MS
%
DUT
( )
AW
B
V+ V
DD
%
V
MS
V
DD
V
DD
V
A
V
MS
V+ = V
DD
± 10%
PSRR (dB) = 20 LOG
PSS (%/%) =
Figure 27. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
04104-0-030
+15V
–15V
W
A
2.5V
BV
OUT
OFFSET
GND
DUT
AD8610
V
IN
Figure 28. Test Circuit for Gain vs. Frequency
W
BV
CM
I
CM
A
NC
GND
NC
V
DD
DUT
NC = NO CONNECT
04104-0-032
Figure 29. Test Circuit for Common-Mode Leakage Current
AD5170
Rev. 0 | Page 12 of 24
OPERATION
SDA
SCL A
W
B
FUSES
EN
DAC
REG.
I
2
C INTERFACE
COMPARATOR
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
MUX DECODER
FUSE
REG.
04103-0-026
Figure 30. Detailed Functional Block Diagram
The AD5170 is a 256-position, digitally controlled variable
resistor (VR) that employs fuse link technology to achieve
memory retention of resistance setting.
An internal power-on preset places the wiper at midscale
during power-on. If the OTP function has been activated, the
device powers up at the user-defined permanent setting.
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5170 presets to midscale during
initial power-on. After the wiper is set at the desired position,
the resistance can be permanently set by programming the T bit
high along with the proper coding (see Table 5 and Table 6).
Note that fuse link technology requires 6 V to blow the internal
fuses to achieve a given setting. The user is allowed only one
attempt at blowing the fuses. Once programming is completed,
the power supply voltage must be reduced to the normal
operating range of 2.7 V to 5.5 V.
The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 7). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses have
been blown, all fuse latches are enabled upon subsequent
power-on; therefore, the output corresponds to the stored
setting. Figure 30 shows a detailed functional block diagram.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal
resistance (RAB) of the VR has 256 contact points accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings.
A
W
B
A
W
B
A
W
B
04103-0-027
Figure 31. Rheostat Mode Configuration
Assuming a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
139 Ω (RWB = RAB/256+ 2 × RW = 39 Ω + 2 × 50 Ω) for data
0x01. The third connection is the next tap point, representing
178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
SD BIT
04104-0-034
Figure 32. AD5170 Equivalent RDAC Circuit
AD5170
Rev. 0 | Page 13 of 24
The general equation that determines the digitally programmed
output resistance between W and B is
WABWB RR
D
DR ×+×= 2
128
)( (1)
where D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register, RAB is the end-to-end resistance, and
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB = 10 kΩ and the A terminal is open-
circuited, the output resistance RWB is set for the RDAC latch
codes, as shown in Table 5.
Table 5. Codes and Corresponding RWB Resistance
D (Dec.) RWB (Ω) Output State
255 9,961 Full Scale (RAB – 1 LSB + RW)
128 5,060 Midscale
1 139 1 LSB
0 100 Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance, RWA . When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
WABWA RR
D
DR ×+×= 2
128
256
)( (2)
For RAB = 10 kΩ and the B terminal open-circuited, the
following output resistance RWA is set for the RDAC latch codes,
as shown in Table 6.
Table 6. Codes and Corresponding RWA Resistance
D (Dec.) RWA (Ω) Output State
255 139 Full Scale
128 5,060 Midscale
1 9,961 1 LSB
0 10,060 Zero Scale
Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. Since the resistance element is pro-
cessed using thin film technology, the change in RAB with
temperature has a very low 35 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across AB, WA, and W–B can be at either
polarity.
A
V
I
W
B
V
O
04104-0-035
Figure 33. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to Terminals A and B is
B
A
WV
D
V
D
DV
256
256
256
)(
+= (3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW can be found as
B
AB
WA
A
AB
WB
WV
R
DR
V
R
DR
DV )(
)(
)( += (4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the abso-
lute values. Thus, the temperature drift reduces to 15 ppm/°C.
AD5170
Rev. 0 | Page 14 of 24
ESD PROTECTION
All digital inputs—SDA, SCL, AD0, and AD1— are protected
with a series input resistor and parallel Zener ESD structures, as
shown in Figure 34 and Figure 35.
LOGIC
340
GND
04104-0-037
Figure 34. ESD Protection of Digital Pins
A, B, W
GND
04104-0-038
Figure 35. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5170 V
DD
to GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on Terminals A, B, and W that
exceed V
DD
or GND will be clamped by the internal forward-
biased diodes (see Figure 36).
GND
A
W
B
V
DD
04104-0-039
Figure 36. Maximum Terminal Voltages Set by V
DD
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminals A, B, and W (see Figure 36), it is important to
power V
DD
/GND before applying any voltage to Terminals A, B,
and W. Otherwise, the diode will be forward biased such that
V
DD
is powered unintentionally and may affect the rest of the
user’s circuit. The ideal power-up sequence is GND, V
DD
, the
digital inputs, and then V
A
/V
B
/V
W
. The relative order of
powering V
A
, V
B
, V
W
, and the digital inputs is not important as
long as they are powered after V
DD
/GND.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time pro-
gramming and normal operating voltage supplies are applied to
the same V
DD
terminal of the AD5170. The AD5170 employs
fuse link technology that requires 6 V to blow the internal fuses
to achieve a given setting. The user is allowed only one attempt
at blowing the fuses. Once programming is completed, power
supply voltage must be reduced to the normal operating range
of 2.7 V to 5.5 V. Such dual voltage requirements require
isolation between the supplies. The fuse programming supply
(either an on-board regulator or rack-mount power supply)
must be rated at 6 V and must be able to provide a 100 mA
transient current for 400 ms in order for successful one-time
programming. Once programming is complete, the 6 V supply
must be removed to allow normal operation at 2.7 V to 5.5 V at
regular microamp current levels. Figure 37 shows the simplest
implementation using a jumper. This approach saves one
voltage supply but draws additional current and requires
manual configuration.
VDD
6V
R1 50k
R2
C1
1µFC2
1nF
250k
5V
CONNECT J1 HERE
FOR OTP
CONNECT J1 HERE
AFTER OTP
AD5170
04104-0-049
Figure 37. Power Supply Requirement
An alternate approach in 3.5 V to 5.5 V systems adds a signal
diode between the system supply and the OTP supply for
isolation, as shown in Figure 38.
V
DD
3.5V–5.5V
6V
D1
C1
1µFC2
1nF
APPLY FOR OTP ONLY
AD5170
04104-0-050
Figure 38. Isolate 6 V OTP Supply from 3.5 V to 5.5 V Normal Operating
Supply. The 6 V supply must be removed once OTP is completed.
AD5170
Rev. 0 | Page 15 of 24
V
DD
2.7V
6V
P1
P1=P2=FDV302P, NDS0610
R1
10k
P2 C1
1µFC2
1nF
APPLY FOR OTP ONLY
AD5170
04104-0-051
LAYOUT CONSIDERATIONS
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Note that the digital ground should also be joined remotely to
the analog ground at one point to minimize the ground bounce.
V
DD
GND
V
DD
C1
1µFC2
1nF
AD5170
+
04104-0-040
Figure 39. Isolate 6 V OTP Supply from 2.7 V Normal Operating Supply.
The 6 V supply must be removed once OTP is completed
For users who operate their systems at 2.7 V, use of the
bidirectional low threshold P-Ch MOSFETs is recommended
for the supply’s isolation. As shown in Figure 39, this assumes
that the 2.7 V system voltage is applied first, and that the P1 and
P2 gates are pulled to ground, thus turning on P1 and subse-
quently P2. As a result, VDD of the AD5170 approaches 2.7 V.
When the AD5170 setting is found, the factory tester applies the
6 V to VDD; the 6 V is also applied to the gates of P1 and P2 to
turn them off. The OTP command is executed at this time to
program the AD5170; the 2.7 V source is therefore protected.
Once the OTP is completed, the tester withdraws the 6 V and
the AD5170’s setting is fixed permanently.
Figure 40. Power Supply Bypassing
AD5170 achieves the OTP function through blowing internal
fuses. Users should always apply the 6 V one time program
voltage requirement at the first program command. Failure to
comply with this requirement may lead to the change of fuse
structures, rendering programming inoperable.
AD5170
Rev. 0 | Page 16 of 24
EVALUATION SOFTWARE/HARDWARE
Figure 41. AD5170 Computer Software Interface
There are two ways of controlling the AD5170. Users can either
program the devices with computer software or external I2C
controllers.
SOFTWARE PROGRAMMING
Due to the advantages of the one-time programmable feature,
users may consider programming the device in the factory
before shipping the final product to end-users. ADI offers a
device programming software that can be implemented in the
factory on PCs running Windows 95 or later. As a result,
external controllers are not required, which significantly
reduces development time. The program is an executable file
that does not require any programming languages or user
programming skills. It is easy to set up and to use. Figure 41
shows the software interface. The software can be downloaded
from www.analog.com.
The AD5170 starts at midscale after power-up prior to OTP
programming. To increment or decrement the resistance, the
user may simply move the scrollbars on the left. To write any
specific value, the user should use the bit pattern in the upper
screen and press the Run button. The format of writing data to
the device is shown in Table 7. Once the desired setting is found,
the user may press the Program Permanent button to blow the
internal fuse links.
To read the validation bits and data out from the device, the
user simply presses the Read button. The format of the read bits
is shown in Table 8.
To apply the device programming software in the factory, users
must modify a parallel port cable and configure Pins 2, 3, 15,
and 25 for SDA_write, SCL, SDA_read, and DGND, respectively,
for the control signals (Figure 42). Users should also lay out the
PCB of the AD5170 with SCL and SDA pads, as shown in
Figure 43, such that pogo pins can be inserted for factory
programming.
AD5170
Rev. 0 | Page 17 of 24
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
SCL
R3
100
R2
100
R1
100
SDA
READ
WRITE
04104-0-042
AD5170
B
A
AD0
GND
VDD
W
NC
AD1
SDA
SCL
04104-0-043
Figure 43. Recommended AD5170 PCB Layout. The SCL and SDA pads allow
pogo pins to be inserted so that signals can be communicated through the
parallel port for programming (Figure 42).
Figure 42. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL,
Pin 15 = SDA_read, and Pin 25 = DGND.
AD5170
Rev. 0 | Page 18 of 24
I2C INTERFACE
Table 7. Write Mode
S 0 1 0 1 1 AD1 AD0
W A 2T SD T 0 OW X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
Table 8. Read Mode
S 0 1 0 1 1 AD1 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A E1 E0 X X X X X X A P
Slave Address Byte Instruction Byte Data Byte
S = Start Condition
P = Stop Condition
A = Acknowledge
AD0, AD1 = Package Pin Programmable Address Bits
X = Dont Care
W = Write
R = Read
2T = Second fuse link array for two-time programming. Logic 0
corresponds to first trim. Logic 1 corresponds to second trim.
Note that blowing trim#2 before trim#1 effectively disables
trim#1 and in turn only allows one-time programming.
SD = Shutdown connects wiper to B terminal and open circuits
the A terminal. It does not change the contents of the wiper
register.
T = OTP Programming Bit. Logic 1 programs the wiper
permanently.
OW = Overwrite the fuse setting and program the digital
potentiometer to a different setting. Note that upon power-up,
the digital potentiometer presets to either midscale or fuse
setting depending on whether the fuse link has been blown.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
E1, E0 = OTP Validation Bits.
0, 0 = Ready to Program.
1, 0 = Fatal Error. Some fuses not blown. Do not retry.
Discard this unit.
1, 1 = Programmed Successfully. No further adjustments are
possible.
AD5170
Rev. 0 | Page 19 of 24
04104-0-044
t1
t2t3
t8
t8
t9
t9
t6
t4t7t5
t2
t10
PS S
SCL
SDA
P
Figure 44. I2C Interface Detailed Timing Diagram
04104-0-045
SCL
START BY
MASTER
SDA 01
1
FRAME 1
SLAVE ADDRESS BYTE
0 1 1 AD1 AD0
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5170
R/W A0 SD 0 OW X X X
19
D7 D6 D5 D4 D3
ACK BY
AD5170 FRAME 3
DATA BYTE
19
T
STOP BY
MASTER
9
D2 D1 D0
ACK BY
AD5170
Figure 45. Writing to the RDAC Register
04104-0-046
SCL
START BY
MASTER
SDA 01
1
FRAME 1
SLAVE ADDRESS BYTE
0 1 1 AD1 AD0
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5170
R/W D7 D6 D4 D3 D2 D1 D0
19
E1 E0 X X X
ACK BY
MASTER FRAME 3
DATA BYTE
19
D5
STOP BY
MASTER
9
XXX
NO ACK
BY MASTER
Figure 46. Reading Data from the RDAC Register
AD5170
Rev. 0 | Page 20 of 24
I2C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 45). The
following byte is the slave address byte, which consists of
the slave address followed by an R/W bit (this bit deter-
mines whether data is read from or written to the slave
device). AD0 and AD1 are configurable address bits which
allow up to four devices on one bus (see Table 7).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master will read
from the slave device. If the R/W bit is low, the master will
write to the slave device.
2. In the write mode, the second byte is the instruction byte.
The first bit (MSB), 2T, of the instruction byte is the second
trim enable bit. A logic low selects the first array of fuses
and a logic high selects the second array. This means that
after blowing the fuses with trim#1, the user still has
another chance to blow them again with trim#2. Note that
using trim#2 before trim#1 effectively disables trim#1 and
in turn only allows one-time programming.
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 Ω in rheostat
mode or 0 V in potentiometer mode. It is important to note
that the shutdown operation does not disturb the contents
of the register. When brought out of shutdown, the
previous setting is applied to the RDAC. Also, during
shutdown, new settings can be programmed. When the
part is returned from shutdown, the corresponding VR
setting is applied to the RDAC.
The third MSB, T, is the OTP (one-time programmable)
programming bit. A logic high blows the poly fuses and
programs the resistor setting permanently. For example, if
the user wanted to blow the first array of fuses, the
instruction byte would be 00100XXX. If the user wanted to
blow the second array of fuses, the instruction byte would
be 10100XXX. A logic low of the T bit simply allows the
device to act as a typical volatile digital potentiometer.
The fourth MSB must always be at Logic 0.
The fifth MSB, OW, is an overwrite bit. When raised to a
logic high, OW allows the RDAC setting to be changed
even after the internal fuses have been blown. However
once OW is returned to a logic zero, the position of the
RDAC returns to the setting prior to overwrite. Because
OW is not static, if the device is powered off and on, the
RDAC presets to midscale or to the setting at which the
fuses were blown, depending on whether or not the fuses
have been permanently set already.
The remainder of the bits in the instruction byte are dont
cares (see Figure 45).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see
Figure 44).
3. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference from the write mode, with eight
data bits followed by an acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 46).
Following the data byte, the validation byte contains two
validation bits, E0 and E1. These bits signify the status of
the one-time programming (see Figure 46).
4. After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a STOP
condition (see Figure 45). In read mode, the master issues a
No Acknowledge for the 9th clock pulse (i.e., the SDA line
remains high). The master then brings the SDA line low
before the 10th clock pulse, which goes high to establish a
STOP condition (see Figure 46).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and
instructing the part only once. For example, after the RDAC has
acknowledged its slave address and instruction bytes in the
write mode, the RDAC output updates on each successive byte.
If different instructions are needed, the write/read mode has to
start again with a new slave address, instruction, and data byte.
Similarly, a repeated read function of the RDAC is also allowed.
AD5170
Rev. 0 | Page 21 of 24
SDA
SDA
AD1
AD0
MASTER
SCL
SCL
AD5170
SDA
AD1
AD0
SCL
AD5170
SDA
AD1
AD0
SCL
AD5170
SDA
5V
R
P
R
P
5V
5V
5V
AD1
AD0
SCL
AD5170
04104-0-047
Table 9. Validation Status
E1 E0 Status
0 0 Ready for Programming
1 0 Fatal Error. Some fuses not blown. Do not retry.
Discard this unit.
1 1 Successful. No further programming is possible
Multiple Devices on One Bus
Figure 47 shows four AD5170s on the same serial bus. Each has
a different slave address because the states of their AD0 and
AD1 pins are different. This allows each device on the bus to be
written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully I2C
compatible interface.
Figure 47. Multiple AD5170s on One I2C Bus
AD5170
Rev. 0 | Page 22 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10
9
8
7
1
2
3
4
B
A
AD0
W
NC
AD1
SDAGND
6
5
SCLV
DD
TOP VIEW
AD5170
04104-0-048
Figure 48. Pin Configuration
Table 10. Pin Function Descriptions
Pin Mnemonic Description
1 B B Terminal.
2 A A Terminal.
3 AD0 Programmable Address Bit 0 for Multiple Package Decoding.
4 GND Digital Ground.
5 VDD Positive Power Supply.
6 SCL Serial Clock Input. Positive edge triggered.
7 SDA Serial Data Input/Output.
8 AD1 Programmable Address Bit 1 for Multiple Package Decoding.
9 NC No Connect.
10 W W Terminal.
AD5170
Rev. 0 | Page 23 of 24
OUTLINE DIMENSIONS
0.23
0.08
0.80
0.60
0.40
0.15
0.00 0.27
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5
1
0.50 BSC
3.00 BSC
3.00 BSC
4.90 BSC
PIN 1
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 49. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model RAB (kΩ) Temperature Package Description Package Option Branding
AD5170BRM2.5 2.5 –40°C to +125°C MSOP-10 RM-10 D0Y
AD5170BRM2.5-RL7 2.5 –40°C to +125°C MSOP-10 RM-10 D0Y
AD5170BRM10 10 –40°C to +125°C MSOP-10 RM-10 D0Z
AD5170BRM10-RL7 10 –40°C to +125°C MSOP-10 RM-10 D0Z
AD5170BRM50 50 –40°C to +125°C MSOP-10 RM-10 D0W
AD5170BRM50-RL7 50 –40°C to +125°C MSOP-10 RM-10 D0W
AD5170BRM100 100 –40°C to +125°C MSOP-10 RM-10 D0X
AD5170BRM100-RL7 100 –40°C to +125°C MSOP-10 RM-10 D0X
AD5170EVAL1 Evaluation Board
1 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options
AD5170
Rev. 0 | Page 24 of 24
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04104–0–1/04(0)