COP8SAX Family - National Semiconductor

COP8SAx Family

8-Bit CMOS ROM Based and One-Time Programmable

(OTP) Microcontroller with 1k to 4k Memory, Power On

Reset, and Very Small Packaging

General Description

Note: COP8SAx devices are instruction set and pin com-

patible supersets of the COP800 Family devices, and are

replacements for these in new designs when possible.

The COPSAx Rom based and OTP microcontrollers are

highly integrated COP8™feature core devices, with 1k to 4k

memory and advanced features including low EMI. These

single-chip CMOS devices are suited for low cost applica-

tions requiring a full featured controller, low EMI, and POR.

100%form-fit-function compatible OTP versions are avail-

able with 1k, 2k, and 4k memory, and in a variety of pack-

ages including 28-pin CSP. Erasable windowed versions are

available for use with a range of COP8 software and hard-

ware development tools.

Family features include an 8-bit memory mapped architec-

ture, 10 MHz CKI with 1 µs instruction cycle, one multi-

function 16-bit timer/counter with PWM output,

MICROWIRE/PLUS™serial I/O, two power saving HALT/

IDLE modes, MIWU, idle timer, on-chip R/C oscillator, 12

high current outputs, user selectable options (WATCH-

DOG™, 4 clock/oscillator modes, power-on-reset), low EMI

2.7V to 5.5V operation, and 16/20/28/40/44 pin packages.

Devices included in this datasheet are:

Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature

COP8SAA5 1k ROM 64 12/16/24 16/20/28 DIP/SOIC 0 to +70˚C, -40 to +85˚C, -40

to +125˚C

COP8SAB5 2k ROM 128 16/24 20/28 DIP/SOIC 0 to +70˚C, -40 to +85˚C, -40

to +125˚C

COP8SAC5 4k ROM 128 16/24/36/40 20/28 DIP/SOIC, 28 CSP, 40

DIP, 44 PLCC/QFP 0 to +70˚C, -40 to +85˚C, -40

to +125˚C

COP8SAA7 1k OTP EPROM 64 12/16/24 16/20/28 DIP/SOIC 0 to +70˚C, -40 to +85˚C, -40

to +125˚C

COP8SAB7 2k OTP EPROM 128 16/24 20/28 DIP/SOIC 0 to +70˚C, -40 to +85˚C, -40

to +125˚C

COP8SAC7 4k OTP EPROM 128 16/24 20/28 DIP/SOIC, 28 CSP, 40

DIP, 44 PLCC/QFP 0 to +70˚C, -40 to +85˚C, -40

to +125˚C

COP8SAA7SLB9 1k OTP EPROM 64 24 28 CSP 0 to +70˚C

COP8SAB7SLB9 2k OTP EPROM 128 24 28 CSP 0 to +70˚C

COP8SAC7SLB9 4k OTP EPROM 128 24 28 CSP 0 to +70˚C

COP8SAC7-Q3 4k EPROM 128 16/24/36 20/28/40 DIP Room Temp. Only

COP8SAC7-J3 4k EPROM 128 40 44 PLCC Room Temp. Only

Key Features

nLow cost 8-bit OTP microcontroller

nOTP program space with read/write protection (fully

secured)

nQuiet Design (low radiated emissions)

nMulti-Input Wakeup pins with optional interrupts

(4 to 8 pins)

n8 bytes of user storage space in EPROM

nUser selectable clock options

— Crystal/Resonator options

— Crystal/Resonator option with on-chip bias resistor

— External oscillator

— Internal R/C oscillator

nInternal Power-On Reset—user selectable

nWATCHDOG and Clock Monitor Logic— user selectable

nUp to 12 high current outputs

CPU Features

nVersatile easy to use instruction set

n1 µs instruction cycle time

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

MICROWIRE/PLUS™, COP8™, MICROWIRE™and WATCHDOG™are trademarks of National Semiconductor Corporation.

iceMASTER®is a registered trademark of MetaLink Corporation.

PRELIMINARY

July 1999

COP8SAx Family, 8-Bit CMOS ROM Based and One-Time Programmable (OTP) Microcontroller

with 1k to 4k Memory, Power On Reset, and Very Small Packaging

CPU Features (Continued)

nEight multi-source vectored interrupts servicing

— External interrupt

— Idle Timer T0

— One Timer (with 2 interrupts)

— MICROWIRE/PLUS Serial Interface

— Multi-Input Wake Up

— Software Trap

— Default VIS (default interrupt)

n8-bit Stack Pointer SP (stack in RAM)

nTwo 8-bit Register Indirect Data Memory Pointers

nTrue bit manipulation

nMemory mapped I/O

nBCD arithmetic instructions

Peripheral Features

nMulti-Input Wakeup Logic

nOne 16-bit timer with two 16-bit registers supporting:

— Processor Independent PWM mode

— External Event counter mode

— Input Capture mode

nIdle Timer

nMICROWIRE/PLUS Serial Interface (SPI Compatible)

I/O Features

nSoftware selectable I/O options

— TRI-STATE®Output

— Push-Pull Output

— Weak Pull Up Input

— High Impedance Input

nSchmitt trigger inputs on ports G and L

nUp to 12 high current outputs

nPin efficient (i.e., 40 pins in 44-pin package are devoted

to useful I/O)

Fully Static CMOS Design

nLow current drain (typically <4 µA)

nSingle supply operation: 2.7V to 5.5V

nTwo power saving modes: HALT and IDLE

Temperature Ranges

0˚C to +70˚C, −40˚C to +85˚C, and −40˚C to +125˚C

Development Support

nWindowed packages for DIP and PLCC

nReal time emulation and full program debug offered by

MetaLink Development System

Block Diagram

General Description (Continued)

Key features include an 8-bit memory mapped architecture,

a 16-bit timer/counter with two associated 16-bit registers

supporting three modes (Processor Independent PWM gen-

eration, External Event counter, and Input Capture capabili-

ties), two power saving HALT/IDLE modes with a

multi-sourced wakeup/interrupt capability, on-chip R/C oscil-

lator, high current outputs, user selectable options such as

WATCHDOG, Oscillator configuration, and power-on-reset.

1.1 EMI REDUCTION

The COP8SAx family of devices incorporates circuitry that

guards against electromagnetic interference— an increasing

problem in today’s microcontroller board designs. National’s

DS012838-1

FIGURE 1. COP8SAx Block Diagram

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General Description (Continued) (Continued)

patented EMI reduction technology offers low EMI clock cir-

cuitry, gradual turn-on output drivers (GTOs) and internal I

smoothing filters, to help circumvent many of the EMI issues

influencing embedded control designs. National has

achieved 15 dB–20 dB reduction in EMI transmissions when

designs have incorporated its patented EMI reducing cir-

cuitry.

1.2 ARCHITECTURE

The COP8SAx family is based on a modified Harvard archi-

tecture, which allows data tables to be accessed directly

from program memory. This is very important with modern

microcontroller-based applications, since program memory

is usually ROM or EPROM, while data memory is usually

RAM. Consequently data tables usually need to be con-

tained in ROM or EPROM, so they are not lost when the mi-

crocontroller is powered down. In a modified Harvard archi-

tecture, instruction fetch and memory data transfers can be

overlapped with a two stage pipeline, which allows the next

instruction to be fetched from program memory while the

current instruction is being executed using data memory.

This is not possible with a Von Neumann single-address bus

architecture.

The COP8SAx family supports a software stack scheme that

allows the user to incorporate many subroutine calls. This

capability is important when using High Level Languages.

With a hardware stack, the user is limited to a small fixed

number of stack levels.

1.3 INSTRUCTION SET

In today’s 8-bit microcontroller application arena cost/

performance, flexibility and time to market are several of the

key issues that system designers face in attempting to build

well-engineered products that compete in the marketplace.

Many of these issues can be addressed through the manner

in which a microcontroller’s instruction set handles process-

ing tasks. And that’s why COP8 family offers a unique and

code-efficient instruction set—one that provides the flexibil-

ity, functionality, reduced costs and faster time to market that

today’s microcontroller based products require.

Code efficiency is important because it enables designers to

pack more on-chip functionality into less program memory

space (ROM/OTP). Selecting a microcontroller with less pro-

gram memory size translates into lower system costs, and

the added security of knowing that more code can be packed

into the available program memory space.

1.3.1 Key Instruction Set Features

The COP8SAx family incorporates a unique combination of

instruction set features, which provide designers with opti-

mum code efficiency and program memory utilization.

Single Byte/Single Cycle Code Execution

The efficiency is due to the fact that the majority of instruc-

tions are of the single byte variety, resulting in minimum pro-

gram space. Because compact code does not occupy a sub-

stantial amount of program memory space, designers can

integrate additional features and functionality into the micro-

controller program memory space.Also, the majority instruc-

tions executed by the device are single cycle, resulting in

minimum program execution time. In fact, 77%of the instruc-

tions are single byte single cycle, providing greater code and

I/O efficiency, and faster code execution.

1.3.2 Many Single-Byte, Multifunction Instructions

The COP8SAx instruction set utilizes many single-byte, mul-

tifunction instructions. This enables a single instruction to ac-

complish multiple functions, such as DRSZ, DCOR, JID, and

LOAD/EXCHANGE instructions with post-incrementing and

post-decrementing, to name just a few examples. In many

cases, the instruction set can simultaneously execute as

many as three functions with the same single-byte instruc-

tion.

JID: (Jump Indirect); Single byte instruction; decodes exter-

nal events and jumps to corresponding service routines

(analogous to “DO CASE” statements in higher level lan-

guages).

LAID: (Load Accumulator-Indirect); Single byte look up table

instruction provides efficient data path from the program

memory to the CPU. This instruction can be used for table

lookup and to read the entire program memory for checksum

calculations.

RETSK: (Return Skip); Single byte instruction allows return

from subroutine and skips next instruction. Decision to

branch can be made in the subroutine itself, saving code.

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General Description (Continued) (Continued)

AUTOINC/DEC: (Auto-Increment/Auto-Decrement); These

instructions use the two memory pointers B and X to effi-

ciently process a block of data (analogous to “FOR NEXT” in

higher level languages).

1.3.3 Bit-Level Control

Bit-level control over many of the microcontroller’s I/O ports

provides a flexible means to ease layout concerns and save

board space. All members of the COP8 family provide the

ability to set, reset and test any individual bit in the data

memory address space, including memory-mapped I/O ports

and associated registers. Three memory-mapped pointers

handle register indirect addressing and software stack

pointer functions. The memory data pointers allow the option

of post-incrementing or post-decrementing with the data

movement instructions (LOAD/EXCHANGE). And 15

memory-maped registers allow designers to optimize the

precise implementation of certain specific instructions.

1.4 PACKAGING/PIN EFFICIENCY

Real estate and board configuration considerations demand

maximum space and pin efficiency, particularly given today’s

high integration and small product form factors. Microcontrol-

ler users try to avoid using large packages to get the I/O

needed. Large packages take valuable board space and in-

creases device cost, two trade-offs that microcontroller de-

signs can ill afford.

The COP8 family offers a wide range of packages and do not

waste pins: up to 90.9%(or 40 pins in the 44-pin package)

are devoted to useful I/O.

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Connection Diagrams

DS012838-2

Top View

DS012838-3

Top View

DS012838-4

Top View

DS012838-39

Top View

DS012838-5

Top View

DS012838-6

Top View

FIGURE 2. Connection Diagrams

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Ordering Information

1k EPROM 2k EPROM 4k EPROM 4k EPROM

Windowed

Device

Temperature Order Number Package Order Number Package Order Number Package Order Number Package

0˚C to +70˚C COP8SAA716M9 16M

COP8SAA720M9 20M COP8SAB720M9 20M COP8SAC720M9 20M

COP8SAA728M9 28M COP8SAB728M9 28M COP8SAC728M9 28M

COP8SAA716N9 16N

COP8SAA720N9 20N COP8SAB720N9 20N COP8SAC720N9 20N COP8SAC720Q3 20Q

COP8SAA728N9 28N COP8SAB728N9 28N COP8SAC728N9 28N COP8SAC728Q3 28Q

COP8SAC740N9 40N COP8SAC740Q3 40Q

COP8SAC744V9 44V COP8SAC744J3 44J

−40˚C to +85˚C COP8SAA716M8 16M

COP8SAA720M8 20M COP8SAB720M8 20M COP8SAC720M8 20M

COP8SAA728M8 28M COP8SAB728M8 28M COP8SAC728M8 28M

COP8SAA716N8 16N

COP8SAA720N8 20N COP8SAB720N8 20N COP8SAC720N8 20N

COP8SAA728N8 28N COP8SAB728N8 28N COP8SAC728N8 28N

COP8SAC740N8 40N

COP8SAC744V8 44V

COP8SAA7SLB8 SLB COP8SAB7SLB8 SLB COP8SAC7SLB8 SLB

−40˚C to

+125˚C COP8SAC720M7 20M

COP8SAC728M7 28M

COP8SAC720N7 20N

COP8SAC728N7 28N

COP8SAC740N7 40N

COP8SAC744V7 44V

DS012838-8

FIGURE 3. Part Numbering Scheme

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4.0 Electrical Characteristics

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)7V

Voltage at Any Pin −0.6V to V

+0.6V

ESD Protection Level 2 kV

(Human Body Model)

Total Current into V

Pin (Source) 80 mA

Total Current out of GND Pin (Sink) 100 mA

Storage Temperature Range −65˚C to +140˚C

Note 1:

Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

DC Electrical Characteristics

0˚C ≤T

≤+70˚C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Operating Voltage (Note 8) 2.7 5.5 V

Power Supply Rise Time from 0.0V

(On-Chip Power-On Reset Selected) 10 ns 50 ms

Start Voltage to Guarantee POR 0.25 V

Power Supply Ripple (Note 3) Peak-to-Peak 0.1 V

Supply Current (Note 4)

CKI =10 MHz V

=5.5V, t

=1µs 6 mA

CKI =4 MHz V

=4.5V, t

=2.5 µs 2.1 mA

HALT Current (Note 5) —WATCHDOG Disabled V

=5.5V, CKI =0 MHz <48 µA

IDLE Current (Note 4)

CKI =10 MHz V

=5.5V, t

=1 µs 1.5 mA

CKI =4 MHz V

=4.5V, t

=2.5 µs 0.8 mA

Input Levels (V

)

RESET

Logic High 0.8 V

Logic Low 0.2 V

CKI, All Other Inputs

Logic High 0.7 V

Logic Low 0.2 V

Value of the Internal Bias Resistor 0.5 1.0 2.0 MΩ

for the Crystal/Resonator Oscillator

CKI Resistance to V

or GND when R/C V

=5.5V 5 8 11 kΩ

Oscillator is Selected

Hi-Z Input Leakage (same as TRI-STATE output) V

=5.5V −2 +2 µA

Input Pullup Current V

=5.5V, V

=0V −40 −250 µA

G and L Port Input Hysteresis 0.25 V

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DC Electrical Characteristics (Continued)

0˚C ≤T

≤+70˚C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Output Current Levels

D Outputs

Source V

=4.5V, V

=3.3V −0.4 mA

=2.7V, V

=1.8V −0.2 mA

Sink V

=4.5V, V

=1.0V 10 mA

=2.7V, V

=0.4V 2 mA

L Port

Source (Weak Pull-Up) V

=4.5V, V

=2.7V −10 −110 µA

=2.7V, V

=1.8V −2.5 −33 µA

Source (Push-Pull Mode) V

=4.5V, V

=3.3V −0.4 mA

=2.7V, V

=1.8V −0.2 mA

Sink (L0–L3, Push-Pull Mode) V

=4.5V, V

=1.0V 10 mA

=2.7V, V

=0.4V 2 mA

Sink (L4–L7, Push-Pull Mode) V

=4.5V, V

=0.4V 1.6 mA

=2.7V, V

=0.4V 0.7 mA

All Others

Source (Weak Pull-Up Mode) V

=4.5V, V

=2.7V −10 −110 µA

=2.7V, V

=1.8V −2.5 −33 µA

Source (Push-Pull Mode) V

=4.5V, V

=3.3V −0.4 mA

=2.7V, V

=1.8V −0.2 mA

Sink (Push-Pull Mode) V

=4.5V, V

=0.4V 1.6 mA

=2.7V, V

=0.4V 0.7 mA

Allowable Sink Current per Pin (Note 8)

D Outputs and L0 to L3 15 mA

All Others 3mA

Maximum Input Current without Latchup ±200 mA

(Note 6)

RAM Retention Voltage, Vr 2.0 V

Rise Time from a V

≥2.0V (Note 9) 12 µs

Input Capacitance (Note 8) 7 pF

Load Capacitance on D2 (Note 8) 1000 pF

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AC Electrical Characteristics

0˚C ≤T

≤+70˚C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (t

)

Crystal/Resonator, External 4.5V ≤V

≤5.5V 1.0 DC µs

2.7V ≤V

<4.5V 2.0 DC µs

Internal R/C Oscillator 4.5V ≤V

≤5.5V 2.0 µs

2.7V ≤V

<4.5V TBD µs

R/C Oscillator Frequency Variation 4.5V ≤V

≤5.5V ±35 %

(Note 8) 2.7V ≤V

<4.5V TBD %

External CKI Clock Duty Cycle (Note 8) fr =Max 45 55 %

Rise Time (Note 8) fr =10 MHz Ext Clock 12 ns

Fall Time (Note 8) fr =10 MHz Ext Clock 8 ns

Inputs

SETUP

4.5V ≤V

≤5.5V 200 ns

2.7V ≤V

<4.5V 500 ns

HOLD

4.5V ≤V

≤5.5V 60 ns

2.7V ≤V

<4.5V 150 ns

Output Propagation Delay (Note 7) R

=2.2k, C

=100 pF

PD1

PD0

SO, SK 4.5V ≤V

≤5.5V 0.7 µs

2.7V ≤V

<4.5V 1.75 µs

All Others 4.5V ≤V

≤5.5V 1.0 µs

2.7V ≤V

<4.5V 2.5 µs

MICROWIRE Setup Time (t

UWS

) (Note 7) 20 ns

MICROWIRE Hold Time (t

UWH

) (Note 7) 56 ns

MICROWIRE Output Propagation Delay (t

UPD

) 220 ns

MICROWIRE Maximum Shift Clock

Master Mode 500 kHz

Slave Mode 1 MHz

Input Pulse Width (Note 7)

Interrupt Input High Time 1 t

Interrupt Input Low Time 1 t

Timer 1 Input High Time 1 t

Timer 1 Input Low Time 1 t

Reset Pulse Width 1 µs

Note 2: tC=Instruction cycle time (Clock input frequency divided by 10).

Note 3: Maximum rate of voltage change must be <0.5 V/ms.

Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC

and outputs driven low but not connected to a load.

Note 5: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal

or external configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5 pro-

grammed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; WATCHDOG and clock monitor disabled.

Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.

Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages >VCC and the pins will have sink current to VCC when

biased at voltages >VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω(typical). These two

pins will not latch up. The voltage at the pins must be limited to <14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-

cludes ESD transients.

Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 8: Parameter characterized but not tested.

Note 9: Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.

www.national.com9

Absolute Maximum Ratings (Note 10)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)7V

Voltage at Any Pin −0.6V to V

+0.6V

ESD Protection Level 2 kV

(Human Body Model)

Total Current into V

Pin (Source) 80 mA

Total Current out of GND Pin (Sink) 100 mA

Storage Temperature Range −65˚C to +140˚C

Note 10:

Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

DC Electrical Characteristics

−40˚C ≤T

≤+85˚C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Operating Voltage 2.7 5.5 V

Power Supply Rise Time from 0.0V (Note 17)

(On-Chip Power-On Reset Selected) 10 ns 50 ms

Start Voltage to Guarantee POR 0.25 V

Power Supply Ripple (Note 12) Peak-to-Peak 0.1 V

Supply Current (Note 13)

CKI =10 MHz V

=5.5V, t

=1 µs 6.0 mA

HALT Current (Note 14) —WATCHDOG Disabled V

=5.5V, CKI =0 MHz <4 10.0 µA

IDLE Current (Note 13)

CKI =10 MHz V

=5.5V, t

=1 µs 1.5 mA

Input Levels (V

)

RESET

Logic High 0.8 V

Logic Low 0.2 V

CKI, All Other Inputs

Logic High 0.7 V

Logic Low 0.2 V

Value of the Internal Bias Resistor 0.5 1.0 2.0 MΩ

for the Crystal/Resonator Oscillator

CKI Resistance to V

or GND when R/C V

=5.5V 5 8 11 kΩ

Oscillator is Selected

Hi-Z Input Leakage (same as TRI-STATE output) V

=5.5V −2 +2 µA

Input Pullup Current V

=5.5V, V

=0V −40 −250 µA

G and L Port Input Hysteresis 0.25 V

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DC Electrical Characteristics (Continued)

−40˚C ≤T

≤+85˚C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Output Current Levels

D Outputs

Source V

=4.5V, V

=3.3V −0.4 mA

=2.7V, V

=1.8V −0.2 mA

Sink V

=4.5V, V

=1.0V 10 mA

=2.7V, V

=0.4V 2 mA

L Port

Source (Weak Pull-Up) V

=4.5V, V

=2.7V −10.0 −110 µA

=2.7V, V

=1.8V −2.5 −33 µA

Source (Push-Pull Mode) V

=4.5V, V

=3.3V −0.4 mA

=2.7V, V

=1.8V −0.2 mA

Sink (L0–L3, Push-Pull Mode) V

=4.5V, V

=1.0V 10.0 mA

=2.7V, V

=0.4V 2 mA

Sink (L4–L7, Push-Pull Mode) V

=4.5V, V

=0.4V 1.6 mA

=2.7V, V

=0.4V 0.7 mA

All Others

Source (Weak Pull-Up Mode) V

=4.5V, V

=2.7V −10.0 −110 µA

=2.7V, V

=1.8V −2.5 −33 µA

Source (Push-Pull Mode) V

=4.5V, V

=3.3V −0.4 mA

=2.7V, V

=1.8V −0.2 mA

Sink (Push-Pull Mode) V

=4.5V, V

=0.4V 1.6 mA

=2.7V, V

=0.4V 0.7 mA

Allowable Sink Current per Pin (Note 17)

D Outputs and L0 to L3 15 mA

All Others 3mA

Maximum Input Current without Latchup (Note 15) ±200 mA

RAM Retention Voltage, Vr 2.0 V

Rise Time from a V

≥2.0V (Note 18) 12 µs

Input Capacitance (Note 17) 7 pF

Load Capacitance on D2 (Note 17) 1000 pF

AC Electrical Characteristics

−40˚C ≤T

≤+85˚C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (t

)

Crystal/Resonator, External 4.5V ≤V

≤5.5V 1.0 DC µs

2.7V ≤V

<4.5V 2.0 DC µs

Internal R/C Oscillator 4.5V ≤V

≤5.5V 2.0 µs

2.7V ≤V

<4.5V TBD µs

R/C Oscillator Frequency Variation 4.5V ≤V

≤5.5V ±35 %

(Note 17) 2.7V ≤V

<4.5V TBD %

External CKI Clock Duty Cycle (Note 17) fr =Max 45 55 %

Rise Time (Note 17) fr =10 MHz Ext Clock 12 ns

Fall Time (Note 17) fr =10 MHz Ext Clock 8 ns

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AC Electrical Characteristics (Continued)

−40˚C ≤T

≤+85˚C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Inputs

SETUP

4.5V ≤V

≤5.5V 200 ns

2.7V ≤V

<4.5V 500 ns

HOLD

4.5V ≤V

≤5.5V 60 ns

2.7V ≤V

<4.5V 150 ns

Output Propagation Delay (Note 16) R

=2.2k, C

=100 pF

PD1

PD0

SO, SK 4.5V ≤V

≤5.5V 0.7 µs

2.7V ≤V

<4.5V 1.75 µs

All Others 4.5V ≤V

≤5.5V 1.0 µs

2.7V ≤V

<4.5V 2.5 µs

MICROWIRE Setup Time (t

UWS

) (Note 16) 20 ns

MICROWIRE Hold Time (t

UWH

) (Note 16) 56 ns

MICROWIRE Output Propagation Delay (t

UPD

) 220 ns

MICROWIRE Maximum Shift Clock

Master Mode 500 kHz

Slave Mode 1 MHz

Input Pulse Width (Note 17)

Interrupt Input High Time 1 t

Interrupt Input Low Time 1 t

Timer 1 Input High Time 1 t

Timer 1 Input Low Time 1 t

Reset Pulse Width 1 µs

Note 11: tC=Instruction cycle time (Clock input frequency divided by 10).

Note 12: Maximum rate of voltage change must be <0.5 V/ms.

Note 13: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC

and outputs driven low but not connected to a load.

Note 14: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal

or external configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5 pro-

grammed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers

to HALT mode entered via setting bit 7 of the G Port data register.

Note 15: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages >VCC and the pins will have sink current to VCC when

biased at voltages >VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω(typical). These two

pins will not latch up. The voltage at the pins must be limited to <14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes

ESD transients.

Note 16: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 17: Parameter characterized but not tested.

Note 18: Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.

DS012838-9

FIGURE 4. MICROWIRE/PLUS Timing

www.national.com 12

Absolute Maximum Ratings (Note 19)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)7V

Voltage at Any Pin −0.6V to V

+0.6V

ESD Protection Level 2 kV

(Human Body Model)

Total Current into V

Pin (Source) 80 mA

Total Current out of GND Pin (Sink) 100 mA

Storage Temperature Range −65˚C to +140˚C

Note 19:

Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

DC Electrical Characteristics

−40˚C ≤T

≤+125˚C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Operating Voltage 4.5 5.5 V

Power Supply Rise Time from 0.0V (Note 17)

(On-Chip Power-On Reset Selected) 10 ns 50 ms

Start Voltage to Guarantee POR 0.25 V

Power Supply Ripple (Note 12) Peak-to-Peak 0.1 V

Supply Current (Note 13)

CKI =10 MHz V

=5.5V, t

=1 µs 6.0 mA

HALT Current (Note 14) —WATCHDOG

Disabled V

=5.5V, CKI =0 MHz <10 30 µA

IDLE Current (Note 13)

CKI =10 MHz V

=5.5V, t

=1 µs 1.5 mA

Input Levels (V

)

RESET

Logic High 0.8 V

Logic Low 0.2 V

CKI, All Other Inputs

Logic High 0.7 V

Logic Low 0.2 V

Value of the Internal Bias Resistor 0.5 1.0 2.0 MΩ

for the Crystal/Resonator Oscillator

CKI Resistance to V

or GND when R/C V

=5.5V 5 8 11 kΩ

Oscillator is Selected

Hi-Z Input Leakage V

=5.5V −5 +5 µA

Input Pullup Current V

=5.5V, V

=0V −35 −400 µA

G and L Port Input Hysteresis 0.25 V

Output Current Levels

D Outputs

Source V

=4.5V, V

=3.3V −0.4 mA

Sink V

=4.5V, V

=1.0V 9 mA

L Port

Source (Weak Pull-Up) V

=4.5V, V

=2.7V −9 −140 µA

Source (Push-Pull Mode) V

=4.5V, V

=3.3V −0.4 mA

Sink (L0–L3, Push-Pull Mode) V

=4.5V, V

=1.0V 9 mA

Sink (L4–L7, Push-Pull Mode) V

=4.5V, V

=0.4V 1.4 mA

All Others

Source (Weak Pull-Up Mode) V

=4.5V, V

=2.7V −9 −140 µA

Source (Push-Pull Mode) V

=4.5V, V

=3.3V −0.4 mA

Sink (Push-Pull Mode) V

=4.5V, V

=0.4V 1.4 mA

TRI-STATE Leakage V

=5.5V −5 +5 µA

www.national.com13

DC Electrical Characteristics (Continued)

−40˚C ≤T

≤+125˚C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Allowable Sink Current per Pin (Note 17)

D Outputs and L0 to L3 15 mA

All Others 3mA

Maximum Input Current without Latchup Room Temp ±200 mA

(Note 15)

RAM Retention Voltage, Vr 2.0 V

Rise Time from a V

≥2.0V (Note 18) 12 µs

Input Capacitance (Note 17) 7 pF

Load Capacitance on D2 (Note 17) 1000 pF

AC Electrical Characteristics

−40˚C ≤T

≤+125˚C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (t

)

Crystal/Resonator, External 4.5V ≤V

≤5.5V 1.0 DC µs

Internal R/C Oscillator 4.5V ≤V

≤5.5V 2.0 DC µs

R/C Oscillator Frequency Variation 4.5V ≤V

≤5.5V TBD %

(Note 6)

External CKI Clock Duty Cycle (Note 6) fr =Max 45 55 %

Rise Time (Note 6) fr =10 MHz Ext Clock 12 ns

Fall Time (Note 6) fr =10 MHz Ext Clock 8 ns

Inputs

SETUP

4.5V ≤V

≤5.5V 200 ns

HOLD

4.5V ≤V

≤5.5V 60 ns

Output Propagation Delay (Note 5) R

=2.2k, C

=100 pF

PD1

PD0

SO, SK 4.5V ≤V

≤5.5V 0.7 µs

All Others 4.5V ≤V

≤5.5V 1.0 µs

MICROWIRE Setup Time (t

UWS

) (Note 5) 20 ns

MICROWIRE Hold Time (t

UWH

) (Note 5) 56 ns

MICROWIRE Output Propagation Delay (t

UPD

) 220 ns

MICROWIRE Maximum Shift Clock

Master Mode 500 kHz

Slave Mode 1 MHz

Input Pulse Width (Note 6)

Interrupt Input High Time 1 t

Interrupt Input Low Time 1 t

Timer 1, 2, 3 Input High Time 1 t

Timer 1, 2, 3 Input Low Time 1 t

Reset Pulse Width 1 µs

www.national.com 14

5.0 Pin Descriptions

COP8SAx I/O structure minimizes external component re-

quirements. Software-switchable I/O enables designers to

reconfigure the microcontroller’s I/O functions with a

single instruction. Each individual I/O pin can be indepen-

dently configured as an output pin low, an output high, an

input with high impedance or an input with a weak pull-up

device.A typical example is the use of I/O pins as the key-

board matrix input lines. The input lines can be pro-

grammed with internal weak pull-ups so that the input

lines read logic high when the keys are all up. With a key

closure, the corresponding input line will read a logic zero

since the weak pull-up can easily be overdriven. When the

key is released, the internal weak pullup will pull the input

line back to logic high. This flexibility eliminates the need

for external pull-up resistors. The High current options are

available for driving LEDs, motors and speakers. This

flexibility helps to ensure a cleaner design, with less exter-

nal components and lower costs. Below is the general de-

scription of all available pins.

and GND are the power supply pins. All V

and

GND pins must be connected.

CKI is the clock input. This can come from the Internal

R/C oscillator, external, or a crystal oscillator (in conjunc-

tion with CKO). See Oscillator Description section.

RESET is the master reset input. See Reset description

section.

The device contains four bidirectional 8-bit I/O ports (C, G,

L and F), where each individual bit may be independently

configured as an input (Schmitt trigger inputs on ports L

and G), output or TRI-STATE under program control.

Three data memory address locations are allocated for

each of these I/O ports. Each I/O port has two associated

8-bit memory mapped registers, the CONFIGURATION

address is also reserved for the input pins of each I/O

port. (See the memory map for the various addresses as-

sociated with the I/O ports.)

Figure 5

shows the I/O port

configurations. The DATA and CONFIGURATION regis-

ters allow for each port bit to be individually configured un-

der software control as shown below:

CONFIGURATION DATA Port Set-Up

0 0 Hi-Z Input

(TRI-STATE Output)

0 1 Input with Weak Pull-Up

1 0 Push-Pull Zero Output

1 1 Push-Pull One Output

Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on

the inputs.

Port L supports the Multi-Input Wake Up feature on all eight

pins. The 16-pin device does not have a full complement of

Port L pins. The unavailable pins are not terminated. A read

operation these unterminated pins are not terminated.A read

operation these unterminated pins will return unpredictable

values. To minimize current drain, the unavailable pins must

be programmed as outputs.

Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O

ports. Pin G6 is always a general purpose Hi-Z input.All pins

have Schmitt Triggers on their inputs. Pin G1 serves as the

dedicated WDOUT WATCHDOG output with weak pullup

if WATCHDOG feature is selected by the ECON register.

The pin is a general purpose I/O if WATCHDOG feature is

not selected. If WATCHDOG feature is selected, bit 1 of the

Port G configuration and data register does not have any ef-

fect on Pin G1 setup. Pin G7 is either input or output depend-

ing on the oscillator option selected. With the crystal oscilla-

tor option selected, G7 serves as the dedicated output pin for

the CKO clock output. With the internal R/C or the external

oscillator option selected, G7 serves as a general purpose

Hi-Z input pin and is also used to bring the device out of

HALT mode with a low to high transition on G7. There are

two registers associated with Port G, a data register and a

configuration register. Using these registers, each of the 5

I/O pins (G0, G2–G5) can be individually configured under

software control.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin (crystal clock option) or general purpose in-

put (R/C or external clock option), the associated bits in the

data and configuration registers for G6 and G7 are used for

special purpose functions as outlined below. Reading the G6

and G7 data bits will return zeroes.

The device will be placed in the HALT mode by writing a “1”

to bit 7 of the Port G Data Register. Similarly the device will

be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register en-

ables the MICROWIRE/PLUS to operate with the alternate

phase of the SK clock. The G7 configuration bit, if set high,

enables the clock start up delay after HALT when the R/C

clock configuration is used.

Config. Reg. Data Reg.

G7 CLKDLY HALT

G6 Alternate SK IDLE

Port G has the following alternate features:

G6 SI (MICROWIRE Serial Data Input)

G5 SK (MICROWIRE Serial Clock)

G4 SO (MICROWIRE Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G0 INTR (External Interrupt Input)

Port G has the following dedicated functions:

G7 CKO Oscillator dedicated output or general purpose in-

put

G1 WDOUT WATCHDOG and/or CLock Monitor if WATCH-

DOG enabled, otherwise it is a general purpose I/O

Port C is an 8-bit I/O port. The 40-pin device does not have

a full complement of Port C pins. The unavailable pins are

not terminated. A read operation on these unterminated pins

will return unpredictable values. Only the COP8SAC7 device

contains Port C. The 20/28 pin devices do not offer Port C.

On these devices, the associated Port C Data and Configu-

ration registers should not be used.

Port F is an 8-bit I/O port. The 28-pin device does not have

a full complement of Port F pins. The unavailable pins are

not terminated. A read operation on these unterminated pins

will return unpredictable values.

www.national.com15

5.0 Pin Descriptions (Continued)

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more D port outputs (ex-

cept D2) together in order to get a higher drive.

Note: Care must be exercised with the D2 pin operation. At RESET, the ex-

ternal loads on this pin must ensure that the output voltages stay

above 0.7 VCC to prevent the chip from entering special modes. Also

keep the external loading on D2 to less than 1000 pF.

6.0 Functional Description

The architecture of the device is a modified Harvard archi-

tecture. With the Harvard architecture, the program memory

EPROM is separated from the data store memory (RAM).

Both EPROM and RAM have their own separate addressing

space with separate address buses. The architecture,

though based on the Harvard architecture, permits transfer

of data from EPROM to RAM.

6.1 CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t

) cycle time.

There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). With reset the SP is initialized to

RAM address 02F Hex (devices with 64 bytes of RAM), or

initialized to RAM address 06F Hex (devices with 128 bytes

of RAM).

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

6.2 PROGRAM MEMORY

The program memory consists of 1024, 2048, or 4096 bytes

of EPROM or ROM.

Table 1

shows the program memory

sizes for the different devices. These bytes may hold pro-

gram instructions or constant data (data tables for the LAID

instruction, jump vectors for the JID instruction, and interrupt

vectors for the VIS instruction). The program memory is ad-

dressed by the 15-bit program counter (PC). All interrupts in

the device vector to program memory location 0FF Hex. The

contents of the program memory read 00 Hex in the erased

state.

6.3 DATA MEMORY

The data memory address space includes the on-chip RAM

and data registers, the I/O registers (Configuration, Data and

Pin), the control registers, the MICROWIRE/PLUS SIO shift

with the timers (with the exception of the IDLE timer). Data

memory is addressed directly by the instruction or indirectly

by the B, X and SP pointers.

The data memory consists of 64 or 128 bytes of RAM.

Table

shows the data memory sizes for the different devices. Fif-

teen bytes of RAM are mapped as “registers” at addresses

0F0 to 0FE Hex. These registers can be loaded immediately,

and also decremented and tested with the DRSZ (decrement

registers X, SP and B are memory mapped into this space at

address locations 0FC to 0FE Hex respectively, with the

other registers (except 0FF) being available for general us-

age.Address location 0FF is reserved for future RAM expan-

sion. If compatibility with future devices (with more RAM) is

not desired, this location can be used as a general purpose

RAM location.

DS012838-10

FIGURE 5. I/O Port Configurations

DS012838-12

FIGURE 6. I/O Port Configurations— Output Mode

DS012838-11

FIGURE 7. I/O Port Configurations— Input Mode

www.national.com 16

6.0 Functional Description (Continued)

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore, I/O bits and register bits can be

directly and individually set, reset and tested. The accumula-

tor (A) bits can also be directly and individually tested.

RAM contents are undefined upon power-up.

TABLE 1. Program/Data Memory Sizes

Program Data User

Device Memory Memory Storage

(Bytes) (Bytes) (Bytes)

COP8SAA7 1024 64 8

COP8SAB7 2048 128 8

COP8SAC7 4096 128 8

6.4 ECON (CONFIGURATION) REGISTER

The ECON register is used to configure the user selectable

clock, security, power-on reset, WATCHDOG, and HALT op-

tions. The register can be programmed and read only in

EPROM programming mode. Therefore, the register should

be programmed at the same time as the program memory.

The contents of the ECON register shipped from the factory

read 00 Hex (windowed device), 80 Hex (OTP device) or as

specified by the customer (ROM device).

The format of the ECON register is as follows:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X POR SECURITY CKI 2 CKI 1 WATCH Reserved HALT

DOG

Bit 7 =x This is for factory test. The polarity is al-

ways 0.

Bit 6 =1 Power-on reset enabled.

=0 Power-on reset disabled.

Bit 5 =1 Security enabled. EPROM read and write

are not allowed.

=0 Security disabled. EPROM read and write

are allowed.

Bits 4, 3 =0, 0 External CKI option selected. G7 is avail-

able as a HALT restart and/or general pur-

pose input. CKI is clock input.

=0, 1 R/C oscillator option selected. G7 is avail-

able as a HALT restart and/or general pur-

pose input. CKI clock input. Internal R/C

components are supplied for maximum

R/C frequency.

=1, 0 Crystal oscillator with on-chip crystal bias

resistor disabled. G7 (CKO) is the clock

generator output to crystal/resonator.

=1, 1 Crystal oscillator with on-chip crystal bias

resistor enabled. G7 (CKO) is the clock

generator output to crystal/resonator.

Bit 2 =1 WATCHDOG feature disabled. G1 is a

general purpose I/O.

=0 WATCHDOG feature enabled. G1 pin is

WATCHDOG output with waek pullup.

Bit 1 =Reserved.

Bit 0 =1 HALT mode disabled.

=0 HALT mode enabled.

6.5 USER STORAGE SPACE IN EPROM

In addition to the ECON register, there are 8 bytes of

EPROM available for “user information”. ECON and these 8

bytes are outside of the code area and are not protected by

the security bit of the ECON register. Even when security is

set, information in the 8-byte USER area is both read and

write enabled allowing the user to read from and write into

the area at all times while still protecting the code from unau-

thorized access.

Both ECON and USER area, 9 bytes total, are outside of the

normal address range of the EPROM and can not be ac-

cessed by the executing software. This allows for the stor-

age of non-secured information. Typical uses are for storage

of serial numbers, data codes, version numbers, copyright

information, lot numbers, etc.

The COP8 assembler defines a special ROM section type,

CONF, into which the ECON and USER data may be coded.

Both ECON and User Data are programmed automatically

by programmers that are certified by National.

The following examples illustrate the declaration of ECON

and the User information.

Syntax:

[label:] .sect econ, conf

.db value ;1 byte,

;configures options

.db

.endsect<user information>

;up to 8 bytes

Example: The following sets a value in the ECON register

and User Identification for a COP8SAC728M7. The ECON

bit values shown select options: Power-on enabled, Security

disabled, Crystal oscillator with on-chip bias disabled,

WATCHDOG enabled and HALT mode enabled.

.chip 8SAC

.sect econ, conf

.db 0x55 ;por, extal, wd, halt

.db 'my v1.00' ;user data declaration

.endsect

...

.end start

Note: All programmers certified for programming this family of parts will sup-

port programming of the CONFiguration section. Please contact Na-

tional or your device programmer supplier for more information.

6.6 OTP SECURITY

The device has a security feature that, when enabled, pre-

vents external reading of the OTP program memory. The se-

curity bit in the ECON register determines, whether security

is enabled or disabled. If the security feature is disabled, the

contents of the internal EPROM may be read.

If the security feature is enabled, then any attempt to ex-

ternally read the contents of the EPROM will result in the

value FF Hex being read from all program locations. Un-

der no circumstances can a secured part be read. In ad-

dition, with the security feature enabled, the write operation

to the EPROM program memory and ECON register is inhib-

ited. The ECON register is readable regardless of the state

of the security bit. The security bit, when set, cannot be

erased, even in windowed packages. If the security bit is

set in a device in a windowed package, that device may be

erased but will not be further programmable.

If security is being used, it is recommended that all other bits

in the ECON register be programmed first. Then the security

bit can be programmed.

www.national.com17

6.0 Functional Description (Continued)

6.7 RESET

The device is initialized when the RESET pin is pulled low or

the On-chip Power-On Reset is enabled.

The following occurs upon initialization:

Port L: TRISTATE

Port C: TRISTATE

Port G: TRISTATE

Port F: TRISTATE

Port D: HIGH

PC: CLEARED to 0000

PSW, CNTRL and ICNTRL registers: CLEARED

SIOR: UNAFFECTED after RESET with power already

applied

RANDOM after RESET at power-on

T1CNTRL: CLEARED

Accumulator, Timer 1:

RANDOM after RESET with crystal clock option

(power already applied)

UNAFFECTED after RESET with R/C clock option

(power already applied)

RANDOM after RESET at power-on

WKEN, WKEDG: CLEARED

WKPND: RANDOM

SP (Stack Pointer):

Initialized to RAM address 02F Hex (devices with

64 bytes of RAM), or initialized to

RAM address 06F Hex (devices with

128 bytes of RAM).

B and X Pointers:

UNAFFECTED after RESET with power

already applied

RANDOM after RESET at power-on

RAM:

UNAFFECTED after RESET with power already

applied

RANDOM after RESET at power-on

WATCHDOG (if enabled):

The device comes out of reset with both the WATCHDOG

logic and the Clock Monitor detector armed, with the

WATCHDOG service window bits set and the Clock Monitor

bit set. The WATCHDOG and Clock Monitor circuits are in-

hibited during reset. The WATCHDOG service window bits

being initialized high default to the maximum WATCHDOG

service window of 64k t

clock cycles. The Clock Monitor bit

being initialized high will cause a Clock Monitor error follow-

ing reset if the clock has not reached the minimum specified

frequency at the termination of reset. A Clock Monitor error

will cause an active low error output on pin G1. This error

output will continue until 16 t

–32 t

clock cycles following

the clock frequency reaching the minimum specified value,

at which time the G1 output will go high.

6.7.1 External Reset

The RESET input when pulled low initializes the device. The

RESET pin must be held low for a minimum of one instruc-

tion cycle to guarantee a valid reset. During Power-Up initial-

ization, the user must ensure that the RESET pin is held low

until the device is within the specified V

voltage. An R/C

circuit on the RESET pin with a delay 5 times (5x) greater

than the power supply rise time or 15 µs whichever is

greater, is recommended. Reset should also be wide enough

to ensure crystal start-up upon Power-Up.

RESET may also be used to cause an exit from the HALT

mode.

Arecommended reset circuit for this deviced is shown in

Fig-

ure 9

6.7.2 On-Chip Power-On Reset

The on-chip reset circuit is selected by a bit in the ECON reg-

ister. When enabled, the device generates an internal reset

as V

rises to a voltage level above 2.0V. The on-chip reset

circuitry is able to detect both fast and slow rise times on V

rise time between 10 ns and 50 ms).

Under no circumstances should the RESET pin be allowed

to float. If the on-chip Power-On Reset feature is being used,

RESET pin should be connected directly to V

. The output

of the power-on reset detector will always preset the Idle

timer to 0FFF(4096 t

). At this time, the internal reset will be

generated.

If the Power-On Reset feature is enabled, the internal reset

will not be turned off until the Idle timer underflows. The inter-

nal reset will perform the same functions as external reset.

The user is responsible for ensuring that V

is at the mini-

mum level for the operating frequency within the 4096 t

. Af-

ter the underflow, the logic is designed such that no addi-

tional internal resets occur as long as V

remains above

2.0V.

Note: While the POR feature of the COP8SAx was never intended to function

as a brownout detector, there are certain constraints of this block that

the system designer must address to properly recover from a brownout

condition. This is true regardless of whether the internal POR or the

external reset feature is used.

A brownout condition is reached when VCC of the device goes below

the minimum operating conditions of the device. The minimum guaran-

teed operating conditions are defined as VCC = 4.5V @10 MHz CKI,

VCC = 2.7V @4 MHz, or VCC = 2.0V during HALT mode (or when CKI

is stopped) operation.

When using either the external reset or the POR feature to recover

from a brownout condition, VCC must be lowered to 0.25V or an exter-

nal reset must be applied whenever it goes below the minimum oper-

ating conditions as stated above.

DS012838-13

FIGURE 8. Reset Logic

DS012838-14

RC >5x power supply rise time or 15 µs, whichever is greater.

FIGURE 9. Reset Circuit Using External Reset

www.national.com 18

6.0 Functional Description (Continued)

The contents of data registers and RAM are unknown follow-

ing the on-chip reset.

6.8 OSCILLATOR CIRCUITS

There are four clock oscillator options available: Crystal Os-

cillator with or without on-chip bias resistor, R/C Oscillator

with on-chip resistor and capacitor, and External Oscillator.

The oscillator feature is selected by programming the ECON

Table 2

TABLE 2. Oscillator Option

ECON4 ECON3 Oscillator Option

0 0 External Oscillator

1 0 Crystal Oscillator without Bias Resistor

0 1 R/C Oscillator

ECON4 ECON3 Oscillator Option

1 1 Crystal Oscillator with Bias Resistor

DS012838-15

FIGURE 10. Reset Timing (Power-On Reset Enabled)

with V

Tied to RESET

DS012838-16

FIGURE 11. Reset Circuit Using Power-On Reset

www.national.com19

6.0 Functional Description (Continued)

6.8.1 Crystal Oscillator

The crystal Oscillator mode can be selected by programming

ECON Bit 4 to 1. CKI is the clock input while G7/CKO is the

clock generator output to the crystal.An on-chip bias resistor

connected between CKI and CKO can be enabled by pro-

gramming ECON Bit 3 to 1 with the crystal oscillator option

selection. The value of the resistor is in the range of 0.5M to

2M (typically 1.0M).

Table 3

shows the component values re-

quired for various standard crystal values. Resistor R2 is

only used when the on-chip bias resistor is disabled.

Figure

shows the crystal oscillator connection diagram.

TABLE 3. Crystal Oscillator Configuration,

=25˚C, V

=5V

R1 (kΩ)R2(MΩ) C1 (pF) C2 (pF) CKI Freq. (MHz)

0 1 30 30 15

0 1 32 32 10

0 1 45 30–36 4

5.6 1 100 100–156 0.455

6.8.2 External Oscillator

The External Oscillator mode can be selected by program-

ming ECON Bit 3 to 0 and ECON Bit 4 to 0. CKI can be

driven by an external clock signal provided it meets the

specified duty cycle, rise and fall times, and input levels. G7/

CKO is available as a general purpose input G7 and/or Halt

control.

Figure 13

shows the external oscillator connection

diagram.

6.8.3 R/C Oscillator

The R/C Oscillator mode can be selected by programming

ECON Bit 3 to 1 and ECON Bit 4 to 0. In R/C oscillation

mode, CKI is left floating, while G7/CKO is available as a

general purpose input G7 and/or HALT control.The R/C con-

trolled oscillator has on-chip resistor and capacitor for maxi-

mum R/C oscillator frequency operation. The maximum fre-

quency is 5 MHz ±35%for V

between 4.5V to 5.5V and

temperature range of −40˚C to +85˚C. For max frequency

operation, the CKI pin should be left floating. For lower fre-

quencies, an external capacitor should be connected be-

tween CKI and either V

or GND. Immunity of the R/C os-

cillator to external noise can be improved by connecting one

half the external capacitance to V

and one half to GND.

PC board trace length on the CKI pin should be kept as short

as possible.

Table 4

shows the oscillator frequency as a

function of external capacitance on the CKI pin.

Figure 14

shows the R/C oscillator configuration.

TABLE 4. R/C Oscillator Configuration,

−40˚C to +85˚C, V

=4.5V to 5.5V,

OSC Freq. Variation of ±35%

External Capacitor R/C OSC Freq Instr. Cycle

(pF) (MHz) (µs)

0 5 2.0

9 4 2.5

52 2 5.0

150 1 10

TBD 32 kHz 312.5

With On-Chip Bias Resistor

DS012838-17

Without On-Chip Bias Resistor

DS012838-18

FIGURE 12. Crystal Oscillator

DS012838-19

FIGURE 13. External Oscillator

www.national.com 20

6.0 Functional Description (Continued)

DS012838-20

For operation at lower than maximum R/C oscillator frequency.

DS012838-21

For operation at maximum R/C oscillator frequency.

FIGURE 14. R/C Oscillator

www.national.com21

6.0 Functional Description (Continued)

6.9 CONTROL REGISTERS

CNTRL Register (Address X'00EE)

T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0

Bit 7 Bit 0

The Timer1 (T1) and MICROWIRE/PLUS control register

contains the following bits:

T1C3 Timer T1 mode control bit

T1C2 Timer T1 mode control bit

T1C1 Timer T1 mode control bit

T1C0 Timer T1 Start/Stop control in timer

modes 1 and 2, T1 Underflow Interrupt

Pending Flag in timer mode 3

MSEL Selects G5 and G4 as MICROWIRE/PLUS

signals SK and SO respectively

IEDG External interrupt edge polarity select

(0 = Rising edge, 1 = Falling edge)

SL1 & SL0 Select the MICROWIRE/PLUS clock divide

by (00 = 2, 01 = 4, 1x = 8)

PSW Register (Address X'00EF)

HC C T1PNDA T1ENA EXPND BUSY EXEN GIE

Bit 7 Bit 0

The PSW register contains the following select bits:

HC Half Carry Flag

C Carry Flag

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload

RA in mode 1, T1 Underflow in Mode 2, T1A

capture edge in mode 3)

T1ENA Timer T1 Interrupt Enable for Timer Underflow

or T1A Input capture edge

EXPND External interrupt pending

BUSY MICROWIRE/PLUS busy shifting flag

EXEN Enable external interrupt

GIE Global interrupt enable (enables interrupts)

The Half-Carry flag is also affected by all the instructions that

affect the Carry flag. The SC (Set Carry) and R/C (Reset

Carry) instructions will respectively set or clear both the carry

flags. In addition to the SC and R/C instructions, ADC,

SUBC, RRC and RLC instructions affect the Carry and Half

Carry flags.

ICNTRL Register (Address X'00E8)

Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB

Bit 7 Bit 0

The ICNTRL register contains the following bits:

Reserved This bit is reserved and should to zero

LPEN L Port Interrupt Enable (Multi-Input Wakeup/

Interrupt)

T0PND Timer T0 Interrupt pending

T0EN Timer T0 Interrupt Enable (Bit 12 toggle)

µWPND MICROWIRE/PLUS interrupt pending

µWEN Enable MICROWIRE/PLUS interrupt

T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-

ture edge

T1ENB Timer T1 Interrupt Enable for T1B Input cap-

ture edge

7.0 Timers

The device contains a very versatile set of timers (T0, T1).

Timer T1 and associated autoreload/capture registers power

up containing random data.

7.1 TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining

real time and low power with the IDLE mode. This IDLE

mode support is furnished by the IDLE timer T0. The Timer

T0 runs continuously at the fixed rate of the instruction cycle

clock, t

. The user cannot read or write to the IDLETimer T0,

which is a count down timer.

The Timer T0 supports the following functions:

•Exit out of the Idle Mode (See Idle Mode description)

•WATCHDOG logic (See WATCHDOG description)

•Start up delay out of the HALT mode

•Timing the width of the internal power-on-reset

The IDLE Timer T0 can generate an interrupt when the

twelfth bit toggles. This toggle is latched into the T0PND

pending flag, and will occur every 4.096 ms at the maximum

clock frequency (t

=1 µs).Acontrol flag T0EN allows the in-

terrupt from the twelfth bit of Timer T0 to be enabled or dis-

abled. Setting T0EN will enable the interrupt, while resetting

it will disable the interrupt.

7.2 TIMER T1

One of the main functions of a microcontroller is to provide

timing and counting capability for real-time control tasks. The

COP8 family offers a very versatile 16-bit timer/counter

structure, and two supporting 16-bit autoreload/capture reg-

isters (R1A and R1B), optimized to reduce software burdens

in real-time control applications. The timer block has two pins

associated with it, T1A and T1B. Pin T1A supports I/O re-

quired by the timer block, while pin T1B is an input to the

timer block.

The timer block has three operating modes: Processor Inde-

pendent PWM mode, External Event Counter mode, and In-

put Capture mode.

The control bits T1C3,T1C2, and T1C1 allow selection of the

different modes of operation.

7.2.1 Mode 1. Processor Independent PWM Mode

One of the timer’s operating modes is the Processor Inde-

pendent PWM mode. In this mode, the timer generates a

“Processor Independent” PWM signal because once the

timer is setup, no more action is required from the CPU

which translates to less software overhead and greater

throughput. The user software services the timer block only

when the PWM parameters require updating. This capability

is provided by the fact that the timer has two separate 16-bit

reload registers. One of the reload registers contains the

“ON” timer while the other holds the “OFF” time. By contrast,

a microcontroller that has only a single reload register re-

quires an additional software to update the reload value (al-

ternate between the on-time/off-time).

The timer can generate the PWM output with the width and

duty cycle controlled by the values stored in the reload reg-

isters. The reload registers control the countdown values

and the reload values are automatically written into the timer

when it counts down through 0, generating interrupt on each

reload. Under software control and with minimal overhead,

www.national.com 22

7.0 Timers (Continued)

the PMW outputs are useful in controlling motors, triacs, the

intensity of displays, and in providing inputs for data acquisi-

tion and sine wave generators.

In this mode, the timer T1 counts down at a fixed rate of t

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, R1A and R1B. The very

first underflow of the timer causes the timer to reload from

the register R1A. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the

timer for PWM mode operation.

Figure 15

shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the T1Aoutput

pin. The underflows can also be programmed to generate in-

terrupts.

Underflows from the timer are alternately latched into two

pending flags, T1PNDA and T1PNDB. The user must reset

these pending flags under software control. Two control en-

able flags, T1ENA and T1ENB, allow the interrupts from the

timer underflow to be enabled or disabled. Setting the timer

enable flag T1ENA will cause an interrupt when a timer un-

derflow causes the R1A register to be reloaded into the

timer. Setting the timer enable flag T1ENB will cause an in-

terrupt when a timer underflow causes the R1B register to be

reloaded into the timer. Resetting the timer enable flags will

disable the associated interrupts.

Either or both of the timer underflow interrupts may be en-

abled. This gives the user the flexibility of interrupting once

per PWM period on either the rising or falling edge of the

PWM output. Alternatively, the user may choose to interrupt

on both edges of the PWM output.

7.2.2 Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, T1, is clocked by the input signal from the T1Apin. The

T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer

to be clocked either on a positive or negative edge from the

T1A pin. Underflows from the timer are latched into the

T1PNDA pending flag. Setting the T1ENA control flag will

cause an interrupt when the timer underflows.

In this mode the input pin T1B can be used as an indepen-

dent positive edge sensitive interrupt input if the T1ENB con-

trol flag is set. The occurrence of a positive edge on the T1B

input pin is latched into the T1PNDB flag.

Figure 16

shows a block diagram of the timer in External

Event Counter mode.

Note: The PWM output is not available in this mode since the T1A pin is be-

ing used as the counter input clock.

DS012838-22

FIGURE 15. Timer in PWM Mode

DS012838-23

FIGURE 16. Timer in External Event Counter Mode

www.national.com23

7.0 Timers (Continued)

7.2.3 Mode 3. Input Capture Mode

The device can precisely measure external frequencies or

time external events by placing the timer block, T1, in the in-

put capture mode. In this mode, the reload registers serve as

independent capture registers, capturing the contents of the

timer when an external event occurs (transition on the timer

input pin). The capture registers can be read while maintain-

ing count, a feature that lets the user measure elapsed time

and time between events. By saving the timer value when

the external event occurs, the time of the external event is

recorded. Most microcontrollers have a latency time be-

cause they cannot determine the timer value when the exter-

nal event occurs. The capture register eliminates the latency

time, thereby allowing the applications program to retrieve

the timer value stored in the capture register.

In this mode, the timer T1 is constantly running at the fixed t

rate. The two registers, R1A and R1B, act as capture regis-

ters. Each register acts in conjunction with a pin. The register

R1A acts in conjunction with the T1A pin and the register

R1B acts in conjunction with the T1B pin.

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin. Control bits,

T1C3, T1C2 and T1C1, allow the trigger events to be speci-

fied either as a positive or a negative edge. The trigger con-

dition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the T1Aand T1B pins will be respectively latched into the

pending flags, T1PNDA and T1PNDB. The control flag

T1ENA allows the interrupt on T1A to be either enabled or

disabled. Setting the T1ENA flag enables interrupts to be

generated when the selected trigger condition occurs on the

T1A pin. Similarly, the flag T1ENB controls the interrupts

from the T1B pin.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer T1C0

pending flag (the T1C0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the T1C0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the T1ENA control flag. When a T1A interrupt

occurs in the Input Capture mode, the user must check both

the T1PNDA and T1C0 pending flags in order to determine

whether a T1A input capture or a timer underflow (or both)

caused the interrupt.

Figure 17

shows a block diagram of the timer in Input Cap-

ture mode.

DS012838-24

FIGURE 17. Timer in Input Capture Mode

www.national.com 24

7.0 Timers (Continued)

7.3 TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

T1C3 Timer mode control

T1C2 Timer mode control

T1C1 Timer mode control

T1C0 Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in

Mode 3 (Input Capture)

T1PNDA Timer Interrupt Pending Flag

T1ENA Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

T1PNDB Timer Interrupt Pending Flag

T1ENB Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below:

Mode T1C3 T1C2 T1C1 Description Interrupt A

Source Interrupt B

Source Timer

Counts On

11 0 1 PWM: T1A Toggle Autoreload RA Autoreload RB t

1 0 0 PWM: No T1A

Toggle Autoreload RA Autoreload RB t

0 0 0 External Event

Counter Timer

Underflow Pos. T1B Edge Pos. T1A

Edge

0 0 1 External Event

Counter Timer

Underflow Pos. T1B Edge Pos. T1A

Edge

0 1 0 Captures: Pos. T1A Edge Pos. T1B Edge t

T1A Pos. Edge or Timer

T1B Pos. Edge Underflow

1 1 0 Captures: Pos. T1A Neg. T1B t

T1A Pos. Edge Edge or Timer Edge

T1B Neg. Edge Underflow

0 1 1 Captures: Neg. T1A Neg. T1B t

T1A Neg. Edge Edge or Timer Edge

T1B Neg. Edge Underflow

1 1 1 Captures: Neg. T1A Neg. T1B t

T1A Neg. Edge Edge or Timer Edge

T1B Neg. Edge Underflow

www.national.com25

8.0 Power Save Modes

Today, the proliferation of battery-operated based applica-

tions has placed new demands on designers to drive power

consumption down. Battery-operated systems are not the

only type of applications demanding low power. The power

budget constraints are also imposed on those consumer/

industrial applications where well regulated and expensive

power supply costs cannot be tolerated. Such applications

rely on low cost and low power supply voltage derived di-

rectly from the “mains” by using voltage rectifier and passive

components. Low power is demanded even in automotive

applications, due to increased vehicle electronics content.

This is required to ease the burden from the car battery. Low

power 8-bit microcontrollers supply the smarts to control

battery-operated, consumer/industrial, and automotive appli-

cations.

The COP8SAx devices offer system designers a variety of

low-power consumption features that enable them to meet

the demanding requirements of today’s increasing range of

low-power applications. These features include low voltage

operation, low current drain, and power saving features such

as HALT, IDLE, and Multi-Input wakeup (MIWU).

The devices offer the user two power save modes of opera-

tion: HALT and IDLE. In the HALT mode, all microcontroller

activities are stopped. In the IDLE mode, the on-board oscil-

lator circuitry and timer T0 are active but all other microcon-

troller activities are stopped. In either mode, all on-board

RAM, registers, I/O states, and timers (with the exception of

T0) are unaltered.

Clock Monitor if enabled can be active in both modes.

8.1 HALT MODE

The device can be placed in the HALT mode by writing a “1”

to the HALT flag (G7 data bit). All microcontroller activities,

including the clock and timers, are stopped. The WATCH-

DOG logic on the device is disabled during the HALT mode.

However, the clock monitor circuitry, if enabled, remains ac-

tive and will cause the WATCHDOG output pin (WDOUT) to

go low. If the HALT mode is used and the user does not want

to activate the WDOUT pin, the Clock Monitor should be dis-

abled after the device comes out of reset (resetting the Clock

Monitor control bit with the first write to the WDSVR register).

In the HALT mode, the power requirements of the device are

minimal and the applied voltage (V

) may be decreased to

=2.0V) without altering the state of the machine.

The device supports three different ways of exiting the HALT

mode. The first method of exiting the HALT mode is with the

Multi-Input Wakeup feature on Port L. The second method is

with a low to high transition on the CKO (G7) pin. This

method precludes the use of the crystal clock configuration

(since CKO becomes a dedicated output), and so may only

be used with an R/C clock configuration. The third method of

exiting the HALT mode is by pulling the RESET pin low.

Since a crystal or ceramic resonator may be selected as the

oscillator, the Wakeup signal is not allowed to start the chip

running immediately since crystal oscillators and ceramic

resonators have a delayed start up time to reach full ampli-

tude and frequency stability. The IDLE timer is used to gen-

erate a fixed delay to ensure that the oscillator has indeed

stabilized before allowing instruction execution. In this case,

upon detecting a valid Wakeup signal, only the oscillator cir-

cuitry is enabled. The IDLE timer is loaded with a value of

256 and is clocked with the t

instruction cycle clock. The t

clock is derived by dividing the oscillator clock down by a fac-

tor of 10. The Schmitt trigger following the CKI inverter on

the chip ensures that the IDLE timer is clocked only when the

oscillator has a sufficiently large amplitude to meet the

Schmitt trigger specifications. This Schmitt trigger is not part

of the oscillator closed loop. The start-up time-out from the

IDLE timer enables the clock signals to be routed to the rest

of the chip.

If an R/C clock option is being used, the fixed delay is intro-

duced optionally. A control bit, CLKDLY, mapped as configu-

ration bit G7, controls whether the delay is to be introduced

or not. The delay is included if CLKDLY is set, and excluded

if CLKDLY is reset. The CLKDLY bit is cleared on reset.

The device has two options associated with the HALT mode.

The first option enables the HALT mode feature, while the

second option disables the HALT mode selected through bit

0 of the ECON register. With the HALT mode enable option,

the device will enter and exit the HALT mode as described

above. With the HALT disable option, the device cannot be

placed in the HALT mode (writing a “1” to the HALT flag will

have no effect, the HALT flag will remain “0”).

The WATCHDOG detector circuit is inhibited during the

HALT mode. However, the clock monitor circuit if enabled re-

mains active during HALT mode in order to ensure a clock

monitor error if the device inadvertently enters the HALT

mode as a result of a runaway program or power glitch.

If the device is placed in the HALT mode, with the R/C oscil-

lator selected, the clock input pin (CKI) is forced to a logic

high internally. With the crystal or external oscillator the CKI

pin is TRI-STATE.

www.national.com 26

8.0 Power Save Modes (Continued)

8.2 IDLE MODE

The device is placed in the IDLE mode by writing a “1” to the

IDLE flag (G6 data bit). In this mode, all activities, except the

associated on-board oscillator circuitry and the IDLE Timer

T0, are stopped.

As with the HALT mode, the device can be returned to nor-

mal operation with a reset, or with a Multi-Input Wakeup from

the L Port. Alternately, the microcontroller resumes normal

operation from the IDLE mode when the twelfth bit (repre-

senting 4.096 ms at internal clock frequency of 10 MHz, t

1 µs) of the IDLE Timer toggles.

This toggle condition of the twelfth bit of the IDLE Timer T0 is

latched into the T0PND pending flag.

The user has the option of being interrupted with a transition

on the twelfth bit of the IDLE Timer T0. The interrupt can be

enabled or disabled via the T0EN control bit. Setting the

T0EN flag enables the interrupt and vice versa.

The user can enter the IDLE mode with the Timer T0 inter-

rupt enabled. In this case, when the T0PND bit gets set, the

device will first execute the Timer T0 interrupt service routine

and then return to the instruction following the “Enter Idle

Mode” instruction.

Alternatively, the user can enter the IDLE mode with the

IDLE Timer T0 interrupt disabled. In this case, the device will

resume normal operation with the instruction immediately

following the “Enter IDLE Mode” instruction.

Note: It is necessary to program two NOP instructions following both the set

HALT mode and set IDLE mode instructions. These NOP instructions

are necessary to allow clock resynchronization following the HALT or

IDLE modes.

DS012838-25

FIGURE 18. Wakeup from HALT

DS012838-26

FIGURE 19. Wakeup from IDLE

www.national.com27

8.0 Power Save Modes (Continued)

8.3 MULTI-INPUT WAKEUP

The Multi-Input Wakeup feature is used to return (wakeup)

the device from either the HALT or IDLE modes. Alternately

Multi-Input Wakeup/Interrupt feature may also be used to

generate up to 8 edge selectable external interrupts.

Figure 20

shows the Multi-Input Wakeup logic.

The Multi-Input Wakeup feature utilizes the L Port. The user

selects which particular L port bit (or combination of L Port

bits) will cause the device to exit the HALT or IDLE modes.

The selection is done through the register WKEN. The regis-

ter WKEN is an 8-bit read/write register, which contains a

control bit for every L port bit. Setting a particular WKEN bit

enables a Wakeup from the associated L port pin.

The user can select whether the trigger condition on the se-

lected L Port pin is going to be either a positive edge (low to

high transition) or a negative edge (high to low transition).

This selection is made via the register WKEDG, which is an

8-bit control register with a bit assigned to each L Port pin.

Setting the control bit will select the trigger condition to be a

negative edge on that particular L Port pin. Resetting the bit

selects the trigger condition to be a positive edge. Changing

an edge select entails several steps in order to avoid a

Wakeup condition as a result of the edge change. First, the

associated WKEN bit should be reset, followed by the edge

select change in WKEDG. Next, the associated WKPND bit

should be cleared, followed by the associated WKEN bit be-

ing re-enabled.

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

to negative (high going low) for L Port bit 5, where bit 5 has

previously been enabled for an input interrupt. The program

would be as follows:

RBIT 5, WKEN ; Disable MIWU

SBIT 5, WKEDG ; Change edge polarity

RBIT 5, WKPND ; Reset pending flag

SBIT 5, WKEN ; Enable MIWU

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup/Interrupt, a safety

procedure should also be followed to avoid wakeup condi-

tions. After the selected L port bits have been changed from

output to input but before the associated WKEN bits are en-

abled, the associated edge select bits in WKEDG should be

set or reset for the desired edge selects, followed by the as-

sociated WKPND bits being cleared.

This same procedure should be used following reset, since

the L port inputs are left floating as a result of reset.

The occurrence of the selected trigger condition for

Multi-Input Wakeup is latched into a pending register called

WKPND. The respective bits of the WKPND register will be

set on the occurrence of the selected trigger edge on the cor-

responding Port L pin. The user has the responsibility of

clearing these pending flags. Since WKPND is a pending

the device will not enter the HALT mode if any Wakeup bit is

both enabled and pending. Consequently, the user must

clear the pending flags before attempting to enter the HALT

mode.

WKEN and WKEDG are all read/write registers, and are

cleared at reset. WKPND register contains random value af-

ter reset.

DS012838-27

FIGURE 20. Multi-Input Wake Up Logic

www.national.com 28

9.0 Interrupts

9.1 INTRODUCTION

The device supports eight vectored interrupts. Interrupt

sources include Timer 1, Timer T0, Port L Wakeup, Software

Trap, MICROWIRE/PLUS, and External Input.

All interrupts force a branch to location 00FF Hex in program

memory. The VIS instruction may be used to vector to the

appropriate service routine from location 00FF Hex.

The Software trap has the highest priority while the default

VIS has the lowest priority.

Each of the six maskable inputs has a fixed arbitration rank-

ing and vector.

Figure 21

shows the Interrupt Block Diagram.

DS012838-28

FIGURE 21. Interrupt Block Diagram

www.national.com29

9.0 Interrupts (Continued)

9.2 MASKABLE INTERRUPTS

All interrupts other than the Software Trap are maskable.

Each maskable interrupt has an associated enable bit and

pending flag bit. The pending bit is set to 1 when the interrupt

condition occurs. The state of the interrupt enable bit, com-

bined with the GIE bit determines whether an active pending

flag actually triggers an interrupt. All of the maskable inter-

rupt pending and enable bits are contained in mapped con-

trol registers, and thus can be controlled by the software.

Amaskable interrupt condition triggers an interrupt under the

following conditions:

1. The enable bit associated with that interrupt is set.

2. The GIE bit is set.

3. The device is not processing a non-maskable interrupt.

(If a non-maskable interrupt is being serviced, a

maskable interrupt must wait until that service routine is

completed.)

An interrupt is triggered only when all of these conditions are

met at the beginning of an instruction. If different maskable

interrupts meet these conditions simultaneously, the highest

priority interrupt will be serviced first, and the other pending

interrupts must wait.

Upon Reset, all pending bits, individual enable bits, and the

GIE bit are reset to zero. Thus, a maskable interrupt condi-

tion cannot trigger an interrupt until the program enables it by

setting both the GIE bit and the individual enable bit. When

enabling an interrupt, the user should consider whether or

not a previously activated (set) pending bit should be ac-

knowledged. If, at the time an interrupt is enabled, any pre-

vious occurrences of the interrupt should be ignored, the as-

sociated pending bit must be reset to zero prior to enabling

the interrupt. Otherwise, the interrupt may be simply en-

abled; if the pending bit is already set, it will immediately trig-

ger an interrupt. A maskable interrupt is active if its associ-

ated enable and pending bits are set.

An interrupt is an asychronous event which may occur be-

fore, during, or after an instruction cycle. Any interrupt which

occurs during the execution of an instruction is not acknowl-

edged until the start of the next normally executed instruction

is to be skipped, the skip is performed before the pending in-

terrupt is acknowledged.

At the start of interrupt acknowledgment, the following ac-

tions occur:

1. The GIE bit is automatically reset to zero, preventing any

subsequent maskable interrupt from interrupting the cur-

rent service routine. This feature prevents one maskable

interrupt from interrupting another one being serviced.

2. The address of the instruction about to be executed is

pushed onto the stack.

3. The program counter (PC) is loaded with 00FF Hex,

causing a jump to that program memory location.

The device requires seven instruction cycles to perform the

actions listed above.

If the user wishes to allow nested interrupts, the interrupts

service routine may set the GIE bit to 1 by writing to the PSW

the current service routine. If nested interrupts are allowed,

caution must be exercised. The user must write the program

in such a way as to prevent stack overflow, loss of saved

context information, and other unwanted conditions.

The interrupt service routine stored at location 00FF Hex

should use the VIS instruction to determine the cause of the

interrupt, and jump to the interrupt handling routine corre-

sponding to the highest priority enabled and active interrupt.

Alternately, the user may choose to poll all interrupt pending

and enable bits to determine the source(s) of the interrupt. If

more than one interrupt is active, the user’s program must

decide which interrupt to service.

Within a specific interrupt service routine, the associated

pending bit should be cleared. This is typically done as early

as possible in the service routine in order to avoid missing

the next occurrence of the same type of interrupt event.

Thus, if the same event occurs a second time, even while the

first occurrence is still being serviced, the second occur-

rence will be serviced immediately upon return from the cur-

rent interrupt routine.

An interrupt service routine typically ends with an RETI in-

struction. This instruction sets the GIE bit back to 1, pops the

address stored on the stack, and restores that address to the

program counter. Program execution then proceeds with the

next instruction that would have been executed had there

been no interrupt. If there are any valid interrupts pending,

the highest-priority interrupt is serviced immediately upon re-

turn from the previous interrupt.

9.3 VIS INSTRUCTION

The general interrupt service routine, which starts at address

00FF Hex, must be capable of handling all types of inter-

rupts. The VIS instruction, together with an interrupt vector

table, directs the device to the specific interrupt handling rou-

tine based on the cause of the interrupt.

VIS is a single-byte instruction, typically used at the very be-

ginning of the general interrupt service routine at address

00FF Hex, or shortly after that point, just after the code used

for context switching. The VIS instruction determines which

enabled and pending interrupt has the highest priority, and

causes an indirect jump to the address corresponding to that

interrupt source. The jump addresses (vectors) for all pos-

sible interrupts sources are stored in a vector table.

The vector table may be as long as 32 bytes (maximum of 16

vectors) and resides at the top of the 256-byte block contain-

ing the VIS instruction. However, if the VIS instruction is at

the very top of a 256-byte block (such as at 00FF Hex), the

vector table resides at the top of the next 256-byte block.

Thus, if the VIS instruction is located somewhere between

00FF and 01DF Hex (the usual case), the vector table is lo-

cated between addresses 01E0 and 01FF Hex. If the VIS in-

struction is located between 01FF and 02DF Hex, then the

vector table is located between addresses 02E0 and 02FF

Hex, and so on.

Each vector is 15 bits long and points to the beginning of a

specific interrupt service routine somewhere in the 32 kbyte

memory space. Each vector occupies two bytes of the vector

table, with the higher-order byte at the lower address. The

vectors are arranged in order of interrupt priority. The vector

of the maskable interrupt with the lowest rank is located to

0yE0 (higher-order byte) and 0yE1 (lower-order byte). The

next priority interrupt is located at 0yE2 and 0yE3, and so

forth in increasing rank. The Software Trap has the highest

rank and its vector is always located at 0yFE and 0yFF. The

number of interrupts which can become active defines the

size of the table.

Table 5

shows the types of interrupts, the interrupt arbitration

ranking, and the locations of the corresponding vectors in

the vector table.

The vector table should be filled by the user with the memory

locations of the specific interrupt service routines. For ex-

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9.0 Interrupts (Continued)

ample, if the Software Trap routine is located at 0310 Hex,

then the vector location 0yFE and -0yFF should contain the

data 03 and 10 Hex, respectively. When a Software Trap in-

terrupt occurs and the VIS instruction is executed, the pro-

gram jumps to the address specified in the vector table.

The interrupt sources in the vector table are listed in order of

rank, from highest to lowest priority. If two or more enabled

and pending interrupts are detected at the same time, the

one with the highest priority is serviced first. Upon return

from the interrupt service routine, the next highest-level

pending interrupt is serviced.

If the VIS instruction is executed, but no interrupts are en-

abled and pending, the lowest-priority interrupt vector is

used, and a jump is made to the corresponding address in

the vector table. This is an unusual occurrence, and may be

the result of an error. It can legitimately result from a change

in the enable bits or pending flags prior to the execution of

the VIS instruction, such as executing a single cycle instruc-

tion which clears an enable flag at the same time that the

pending flag is set. It can also result, however, from inadvert-

ent execution of the VIS command outside of the context of

an interrupt.

The default VIS interrupt vector can be useful for applica-

tions in which time critical interrupts can occur during the

servicing of another interrupt. Rather than restoring the pro-

gram context (A, B, X, etc.) and executing the RETI instruc-

tion, an interrupt service routine can be terminated by return-

ing to the VIS instruction. In this case, interrupts will be

serviced in turn until no further interrupts are pending and

the default VIS routine is started. After testing the GIE bit to

ensure that execution is not erroneous, the routine should

restore the program context and execute the RETI to return

to the interrupted program.

This technique can save up to fifty instruction cycles (t

), or

more, (50 µs at 10 MHz oscillator) of latency for pending in-

terrupts with a penalty of fewer than ten instruction cycles if

no further interrupts are pending.

To ensure reliable operation, the user should always use the

VIS instruction to determine the source of an interrupt. Al-

though it is possible to poll the pending bits to detect the

source of an interrupt, this practice is not recommended. The

use of polling allows the standard arbitration ranking to be al-

tered, but the reliability of the interrupt system is compro-

mised. The polling routine must individually test the enable

and pending bits of each maskable interrupt. If a Software

Trap interrupt should occur, it will be serviced last, even

though it should have the highest priority. Under certain con-

ditions, a Software Trap could be triggered but not serviced,

resulting in an inadvertent “locking out” of all maskable inter-

rupts by the Software Trap pending flag. Problems such as

this can be avoided by using VIS instruction.

TABLE 5. Interrupt Vector Table

Arbitration Vector (Note 20)

Ranking Source Description Address

(Hi-Low Byte)

(1) Highest Software INTR Instruction 0yFE–0yFF

(2) Reserved Future 0yFC–0yFD

(3) External G0 0yFA–0yFB

(4) Timer T0 Underflow 0yF8–0yF9

(5) Timer T1 T1A/Underflow 0yF6–0yF7

(6) Timer T1 T1B 0yF4–0yF5

(7) MICROWIRE/PLUS BUSY Low 0yF2–0yF3

(8) Reserved Future 0yF0–0yF1

(9) Reserved Future 0yEE–0yEF

(10) Reserved Future 0yEC–0yED

(11) Reserved Future 0yEA–0yEB

(12) Reserved Future 0yE8–0yE9

(13) Reserved Future 0yE6–0yE7

(14) Reserved Future 0yE4–0yE5

(15) Port L/Wakeup Port L Edge 0yE2–0yE3

(16) Lowest Default VIS Instruction 0yE0–0yE1

Execution without any interrupts

Note 20: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last ad-

dress of a block. In this case, the table must be in the next block.

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9.0 Interrupts (Continued)

9.3.1 VIS Execution

When the VIS instruction is executed it activates the arbitra-

tion logic. The arbitration logic generates an even number

between E0 and FE (E0, E2, E4, E6 etc...) depending on

which active interrupt has the highest arbitration ranking at

the time of the 1st cycle of VIS is executed. For example, if

the software trap interrupt is active, FE is generated. If the

external interrupt is active and the software trap interrupt is

not, then FAis generated and so forth. If the only active inter-

rupt is software trap, than E0 is generated. This number re-

places the lower byte of the PC. The upper byte of the PC re-

mains unchanged. The new PC is therefore pointing to the

vector of the active interrupt with the highest arbitration rank-

ing. This vector is read from program memory and placed

into the PC which is now pointed to the 1st instruction of the

service routine of the active interrupt with the highest arbitra-

tion ranking.

Figure 22

illustrates the different steps performed by the VIS

instruction.

Figure 23

shows a flowchart for the VIS instruc-

tion.

The non-maskable interrupt pending flag is cleared by the

RPND (Reset Non-Maskable Pending Bit) instruction (under

certain conditions) and upon RESET.

DS012838-29

FIGURE 22. VIS Operation

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9.0 Interrupts (Continued)

DS012838-30

FIGURE 23. VIS Flowchart

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9.0 Interrupts (Continued)

Programming Example: External Interrupt

PSW =00EF

CNTRL =00EE

RBIT 0,PORTGC

RBIT 0,PORTGD ; G0 pin configured Hi-Z

SBIT IEDG, CNTRL ; Ext interrupt polarity; falling edge

SBIT GIE, PSW ; Set the GIE bit

SBIT EXEN, PSW ; Enable the external interrupt

WAIT: JP WAIT ; Wait for external interrupt

.=0FF ; The interrupt causes a

VIS ; branch to address 0FF

;The VIS causes a branch to

;interrupt vector table

.=01FA ; Vector table (within 256 byte

.ADDRW SERVICE ; of VIS inst.) containing the ext

;interrupt service routine

SERVICE: ; Interrupt Service Routine

RBIT, EXPND, PSW ; Reset ext interrupt pend. bit

RET ; Return, set the GIE bit

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9.0 Interrupts (Continued)

9.4 NON-MASKABLE INTERRUPT

9.4.1 Pending Flag

There is a pending flag bit associated with the non-maskable

interrupt, called STPND. This pending flag is not

memory-mapped and cannot be accessed directly by the

software.

The pending flag is reset to zero when a device Reset oc-

curs. When the non-maskable interrupt occurs, the associ-

ated pending bit is set to 1. The interrupt service routine

should contain an RPND instruction to reset the pending flag

to zero. The RPND instruction always resets the STPND

flag.

9.4.2 Software Trap

The Software Trap is a special kind of non-maskable inter-

rupt which occurs when the INTR instruction (used to ac-

knowledge interrupts) is fetched from program memory and

placed in the instruction register. This can happen in a vari-

ety of ways, usually because of an error condition. Some ex-

amples of causes are listed below.

If the program counter incorrectly points to a memory loca-

tion beyond the available program memory space, the

non-existent or unused memory location returns zeroes

which is interpreted as the INTR instruction.

If the stack is popped beyond the allowed limit (address 02F

or 06F Hex), a Software Trap is triggered.

A Software Trap can be triggered by a temporary hardware

condition such as a brownout or power supply glitch.

The Software Trap has the highest priority of all interrupts.

When a Software Trap occurs, the STPND bit is set. The GIE

bit is not affected and the pending bit (not accessible by the

user) is used to inhibit other interrupts and to direct the pro-

gram to the ST service routine with the VIS instruction. Noth-

ing can interrupt a Software Trap service routine except for

another Software Trap. The STPND can be reset only by the

RPND instruction or a chip Reset.

The Software Trap indicates an unusual or unknown error

condition. Generally, returning to normal execution at the

point where the Software Trap occurred cannot be done re-

liably. Therefore, the Software Trap service routine should

reinitialize the stack pointer and perform a recovery proce-

dure that restarts the software at some known point, similar

to a device Reset, but not necessarily performing all the

same functions as a device Reset. The routine must also ex-

ecute the RPND instruction to reset the STPND flag. Other-

wise, all other interrupts will be locked out. To the extent pos-

sible, the interrupt routine should record or indicate the

context of the device so that the cause of the Software Trap

can be determined.

If the user wishes to return to normal execution from the

point at which the Software Trap was triggered, the user

must first execute RPND, followed by RETSK rather than

RETI or RET. This is because the return address stored on

the stack is the address of the INTR instruction that triggered

the interrupt. The program must skip that instruction in order

to proceed with the next one. Otherwise, an infinite loop of

Software Traps and returns will occur.

Programming a return to normal execution requires careful

consideration. If the Software Trap routine is interrupted by

another Software Trap, the RPND instruction in the service

routine for the second Software Trap will reset the STPND

flag; upon return to the first Software Trap routine, the

STPND flag will have the wrong state. This will allow

maskable interrupts to be acknowledged during the servicing

of the first Software Trap. To avoid problems such as this, the

user program should contain the Software Trap routine to

perform a recovery procedure rather than a return to normal

execution.

Under normal conditions, the STPND flag is reset by a

RPND instruction in the Software Trap service routine. If a

programming error or hardware condition (brownout, power

supply glitch, etc.) sets the STPND flag without providing a

way for it to be cleared, all other interrupts will be locked out.

To alleviate this condition, the user can use extra RPND in-

structions in the main program and in the WATCHDOG ser-

vice routine (if present). There is no harm in executing extra

RPND instructions in these parts of the program.

9.5 PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port L interrupts. Setting the LPEN flag will enable inter-

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

(See HALT MODE for clock option wakeup information.)

9.6 INTERRUPT SUMMARY

The device uses the following types of interrupts, listed be-

low in order of priority:

1. The Software Trap non-maskable interrupt, triggered by

the INTR (00 opcode) instruction. The Software Trap is

acknowledged immediately. This interrupt service rou-

tine can be interrupted only by another Software Trap.

The Software Trap should end with two RPND instruc-

tions followed by a restart procedure.

2. Maskable interrupts, triggered by an on-chip peripheral

block or an external device connected to the device. Un-

der ordinary conditions, a maskable interrupt will not in-

terrupt any other interrupt routine in progress. A

maskable interrupt routine in progress can be inter-

rupted by the non-maskable interrupt request. A

maskable interrupt routine should end with an RETI in-

struction.

10.0 WATCHDOG/Clock Monitor

The devices contain a user selectable WATCHDOG and

clock monitor. The following section is applicable only if

WATCHDOG feature has been selected in the ECON regis-

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10.0 WATCHDOG/Clock Monitor

(Continued)

ter. The WATCHDOG is designed to detect the user program

getting stuck in infinite loops resulting in loss of program con-

trol or “runaway” programs.

The WATCHDOG logic contains two separate service win-

dows. While the user programmable upper window selects

the WATCHDOG service time, the lower window provides

protection against an infinite program loop that contains the

WATCHDOG service instruction.

The COP8SAx devices provide the added feature of a soft-

ware trap that provides protection against stack overpops

and addressing locations outside valid user program space.

The Clock Monitor is used to detect the absence of a clock or

a very slow clock below a specified rate on the CKI pin.

The WATCHDOG consists of two independent logic blocks:

WD UPPER and WD LOWER. WD UPPER establishes the

upper limit on the service window and WD LOWER defines

the lower limit of the service window.

Servicing the WATCHDOG consists of writing a specific

value to a WATCHDOG Service Register named WDSVR

which is memory mapped in the RAM. This value is com-

posed of three fields, consisting of a 2-bit Window Select, a

5-bit Key Data field, and the 1-bit Clock Monitor Select field.

Table 6

shows the WDSVR register.

TABLE 6. WATCHDOG Service Register (WDSVR)

Window Key Data Clock

Select Monitor

X X 01100 Y

The lower limit of the service window is fixed at 256 instruc-

tion cycles. Bits 7 and 6 of the WDSVR register allow the

user to pick an upper limit of the service window.

Table 7

shows the four possible combinations of lower and

upper limits for the WATCHDOG service window. This flex-

ibility in choosing the WATCHDOG service window prevents

any undue burden on the user software.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the

5-bit Key Data field. The key data is fixed at 01100. Bit 0 of

the WDSVR Register is the Clock Monitor Select bit.

TABLE 7. WATCHDOG Service Window Select

WDSVR WDSVR Clock Service Window

Bit 7 Bit 6 Monitor (Lower-Upper Limits)

0 0 x 2048–8k t

Cycles

0 1 x 2048–16k t

Cycles

1 0 x 2048–32k t

Cycles

1 1 x 2048–64k t

Cycles

x x 0 Clock Monitor Disabled

x x 1 Clock Monitor Enabled

10.1 CLOCK MONITOR

The Clock Monitor aboard the device can be selected or de-

selected under program control. The Clock Monitor is guar-

anteed not to reject the clock if the instruction cycle clock (1/

) is greater or equal to 10 kHz. This equates to a clock

input rate on CKI of greater or equal to 100 kHz.

10.2 WATCHDOG/CLOCK MONITOR OPERATION

The WATCHDOG is enabled by bit 2 of the ECON register.

When this ECON bit is 0, the WATCHDOG is enabled and

pin G1 becomes the WATCHDOG output with a weak pullup.

The WATCHDOG and Clock Monitor are disabled during re-

set. The device comes out of reset with the WATCHDOG

armed, the WATCHDOG Window Select bits (bits 6, 7 of the

WDSVR Register) set, and the Clock Monitor bit (bit 0 of the

WDSVR Register) enabled. Thus, a Clock Monitor error will

occur after coming out of reset, if the instruction cycle clock

frequency has not reached a minimum specified value, in-

cluding the case where the oscillator fails to start.

The WDSVR register can be written to only once after reset

and the key data (bits 5 through 1 of the WDSVR Register)

must match to be a valid write. This write to the WDSVR reg-

ister involves two irrevocable choices: (i) the selection of the

WATCHDOG service window (ii) enabling or disabling of the

Clock Monitor. Hence, the first write to WDSVR Register in-

volves selecting or deselecting the Clock Monitor, select the

WATCHDOG service window and match the WATCHDOG

key data. Subsequent writes to the WDSVR register will

compare the value being written by the user to the WATCH-

DOG service window value and the key data (bits 7 through

1) in the WDSVR Register.

Table 8

shows the sequence of

events that can occur.

The user must service the WATCHDOG at least once before

the upper limit of the service window expires. The WATCH-

DOG may not be serviced more than once in every lower

limit of the service window. The user may service the

WATCHDOG as many times as wished in the time period be-

tween the lower and upper limits of the service window. The

first write to the WDSVR Register is also counted as a

WATCHDOG service.

The WATCHDOG has an output pin associated with it. This

is the WDOUT pin, on pin 1 of the port G. WDOUT is active

low and must be externally connected to the RESET pin or to

some other external logic which handles WATCHDOG event.

The WDOUT pin has a weak pullup in the inactive state. This

pull-up is sufficient to serve as the connection to V

for sys-

tems which use the internal Power On Reset. Upon trigger-

ing the WATCHDOG, the logic will pull the WDOUT (G1) pin

low for an additional 16 t

–32 t

cycles after the signal level

on WDOUT pin goes below the lower Schmitt trigger thresh-

old. After this delay, the device will stop forcing the WDOUT

output low. The WATCHDOG service window will restart

when the WDOUT pin goes high.

AWATCHDOG service while the WDOUT signal is active will

be ignored. The state of the WDOUT pin is not guaranteed

on reset, but if it powers up low then the WATCHDOG will

time out and WDOUT will go high.

The Clock Monitor forces the G1 pin low upon detecting a

clock frequency error. The Clock Monitor error will continue

until the clock frequency has reached the minimum specified

value, after which the G1 output will go high following 16

–32 t

clock cycles. The Clock Monitor generates a con-

tinual Clock Monitor error if the oscillator fails to start, or fails

to reach the minimum specified frequency. The specification

for the Clock Monitor is as follows:

1/t

>10 kHz—No clock rejection.

1/t

<10 Hz—Guaranteed clock rejection.

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10.0 WATCHDOG/Clock Monitor (Continued)

TABLE 8. WATCHDOG Service Actions

Key Window Clock Action

Data Data Monitor

Match Match Match Valid Service: Restart Service Window

Don’t Care Mismatch Don’t Care Error: Generate WATCHDOG Output

Mismatch Don’t Care Don’t Care Error: Generate WATCHDOG Output

Don’t Care Don’t Care Mismatch Error: Generate WATCHDOG Output

10.3 WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the WATCHDOG and

CLOCK MONITOR should be noted:

•Both the WATCHDOG and CLOCK MONITOR detector

circuits are inhibited during RESET.

•Following RESET, the WATCHDOG and CLOCK MONI-

TOR are both enabled, with the WATCHDOG having the

maximum service window selected.

•The WATCHDOG service window and CLOCK MONI-

TOR enable/disable option can only be changed once,

during the initial WATCHDOG service following RESET.

•The initial WATCHDOG service must match the key data

value in the WATCHDOG Service register WDSVR in or-

der to avoid a WATCHDOG error.

•Subsequent WATCHDOG services must match all three

data fields in WDSVR in order to avoid WATCHDOG er-

rors.

•The correct key data value cannot be read from the

WATCHDOG Service register WDSVR. Any attempt to

read this key data value of 01100 from WDSVR will read

as key data value of all 0’s.

•The WATCHDOG detector circuit is inhibited during both

the HALT and IDLE modes.

•The CLOCK MONITOR detector circuit is active during

both the HALT and IDLE modes. Consequently, the de-

vice inadvertently entering the HALT mode will be de-

tected as a CLOCK MONITOR error (provided that the

CLOCK MONITOR enable option has been selected by

the program).

•With the single-pin R/C oscillator option selected and the

CLKDLY bit reset, the WATCHDOG service window will

resume following HALT mode from where it left off before

entering the HALT mode.

•With the crystal oscillator option selected, or with the

single-pin R/C oscillator option selected and the CLKDLY

bit set, the WATCHDOG service window will be set to its

selected value from WDSVR following HALT. Conse-

quently, the WATCHDOG should not be serviced for at

least 256 instruction cycles following HALT, but must be

serviced within the selected window to avoid a WATCH-

DOG error.

•The IDLE timer T0 is not initialized with external RESET.

•The user can sync in to the IDLE counter cycle with an

IDLE counter (T0) interrupt or by monitoring the T0PND

flag. TheT0PND flag is set whenever the twelfth bit of the

IDLE counter toggles (every 4096 instruction cycles). The

user is responsible for resetting the T0PND flag.

•A hardware WATCHDOG service occurs just as the de-

vice exits the IDLE mode. Consequently, the WATCH-

DOG should not be serviced for at least 256 instruction

cycles following IDLE, but must be serviced within the se-

lected window to avoid a WATCHDOG error.

•Following RESET, the initial WATCHDOG service (where

the service window and the CLOCK MONITOR enable/

disable must be selected) may be programmed any-

where within the maximum service window (65,536 in-

struction cycles) initialized by RESET. Note that this initial

WATCHDOG service may be programmed within the ini-

tial 256 instruction cycles without causing a WATCHDOG

error.

•In order to RESET the device on the occurrence of a

WATCH event, the user must connect the WDOUT pin

(G1) pin to the RESET external to the device. The weak

pull-up on the WDOUT pin is sufficient to provide the RE-

SET connection to V

for devices which use both Power

On Reset and WATCHDOG.

10.4 DETECTION OF ILLEGAL CONDITIONS

The device can detect various illegal conditions resulting

from coding errors, transient noise, power supply voltage

drops, runaway programs, etc.

Reading of undefined ROM gets zeroes. The opcode for

software interrupt is 00. If the program fetches instructions

from undefined ROM, this will force a software interrupt, thus

signaling that an illegal condition has occurred.

The subroutine stack grows down for each call (jump to sub-

routine), interrupt, or PUSH, and grows up for each return or

POP.The stack pointer is initialized to RAM location 06F Hex

during reset. Consequently, if there are more returns than

calls, the stack pointer will point to addresses 070 and 071

Hex (which are undefined RAM). Undefined RAM from ad-

dresses 070 to 07F (Segment 0), and all other segments

(i.e., Segments 4 … etc.) is read as all 1’s, which in turn will

cause the program to return to address 7FFF Hex. This is an

undefined ROM location and the instruction fetched (all 0’s)

from this location will generate a software interrupt signaling

an illegal condition.

Thus, the chip can detect the following illegal conditions:

1. Executing from undefined ROM

2. Over “POP”ing the stack by having more returns than

calls.

When the software interrupt occurs, the user can re-initialize

the stack pointer and do a recovery procedure before restart-

ing (this recovery program is probably similar to that follow-

ing reset, but might not contain the same program initializa-

tion procedures). The recovery program should reset the

software interrupt pending bit using the RPND instruction.

11.0 MICROWIRE/PLUS

MICROWIRE/PLUS is a serial SPI compatible synchronous

communications interface. The MICROWIRE/PLUS capabil-

ity enables the device to interface with MICROWIRE/PLUS

or SPI peripherals (i.e. A/D converters, display drivers, EE-

PROMs etc.) and with other microcontrollers which support

the MICROWIRE/PLUS or SPI interface. It consists of an

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11.0 MICROWIRE/PLUS (Continued)

8-bit serial shift register (SIO) with serial data input (SI), se-

rial data output (SO) and serial shift clock (SK).

Figure 24

shows a block diagram of the MICROWIRE/PLUS logic.

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS ar-

rangement with the internal clock source is called the Master

mode of operation. Similarly, operating the MICROWIRE/

PLUS arrangement with an external shift clock is called the

Slave mode of operation.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,

the MSEL bit in the CNTRL register is set to one. In the mas-

ter mode, the SK clock rate is selected by the two bits, SL0

and SL1, in the CNTRL register.

Table 9

details the different

clock rates that may be selected.

TABLE 9. MICROWIRE/PLUS

Master Mode Clock Select

SL1 SL0 SK Period

0 0 2xt

0 1 4xt

1 x 8xt

Where tCis the instruction cycle clock

11.1 MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave.

Figure 24

shows how

two microcontroller devices and several peripherals may be

interconnected using the MICROWIRE/PLUS arrangements.

WARNING

The SIO register should only be loaded when the SK clock is

in the idle phase. Loading the SIO register while the SK clock

is in the active phase, will result in undefined data in the SIO

Setting the BUSY flag when the input SK clock is in the ac-

tive phase while in the MICROWIRE/PLUS is in the slave

mode may cause the current SK clock for the SIO shift reg-

ister to be narrow. For safety, the BUSY flag should only be

set when the input SK clock is in the idle phase.

11.1.1 MICROWIRE/PLUS Master Mode Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE

Master always initiates all data exchanges. The MSEL bit in

the CNTRL register must be set to enable the SO and SK

functions onto the G Port. The SO and SK pins must also be

selected as outputs by setting appropriate bits in the Port G

configuration register. In the slave mode, the shift clock

stops after 8 clock pulses.

Table 10

summarizes the bit set-

tings required for Master mode of operation.

DS012838-32

FIGURE 24. MICROWIRE/PLUS Application

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11.0 MICROWIRE/PLUS (Continued)

11.1.2 MICROWIRE/PLUS Slave Mode Operation

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and re-

setting the appropriate bits in the Port G configuration regis-

ter.

Table 10

summarizes the settings required to enter the

Slave mode of operation.

This table assumes that the control flag MSEL is set.

TABLE 10. MICROWIRE/PLUS Mode Settings

G4 (SO) G5 (SK) G4 G5 Operation

Config. Bit Config. Bit Fun. Fun.

1 1 SO Int. MICROWIRE/PLUS

SK Master

0 1 TRI- Int. MICROWIRE/PLUS

STATE SK Master

1 0 SO Ext. MICROWIRE/PLUS

SK Slave

0 0 TRI- Ext. MICROWIRE/PLUS

STATE SK Slave

The user must set the BUSY flag immediately upon entering

the Slave mode. This ensures that all data bits sent by the

Master is shifted properly. After eight clock pulses the BUSY

flag is clear, the shift clock is stopped, and the sequence

may be repeated.

10.1.3 Alternate SK Phase Operation

and SK Idle Polarity

The device allows either the normal SK clock or an alternate

phase SK clock to shift data in and out of the SIO register. In

both the modes the SK idle polarity can be either high or low.

The polarity is selected by bit 5 of Port G data register. In the

normal mode data is shifted in on the rising edge of the SK

clock and the data is shifted out on the falling edge of the SK

clock. The SIO register is shifted on each falling edge of the

SK clock. In the alternate SK phase operation, data is shifted

in on the falling edge of the SK clock and shifted out on the

rising edge of the SK clock. Bit 6 of Port G configuration reg-

ister selects the SK edge.

A control flag, SKSEL, allows either the normal SK clock or

the alternate SK clock to be selected. Resetting SKSEL

causes the MICROWIRE/PLUS logic to be clocked from the

normal SK signal. Setting the SKSEL flag selects the alter-

nate SK clock. The SKSEL is mapped into the G6 configura-

tion bit. The SKSEL flag will power up in the reset condition,

selecting the normal SK signal.

TABLE 11. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase

Port G SO Clocked Out On: SI Sampled On: SK Idle

Phase

SK Phase G6 (SKSEL) G5

Config. Bit Data Bit

Normal 0 0 SK Falling Edge SK Rising Edge Low

Alternate 1 0 SK Rising Edge SK Falling Edge Low

Alternate 0 1 SK Rising Edge SK Falling Edge High

Normal 1 1 SK Falling Edge SK Rising Edge High

DS012838-33

FIGURE 25. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low

DS012838-34

FIGURE 26. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low

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11.0 MICROWIRE/PLUS (Continued)

DS012838-35

FIGURE 27. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High

DS012838-31

FIGURE 28. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High

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12.0 Memory Map

All RAM, ports and registers (except A and PC) are mapped into data memory address space.

RAM Address Contents

Select ADD REG

64 On-Chip RAM Bytes. 02 to 2F On-Chip RAM (48 Bytes)

(COP8SAAx) 30 to 7F Unused RAM (Reads as all ones)

128 On-Chip RAM Bytes 00 to 6F On-Chip RAM (112 Bytes)

COP8SABx/SACx 70 to 7F Unused RAM (Reads as all ones)

80 to 93 Reserved

94 Port F Data Register

95 Port F Configuration Register

96 Port F Input Pins (Read Only)

97 Reserved

A0 to C6 Reserved

C7 WATCHDOG Service Register (Reg: WDSVR)

C8 MIWU Edge Select Register (Reg: WKEDG)

C9 MIWU Enable Register (Reg: WKEN)

CA MIWU Pending Register (Reg: WKPND)

CB to CF Reserved

D0 Port L Data Register

D1 Port L Configuration Register

D2 Port L Input Pins (Read Only)

D3 Reserved

D4 Port G Data Register

D5 Port G Configuration Register

D6 Port G Input Pins (Read Only)

D7 Reserved

D8 Port C Data Register

D9 Port C Configuration Register

DA Port C Input Pins (Read Only)

DB Reserved

DC Port D

DD to DF Reserved

E0 to E5 Reserved

E6 Timer T1 Autoload Register T1RB Lower Byte

E7 Timer T1 Autoload Register T1RB Upper Byte

E8 ICNTRL Register

E9 MICROWIRE/PLUS Shift Register

EA Timer T1 Lower Byte

EB Timer T1 Upper Byte

EC Timer T1 Autoload Register T1RA Lower Byte

ED Timer T1 Autoload Register T1RA Upper Byte

EE CNTRL Control Register

EF PSW Register

F0 to FB On-Chip RAM Mapped as Registers

FC X Register

FD SP Register

FE B Register

FF Reserved (Segment Register)

Reading any undefined memory location in the address range of 0080H–00FFH will return undefined data.

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13.0 Instruction Set

13.1 INTRODUCTION

This section defines the instruction set of the COP8SAx

Family members. It contains information about the instruc-

tion set features, addressing modes and types.

13.2 INSTRUCTION FEATURES

The strength of the instruction set is based on the follow-

ing features:

•Mostly single-byte opcode instructions minimize pro-

gram size.

•One instruction cycle for the majority of single-byte in-

structions to minimize program execution time.

•Many single-byte, multiple function instructions such

as DRSZ.

•Three memory mapped pointers: two for register indi-

rect addressing, and one for the software stack.

•Sixteen memory mapped registers that allow an opti-

mized implementation of certain instructions.

•Ability to set, reset, and test any individual bit in data

memory address space, including the

memory-mapped I/O ports and registers.

•Register-Indirect LOAD and EXCHANGE instructions

with optional automatic post-incrementing or decre-

menting of the register pointer. This allows for greater

efficiency (both in cycle time and program code) in

loading, walking across and processing fields in data

memory.

•Unique instructions to optimize program size and

throughput efficiency. Some of these instructions are

DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.

12.3 ADDRESSING MODES

The instruction set offers a variety of methods for specify-

ing memory addresses. Each method is called an ad-

dressing mode. These modes are classified into two cat-

egories: operand addressing modes and

transfer-of-control addressing modes. Operand address-

ing modes are the various methods of specifying an ad-

dress for accessing (reading or writing) data.

Transfer-of-control addressing modes are used in con-

junction with jump instructions to control the execution se-

quence of the software program.

13.3.1 Operand Addressing Modes

The operand of an instruction specifies what memory lo-

cation is to be affected by that instruction. Several differ-

ent operand addressing modes are available, allowing

memory locations to be specified in a variety of ways. An

instruction can specify an address directly by supplying

the specific address, or indirectly by specifying a register

pointer. The contents of the register (or in some cases,

two registers) point to the desired memory location. In the

immediate mode, the data byte to be used is contained in

the instruction itself.

Each addressing mode has its own advantages and dis-

advantages with respect to flexibility, execution speed,

and program compactness. Not all modes are available

with all instructions. The Load (LD) instruction offers the

largest number of addressing modes.

The available addressing modes are:

•Direct

•Register B or X Indirect

•Register B or X Indirect with Post-Incrementing/

Decrementing

•Immediate

•Immediate Short

•Indirect from Program Memory

The addressing modes are described below. Each de-

scription includes an example of an assembly language

instruction using the described addressing mode.

Direct. The memory address is specified directly as a byte

in the instruction. In assembly language, the direct ad-

dress is written as a numerical value (or a label that has

been defined elsewhere in the program as a numerical

value).

Example: Load Accumulator Memory Direct

LD A,05

Reg/Data Contents Contents

Memory Before After

Accumulator XX Hex A6 Hex

Memory Location A6 Hex A6 Hex

0005 Hex

by the contents of the B Register or X register (pointer regis-

ter). In assembly language, the notation [B] or [X] specifies

which register serves as the pointer.

Example: Exchange Memory with Accumulator, B Indirect

X A,[B]

Reg/Data Contents Contents

Memory Before After

Accumulator 01 Hex 87 Hex

Memory Location 87 Hex 01 Hex

0005 Hex

B Pointer 05 Hex 05 Hex

Decrementing. The relevant memory address is specified

by the contents of the B Register or X register (pointer regis-

ter). The pointer register is automatically incremented or

decremented after execution, allowing easy manipulation of

memory blocks with software loops. In assembly language,

the notation [B+], [B−], [X+], or [X−] specifies which register

serves as the pointer, and whether the pointer is to be incre-

mented or decremented.

Example: Exchange Memory with Accumulator, B Indirect

with Post-Increment

X A,[B+]

Reg/Data Contents Contents

Memory Before After

Accumulator 03 Hex 62 Hex

Memory Location 62 Hex 03 Hex

0005 Hex

B Pointer 05 Hex 06 Hex

Intermediate. The data for the operation follows the instruc-

tion opcode in program memory. In assembly language, the

number sign character (#) indicates an immediate operand.

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13.0 Instruction Set (Continued)

Example: Load Accumulator Immediate

LD A,#05

Reg/Data Contents Contents

Memory Before After

Accumulator XX Hex 05 Hex

Immediate Short. This is a special case of an immediate in-

struction. In the “Load B immediate” instruction, the 4-bit im-

mediate value in the instruction is loaded into the lower

nibble of the B register. The upper nibble of the B register is

reset to 0000 binary.

Example: Load B Register Immediate Short

LD B,#7

Reg/Data Contents Contents

Memory Before After

B Pointer 12 Hex 07 Hex

Indirect from Program Memory. This is a special case of

an indirect instruction that allows access to data tables

stored in program memory. In the “Load Accumulator Indi-

rect” (LAID) instruction, the upper and lower bytes of the Pro-

gram Counter (PCU and PCL) are used temporarily as a

pointer to program memory. For purposes of accessing pro-

gram memory, the contents of the Accumulator and PCL are

exchanged. The data pointed to by the Program Counter is

loaded into theAccumulator, and simultaneously, the original

contents of PCL are restored so that the program can re-

sume normal execution.

Example: Load Accumulator Indirect

LAID

Reg/Data Contents Contents

Memory Before After

PCU 04 Hex 04 Hex

PCL 35 Hex 36 Hex

Accumulator 1F Hex 25 Hex

Memory Location 25 Hex 25 Hex

041F Hex

13.3.2 Tranfer-of-Control Addressing Modes

Program instructions are usually executed in sequential or-

der. However, Jump instructions can be used to change the

normal execution sequence. Several transfer-of-control ad-

dressing modes are available to specify jump addresses.

A change in program flow requires a non-incremental

change in the Program Counter contents. The Program

Counter consists of two bytes, designated the upper byte

(PCU) and lower byte (PCL). The most significant bit of PCU

is not used, leaving 15 bits to address the program memory.

Different addressing modes are used to specify the new ad-

dress for the Program Counter. The choice of addressing

mode depends primarily on the distance of the jump. Farther

jumps sometimes require more instruction bytes in order to

completely specify the new Program Counter contents.

The available transfer-of-control addressing modes are:

•Jump Relative

•Jump Absolute

•Jump Absolute Long

•Jump Indirect

The transfer-of-control addressing modes are described be-

low. Each description includes an example of a Jump in-

struction using a particular addressing mode, and the effect

on the Program Counter bytes of executing that instruction.

Jump Relative. In this 1-byte instruction, six bits of the in-

struction opcode specify the distance of the jump from the

current program memory location. The distance of the jump

can range from −31 to +32.A JP+1 instruction is not allowed.

The programmer should use a NOP instead.

Example: Jump Relative

JP 0A

Reg Contents Contents

Before After

PCU 02 Hex 02 Hex

PCL 05 Hex 0F Hex

Jump Absolute. In this 2-byte instruction, 12 bits of the in-

struction opcode specify the new contents of the Program

Counter. The upper three bits of the Program Counter re-

main unchanged, restricting the new Program Counter ad-

dress to the same 4 kbyte address space as the current in-

struction.

(This restriction is relevant only in devices using more than

one 4 kbyte program memory space.)

Example: Jump Absolute

JMP 0125

Reg Contents Contents

Before After

PCU 0C Hex 01 Hex

PCL 77 Hex 25 Hex

Jump Absolute Long. In this 3-byte instruction, 15 bits of

the instruction opcode specify the new contents of the Pro-

gram Counter.

Example: Jump Absolute Long

JMP 03625

Reg/ Contents Contents

Memory Before After

PCU 42 Hex 36 Hex

PCL 36 Hex 25 Hex

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13.0 Instruction Set (Continued)

Jump Indirect. In this 1-byte instruction, the lower byte of

the jump address is obtained from a table stored in program

memory, with the Accumulator serving as the low order byte

of a pointer into program memory. For purposes of access-

ing program memory, the contents of the Accumulator are

written to PCL (temporarily). The data pointed to by the Pro-

gram Counter (PCH/PCL) is loaded into PCL, while PCH re-

mains unchanged.

Example: Jump Indirect

JID

Reg/ Contents Contents

Memory Before After

PCU 01 Hex 01 Hex

PCL C4 Hex 32 Hex

Accumulator 26 Hex 26 Hex

Memory

Location 32 Hex 32 Hex

0126 Hex

The VIS instruction is a special case of the Indirect Transfer

of Control addressing mode, where the double-byte vector

associated with the interrupt is transferred from adjacent ad-

dresses in program memory into the Program Counter in or-

der to jump to the associated interrupt service routine.

13.4 INSTRUCTION TYPES

The instruction set contains a wide variety of instructions.

The available instructions are listed below, organized into re-

lated groups.

Some instructions test a condition and skip the next instruc-

tion if the condition is not true. Skipped instructions are ex-

ecuted as no-operation (NOP) instructions.

13.4.1 Arithmetic Instructions

The arithmetic instructions perform binary arithmetic such as

addition and subtraction, with or without the Carry bit.

Add (ADD)

Add with Carry (ADC)

Subtract (SUB)

Subtract with Carry (SUBC)

Increment (INC)

Decrement (DEC)

Decimal Correct (DCOR)

Clear Accumulator (CLR)

Set Carry (SC)

Reset Carry (RC)

13.4.2 Transfer-of-Control Instructions

The transfer-of-control instructions change the usual se-

quential program flow by altering the contents of the Pro-

gram Counter. The Jump to Subroutine instructions save the

Program Counter contents on the stack before jumping; the

Return instructions pop the top of the stack back into the

Program Counter.

Jump Relative (JP)

Jump Absolute (JMP)

Jump Absolute Long (JMPL)

Jump Indirect (JID)

Jump to Subroutine (JSR)

Jump to Subroutine Long (JSRL)

Return from Subroutine (RET)

Return from Subroutine and Skip (RETSK)

Return from Interrupt (RETI)

Software Trap Interrupt (INTR)

Vector Interrupt Select (VIS)

13.4.3 Load and Exchange Instructions

The load and exchange instructions write byte values in reg-

isters or memory. The addressing mode determines the

source of the data.

Load (LD)

Load Accumulator Indirect (LAID)

Exchange (X)

13.4.4 Logical Instructions

The logical instructions perform the operations AND, OR,

and XOR (Exclusive OR). Other logical operations can be

performed by combining these basic operations. For ex-

ample, complementing is accomplished by exclusiveORing

the Accumulator with FF Hex.

Logical AND (AND)

Logical OR (OR)

Exclusive OR (XOR)

13.4.5 Accumulator Bit Manipulation Instructions

The Accumulator bit manipulation instructions allow the user

to shift the Accumulator bits and to swap its two nibbles.

Rotate Right Through Carry (RRC)

Rotate Left Through Carry (RLC)

Swap Nibbles of Accumulator (SWAP)

13.4.6 Stack Control Instructions

Push Data onto Stack (PUSH)

Pop Data off of Stack (POP)

13.4.7 Memory Bit Manipulation Instructions

The memory bit manipulation instructions allow the user to

set and reset individual bits in memory.

Set Bit (SBIT)

Reset Bit (RBIT)

Reset Pending Bit (RPND)

13.4.8 Conditional Instructions

The conditional instruction test a condition. If the condition is

true, the next instruction is executed in the normal manner; if

the condition is false, the next instruction is skipped.

If Equal (IFEQ)

If Not Equal (IFNE)

If Greater Than (IFGT)

If Carry (IFC)

If Not Carry (IFNC)

If Bit (IFBIT)

If B Pointer Not Equal (IFBNE)

And Skip if Zero (ANDSZ)

Decrement Register and Skip if Zero (DRSZ)

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13.0 Instruction Set (Continued)

13.4.9 No-Operation Instruction

The no-operation instruction does nothing, except to occupy

space in the program memory and time in execution.

No-Operation (NOP)

Note: The VIS is a special case of the Indirect Transfer of Control addressing

mode, where the double byte vector associated with the interrupt is

transferred from adjacent addresses in the program memory into the

program counter (PC) in order to jump to the associated interrupt ser-

vice routine.

13.5 REGISTER AND SYMBOL DEFINITION

The following abbreviations represent the nomenclature

used in the instruction description and the COP8

cross-assembler.

Registers

A 8-Bit Accumulator Register

B 8-Bit Address Register

X 8-Bit Address Register

SP 8-Bit Stack Pointer Register

PC 15-Bit Program Counter Register

PU Upper 7 Bits of PC

PL Lower 8 Bits of PC

C 1 Bit of PSW Register for Carry

HC 1 Bit of PSW Register for Half Carry

GIE 1 Bit of PSW Register for Global Interrupt

Enable

VU Interrupt Vector Upper Byte

VL Interrupt Vector Lower Byte

Symbols

[B] Memory Indirectly Addressed by B Register

[X] Memory Indirectly Addressed by X Register

MD Direct Addressed Memory

Mem Direct Addressed Memory or [B]

Meml Direct Addressed Memory or [B] or

Immediate Data

Imm 8-Bit Immediate Data

Reg Register Memory: Addresses F0 to FF

(Includes B, X and SP)

Bit Bit Number (0 to 7)

←Loaded with

↔Exchanged with

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13.0 Instruction Set (Continued)

13.6 INSTRUCTION SET SUMMARY

ADD A,Meml ADD A←A + Meml

ADC A,Meml ADD with Carry A←A+Meml+C,C

←

Carry,

HC←Half Carry

SUBC A,Meml Subtract with Carry A←A−MemI+C,C

←

Carry,

HC←Half Carry

AND A,Meml Logical AND A←A and Meml

ANDSZ A,Imm Logical AND Immed., Skip if Zero Skip next if (A and Imm) =0

OR A,Meml Logical OR A←A or Meml

XOR A,Meml Logical EXclusive OR A←A xor Meml

IFEQ MD,Imm IF EQual Compare MD and Imm, Do next if MD =Imm

IFEQ A,Meml IF EQual Compare A and Meml, Do next if A =Meml

IFNE A,Meml IF Not Equal Compare A and Meml, Do next if A ≠Meml

IFGT A,Meml IF Greater Than Compare A and Meml, Do next if A >Meml

IFBNE #If B Not Equal Do next if lower 4 bits of B ≠Imm

DRSZ Reg Decrement Reg., Skip if Zero Reg←Reg − 1, Skip if Reg =0

SBIT #,Mem Set BIT 1 to bit, Mem (bit =0 to 7 immediate)

RBIT #,Mem Reset BIT 0 to bit, Mem

IFBIT #,Mem IF BIT If bit #, A or Mem is true do next instruction

RPND Reset PeNDing Flag Reset Software Interrupt Pending Flag

X A,Mem EXchange A with Memory A↔Mem

X A,[X] EXchange A with Memory [X] A↔[X]

LD A,Meml LoaD A with Memory A←Meml

LD A,[X] LoaD A with Memory [X] A←[X]

LD B,Imm LoaD B with Immed. B←Imm

LD Mem,Imm LoaD Memory Immed. Mem←Imm

LD Reg,Imm LoaD Register Memory Immed. Reg←Imm

XA,[B

] EXchange A with Memory [B] A↔[B], (B←B±1)

XA,[X

] EXchange A with Memory [X] A↔[X], (X←X±1)

LD A, [B±] LoaD A with Memory [B] A←[B], (B←B±1)

LD A, [X±] LoaD A with Memory [X] A←[X], (X←X±1)

LD [B±],Imm LoaD Memory [B] Immed. [B]←Imm, (B←B±1)

CLR A CLeaR A A←0

INC A INCrement A A←A+1

DEC A DECrement A A←A−1

LAID Load A InDirect from ROM A←ROM (PU,A)

DCOR A Decimal CORrect A A←BCD correction of A (follows ADC, SUBC)

RRC A Rotate A Right thru C C→A7→…→A0→C

RLC A Rotate A Left thru C C←A7←…←A0←C, HC←A0

SWAP A SWAP nibbles of A A7…A4↔A3…A0

SC Set C C←1, HC←1

RC Reset C C←0, HC←0

IFC IF C IF C is true, do next instruction

IFNC IF Not C If C is not true, do next instruction

POP A POP the stack into A SP←SP+1,A

←

[SP]

PUSH A PUSH A onto the stack [SP]←A, SP←SP−1

VIS Vector to Interrupt Service Routine PU←[VU], PL←[VL]

JMPL Addr. Jump absolute Long PC←ii (ii =15 bits, 0 to 32k)

JMP Addr. Jump absolute PC9…0←i(i=12 bits)

JP Disp. Jump relative short PC←PC+r(ris−31to+32, except 1)

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13.0 Instruction Set (Continued)

JSRL Addr. Jump SubRoutine Long [SP]←PL, [SP−1]←PU,SP−2, PC←ii

JSR Addr. Jump SubRoutine [SP]←PL, [SP−1]←PU,SP−2, PC9…0←i

JID Jump InDirect PL←ROM (PU,A)

RET RETurn from subroutine SP + 2, PL←[SP], PU←[SP−1]

RETSK RETurn and SKip SP + 2, PL←[SP],PU←[SP−1],

skip next instruction

RETI RETurn from Interrupt SP + 2, PL ←[SP],PU←[SP−1],GIE←1

INTR Generate an Interrupt [SP]←PL, [SP−1]←PU, SP−2, PC←0FF

NOP No OPeration PC←PC+1

13.7 INSTRUCTION EXECUTION TIME

Most instructions are single byte (with immediate addressing

mode instructions taking two bytes).

Most single byte instructions take one cycle time to execute.

Skipped instructions require x number of cycles to be

skipped, where x equals the number of bytes in the skipped

instruction opcode.

See the BYTES and CYCLES per INSTRUCTION table for

details.

Bytes and Cycles per Instruction

The following table shows the number of bytes and cycles for

each instruction in the format of byte/cycle.

Arithmetic and Logic Instructions

[B] Direct Immed.

ADD 1/1 3/4 2/2

ADC 1/1 3/4 2/2

SUBC 1/1 3/4 2/2

AND 1/1 3/4 2/2

OR 1/1 3/4 2/2

XOR 1/1 3/4 2/2

IFEQ 1/1 3/4 2/2

IFGT 1/1 3/4 2/2

IFBNE 1/1

DRSZ 1/3

SBIT 1/1 3/4

RBIT 1/1 3/4

IFBIT 1/1 3/4

RPND 1/1

Instructions Using A & C

CLRA 1/1

INCA 1/1

DECA 1/1

LAID 1/3

DCORA 1/1

RRCA 1/1

RLCA 1/1

SWAPA 1/1

SC 1/1

RC 1/1

IFC 1/1

IFNC 1/1

PUSHA 1/3

POPA 1/3

ANDSZ 2/2

Transfer of Control Instructions

JMPL 3/4

JMP 2/3

JP 1/3

JSRL 3/5

JSR 2/5

JID 1/3

VIS 1/5

RET 1/5

RETSK 1/5

RETI 1/5

INTR 1/7

NOP 1/1

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13.0 Instruction Set (Continued)

Memory Transfer Instructions

Indirect Auto Incr. & Decr.

[B] [X] [B+, B−] [X+, X−]

X A, (Note 21) 1/1 1/3 2/3 1/2 1/3

LD A, (Note 21) 1/1 1/3 2/3 2/2 1/2 1/3

LD B, Imm 1/1 (If B <16)

LD B, Imm 2/2 (If B >15)

LD Mem, Imm 2/2 3/3 2/2

LD Reg, Imm 2/3

IFEQ MD, Imm 3/3

Note 21: =>Memory location addressed by B or X or directly.

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13.8 OPCODE TABLE

Upper Nibble

F E D C BA9 876 5 4 3 2 10

Lower Nibble

JP−15 JP−31 LD 0F0, #i DRSZ

0F0 RRCA RC ADC

A,#i ADC

A,[B] IFBIT

0,[B] ANDSZ

A, #i LD

B,#0F IFBNE 0 JSR

x000–x0FF JMP

x000–x0FF JP+17 INTR 0

JP−14 JP−30 LD 0F1, #i DRSZ

0F1 * SC SUBC

A, #i SUBC

A,[B] IFBIT

1,[B] *LD

B,#0E IFBNE 1 JSR

x100–x1FF JMP

x100–x1FF JP+18 JP+2 1

JP−13 JP−29 LD 0F2, #i DRSZ

0F2 X

A,[X+] X

A,[B+] IFEQ

A,#i IFEQ

A,[B] IFBIT

2,[B] *LD

B,#0D IFBNE 2 JSR

x200–x2FF JMP

x200–x2FF JP+19 JP+3 2

JP−12 JP−28 LD 0F3, #i DRSZ

0F3 X

A,[X−] X

A,[B−] IFGT

A,#i IFGT

A,[B] IFBIT

3,[B] *LD

B,#0C IFBNE 3 JSR

x300–x3FF JMP

x300–x3FF JP+20 JP+4 3

JP−11 JP−27 LD 0F4, #i DRSZ

0F4 VIS LAID ADD

A,#i ADD

A,[B] IFBIT

4,[B] CLRA LD

B,#0B IFBNE 4 JSR

x400–x4FF JMP

x400–x4FF JP+21 JP+5 4

JP−10 JP−26 LD 0F5, #i DRSZ

0F5 RPND JID AND

A,#i AND

A,[B] IFBIT

5,[B] SWAPA LD

B,#0A IFBNE 5 JSR

x500–x5FF JMP

x500–x5FF JP+22 JP+6 5

JP−9 JP−25 LD 0F6, #i DRSZ

0F6 X A,[X] X

A,[B] XOR

A,#i XOR

A,[B] IFBIT

6,[B] DCORA LD

B,#09 IFBNE 6 JSR

x600–x6FF JMP

x600–x6FF JP+23 JP+7 6

JP−8 JP−24 LD 0F7, #i DRSZ

0F7 * * OR A,#i OR

A,[B] IFBIT

7,[B] PUSHA LD

B,#08 IFBNE 7 JSR

x700–x7FF JMP

x700–x7FF JP+24 JP+8 7

JP−7 JP−23 LD 0F8, #i DRSZ

0F8 NOP RLCA LD A,#i IFC SBIT

0,[B] RBIT

0,[B] LD

B,#07 IFBNE 8 JSR

x800–x8FF JMP

x800–x8FF JP+25 JP+9 8

JP−6 JP−22 LD 0F9, #i DRSZ

0F9 IFNE

A,[B] IFEQ

Md,#i IFNE

A,#i IFNC SBIT

1,[B] RBIT

1,[B] LD

B,#06 IFBNE 9 JSR

x900–x9FF JMP

x900–x9FF JP+26 JP+10 9

JP−5 JP−21 LD 0FA, #i DRSZ

0FA LD

A,[X+] LD

A,[B+] LD

[B+],#i INCA SBIT

2,[B] RBIT

2,[B] LD

B,#05 IFBNE 0A JSR

xA00–xAFF JMP

xA00–xAFF JP+27 JP+11 A

JP−4 JP−20 LD 0FB, #i DRSZ

0FB LD

A,[X−] LD

A,[B−] LD

[B−],#i DECA SBIT

3,[B] RBIT

3,[B] LD

B,#04 IFBNE 0B JSR

xB00–xBFF JMP

xB00–xBFF JP+28 JP+12 B

JP−3 JP−19 LD 0FC, #i DRSZ

0FC LD

Md,#i JMPL X A,Md POPA SBIT

4,[B] RBIT

4,[B] LD

B,#03 IFBNE 0C JSR

xC00–xCFF JMP

xC00–xCFF JP+29 JP+13 C

JP−2 JP−18 LD 0FD, #i DRSZ

0FD DIR JSRL LD

A,Md RETSK SBIT

5,[B] RBIT

5,[B] LD

B,#02 IFBNE 0D JSR

xD00–xDFF JMP

xD00–xDFF JP+30 JP+14 D

JP−1 JP−17 LD 0FE, #i DRSZ

0FE LD

A,[X] LD

A,[B] LD

[B],#i RET SBIT

6,[B] RBIT

6,[B] LD

B,#01 IFBNE 0E JSR

xE00–xEFF JMP

xE00–xEFF JP+31 JP+15 E

JP−0 JP−16 LD 0FF, #i DRSZ

0FF * * LD B,#i RETI SBIT

7,[B] RBIT

7,[B] LD

B,#00 IFBNE 0F JSR

xF00–xFFF JMP

xF00–xFFF JP+32 JP+16 F

Where,

i is the immediate data

Md is a directly addressed memory location

* is an unused opcode

The opcode 60 Hex is also the opcode for IFBIT #i,A

www.national.com49

14.0 Mask Options

For mask options invormation on COP8SAx5 devices,

please refer to Section 6.4 ECON (CONFIGURATION) REG-

ISTER.

15.0 Development Tools Support

15.1 OVERVIEW

National is engaged with an international community of inde-

pendent 3rd party vendors who provide hardware and soft-

ware development tool support. Through National’s interac-

tion and guidance, these tools cooperate to form a choice of

solutions that fits each developer’s needs.

This section provides a summary of the tool and develop-

ment kits currently available. Up-to-date information, selec-

tion guides, free tools, demos, updates, and purchase infor-

mation can be obtained at our web site at:

www.national.com/cop8.

15.2 SUMMARY OF TOOLS

COP8 Evaluation Tools

•COP8–NSEVAL: Free Software Evaluation package for

Windows. A fully integrated evaluation environment for

COP8, including versions of WCOP8 IDE (Integrated De-

velopment Environment), COP8-NSASM, COP8-MLSIM,

COP8C, DriveWay™COP8, Manuals, and other COP8

information.

•COP8–MLSIM: Free Instruction Level Simulator tool for

Windows. For testing and debugging software instruc-

tions only (No I/O or interrupt support).

•COP8–EPU: Very Low cost COP8 Evaluation & Pro-

gramming Unit. Windows based evaluation and

hardware-simulation tool, with COP8 device programmer

and erasable samples. Includes COP8-NSDEV, Drive-

way COP8 Demo, MetaLink Debugger, I/O cables and

power supply.

•COP8–EVAL-HIxx: Low cost target application evalua-

tion and development board for COP8Sx Families, from

Hilton Inc. Real-time environment with integrated A/D,

Temp Sensor, and Peripheral I/O.

•COP8–EVAL-ICUxx: Very Low cost evaluation and de-

sign test board for COP8ACC and COP8SGx Families,

from ICU. Real-time environment with add-on A/D, D/A,

and EEPROM. Includes software routines and reference

designs.

•Manuals,Applications Notes, Literature: Available free

from our web site at: www.national.com/cop8.

COP8 Integrated Software/Hardware Design Develop-

ment Kits

•COP8-EPU: Very Low cost Evaluation & Programming

Unit. Windows based development and hardware-

simulation tool for COPSx/xG families, with COP8 device

programmer and samples. Includes COP8-NSDEV,

Driveway COP8 Demo, MetaLink Debugger, cables and

power supply.

•COP8-DM: Moderate cost Debug Module from MetaLink.

A Windows based, real-time in-circuit emulation tool with

COP8 device programmer. Includes COP8-NSDEV,

DriveWay COP8 Demo, MetaLink Debugger, power sup-

ply, emulation cables and adapters.

COP8 Development Languages and Environments

•COP8-NSASM: Free COP8 Assembler v5 for Win32.

Macro assembler, linker, and librarian for COP8 software

development. Supports all COP8 devices. (DOS/Win16

v4.10.2 available with limited support). (Compatible with

WCOP8 IDE, COP8C, and DriveWay COP8).

•COP8-NSDEV: Very low cost Software Development

Package for Windows. An integrated development envi-

ronment for COP8, including WCOP8 IDE, COP8C (lim-

ited version), COP8-NSASM, COP8-MLSIM.

•COP8C: Moderately priced C Cross-Compiler and Code

Development System from Byte Craft (no code limit). In-

cludes BCLIDE (Byte Craft Limited Integrated Develop-

ment Environment) for Win32, editor, optimizing C Cross-

Compiler, macro cross assembler, BC-Linker, and

MetaLink tools support. (DOS/SUN versions available;

Compiler is installable under WCOP8 IDE; Compatible

with DriveWay COP8).

•EWCOP8-KS: Very Low cost ANSI C-Compiler and Em-

bedded Workbench from IAR (Kickstart version:

COP8Sx/Fx only with 2k code limit; No FP). A fully inte-

grated Win32 IDE, ANSI C-Compiler, macro assembler,

editor, linker, Liberian, C-Spy simulator/debugger, PLUS

MetaLink EPU/DM emulator support.

•EWCOP8-AS: Moderately priced COP8 Assembler and

Embedded Workbench from IAR (no code limit).Afully in-

tegrated Win32 IDE, macro assembler, editor, linker, li-

brarian, and C-Spy high-level simulator/debugger with

I/O and interrupts support. (Upgradeable with optional

C-Compiler and/or MetaLink Debugger/Emulator sup-

port).

•EWCOP8-BL: Moderately priced ANSI C-Compiler and

Embedded Workbench from IAR (Baseline version: All

COP8 devices; 4k code limit; no FP). A fully integrated

Win32 IDE, ANSI C-Compiler, macro assembler, editor,

linker, librarian, and C-Spy high-level simulator/debugger.

(Upgradeable; CWCOP8-M MetaLink tools interface sup-

port optional).

•EWCOP8: Full featured ANSI C-Compiler and Embed-

ded Workbench for Windows from IAR (no code limit). A

fully integrated Win32 IDE, ANSI C-Compiler, macro as-

sembler, editor, linker, librarian, and C-Spy high-level

simulator/debugger. (CWCOP8-M MetaLink tools inter-

face support optional).

•EWCOP8-M: Full featuredANSI C-Compiler and Embed-

ded Workbench for Windows from IAR (no code limit). A

fully integrated Win32 IDE, ANSI C-Compiler, macro as-

sembler, editor, linker, librarian, C-Spy high-level

simulator/debugger, PLUS MetaLink debugger/hardware

interface (CWCOP8-M).

COP8 Productivity Enhancement Tools

•WCOP8 IDE: Very Low cost IDE (Integrated Develop-

ment Environment) from KKD. Supports COP8C, COP8-

NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink

debugger under a common Windows Project Manage-

ment environment. Code development, debug, and emu-

lation tools can be launched from the project window

framework.

•DriveWay-COP8: Low cost COP8 Peripherals Code

Generation tool from Aisys Corporation. Automatically

generates tested and documented C or Assembly source

code modules containing I/O drivers and interrupt han-

dlers for each on-chip peripheral. Application specific

code can be inserted for customization using the inte-

grated editor. (Compatible with COP8-NSASM, COP8C,

and WCOP8 IDE.)

www.national.com 50

15.0 Development Tools Support

(Continued)

•COP8-UTILS: Free set of COP8 assembly code ex-

amples, device drivers, and utilities to speed up code de-

velopment.

•COP8-MLSIM: Free Instruction Level Simulator tool for

Windows. For testing and debugging software instruc-

tions only (No I/O or interrupt support).

COP8 Real-Time Emulation Tools

•COP8-DM: MetaLink Debug Module. A moderately

priced real-time in-circuit emulation tool, with COP8 de-

vice programmer. Includes MetaLink Debugger, power

supply, emulation cables and adapters.

•IM-COP8: MetaLink iceMASTER®. A full featured, real-

time in-circuit emulator for COP8 devices. Includes

COP8-NSDEV, Driveway COP8 Demo, MetaLink Win-

dows Debugger, and power supply. Package-specific

probes and surface mount adaptors are ordered sepa-

rately.

COP8 Device Programmer Support

•MetaLink’s EPU and Debug Module include development

device programming capability for COP8 devices.

•Third-party programmers and automatic handling equip-

ment cover needs from engineering prototype and pilot

production, to full production environments.

•Factory programming available for high-volume require-

ments.

15.3 TOOLS ORDERING NUMBERS FOR THE COP8SAx FAMILY DEVICES

Note: The following order numbers apply to the COP8 devices in this datasheet only.

Vendor Tools Order Number Cost Notes

National COP8-NSEVAL COP8-NSEVAL Free Web site download

COP8-NSASM COP8-NSASM Free Included in EPU and DM. Web site download

COP8-MLSIM COP8-MLSIM Free Included in EPU and DM. Web site download

COP8-NSDEV COP8-NSDEV VL Included in EPU and DM. Order CD from website

COP8-EPU COP8SA-EPU (-1 or -2) VL -1 = 110V, -2 = 220V; Included p/s, 40 pin DIP target

cable, manuals, software, 16/20/28/40 DIP OTP

programming socket; add DM target adapter or OTP

adapter (if needed)

COP8-DM COP8SA-DM (10 MHz) M Included p/s, 20/28/40 pin DIP target cables, 28 SOIC

converter, manuals, software, 16/20/28/40 DIP/SO and

44 PLCC programming socket; add OTP adapter or

target adapter (if needed)

DM Target

Adapters DM-COP8/20D-SO VL 20 pin DIP to SO converter

DM-COP8/20D-16D VL 20 pin DIP to 16 pin DIP converter

DM-COP8/44P VL 44 pin PLCC target cable

DM-COP8/28D-28CSP L 28 pin DIP to 28 pin CSP converter

DM-COP8/44P-44Q L 44 pin PLCC to 44 QFP converter

Development

Devices COP8SAx7 VL 4k Eraseable or OTP devices

OTP

Programming

Adapters

COP8SA-PGMA L For programming 16/20/28 SOIC and 44 PLCC on the

EPU

COP8-PGMA-44QFP L For programming 44 QFP on any programmer

COP8-PGMA-28CSP L For programming 28 CSP on any programmer

COP8-PGMA-28SO VL For programming 16/20/28 SOIC on any programmer

IM-COP8 Call MetaLink

www.national.com51

15.0 Development Tools Support (Continued)

MetaLink COP8-EPU EPU-COP8SA VL 1 = 110V, 2 = 220V; included p/s, 40 pin DIP target

cable, manuals, software, 16/20/28/40 DIP OTP

programming socket; add DM target adapter or OTP

adapter (if needed)

COP8-DM DM4-COP8-SAx (10

MHz), plus PS-10, plus

DM-COP8/xxx (ie. 28D)

M Included p/s (PS-10), target cable of choice (DIP or

PLCC; i.e. DM-COP8/28D), 16/20/28/40 DIP/SO and

44 PLCC programming sockets. Add OTP adapter (if

needed) and target adapter (if needed)

DM Target

Adapters MHW-CNVxx (xx = 33, 34

etc.) L DM target converters for

16DIP/20SO/28SO/44QFP/28CSP; (i.e. MHW-CNV38

for 20 pin DIP to SO package converter)

OTP

Programming

Adapters

MHW-COP8-PGMA-DS L For programming 16/20/28 SOIC and 44 PLCC on the

EPU

MHW-COP8-PGMA-44QFP L For programming 44 QFP on any programmer

MHW-COP8-PGMA-28CSP L For programming 28 CSP on any programmer

IM-COP8 IM-COP8-AD-464 (-220)

(10 MHz maximum) H Base unit 10 MHz; -220 = 220V; add probe card

(required) and target adapter (if needed); included

software and manuals

IM Probe Card PC-COP8SA28DW-AD-10 M 10 MHz 28 DIP probe card; 2.5V to 6.0V

PC-COP8SA40DW-AD-10 M 10 MHz 40 DIP probe card; 2.5V to 6.0V

IM Probe Target

Adapters MHW-SOICxx (xx = 16,

20, 28) L 16 or 20 or 28 pin SOIC adapter for probe card

MHW-CSPxx (xx = 20,

28) M 20 or 28 pin CSP adapter for probe card

MHW-CONV33 L 44 pin QFP adapter for 44 PLCC probe card

ICU COP8-EVAL-ICUxx Not available for this device

KKD WCOP8-IDE WCOP8-IDE VL Included in EPU and DM

IAR EWCOP8-xx See summary above L - H Included all software and manuals

Byte

Craft COP8C COP8C M Included all software and manuals

Aisys DriveWay COP8 DriveWay COP8 L Included all software and manuals

OTP Programmers Contact vendors L - H For approved programmer listings and vendor

information go to our OTP Support page at:

www.national.com/cop8

Cost: Free; VL =<$100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k

www.national.com 52

15.0 Development Tools Support (Continued)

15.4 WHERE TO GET TOOLS

Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.

Vendor Home Office Electronic Sites Other Main Offices

Aisys U.S.A.: Santa Clara, CA www.aisysinc.com Distributors

1-408-327-8820 info@aisysinc.com

fax: 1-408-327-8830

Byte Craft U.S.A. www.bytecraft.com Distributors

1-519-888-6911 info@bytecraft.com

fax: 1-519-746-6751

IAR Sweden: Uppsala www.iar.se U.S.A.: San Francisco

+46 18 16 78 00 info@iar.se 1-415-765-5500

fax: +46 18 16 78 38 info@iar.com fax: 1-415-765-5503

info@iarsys.co.uk U.K.: London

info@iar.de +44 171 924 33 34

fax: +44 171 924 53 41

Germany: Munich

+49 89 470 6022

fax: +49 89 470 956

ICU Sweden: Polygonvaegen www.icu.se Switzeland: Hoehe

+46 8 630 11 20 support@icu.se +41 34 497 28 20

fax: +46 8 630 11 70 support@icu.ch fax: +41 34 497 28 21

KKD Denmark: www.kkd.dk

MetaLink U.S.A.: Chandler, AZ www.metaice.com Germany: Kirchseeon

1-800-638-2423 sales@metaice.com 80-91-5696-0

fax: 1-602-926-1198 support@metaice.com fax: 80-91-2386

bbs: 1-602-962-0013 islanger@metalink.de

www.metalink.de Distributors Worldwide

National U.S.A.: Santa Clara, CA www.national.com/cop8 Europe: +49 (0) 180 530 8585

1-800-272-9959 support@nsc.com fax: +49 (0) 180 530 8586

fax: 1-800-737-7018 europe.support@nsc.com Distributors Worldwide

The following companies have approved COP8 program-

mers in a variety of configurations. Contact your local office

or distributor. You can link to their web sites and get the lat-

est listing of approved programmers from National’s COP8

OTP Support page at: www.national.com/cop8.

Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Sys-

tems; ICE Technology; Lloyd Research; Logical Devices;

MQP; Needhams; Phyton; SMS; Stag Programmers; Sys-

tem General; Tribal Microsystems; Xeltek.

15.5 CUSTOMER SUPPORT

Complete product information and technical support is avail-

able from National’s customer response centers, and from

our on-line COP8 customer support sites.

www.national.com53

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Hermetic Dual-In-Line Package, EPROM (D)

Order Number COP8SAC720Q3

NS Package Number D20CQ

www.national.com 54

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Small Outline Package (WM)

Order Number COP8SAA716M8 or COP8SAA716M9

NS Package Number M16B

Molded Dual-In-Line Package (N)

Order Number COP8SAA716N8 or COP8SAA716N9

NS Package Number N16A

www.national.com55

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded SO Wide Body Package (WM)

Order Number COP8SAA720M9, COP8SAB720M9, COP8SAC720M9

COP8SAA720M8, COP8SAB720M8 or COP8SAC720M8

NS Package Number M20B

Molded Dual-In-Line Package (N)

Order Number COP8SAA720N9, COP8SAB720N9, COP8SAC720N9,

COP8SAA720N8, COP8SAB720N8 or COP8SAC720N8

NS Package Number N20A

www.national.com 56

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Hermetic Dual-In-Line Package EPROM (D)

Order Number COP8SAC728Q3

NS Package Number D28JQ

www.national.com57

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded SO Wide Body Package (WM)

Order Number COP8SAA728M9, COP8SAB728M9, COP8SAC728M9,

COP8SAA728M8, COP8SAB728M8 or COP8SAC728M8

NS Package Number M28B

Molded Dual-In-Line Package (N),

Order Number COP8SAA728N9, COP8SAB728N9, COP8SAC728N9,

COP8SAA728N8, COP8SAB728N8 or COP8SAC728N8

NS Package Number N28B

www.national.com 58

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28 Lead Chip Scale Package (SLB)

Order Number COP8SAA7SLB8, COP8SAB7SLB8 or COP8SAC7SLB8

NS Package Number 28CSP

www.national.com59

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

40-Lead Hermetic DIP EPROM (D)

Order Number COP8SAC740Q3

NS Package Number D40KQ

Molded Dual-In-Line Package (N)

Order Number COP8SAC740N9 or COP8SAC740N8

NS Package Number N40A

www.national.com 60

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

44-Lead EPROM Leaded Chip Carrier (EL)

Order Number COP8SAC744Q3

NS Package Number EL44C

www.national.com61

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number COP8SAC744V9 or COP8SAC744V8

NS Package Number V44A

SLB package

www.national.com 62

Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe Fax: +49 (0) 1 80-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 1 80-530 85 85

English Tel: +49 (0) 1 80-532 78 32

Français Tel: +49 (0) 1 80-532 93 58

Italiano Tel: +49 (0) 1 80-534 16 80

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

Email: sea.support@nsc.com

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

www.national.com

COP8SAx Family, 8-Bit CMOS ROM Based and One-Time Programmable (OTP) Microcontroller

with 1k to 4k Memory, Power On Reset, and Very Small Packaging

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.