12-Bit, 170/210 MSPS 3.3 V A/D Converter AD9430 FUNCTIONAL BLOCK DIAGRAM FEATURES APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization GENERAL DESCRIPTION The AD9430 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates up to a 210 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The ADC requires a 3.3 V power supply and a differential ENCODE clock for full performance operation. The digital outputs are TTL/CMOS or LVDS compatible and support either twos complement or offset binary format. Separate output power supply pins support interfacing with 3.3 V or 2.5 V CMOS logic. SENSE VREF AGND DRGND DRVDD AVDD AD9430 SCALABLE REFERENCE VIN+ TRACKAND-HOLD VIN- ADC 12-BIT PIPELINE CORE LVDS OUTPUTS 12 CMOS OUTPUTS DATA, OVERRANGE IN LVDS OR 2-PORT CMOS DS+ DS- CLK+ SELECT CMOS OR LVDS CLOCK MANAGEMENT DCO+ DCO- CLK- 02607-001 SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (-0.5 dBFS) SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (-0.5 dBFS) Excellent linearity: DNL = 0.3 LSB (typical) INL = 0.5 LSB (typical) 2 output data options: Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS Interleaved or parallel data output option LVDS at 210 MSPS 700 MHz full-power analog bandwidth On-chip reference and track-and-hold Power dissipation = 1.3 W typical @ 210 MSPS 1.5 V input voltage range 3.3 V supply operation Output data format option Data sync input and data clock output provided Clock duty cycle stabilizer S1 S2 S4 S5 Figure 1. Functional Block Diagram Two output buses support demultiplexed data up to 105 MSPS rates in CMOS mode. A data sync input is supported for proper output data port alignment in CMOS mode, and a data clock output is available for proper output data timing. In LVDS mode, the chip provides data at the ENCODE clock rate. Fabricated on an advanced BiCMOS process, the AD9430 is available in a 100-lead, surface-mount plastic package (100 e-PAD TQFP) specified over the industrial temperature range (-40C to +85C). PRODUCT HIGHLIGHTS 1. High performance. Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input. 2. Low power. Consumes only 1.3 W @ 210 MSPS. 3. Ease of use. LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample/hold provide flexibility in system design. Use of a single 3.3 V supply simplifies system power supply design. 4. Out of range (OR). The OR output bit indicates when the input signal is beyond the selected input range. 5. Pin compatible with 10-bit AD9411 (LVDS only). Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. AD9430 TABLE OF CONTENTS DC Specifications ............................................................................. 4 Analog Inputs ............................................................................. 27 AC Specifications.............................................................................. 5 Gain.............................................................................................. 27 Digital Specifications........................................................................ 6 ENCODE..................................................................................... 27 Switching Specifications .................................................................. 7 Voltage Reference ....................................................................... 27 Absolute Maximum Ratings............................................................ 9 Data Format Select ..................................................................... 27 Explanation of Test Levels ........................................................... 9 I/P Timing Select........................................................................ 27 ESD Caution.................................................................................. 9 Timing Controls ......................................................................... 27 Pin Configurations and Function Descriptions ......................... 10 CMOS Data Outputs.................................................................. 27 Terminology .................................................................................... 14 DAC Outputs .............................................................................. 28 Equivalent Circuits ......................................................................... 16 Crystal Oscillator........................................................................ 28 Typical Performance Characteristics ........................................... 17 Optional Amplifier..................................................................... 28 Application Notes ........................................................................... 24 Troubleshooting.......................................................................... 28 Theory of Operation .................................................................. 24 Evaluation Board, LVDS Mode...................................................... 34 Encode Input............................................................................... 24 Power Connector........................................................................ 34 Analog Input ............................................................................... 25 Analog Inputs ............................................................................. 34 DS Inputs (DS+, DS-)................................................................ 25 Gain.............................................................................................. 34 CMOS Outputs ........................................................................... 25 Clock ............................................................................................ 34 LVDS Outputs............................................................................. 25 Voltage Reference ....................................................................... 34 Clock Outputs (DCO+, DCO-) ............................................... 26 Data Format Select ..................................................................... 34 Voltage Reference ....................................................................... 26 Data Outputs............................................................................... 34 Noise Power Ratio Testing (NPR) ............................................ 26 Crystal Oscillator........................................................................ 34 Evaluation Board, CMOS Mode................................................... 27 Outline Dimensions ....................................................................... 40 Power Connector........................................................................ 27 Ordering Guide .......................................................................... 40 Rev. C | Page 2 of 40 AD9430 REVISION HISTORY 3/03--Rev. 0 to Rev. A Changes to FEATURES ............................................................... 1 Changes to PRODUCT HIGHLIGHTS .................................... 1 Changes to SPECIFICATIONS ................................................... 2 Changes to Figure 2 ...................................................................... 5 Changes to ORDERING GUIDE ................................................ 6 Change to PIN FUNCTION DESCRIPTIONS ........................ 7 Edits to Output Propagation Delay section. ........................... 10 Added TPCs 5-8, 10-12, 14, 16, 18, 20, 22, 27, 31-32, 34 ... 12 Changes to TPCs........................................... 17, 19, 26, 35-36, 38 Added text to ENCODE INPUT section ................................ 18 Added DS INPUTS section ....................................................... 19 Change to Table I ....................................................................... 19 Changes to LVDS Outputs section........................................... 20 Changes to Voltage Reference section ...................................... 20 Replaced Figure 12...................................................................... 20 Change to Troubleshooting section .......................................... 22 Updated OUTLINE DIMENSIONS.......................................... 27 Upgraded for AD9430-210 ............................................Universal 5/02--Revision 0: Initial Version 11/04--Rev. B to Rev. C Changes to Specifications ............................................................. 4 Changes to Figure 60 ................................................................. 31 Changes to LVDS PCB BOM .................................................... 35 Changes to Figure 68 (Evaluation Board--LVDS Mode) ...... 36 Updated Outline Dimensions ................................................... 40 7/03--Rev. A to Rev. B Changed order of Figure 1 and Figure 2 ................................... 5 Updated TPC 13 .......................................................................... 14 Changes to LVDS OUTPUTS section....................................... 20 Add New AD9430 EVALUATION BOARD, LVDS MODE Section ...................................................................................... 27 Updated OUTLINE DIMENSIONS ........................................ 32 Rev. C | Page 3 of 40 AD9430 DC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40C, TMAX = +85C, fIN = -0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Out (VREF) REFERENCE Reference Out (VREF) Output Current1 IVREF Input Current2 ISENSE Input Current ANALOG INPUTS (VIN+, VIN-)3 Differential Input Voltage Range (S5 = GND) Differential Input Voltage Range (S5 = AVDD) Input Common-Mode Voltage Input Resistance Input Capacitance POWER SUPPLY (LVDS Mode) AVDD DRVDD Supply Currents: IANALOG(AVDD = 3.3 V)4 IDIGITAL (DRVDD = 3.3 V) Power Dissipation Power Supply Rejection POWER SUPPLY (CMOS Mode) AVDD DRVDD Supply Currents: IAVDD(AVDD = 3.3 V)5 IDRVDD (DRVDD = 3.3 V) Power Dissipation Power Supply Rejection 2 4 4 5 5 Temp Test Level Min Full 25C 25C 25C Full 25C Full VI I I I VI I VI -3 -5 -1 -1 -1.5 -2.25 Full Full Full V V V 25C 25C 25C 25C I IV I I Full Full Full Full 25C V V VI VI V Full Full IV IV Full Full Full 25C VI VI VI V Full Full IV IV Full Full Full 25C IV IV IV V AD9430-170 Typ Max 12 Min Guaranteed 0.3 0.3 0.5 0.5 1.235 1.6 2.65 2.2 3.1 3.0 3.1 3.0 1.536 0.766 2.8 3 5 -3 -5 -1 -1 -1.75 -2.5 0.3 0.3 0.3 0.3 +3 +5 +1 +1.5 +1.75 +2.5 58 0.02 +0.12/-0.24 1.3 3.0 20 5.0 1.15 1.235 1.6 2.9 3.8 2.65 2.2 3.3 3.3 3.6 3.6 3.2 3.0 335 55 1.29 -7.5 372 62 1.43 3.3 3.3 3.6 3.6 335 24 1.1 -7.5 372 30 1 3.2 3.0 1.536 0.766 2.8 3 5 Rev. C | Page 4 of 40 mV % FS LSB LSB LSB LSB V/C %/C mV/C 1.3 3.0 20 5.0 2.9 3.8 V mA mA mA V V V k pF 3.3 3.3 3.6 3.6 V V 390 55 1.5 -7.5 450 62 1.7 mA mA W mV/V 3.3 3.3 3.6 3.6 V V 390 30 1.3 -7.5 450 30 mA mA W mV/V Internal reference mode; SENSE = Floats. External reference mode; SENSE = DRVDD, VREF driven by external 1.23 V reference. 3 S5 (Pin 1) = GND. See Analog Input section. S5 = GND in all dc, ac tests unless otherwise specified. 4 IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, -0.5 dBFS, sine wave, rated ENCODE rate, and in LVDS output mode. See Typical Performance Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in LVDS output mode. 5 IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, -0.5 dBFS, sine wave, rated ENCODE rate, and in CMOS output mode. See Typical Performance Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in CMOS output mode. 2 Unit Bits Guaranteed +3 +5 +1 +1.5 +1.5 +2.25 58 0.02 +0.12/-0.24 1.15 AD9430-210 Typ Max AD9430 AC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40C, TMAX = +85C, fIN = -0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode, unless otherwise noted. Table 21. Parameter SNR Analog Input @ -0.5 dBFS SINAD Analog Input @ -0.5 dBFS AD9430-170 Typ Max Min AD9430-210 Typ Max Temp Test Level Min Unit 10 MHz 70 MHz 100 MHz 240 MHz 25C 25C 25C 25C I I V V 63.5 63 65 65 65 61 62.5 62.5 64.5 64.5 64.5 61 dB dB dB dB 10 MHz 70 MHz 100 MHz 240 MHz 25C 25C 25C 25C I I V V 63.5 63 65 65 65 60 62.5 62.5 64.5 64.5 64.5 60 dB dB dB dB 10 MHz 70 MHz 100 MHz 240 MHz 25C 25C 25C 25C I I V V 10.2 10.2 10.6 10.6 10.6 9.8 10.2 10.2 10.5 10.5 10.5 9.8 Bits Bits Bits Bits 10 MHz 70 MHz 100 MHz 240 MHz 25C 25C 25C 25C I I V V -85 -85 -77 -63 -75 -75 -84 -84 -77 -63 -74 -74 dBc dBc dBc dBc 10 MHz 70 MHz 100 MHz 240 MHz 25C 25C 25C 25C I I V V -87 -87 -77 -63 -78 -78 -87 -87 -77 -63 -77 -77 dBc dBc dBc dBc 25C 25C V V -75 700 EFFECTIVE NUMBER OF BITS (ENOB) WORST HARMONIC (2nd or 3rd) Analog Input @ -0.5 dBFS 10 MHz WORST HARMONIC (4th or Higher) Analog Input @ -0.5 dBFS 10 MHz TWO-TONE IMD2 F1, F2 @ -7 dBFS ANALOG INPUT BANDWIDTH 1 2 All ac specifications tested by driving CLK+ and CLK- differentially. F1 = 28.3 MHz, F2 = 29.3 MHz. Rev. C | Page 5 of 40 -75 700 dBc MHz AD9430 DIGITAL SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40C, TMAX = +85C, unless otherwise noted. Table 3. Parameter ENCODE AND DS INPUTS (CLK+, CLK-, DS+, DS-)1 Differential Input Voltage2 Common-Mode Voltage3 Input Resistance Input Capacitance LOGIC INPUTS (S1, S2, S4, S5) Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current Logic 0 Input Current Input Resistance Input Capacitance LOGIC OUTPUTS (CMOS Mode) Logic 1 Voltage4 Logic 0 Voltage LOGIC OUTPUTS (LVDS Mode) , 5 VOD Differential Output Voltage VOS Output Offset Voltage Output Coding 4 Temp Test Level Full Full Full 25C IV VI VI V 0.2 1.375 3.2 Full Full Full Full 25C 25C IV IV VI VI V V 2.0 Full IV DRVDD -0.05 Full IV Full Full VI VI Min AD9430-170 Typ Max 1.5 5.5 4 1.575 6.5 Min 0.2 1.375 3.2 AD9430-210 Typ Max 1.5 5.5 4 1.575 6.5 2.0 0.8 190 10 0.8 190 10 30 4 30 4 DRVDD -0.05 0.05 Unit V V k pF V V A A k pF V 0.05 V 4 247 454 1.125 1.375 Twos complement or binary 1 ENCODE and DS inputs identical on-chip. See Equivalent Circuits section. All ac specifications tested by driving CLK+ and CLK- differentially, |(CLK+) - (CLK-)| > 200 mV. 3 ENCODE inputs' common mode can be externally set, such that 0.9 V < ENC < 2.6 V. 4 Digital output logic levels: DRVDD = 3.3 V, CLOAD = 5 pF. 5 LVDS RTERM = 100 , LVDS output current set resistor (RSET) = 3.74 k (1% tolerance). 2 Rev. C | Page 6 of 40 247 454 1.125 1.375 Twos complement or binary mV V AD9430 SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40C, TMAX = +85C, unless otherwise noted.) Table 4. Parameter (Conditions) Maximum Conversion Rate1 Minimum Conversion Rate CLK+ Pulse Width High (tEH) CLK+ Pulse Width Low (tEL) DS Input Setup Time (tSDS)2 DS Input Hold Time (tHDS) OUTPUT (CMOS Mode) Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tPD - tCPD) Interleaved Mode (A, B Latency) Parallel Mode (A, B Latency) OUTPUT (LVDS Mode) Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tPD - tCPD) Latency Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out of Range Recovery Time (CMOS and LVDS) 1 1 1 2 1 2 Temp Full Full Full Full Full Full Test Level VI V IV IV IV IV Full Full 25C 25C Full Full Full Full IV IV V V IV IV IV IV 2 Full Full 25C 25C Full Full Full 25C 25C 25C VI VI V V VI IV IV V V V 2.0 Min 170 AD9430-170 Typ Max 40 12.5 12.5 2 2 -0.5 1.75 -0.5 1.8 0.2 All ac specifications tested by driving CLK+ and CLK- differentially. DS inputs used in CMOS mode only. Rev. C | Page 7 of 40 Min 210 AD9430-210 Typ Max 40 12.5 12.5 2 2 -0.5 1.75 2 3.8 1 1 3.8 0 14, 14 15, 14 5 5 +0.5 -0.5 3.8 1 1 3.8 0 14, 14 15, 14 5 3.2 0.5 0.5 2.7 0.5 14 1.2 0.25 4.3 5 +0.5 2.0 3.2 0.5 0.5 2.7 0.5 14 1.2 0.25 4.3 3.8 0.8 1 1.8 0.2 3.8 0.8 1 Unit MSPS MSPS ns ns ns ns ns ns ns ns ns ns Cycles Cycles ns ns ns ns ns ns Cycles ns ps rms Cycles AD9430 CLK+ CLK- DS+ DS- tSDS tHDS PORT A DA11-DA0 STATIC PORT B DB11-DB0 STATIC tPD 14 CYCLES INTERLEAVED DATA OUT tV N INVALID N+2 INVALID INVALID N+1 N+3 PARALLEL DATA OUT PORT A DA11-DA0 STATIC INVALID INVALID N N+2 PORT B DB11-DB0 STATIC INVALID INVALID N+1 N+3 tCPD 02607-002 DCO- STATIC DCO+ Figure 2. CMOS Timing Diagram N-1 N N+1 AIN tEL tEH 1/fS CLK+ CLK- tPD N-14 DATA OUT N-13 N N+1 14 CYCLES 02607-003 DCO+ DCO- tCPD Figure 3. LVDS Timing Diagram Rev. C | Page 8 of 40 AD9430 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD, DRVDD Analog Inputs Digital Inputs REFIN Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature JA1 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating 4V -0.5 V to AVDD + 0.5 V -0.5 V to DRVDD + 0.5 V -0.5 V to AVDD + 0.5 V 20 mA -55C to +125C -65C to +150C 150C 150C 25C/W, 32C/W EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. Typical JA = 32C/W (heat slug not soldered); typical JA = 25C/W (heat slug soldered) for multilayer board in still air with solid ground plane. II. 100% production tested at 25C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 9 of 40 AD9430 76 DA5 78 DA7 77 DA6 79 DA8 81 DA10 80 DA9 82 DRGND 83 DRVDD 84 DA11 86 AGND 85 OR_A 87 AGND 88 AVDD 89 AVDD 91 AGND 90 AVDD 92 AGND 93 AGND 94 AVDD 96 AGND 95 AVDD 97 AGND 99 AVDD 98 AVDD 100 AGND PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS S5 1 75 DRVDD DNC 2 74 DRGND S4 3 AGND 4 73 DA4 72 DA3 S2 5 S1 6 71 DA2 70 DA1 DNC 7 69 DA0 AVDD 8 AGND 9 68 DNC 67 DRGND 66 DNC 65 DNC SENSE 10 VREF 11 AD9430 AGND 12 64 DCO+ CMOS PINOUT TOP VIEW (Not to Scale) AGND 13 AVDD 14 63 DCO- 62 DRVDD AVDD 15 61 DRGND 60 OR_B AGND 16 59 DB11 AGND 17 AVDD 18 VIN+ 21 56 DB8 55 DB7 AGND 20 Figure 4. CMOS Dual-Mode Pinout Rev. C | Page 10 of 40 DB3 49 DB4 50 DRVDD 47 DRGND 48 DB1 45 DB2 46 DNC 43 DB0 44 DNC 42 AVDD 40 AGND 41 CLK- 37 AGND 38 AVDD 39 AGND 35 CLK+ 36 DS- 33 AVDD 34 51 DB5 AGND 31 DS+ 32 AGND 25 AGND 30 53 DRGND 52 DB6 AVDD 28 AVDD 29 54 DRVDD AGND 26 AVDD 27 VIN- 22 AGND 23 AVDD 24 02607-004 58 DB10 57 DB9 AVDD 19 AD9430 Table 6. Pin Function Descriptions (CMOS Mode) Pin Number Mnemonic 1 S5 2, 7, 42, 43, 65, 66, 68 3 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 5 DNC S4 Function Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential, GND sets fS = 1.536 V p-p differential. Do Not Connect. Interleaved, Parallel Select Pin. High = interleaved. AGND1 Analog Ground. S2 6 S1 Output Mode Select. Low = dual-port CMOS, high = LVDS. Data Format Select. Low = binary, high = twos complement for both CMOS and LVDS mode. 8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99 10 11 21 22 32 33 36 37 44 45 46 47, 54, 62, 75, 83 48, 53, 61, 67, 74, 82 49 50 51 52 55 56 57 58 59 60 63 64 69 70 71 72 73 76 77 78 79 80 81 84 85 1 AVDD 3.3 V Analog Supply. SENSE VREF VIN+ VIN- DS+ DS- CLK+ CLK- DB0 DB1 DB2 DRVDD DRGND DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 OR_B DCO- DCO+ DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 OR_A Reference Mode Select Pin. Float for internal reference operation. 1.235 V Reference I/O--Function Dependent on SENSE. Analog Input--True. Analog Input--Complement. Data Sync (Input)--True. Tie low if not used. Data Sync (Input)--Complement. Tie high if not used. Clock Input--True. Clock Input--Complement. B Port Output Data Bit (LSB). B Port Output Data Bit. B Port Output Data Bit. 3.3 V Digital Output Supply (3.0 V to 3.6 V). Digital Output Ground. B Port Output Data Bit. B Port Output Data Bit. B Port Output Data Bit. B Port Output Data Bit. B Port Output Data Bit. B Port Output Data Bit. B Port Output Data Bit. B Port Output Data Bit. B Port Output Data Bit (MSB). B Port Overrange. Data Clock Output--Complement. Data Clock Output--True. A Port Output Data Bit (LSB). A Port Output Data Bit. A Port Output Data Bit. A Port Output Data Bit. A Port Output Data Bit. A Port Output Data Bit. A Port Output Data Bit. A Port Output Data Bit. A Port Output Data Bit. A Port Output Data Bit. A Port Output Data Bit. A Port Output Data Bit (MSB). A Port Overrange. 1 AGND and DRGND should be tied together to a common ground plane. Rev. C | Page 11 of 40 76 D9- 78 D10- 77 D9+ 79 D10+ 81 D11+ 80 D11- 82 DRGND 83 DRVDD 84 OR- 86 AGND 85 OR+ 87 AGND 89 AVDD 88 AVDD 91 AGND 90 AVDD 92 AGND 94 AVDD 93 AGND 96 AGND 95 AVDD 97 AGND 99 AVDD 98 AVDD 100 AGND AD9430 S5 1 75 DRVDD DNC 2 74 DRGND S4 3 AGND 4 73 D8+ 72 D8- S2 5 S1 6 71 D7+ 70 D7- LVDSBIAS 7 69 D6+ AVDD 8 AGND 9 68 D6- 67 DRGND 66 D5+ 65 D5- SENSE 10 VREF 11 AD9430 AGND 12 64 DCO+ LVDS PINOUT TOP VIEW (Not to Scale) AGND 13 AVDD 14 63 DCO- 62 DRVDD 61 DRGND 60 D4+ AGND 17 59 D4- AVDD 18 AVDD 19 58 D3+ 57 D3- AGND 20 56 D2+ VIN+ 21 55 D2- VIN- 22 54 DRVDD AGND 23 AVDD 24 53 DRGND 52 D1+ AGND 25 51 D1- Figure 5. LVDS Mode Pinout Rev. C | Page 12 of 40 D0+ 50 D0- 49 DRVDD 47 DRGND 48 DNC 46 DNC 45 DNC 44 DNC 43 DNC 42 AGND 41 AVDD 40 AVDD 39 CLK- 37 AGND 38 CLK+ 36 AVDD 34 AGND 35 GND 32 AVDD 33 AGND 31 AGND 30 AVDD 28 AVDD 29 AVDD 27 AGND 26 AVDD 15 02607-005 AGND 16 AD9430 Table 7. Pin Function Descriptions (LVDS Mode) Pin Number 1 Mnemonic S5 2, 42 to 46 DNC 3 S4 Function Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential, GND sets fS = 1.536 V p-p differential. Do Not Connect. Control Pin for CMOS Mode. Tie low when operating in LVDS mode. 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 5 6 AGND1 Analog Ground. S2 S1 7 LVDSBIAS 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99 10 11 21 22 32 36 37 47, 54, 62, 75, 83 48, 53, 61, 67, 74, 82 49 50 51 52 55 56 57 58 59 60 63 64 65 66 68 69 70 71 72 73 76 77 78 79 80 81 84 85 AVDD Output Mode Select. GND = dual-port CMOS; AVDD = LVDS. Data Format Select. GND = binary, AVDD = twos complement. Set Pin for LVDS Output Current. Place 3.74 kW resistor terminated to ground. 3.3 V Analog Supply. SENSE VREF VIN+ VIN- GND CLK+ CLK- DRVDD DRGND D0- D0+ D1- D1+ D2- D2+ D3- D3+ D4- D4+ DCO- DCO+ D5- D5+ D6- D6+ D7- D7+ D8- D8+ D9- D9+ D10- D10+ D11- D11+ OR- OR+ Reference Mode Select Pin. Float for internal reference operation. 1.235 V Reference I/O--Function Dependent on SENSE. Analog Input--True. Analog Input--Complement. Data Sync (Input)--Not Used in LVDS Mode. Tie to GND. Clock Input--True (LVPECL Levels). Clock Input--Complement (LVPECL Levels). 3.3 V Digital Output Supply (3.0 V to 3.6 V). Digital Output Ground. D0 Complement Output Bit (LSB). D0 True Output Bit (LSB). D1 Complement Output Bit. D1 True Output Bit. D2 Complement Output Bit. D2 True Output Bit. D3 Complement Output Bit. D3 True Output Bit. D4 Complement Output Bit. D4 True Output Bit. Data Clock Output--Complement. Data Clock Output--True. D5 Complement Output Bit. D5 True Output Bit. D6 Complement Output Bit. D6 True Output Bit. D7 Complement Output Bit. D7 True Output Bit. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit. D9 True Output Bit. D10 Complement Output Bit. D10 True Output Bit. D11 Complement Output Bit. D11 True Output Bit. Overrange Complement Output Bit. Overrange True Output Bit. 1 1 AGND and DRGND should be tied together to a common ground plane. Rev. C | Page 13 of 40 AD9430 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. PowerFULLSCALE 2 V FULLSCALE RMS = 10 log Z INPUT 0.001 Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Crosstalk Coupling onto one channel being driven by a low level (-40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. Peak-to-peak differential is computed by rotating the input's phase 180 and again taking the peak measurement. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit. Minimum Conversion Rate The ENCODE rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The ENCODE rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK- and the time when all output data bits are within valid logic levels. Noise (for Any Range within the ADC) Calculated as follows: Effective Number of Bits (ENOB) Calculated from the measured SNR based on the equation ENOB = Full-Scale Input Power Expressed in dBm. Computed using the following equation: - SNRdBc - SignaldBFS FS VNOISE = Z x 0.001x 10 dBM 10 SNR MEASURED - 1.76dB 6.02 ENCODE Pulse Width/Duty Cycle Pulse width high is the minimum amount of time the ENCODE pulse (clock pulse) should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time the ENCODE pulse should be left in low state. See timing implications of changing tEH in the Application Notes, Encode Input section. At a given clock rate, these specifications define an acceptable ENCODE duty cycle. where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value of the particular input level, and Signal is the signal level within the ADC, reported in dB below full scale. This value includes input levels both thermal and quantization noise. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Rev. C | Page 14 of 40 AD9430 Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Transient Response Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale). Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Rev. C | Page 15 of 40 AD9430 EQUIVALENT CIRCUITS AVDD FULL SCALE K 12k CLK+ OR DS+ S5 = 0 --> K = 1.24 S5 = 1 --> K = 0.62 12k CLK- OR DS- 150 150 - + A1 1V 10k 200 SENSE 1k DISABLE A1 VDD 02607-009 02607-006 10k 0.1F VREF Figure 6. ENCODE and DS Inputs Figure 9. VREF, SENSE I/O AVDD 3.5k 3.5k 20k 20k DRVDD VIN- 02607-007 VIN+ 02607-010 DX Figure 7. Analog Inputs Figure 10. Data Outputs (CMOS Mode) VDD DRVDD S1, S2, S4, S5 V V DX- DX+ V V 02607-011 02607-008 30k Figure 8. S1-S5 Inputs Figure 11. Data Outputs (LVDS Mode) Rev. C | Page 16 of 40 AD9430 TYPICAL PERFORMANCE CHARACTERISTICS Charts at 170 MSPS, 210 MSPS for -170, -210 grades, respectively. AVDD, DRVDD = 3.3 V, T = 25C, AIN differential drive, Full scale = 1.536 V, internal reference unless otherwise noted. 0 0 SNR = 65.2dB SINAD = 65.1dB H2 = -88.8dBc H3 = -88.1dBc SFDR = 87dBc -20 -30 -20 -30 dB -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -100 10 20 30 40 MHz 50 60 70 80 85 02607-012 -90 -100 Figure 12. FFT: fs = 170 MSPS, AIN = 10.3 MHz @ -0.5 dBFS, LVDS Mode 0 30 40 MHz 50 60 70 80 85 0 SNR = 65.1dB SINAD = 64.9dB FUND = -0.50dBFS H2 = -88.6dBc H3 = -94.6dBc SFDR = 85.9dBc -10 -20 -30 SNR = 63.6dB SINAD = 62.9dB H2 = -82.5dBc H3 = -78.6dBc SFDR = 77.7dBc -10 -20 -30 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 0 10 20 30 40 MHz 50 60 70 80 85 -100 02607-013 -100 0 15 30 45 60 75 90 105 MHz 02607-016 dB -40 dB 20 Figure 15. FFT: fs = 170 MSPS, AIN = 10.3, MHz @ -0.5 dBFS, Single-Ended Input, Full Scale = 0.76 V, LVDS Mode 0 Figure 16. FFT: fs = 210 MSPS, AIN = 10.3 MHZ @ -0.5 dBFS, LVDS Mode Figure 13. FFT: fs = 170 MSPS, AIN = 65 MHz @ -0.5 dBFS, LVDS Mode 0 0 SNR = 64.93dB SINAD = 64.85dB FUND = -0.44dBFS H2 = -92.1dBc H3 = -90.1dBc SFDR = 75.6dBc -10 -20 -30 SNR = 63.1dB SINAD = 62.8dB H2 = -81.1dBc H3 = -76dBc SFDR = -76dBc -10 -20 -30 -40 dB -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 -100 0 10 20 30 40 MHz 50 60 70 80 85 -100 02607-015 dB 10 Figure 14. FFT: fs = 170 MSPS, AIN = 65 MHz @ -0.5 dBFS, CMOS Mode 0 15 30 45 60 MHz 75 90 105 02607-017 dB -40 0 SNR = 62.99dBFS SINAD = 61.45dBFS H2 = -66.8dBc H3 = -82.5dBc SFDR = 66.1dBc -10 02607-015 -10 Figure 17. FFT: fs = 210 MSPS, AIN = 65 MHz @ -0.5 dBFS, CMOS Mode Rev. C | Page 17 of 40 AD9430 0 0 SNR = 63.5dB SINAD = 62.6dB H2 = -79dBc H3 = -76.1dBc SFDR = 75.2dBc -20 -30 -30 -40 -40 dB dB -20 -50 -50 -60 -60 -70 -70 -80 -80 -90 -100 15 30 45 60 75 90 105 MHz 02607-018 -90 -100 0 SNR = 63.3dB SINAD = 63.1dB H2 = -80.38dBc H3 = -81.8dBc SFDR = 80.8dBc -10 0 15 30 45 60 75 90 105 MHz Figure 18. FFT: fs = 210 MSPS, AIN = 65 MHz @ -0.5 dBFS, LVDS Mode 02607-021 -10 Figure 21. FFT: fs = 213 MSP, AIN = 100 MHz @ -0.5 dBFS, LVDS Mode 85 85 80 80 SFDR 75 75 70 70 65 65 dB dB SNR SNR 60 60 55 55 SINAD SINAD FULL SCALE = 0.75 50 45 45 0 50 100 150 200 250 300 350 400 AIN (MHz) 40 02607-019 40 0 50 100 150 200 250 300 350 400 AIN (MHz) Figure 19. SNR, SINAD, and SFDR vs. AIN Frequency, fS = 210 MSPS, AIN @ -0.5 dBFS, LVDS Mode 02607-022 FULL SCALE = 1.5 50 Figure 22. SNR, and SINAD vs. AIN Frequency; fs = 210 MSPS, AIN @ -0.5 dBFS, LVDS Mode, Full Scale = 0.76 V 100 100 THIRD 90 90 THIRD 80 80 70 60 60 50 50 40 50 100 150 200 250 AIN (MHz) 300 350 400 40 0 50 100 150 200 250 AIN (MHz) 300 350 400 Figure 23. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency, fs = 170 MSPS, CMOS Mode Figure 20. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency Rev. C | Page 18 of 40 02607-023 dB SFDR 70 0 SECOND SECOND 02607-020 dB SFDR AD9430 70 0 68 66 -170 SNR -30 64 62 dB dB -210 SNR 60 -60 SFDR = 63dBc 58 -210 SINAD 56 -90 -170 SINAD 54 0 50 100 150 200 250 AIN (MHz) 300 350 400 -120 0 10 20 30 40 50 60 MHz 70 80 90 100 02607-027 50 02607-024 52 Figure 27. Two-Tone Intermodulation Distortion (59 MHz and 60 MHz), LVDS Mode, fs = 210 MSPS Figure 24. SNR, and SINAD vs. AIN Frequency; fs = 170, 210 MSPS, AIN @ -0.5 dBFS, LVDS Mode 85 95 80 90 85 75 SFDR SFDR 80 70 75 65 dB dB SNR 70 60 65 55 SINAD SINAD 50 60 45 0 50 100 150 200 250 300 350 400 AIN (MHz) 50 02607-025 40 0 50 100 150 200 250 MHz 02607-028 55 Figure 28. SINAD and SFDR vs. Clock Rate (AIN = 10.3 MHz @ -0.5 dBFS, LVDS Mode), -170 Grade Figure 25. SNR, and SINAD, SFDR vs. AIN Frequency; fs = 210 MSPS, AIN @ -0.5 dBFS, CMOS Mode 0 85 SFDR = 75dBc -10 80 -20 -30 70 -40 SNR 65 dB dB SFDR 75 -50 SINAD 60 -60 55 -70 50 -80 0 10 20 30 40 50 MHz 60 70 80 85 02607-026 -100 40 0 50 100 150 200 MHz Figure 26. Two-Tone Intermodulation Distortion (28.3 MHz and 29.3 MHz; LVDS Mode, fs = 170 MSPS) Figure 29. SNR, and SINAD, SFDR vs. Clock Rate (AIN = 10.3 MHz, @ -0.5 dBFS), LVDS Mode, -210 Grade Rev. C | Page 19 of 40 250 02607-029 45 -90 AD9430 80 ANALOG SUPPLY CURRENT LVDS MODE 250 OUTPUT SUPPLY CURRENT LVDS MODE 200 40 150 100 20 OUTPUT SUPPLY CURRENT CMOS MODE 50 0 100 120 140 160 180 ENCODE (MSPS) 0 220 200 70 SINAD 55 50 20 350 70 ANALOG SUPPLY CURRENT CMOS MODE 60 300 250 50 OUTPUT SUPPLY CURRENT LVDS MODE 40 200 30 150 OUTPUT SUPPLY CURRENT CMOS MODE 100 20 10 50 0 0 100 120 140 160 180 200 220 60 70 80 1.2 RO = 13 TYP 1.0 VREFOUT (V) 80 50 1.4 IDRVDD (OUTPUT SUPPLY CURRENT) (mA) 400 40 Figure 33. SNR, SINAD, and SFDR vs. ENCODE Pulse Width High, (AIN = 10.3 MHz @ -0.5 dBFS, 210 MSPS, LVDS) 240 0.8 0.6 0.4 0.2 02607-031 ANALOG SUPPLY CURRENT LVDS MODE 30 ENCODE POSITIVE DUTY CYCLE (%) 90 450 SNR 60 Figure 30. IAVDD and IDRVDD vs. Clock Rate (AIN = 10.3 MHz @ -0.5 dBFS) 170 MSPS Grade, CLOAD = 5pF 0 0 1 2 3 4 5 7 6 8 ILOAD (mA) ENCODE (MSPS) Figure 31. IAVDD and IDRVDD vs. Clock Rate (AIN = 10.3 MHz @ -0.5 dBFS) 210 MSPS Grade, CLOAD = 5 pF Figure 34. VREFOUT vs. ILOAD 2.0 85 1.5 80 SFDR 1.0 GAIN ERROR (%) 75 70 dB SNR 65 SINAD 60 0.5 % GAIN ERROR USING EXT REF 0 -0.5 -1.0 55 50 10 20 30 40 50 60 70 ENCODE POSITIVE DUTY CYCLE (%) 80 90 -2.0 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 95 Figure 35. Full-Scale Gain Error vs. Temperature (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS/210 MSPS, LVDS) Figure 32. SINAD and SFDR vs. Clock Pulse Width High (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS, LVDS) Rev. C | Page 20 of 40 02607-035 -1.5 02607-032 IAVDD (ANALOG SUPPLY CURRENT) (mA) 65 02607-033 60 02607-034 300 SFDR 75 dB 350 IDRVDD (OUTPUT SUPPLY CURRENT) (mA) 80 ANALOG SUPPLY CURRENT CMOS MODE 02607-030 IAVDD (ANALOG SUPPLY CURRENT) (mA) 400 AD9430 1.250 1.00 0.75 1.245 0.25 1.240 LSB VREF (V) 0.50 1.235 0 -0.25 -0.50 1.230 2.7 2.9 3.1 3.3 AVDD (V) 3.5 3.7 3.9 -1.00 02607-036 1.225 2.5 Figure 36. VREF Output Voltage vs. AVDD 0 500 1000 1500 2000 CODE 2500 3000 3500 4000 02607-039 -0.75 Figure 39. Typical INL Plot (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS, LVDS) 95 1.00 THIRD 0.75 90 SECOND 0.50 85 SFDR 0.25 dB LSB 80 0 75 -0.25 70 -0.50 SNR 60 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -1.00 0 Figure 37. SNR, SINAD, SFDR vs. Temperature (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS) 500 1000 1500 2000 CODE 2500 3000 3500 4000 Figure 40. Typical DNL Plot (AIN = 10.3 MHz @ -0.5 dBFS) 65 100 64 90 AVDD = 3.6 SFDR -dBFS 80 63 70 61 60 dB 62 60 50 AVDD = 3.135 40 58 30 SFDR -dBc 80dB REFERENCE LINE AVDD = 3.0 57 20 56 10 55 -45 -25 -5 15 35 55 TEMPERATURE (C) 75 0 -100 -90 -80 -70 -60 -50 -40 -30 -20 ANALOG INPUT LEVEL (dBFS) Figure 38. SINAD vs. Temperature, AVDD (AIN = 70 MHz @ -0.5 dB, 210 MSPS, LVDS Mode) Figure 41. SFDR vs. AIN Input Level, AIN @ 10.3MHz,170 MSPS, LVDS Mode Rev. C | Page 21 of 40 -10 0 02607-041 59 02607-038 dB AVDD = 3.3 02607-040 -0.75 SINAD 02607-037 65 AD9430 90 0 80 -20 70 SFDR dBc LVDS MODE FULL SCALE = 1.5 60 -40 dB dB 50 SFDR dBc CMOS MODE FULL SCALE = 1.5 40 19.2 -60 30 -80 20 80dB REFERENCE LINE 10 -70 -60 -50 -40 -30 -20 0 -10 19.2 47.6 38.4 MHz 02607-045 -80 -100 02607-042 0 -90 Figure 45. W-CDMA Four Channels Centered at 38.4 MHz, fs = 153.6 MHz, LVDS Mode Figure 42. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS, LVDS/CMOS Modes 90 90 80 80 SFDR SNR 70 70 SFDR dBc LVDS MODE FULL SCALE = 1.5 60 60 SINAD 50 dB dB 50 40 40 SFDR dBc LVDS MODE FULL SCALE = 0.75 30 30 20 20 80dB REFERENCE LINE -80 -70 -60 -50 -40 -30 -20 -10 0 02607-043 0 -90 0 0 0.5 1.0 1.5 2.0 2.5 FULL-SCALE RANGE (V) Figure 46. SNR, and SINAD. SFDR vs. Full-Scale Range, S5 = 0, Full-Scale Range Varied by Adjusting VREF, 170 MSPS Figure 43. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS, LVDS Mode, Full Scale = 0.76 V/1.536 V 4.5 0 NPR = 56.95dB ENCODE = 170MSPS NOTCH @ 19MHz 4.0 -40 ns -60 3.5 -80 TPD -100 3.0 -140 2.65 21.25 MHz 42.5 2.5 -40 -20 0 20 40 TEMPERATURE (C) 60 80 100 Figure 47. Propagation Delay vs. Temperature, LVDS Mode, 170 MSPS/210 MSPS Figure 44. Noise Power Ratio Plot Rev. C | Page 22 of 40 02607-047 TCPD -120 02607-044 NOISE INPUT LEVEL (dB) -20 02607-046 10 10 AD9430 4.5 900 1.4 800 1.3 TPDR (DATA RISING) 3.0 2.5 -40 -20 0 20 40 60 80 TEMPERATURE (C) Figure 48. Propagation Delay vs. Temperature, CMOS Mode, 170 MSPS/210 MSPS 100 1.2 600 1.1 500 1.0 400 0.9 VOD 300 0.8 200 0.7 100 0.6 0 0 2 4 6 8 10 12 0.5 14 RSET (k) Figure 49. LVDS Output Swing, Common-Mode Voltage vs. RSET, Placed at LVDSBIAS, 170 MSPS/210 MSPS Rev. C | Page 23 of 40 02607-049 VDIF (mV) TPDF (DATA FALLING) 3.5 700 02607-048 ns 4.0 VOS (V) VOS TCPD (CLOCKOUT RISING) AD9430 APPLICATION NOTES with it that needs to be considered in applications where the clock rate can change dynamically, requiring a wait time of 1.5 s to 5 s after a dynamic clock frequency increase before valid data is available. This circuit is always on and cannot be disabled by the user. THEORY OF OPERATION The AD9430 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 12-bit core. For ease of use, the part includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output's logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI-644 compatible) via Pin S2. The clock inputs are internally biased to 1.5 V (nominal) and support either differential or single-ended signals. For best dynamic performance, a differential signal is recommended. An MC100LVEL16 performs well in the circuit to drive the clock inputs, as illustrated in Figure 50. (For trace lengths > 2 inches, a standard LVPECL termination is recommended rather than the simple pull-down as shown.) Note that for this low voltage PECL device, the ac coupling is optional. ENCODE INPUT Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track-andhold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the clock inputs of the AD9430, and the user is advised to give careful thought to the clock source. AD9430 0.1F CLK+ PECL GATE CLK- The AD9430 has an internal clock duty cycle stabilization circuit that locks to the rising edge of CLK+ and optimizes timing internally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 30 MHz nominally. The loop has a time constant associated 0.1F 510 02607-050 510 Figure 50. Driving Clock Inputs with LVEL16 Table 8. Output Select Coding S11 (Data Format Select) 1 0 X X X X X S2 (LVDS/CMOS Mode Select)2 X X 0 0 1 X X 1 S4 (I/P Select) X X 1 0 X X X 1 S5 (Full-Scale Select)3 X X X X X 1 0 1 Mode Twos complement Offset binary Dual-mode CMOS interleaved Dual-mode CMOS parallel LVDS mode Full scale = 0.768 V Full scale = 1.536 V 1 X = Don't care. S4 used in CMOS mode only (S2 = 0). S1 to S5 all have 30 k-resistive pull-downs on-chip. 3 S5 full-scale adjust (see Analog Inputs section). 2 INTERLEAVED MODE PARALLEL MODE Figure 51. Rev. C | Page 24 of 40 02607-051 In interleaved mode, output data on Port A is offset from output data changes on Port B by one-half output clock cycle: AD9430 ANALOG INPUT DS INPUTS (DS+, DS-) The analog input to the AD9430 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN- should match. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a singleended signal. In CMOS output mode, the data sync inputs (DS+, DS-) can be used in applications that require a given sample to appear at a specific output port (A or B) relative to a given external timing signal. The DS inputs can also be used to synchronize two or more ADCs in a system to maintain phasing between Ports A and B on separate ADCs (in effect, synchronizing multiple DCO outputs). When DS+ is held high (DS- low), the ADC data outputs and clock do not switch and are held static. Synchronization is accomplished by the assertion (falling edge) of DS+ within the timing constraints tSDS and tHDS, relative to a clock rising edge. (On initial synchronization, tHDS is not relevant.) If DS+ falls within the required setup time (tSDS) before a given clock rising edge N, the analog value at that point in time will be digitized and available at Port A, 14 cycles later in interleaved mode. A wideband transformer, such as Mini-Circuits' ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 2.8 V. (See the Equivalent Circuits section.) Special care was taken in the design of the analog input section of the AD9430 to prevent damage and corruption of data when the input is overdriven. The nominal differential input range is approximately 1.5 V p-p ~ (768 mV x 2). Note that the best performance is achieved with S5 = 0 (full-scale = 1.5). See Figure 43. S5 = GND VIN+ 768mV 2.8V 2.8V VIN- CMOS OUTPUTS DIGITALOUT = ALL 0s 02607-052 DIGITALOUT = ALL 1s Figure 52. Differential Analog Input Range S5 = AVDD VIN+ 2.8V 768mV 2.8V VIN- = 2.8V The off-chip drivers on the chip can be configured to provide CMOS compatible output levels via Pin S2. The CMOS digital outputs (S2 = 0) are TTL/CMOS compatible for lower power consumption. The outputs are biased from a separate supply (DRVDD), allowing easy interface to external logic. The outputs are CMOS devices that swing from ground to DRVDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short (< 1 inch, for a total CLOAD < 5 pF). When operating in CMOS mode, it is also recommended to place low value (20 ) series damping resistors on the data lines to reduce switching transient effects on performance. LVDS OUTPUTS 02607-053 Figure 53. Single-Ended Analog Input Range The very next sample, N + 1, is sampled by the next rising clock edge and available at Port B, 14 cycles after that clock edge. In dual parallel mode, Port A has a 15-cycle latency and Port B has a 14-cycle latency, but data is available at the same time. Driving each ADC's DS inputs by the same sync signals accomplishes this. An easy way to accomplish synchronization is by a onetime sync at power-on reset. Note that when running the AD9430 in LVDS mode, set DS+ to ground and DS- to 3.3 V, as the DS inputs are relevant only in CMOS output mode, simplifying the design for some applications as well as affording superior SNR/SINAD performance at higher encode/analog frequencies. The off-chip drivers on the chip can be configured to provide LVDS compatible output levels via Pin S2. LVDS outputs are available when S2 = VDD and a 3.74 k RSET resistor is placed at Pin 7 (LVDSBIAS) to ground. The RSET resistor current is ratioed on-chip, setting the output current at each output equal to a nominal 3.5 mA (11 x IRSET). A 100 differential termination resistor placed at the LVDS receiver inputs results Rev. C | Page 25 of 40 AD9430 in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 termination resistor as close to the receiver as possible. It is recommended to keep the trace length two inches maximum and to keep differential output trace lengths as equal as possible. K FULL SCALE S5 = 0 --> K = 1.24 S5 = 1 --> K = 0.62 0.1F VREF + 1V A1 EXTERNAL 1.23V + REFERENCE 200 CLOCK OUTPUTS (DCO+, DCO-) 1k VOLTAGE REFERENCE A stable and accurate 1.23 V voltage reference is built into the AD9430 (VREF). The analog input full-scale range is linearly proportional to the voltage at VREF. Note that an external reference can be used by connecting the SENSE pin to VDD (disabling internal reference) and driving VREF with the external reference source. No appreciable degradation in performance occurs when VREF is adjusted 5%. A 0.1 F capacitor to ground is recommended at the VREF pin in internal and external reference applications. Float the SENSE pin for internal reference operation. SENSE + 3.3V VDD 02607-054 The input ENCODE is divided by two (in CMOS mode) and available off-chip at DCO+ and DCO-. These clocks can facilitate latching off-chip, providing a low skew clocking solution (see Figure 2). The on-chip clock buffers should not drive more than 5 pF of capacitance to limit switching transient effects on performance. Note that the output clocks are CMOS levels when CMOS mode is selected (S2 = 0) and are LVDS levels when in LVDS mode (S2 = VDD), (requiring a 100 differential termination at receiver in LVDS mode). The output clock in LVDS mode switches at the ENCODE rate. DISABLE A1 Figure 54. Using an External Reference NOISE POWER RATIO TESTING (NPR) NPR is a test that is commonly used to characterize the return path of cable systems where the signals are typically QAM signals with a "noise-like" frequency spectrum. NPR performance of the AD9430 was characterized in the lab yielding an effective NPR = 56.9 dB at an analog input of 19 MHz. This agrees with a theoretical maximum NPR of 57.1 dB for an 11-bit ADC at 13.6 dB backoff. The rms noise power of the signal inside the notch is compared with the rms noise level outside the notch using an FFT. Sufficiently long record lengths to guarantee a sufficient number of samples inside the notch are a requirement, as well as a high order bandstop filter that provides the required notch depth for testing. Rev. C | Page 26 of 40 AD9430 EVALUATION BOARD, CMOS MODE The AD9430 evaluation board offers an easy way to test the AD9430 in CMOS mode. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC, an onboard DAC, latches, and a data ready signal. The digital outputs and output clocks are available at two 40-pin connectors, P3 and P4. (See Figure 60.) The board has several different modes of operation and is shipped in the following configurations: * Offset Binary * Internal Voltage Reference * CMOS Parallel Timing * Full-Scale Adjust = Low The ENCODE clock is terminated to ground through 50 at SMB connector J5. The input is ac-coupled to a high speed differential receiver (LVEL16) that provides the required low jitter, fast edge rates needed for optimum performance. J5 input should be > 0.5 V p-p. Power to the EL16 is set at jumper E47. Connecting E47 to E45 powers the buffer from AVDD; connecting E47 to E46 powers the buffer from VCLK/V_XTAL. VOLTAGE REFERENCE POWER CONNECTOR Power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks). (AVDD, DRVDD, and VDL are the minimum required power connections). Table 9. Power Connector, CMOS Mode AVDD 3.3 V DRVDD 3.3 V VDL 3.3 V EXT_VREF VCLK/V_XTAL VAMP ENCODE The AD9430 has an internal 1.23 V voltage reference. The ADC uses the internal reference as the default when jumpers E24-E27 and E25-E26 are left open. The full scale can be increased by placing optional resistor R3. The required value would vary with the process and needs to be tuned for the specific application. Full scale can similarly be reduced by placing R4; tuning is required here as well. An external reference can be used by shorting the SENSE pin to 3.3 V (place jumper E26-E25). E27-E24 jumper connects the ADC VREF pin to the EXT_VREF pin at the power connector. DATA FORMAT SELECT Analog supply for ADC (350 mA) Output supply for ADC (28 mA) Supply for support logic and DAC (350 mA) Optional external reference input Supply for clock buffer/optional CRYSTAL Supply for optional amp Data format select sets the output data format of the ADC. Setting DFS (E1 to E2) low sets the output format to be offset binary; setting DFS high (E1 to E3) sets the output to twos complement. I/P TIMING SELECT ANALOG INPUTS The evaluation board accepts a 1.3 V p-p analog input signal centered at ground at SMB connector J4. This signal is terminated to ground through 50 by R16. The input can be alternatively terminated at transformer T1 secondary by R13 and R14. T1 is a wideband RF transformer providing the singleended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even order harmonics. An optional second transformer, T2, can be placed following T1 if desired. This would provide some performance advantage (~1 dB to 2 dB) for high analog input frequencies (>100 MHz). If T2 is placed, two shorting traces at the pads would need to be cut. The analog signal is low-pass filtered by R41, C12 and R42, C13 at the ADC input. GAIN Full scale is set at E17, E18, and E19. Connecting E17 to E18 sets S5 low, full scale = 1.5 V differential; connecting E17 to E19 sets S5 high, full scale = 0.75 V differential. Output timing is set at E11, E12 and E13. E12 to E11 sets S4 low for parallel output timing mode. E11 to E13 sets S4 high for interleaved timing mode. TIMING CONTROLS Flexibility in latch clocking and output timing is accomplished by allowing for clock inversion at the timing controls section of the PCB. Each buffered clock is buffered by an XOR and can be inverted by moving the appropriate jumper for that clock. CMOS DATA OUTPUTS The ADC CMOS digital outputs are latched on the board by four LVT574s; the latch outputs are available at the two 40-pin connectors at Pins 11-33 on P23 (Channel A) and Pins 11-33 on P3 (Channel B). The latch output clocks (data ready) are available at Pin 37 on P23 (Channel A) and Pin 37 on P3 (Channel B). The data-ready clocks can be inverted at the timing controls section if needed Rev. C | Page 27 of 40 AD9430 0 4.6ns C1 FREQ 84.65608MHz ENCODE 163.84MHz ANALOG 65.02MHz SNR 63.93dB SINAD 63.87dB FUND -0.45dBFS 2ND -85.62dBc 3RD -91.31dBc 4TH -90.54dBc 5TH -90.56dBc 6TH -91.12dBc THD -82.21dBc SFDR 83.93dBc SAMPLES 8k NOISEFLR -100.44dBFS WORSTSP -83.93dBc -10 -20 -30 -40 dB 1 -50 -60 -70 2 -80 CH2 2.00V M 5.00ns CH2 0 20 40 MHz Figure 55. Data Output and Clock @ 80-Pin Connector 60 80 02607-057 2.00V 02607-055 CH1 -90 -100 Figure 57. FFT--Using VF561 CRYSTAL as Clock Source DAC OUTPUTS Each channel is reconstructed by an on-board, dual-channel DAC, an AD9753. This DAC is intended to assist in debug--it should not be used to measure the performance of the ADC. It is a current output DAC with on-board 50 termination resistors. Figure 56 is representative of the DAC output with a full-scale analog input. The scope setting is low bandwidth. ADC input filtering would enhance performance. See the AD8350 data sheet. SNR/SINAD performance of 61 dB/60 dB is possible and would start to degrade at about 30 MHz. CUT TRACE C1 FREQ 10.33592MHz C1 p-p 448mV AD8350 1 CUT TRACE 2.00m M 25.0ns CH1 248mV Figure 58. Using the AD8350 on the AD9430 PCB 02607-056 CH1 02607-058 1 TROUBLESHOOTING If the board does not seem to be working correctly, try the following: Figure 56. DAC Output CRYSTAL OSCILLATOR An optional crystal oscillator can be placed on the board to serve as a clock source for the PCB. Power to the oscillator is through the VCLK/VXTAL pin at the power connector. If an oscillator is used, ensure proper termination for best results. The board has been tested with a Valpey Fisher VF561 and a Vectron JN00158-163.84. Test results for the VF561 are shown in Figure 57. * Verify power at IC pins. * Check that all jumpers are in the correct position for the desired mode of operation. * Verify that VREF is at 1.23 V. * Try running clock and analog inputs at low speeds (10 MSPS/1 MHz) and monitor latch, DAC, and ADC for toggling. OPTIONAL AMPLIFIER The footprint for transformer T2 can be modified to accept a wideband differential amplifier (AD8350) for low frequency applications where gain is required. Note that Pin 2 would need to be lifted and left floating for operation. Input transformer T1 would need to be modified to a 4:1 for impedance matching and The AD9430 evaluation board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. Rev. C | Page 28 of 40 AD9430 SIGNAL GENERATOR REFIN BAND-PASS FILTER 3.3V - AVDD GND ANALOG J4 + 3.3V - DRVDD GND + VDL GND AD9430 EVALUATION BOARD 10MHz REFOUT SIGNAL GENERATOR CLOCK J5 Figure 59. Evaluation Board Connections Rev. C | Page 29 of 40 - DATA CAPTURE AND PROCESSING 02607-059 3.3V + AD9430 Table 10. Evaluation Board Bill of Materials--CMOS No. Quantity Reference Designator Device Package Value Comments 1 47 Capacitor 0603 0.1 F 2 3 4 5 6 7 1 2 1 1 7 9 0603 0603 0603 0603 CAPL 10 pF 20 pF 0.01 F 1 F 10 F 6 2 3 Capacitor Capacitor Capacitor Capacitor Capacitor 3-pin header/jumper 3-pin header/jumper 3-pin header/jumper 4-pin header 3-pin header/jumper 3-pin header/jumper 3-pin header/jumper 3-pin header/jumper 3-pin header/jumper SMB C43, C47 Not placed Not placed Not placed 8 9 10 C1, C3-C11, C15-C17, C19-C29, C31-C48, C58-C62 C2 C12, C13 C14 C18 C30, C49, C63-C67 E3, E1, E2 E19, E17, E18 E13, E11, E12 E26, E25, E27, E24 E46, E47, E45 E35, E33, E34 E32, E30, E31 E29, E23-E28 E22, E16-E21 J1, J2, J3, J4, J5, J6 P3, P231 P4, P21, P22 11 8 12 13 3 14 14 15 16 17 18 5 4 1 1 7 19 20 4 8 21 22 23 24 25 26 27 1 4-pin power connector SMB C30 Not placed J2 Not placed Z5.531.3425.0 Wieland Resistor Post Detachable Connector 0603 25.602.5453.0 50 Wieland R1, R13, R14 Not placed R3, R4 Not placed R15, R21 to R24 Not placed Resistor Resistor 0603 0603 3.74 k 100 Resistor Resistor Resistor Resistor Resistor 0603 0603 0603 0603 0603 0 510 2 k 390 1 k Resistor pack 220 W Resistor pack 22 W SO16RES SO16RES 742C163221JTR 742C163220JTR CTS CTS 2 R1, R5, R16, R25, R27, R28, R41, R42 R2, R3, R4 R6-R8, R10, R15, R21-R24, R33-R36, R38 R9, R11, R12, R30, R37 R17, R18, R19, R20 R26 R29 R31, R32, R39, R40, R43, R44, R45 RZ1, RZ2, RZ3, RZ4 RZ5, RZ6, RZ7, RZ8, RZ9, RZ10, RZ11, RZ12 T1, T2 Transformer CD542 T2 Not placed 1 1 1 4 1 2 U1 U2 U3 U4, U5, U6, U7 U9 R13, R14 AD9430BSV MC100LVEL16D 74LVC86 74LVT574 AD9753AST Resistors TQFP100 SO8NB SO14NB SO20 LQFP48 0603 Mini-Circuits ADT1-1WT ADC Clock buffer XOR Latch DAC 25 W P3, P23 are implemented as one physical 80-pin connector SAMTEC TSW-140-08-L-D-RA. Rev. C | Page 30 of 40 R13, R14 Not placed J4 02607-060 ANALOG C6 0.1F R16 50 P4 P21 P22 PTMICA04 PTMICA04 SEC PRI E15 6 2 3 5 R13 25 GND R14 29 GND GND COUT E7 E20 R39 1k R40 1k C2 10pF C3 0.1F H1 MTHOLES ENCODE J5 R4 R3 C5 0.1F PRI 3 5 VCC R17 510 MC100L VCLK SEC 6 2 T2 ADT1-1WT 4 1 T2 OPTIONAL R27 50 VCC COUTAB COUTA EXT_VREF GND R11 R9 R3, R4 OPTIONAL GND GND H2 COUTB MTHOLES H3 MTHOLES H4 MTHOLES DRVDD VDL R13, R14 OPTIONAL C7 0.1F E2 E3 GND E5 VCC E1 GND E6 VCC E4 E9 GND E10 E8 VCC E13 E18 E12 E11 E14 E17 E19 GND VCC GND VCC GND DRVDD GND AVDD (VCC) 1 P1 2 P2 3 P3 4 P4 GND VCLK/V_XTAL EXT_VREF GND VDL 1 P1 2 P2 3 P3 4 P4 T1 ADT1-1WT 1 4 PTMICA04 E24 E46 E45 R10 510 VEL 16 E47 DQ GND C8 0.1F 8 5 VEE 3 DN 4 VBB 2 U2 QN 6 7 C36 0.1F 13 12 10 9 5 4 GND R20 510 PLB R36 100 R35 100 R34 100 R33 100 R1 50 R5 50 C9 R19 510 0.1F DRB CLKLATB DRA CLKLATA 0 R12 GND C4 0.1F VCC E36 R1 NOT PLACED J2 GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 11 8 6 3 GND GROUND PAD UNDER PART U3 74L VC86 U3 74L VC86 U3 74L VC86 U3 74L VC86 GND C10 0.1F J1 GND C13 20pF GND VCC GND GND GND VCC VCC GND GND VCC VCC GND DATA SYNC R42 25 GND R41 25 VCC GND C12 20pF GND C1 0.1F VCC GND R6 100 COUTAB R7 100 COUTAB R8 100 COUTA R10 100 R2 3.74k E21 E22 E28 E29 E31 E32 E34 GND E16 E23 E30 C11 0.1F C43 0.1F C47 0.1F E29 E27 E26 GND VCC GND VCC GND VCC GND E33 2 1 GND VCC VCC VCC GND GND COUTA VCC GND E35 AD9430 U1 GND + C30 10F GND VCC VCC GND VCC VCC GND GND VCC VCC GND GND GND VCC VCC VCC GND GND CLK+ Figure 60. Evaluation Board Schematic--CMOS CLK GND VAMP DR VDD GND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND Rev. C | Page 31 of 40 DR VDD GND 1 P1 2 P2 3 P3 4 P4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DR VDD GND COUT COUTB DR VDD GND GND DR VDD GND 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 R8 R7 R6 R5 R4 R3 R2 R1 RZ4 220 R8 R7 R6 R5 R4 R3 R2 R1 RZ3 220 R8 R7 R6 R5 R4 R3 R2 R1 RZ2 220 R8 R7 R6 R5 R4 R3 R2 R1 RZ1 220 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 GND GND GND GND GND GND GND GND 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 D GN D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC LVT574 CLOCK U7 LVT574 OUT_EN D GN D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC CLOCK U6 OUT_EN Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 CLOCK LVT574 GND D7 D6 D5 D4 D3 D2 D1 D0 OUT_EN U5 LVT574 GND D7 D6 D5 D4 D3 D2 D1 D0 VCC CLOCK U4 OUT_EN VDL 11 12 13 14 15 16 17 18 19 20 11 12 13 14 15 16 17 18 19 20 11 12 13 14 15 16 17 18 19 20 11 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 R8 R7 R6 R5 R4 R3 R2 R1 RZ5 22 CLKLATB VDL R8 R7 R6 R5 R4 R3 R2 R1 RZ6 22 CLKLATB VDL R8 R7 R6 R5 R4 R3 R2 R1 RZ7 22 CLKLATA VDL R8 R7 R6 R5 R4 R3 R2 R1 RZ8 22 CLKLATA 12 DM5 13 DM6 14 DM7 15 DM8 16 17 18 19 20 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 DYB DYA DY0 DY1 DY2 DY3 DY4 DY5 DY6 DY7 DY8 DY9 DY10 DY11 DRY DXB DXA DX0 DX1 DX2 DX3 DX4 DX5 DX6 DX7 DX8 DX9 DX10 DX11 DRX GND GND P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1 P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1 C4OMS P3 P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2 C4OMS P23 P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2 GND GND DRB GND DY11 DY10 DY9 DY8 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 DYA DYB DRY GND GND DRA GND DX11 DX10 DX9 DX8 DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 DXA DXB DRX AD9430 AD9430 uVCC + C64 10F C16 0.1F C17 0.1F C19 0.1F C21 0.1F C20 0.1F C23 0.1F C24 0.1F C25 0.1F C22 0.1F C27 0.1F C26 0.1F C29 0.1F C28 0.1F C31 0.1F C42 0.1F C41 0.1F C32 0.1F C35 0.1F GND VDL + C67 10F C44 0.1F C15 0.1F C37 0.1F GND VCLK DRVDD C60 0.1F C59 0.1F VREF C58 0.1F GND VAMP C14 0.1F C66 10F + GND + C63 10F GND OPIN B GND VCLK OPIN B GND U8 8 7 6 5 VCLK GND AD8350 R23 100 OPTIONAL AMP P2 IN+ 12 R24 100 OPTIONAL XTAL OUT- P1 R22 100 GND R21 100 VCLK 3 OPIN J6 OPIN C34 VOL 0.1F R25 50 GND GND E4Z GND VOL E40 J3 R30 0 R44 R29 392 GND C33 GND 0.1F GND C18 1F GND E41 R28 50 VOL C38 0.1F GND 1k E39 VOL E37 R26 2k E38 GND R43 1k GND VOL C46 0.1F C45 0.1F 37 38 39 40 41 42 43 44 45 46 R8 8 10 R7 7 36 11 R6 6 35 12 R5 5 34 13 R4 4 33 14 R3 3 5 32 15 R2 2 6 31 16 R1 1 2 0 3 4 DYA DY0 DY1 DY2 DY3 22 GND AD9753 GND DYB RZ10 RZ9 8 28 11 R6 6 DX9 3 R3 14 9 27 12 R5 5 DX8 4 R4 13 10 26 13 R4 4 DX7 5 R5 12 11 25 14 R3 3 DX6 6 R6 11 12 15 R2 2 DX5 7 R7 10 16 R1 1 DX4 8 R8 9 30 9 24 23 15 22 2 21 7 DX10 20 R7 19 10 18 29 17 7 16 16 R2 15 8 1 14 R8 DX11 R1 DY4 DY5 DY6 DY7 DY8 DY9 DY10 DY11 22 22 1 R1 16 DX2 2 R2 15 DX1 3 R3 14 DX0 4 R4 13 DXA 5 R5 12 DXB 6 R6 11 7 R7 10 8 R8 9 22 GND RZ11 DX3 VOL GND C39 0.1F Figure 61. Evaluation Board Schematic--CMOS (continued) Rev. C | Page 32 of 40 02607-061 GND RZ12 9 R37 DRA R32 1k R45 1k 1 GND R31 1k 47 48 GND VOL U10 GND VAMP GND GND 4 OUT+ VCC 6 5 OUTPUT B 4 OUTPUT GND GND 1 E/D 2 NC 3 GND R38 FOR VF561 CRYSTAL C40 0.1F C48 0.1F GND GND R15 100 R38 100 C49 10F GND VCC C62 0.1F IN- C61 0.1F ENBL C65 10F 13 + 02607-062 02607-065 AD9430 Figure 62. PCB Top Side Silkscreen Figure 63. PCB Top Side Copper 02607-066 02607-063 Figure 65. PCB Split Power Plane 02607-064 02607-067 Figure 66. PCB Bottom Side Copper Figure 64. PCB Ground Layer Figure 67. PCB Bottom Side Silkscreen Rev. C | Page 33 of 40 AD9430 EVALUATION BOARD, LVDS MODE GAIN The AD9430 evaluation board offers an easy way to test the AD9430 in LVDS mode. (The board is also compatible with the AD9411.) It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC, latches, and a data-ready signal. The digital outputs and output clocks are available at a 40-pin connector, P23. The board has several different modes of operation and is shipped in the following configurations: Full scale is set at E17-E19, E17-E18 sets S5 low, full scale = 1.5 V differential; E17-E19 sets S5 high, full scale = 0.75 V differential. Best performance is obtained at 1.5 V full scale. CLOCK * Offset Binary * Internal Voltage Reference The CLOCK input is terminated to ground through a 50 resistor at SMB connector J5. The input is ac-coupled to a high speed differential receiver (LVEL16) that provides the required low jitter, fast edge rates needed for optimum performance. J5 input should be > 0.5 V p-p. Power to the LVEL16 is set at Jumper E47. E47-E45 powers the buffer from AVDD; E47-E46 powers the buffer from VCLK/V_XTAL. * Full-Scale Adjust = Low VOLTAGE REFERENCE POWER CONNECTOR Power is supplied to the board via a detachable 8-lead power strip (two 4-pin blocks). Note for the following table that VCC, DRVDD, and VDL are the minimum required power connections, and LVEL16 clock buffer can be powered from VCC or VDL at E47 jumper. Table 11. Power Connector, LVDS Mode VCC 3.3 V DRVDD 3.3 V VDL 3.3 V EXT_VREF Analog supply for ADC (350 mA) Output supply for ADC (50 mA) Supply for support logic Optional external reference input The AD9430 has an internal 1.23 V voltage reference. The ADC uses the internal reference as the default when jumpers E24-E27 and E25-E26 are left open. The full scale can be increased by placing optional resistor R3. The required value varies with the process and needs to be tuned for the specific application. Full scale can similarly be reduced by placing R4; tuning is required here as well. An external reference can be used by shorting the SENSE pin to 3.3 V (place jumper E26-E25). Jumper E27-E24 connects the ADC VREF pin to the EXT_VREF pin at the power connector. DATA FORMAT SELECT Data format select (DFS) sets the output data format of the ADC. Setting DFS low (E1-E2) sets the output format to be offset binary; setting DFS high (E1-E3) sets the output to twos complement. ANALOG INPUTS The evaluation board accepts a 1.3 V p-p analog input signal centered at ground at SMB connector J4. This signal is terminated to ground through 50 by R16. The input can be alternatively terminated at T1 transformer secondary by R13 and R14. T1 is a wideband RF transformer providing the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. An optional second transformer, T2, can be placed following T1 if desired. This provides some performance advantage (~1 - 2dB) for high analog input frequencies (>100 MHz). If T2 is placed, two shorting traces at the pads need to be cut. The analog signal can be low-pass filtered by R41, C12 and R42, C13 at the ADC input. A wideband differential amplifier (AD8351) can be configured on the PCB for DC-coupled applications. Remove C6, C15, C30 to prevent transformer loading of the amp. See the PCB schematic for more information. DATA OUTPUTS The ADC LVDS digital outputs are routed directly to the connector at the card edge. Resistor pads have been placed at the output connector to allow for termination if the connector receiving logic does not have the required differential termination for the data bits and DCO. Each output trace pair should be terminated differentially at the far end of the line with a single 100 ohm resistor. CRYSTAL OSCILLATOR An optional crystal oscillator can be placed on the board to serve as a clock source for the PCB. Power to the oscillator is through the VCLK/VXTAL pin at the power connector. If an oscillator is used, ensure proper termination for best results. The board has been tested with a Valpey Fisher VF561 and a Vectron JN00158-163.84. Rev. C | Page 34 of 40 AD9430 Table 12. Evaluation Board Bill of Material--LVDS PCB No. 1 Quantity 33 Device Capacitors Package 0603 Value 0.1 F 4 Reference Designator C1, C4-C11, C15-C17, C19-C32, C35, C36, C58-C62 C3, C18, C39, C40 C33, C34, C37, C38 2 Capacitor 0402 0.1 F 3 4 4 1 C63-C66 C2 Capacitor Capacitor TAJD 0603 5 2 C12, C13 Capacitor 0603 20 pF 6 7 2 2 J4, J5 P21, P22 8 2 P21, P22 9 1 P23 Jacks Power connectors Top Power connectors Posts 40-pin right-angle connector 10 16 R1, R6-R12, R15, R31-R37 Resistor SMB 25.602.5453.0 Wieland Z5.531.3425.0 Wieland Digi-Key S2131-20-ND 0402 100 11 12 13 14 15 16 17 18 1 3 2 2 2 2 2 2 R2 R5, R16, R27 R17, R18 R19, R20 R29, R30 R41, R42 R3, R4 R13, R14 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 0603 0603 0603 0603 0603 0603 0603 0603 3.8 k 50 510 150 1 k 25 3.8 k 25 19 6 R22, R23, R24, R25, R26, R28 Resistor 0603 100 20 5 R38, R39, R40, R45, R47 Resistor 0402 25 21 2 R43, R44 Resistor 0402 10 k 22 1 R46 Resistor 0402 1.2 k 23 2 R48, R49 Resistor 0402 0 24 2 R50, R51 Resistor 0402 1 k 25 1 T1 T2 RF transformer 26 27 1 1 U2 U9 RF amp Optional crystal oscillator 28 29 1 1 U1 U3 AD9430 MC100LVEL16 Mini circuits ADT1-1WT AD8351 JN00158 or VF561 TQFP-100 SO8NB Rev. C | Page 35 of 40 CAPL 10 uF 10 pF Comment C3, C18, C39, C40 Not placed C33, C34, C37, C38 Not placed C2 Not placed C12, C13 Not placed R1, R6-R12, R15, R31-37 Not placed R13, R14 Not placed R22, R23, R24, R25, R26, R28 Not placed R38, R39, R40, R45, R47 Not placed R43, R44 Not placed R46 Not placed R48, R49 Not placed R50, R51 Not placed T2 Not placed 02607-068 GND NC NC R27 50 R17 510 C5 0.1F C30 0.1F AMPIN 14 15 16 17 18 19 20 VCC VCC GND GND VCC VCC GND R18 510 VDL 25 24 23 22 2 3 4 U3 GND C36 0.1F GND GND C8 0.1F 510 GND R5 50 510 VCC 7 ELOUT D Q DN QN 6 VBB ELOUTB VEE 5 R20 R19 8 E45 E46 GND 10EL16 E47 C13 20pF GND VCC GND 13 GND 21 12 GND 11 10 9 7 6 5 4 3 GND R30 1k 2 1 8 VCC R42 GND 25 C2 10pF C3 0.1F GND C1 0.1F E24 E26 E19 E18 VCC VCC E17 GND MTHOLE6 H1 MTHOLE6 H2 MTHOLE6 H3 MTHOLE6 H4 R29 GND 1k AMPINB C15 R41 0.1F 25 R14 25 GND GND J5 R13 25 6 C11 0.1F 3 PRI SEC 4 2 1 5 ENCODE 4 GND 2 6 C7 0.1F PRI SEC 1 5 3 E27 VREF VCC E25 E2 C12 20pF GND GND ADT1-1WT T2 OPTIONAL GND VCC E3 GND E1 R4 3.8k ADT1-1WT C6 0.1F AMP GND ANALOG R16 J4 50 GND VCC GND VCC DRVDD GND VDL GND GND VREF R3 GND 3.8k R2 3.8k 4 P4 1 P1 3 4 P4 2 3 P3 P3 2 P2 P2 1 P1 T2 P21 P22 T1 PTM1CRO4 PTM1CRO4 GND C9 0.1F C10 0.1F U1 GND P16 C4 0.1F DRVDD GROUND PAD UNDER PART VCC 100 26 GND VCC 99 27 VCC GND 98 28 VCC GND 97 29 VCC VCC 96 30 GND VCC 95 31 GND GND 94 32 GND 93 33 GND 92 34 VCC VCC 91 35 VCC 90 36 VCC 37 89 40 GND GND 84 42 GND 83 43 82 44 88 ~ENC DORB DOR 81 R7 100 D11 R6 100 D11B R8 100 D10B D10 GND 55 56 57 58 59 60 DRVDD 61 GND GND DRVDD 62 63 64 65 66 67 68 69 70 71 72 73 74 75 D9B D9 DR R37 100 DRB D6 R10 100 D6B P3 3 P1 1 P9 9 2 P2 P11 11 10 P10 P5 5 P13 13 12 P12 4 P4 P15 15 14 P14 P7 7 P17 17 16 P16 6 P6 P19 19 18 P18 8 P8 P21 21 P27 27 28 P28 20 P20 P29 29 30 P30 P23 23 P31 31 32 P32 22 P22 P33 33 34 P34 P25 25 P35 35 36 P36 24 P24 P37 37 26 P26 P39 39 GND GND DR GND D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1F D2F DOR D4B D4 D8B D8 38 P38 R33 100 R12 100 40 P40 D3 R32 100 D3B D5 R9 100 D5B D7 R11 100 D7B D2 R31 100 GND DRVDD 54 DRB D2B GND 53 GND 52 D1 D11B R15 51 100 D10B D1B D9B D8B D7B D6B D0 D5B R36 D4B 100 D3B D0B D1F D2B R35 D1B 100 D1FB D0B D2F D1FB R34 100 D2FB D2FB DORB GND CONNECTOR GND 45 GND 38 80 46 87 GND 77 49 86 39 VCC 79 47 DRVDD 85 41 GND 78 48 Rev. C | Page 36 of 40 GND Figure 68. Evaluation Board Schematic--LVDS VCC 76 50 R1 100 AD9430 AD9430 VCC + C64 10F C16 0.1F C17 0.1F C19 0.1F C21 0.1F C23 0.1F C20 0.1F C22 0.1F C25 0.1F C24 0.1F C27 0.1F C26 0.1F C29 0.1F C28 0.1F C31 0.1F C32 0.1F C35 0.1F GND DRVDD VDL + C65 10F C61 0.1F C62 0.1F C60 0.1F C59 0.1F C58 0.1F + C66 10F VREF C18 0.1F GND GND + C63 10F GND TO USE VF561 CRYSTAL GND VDL R28 100 GND 1 E/D VCC 6 2 NC OUTPUTB 5 3 GND OUTPUT 4 R23 100 VDL P4 R25 100 U9 GND VDL R24 100 P5 02607-069 R26 100 GND Figure 69. Evaluation Board Schematic--LVDS (continued) R51 1k R50 1k VDL GND VDL POWER DOWN USE R43 OR R44 VDL GND R38 25k R43 10k C38 0.1F GND GND R44 10k R39 25k AMP C34 0.1F R40 25k R45 25k R47 25k PWUP VOCM 10 RGP1 INHI 3 INLO VPOS 9 OPHI 8 2 OPLO 4 AMP IN GND U2 AD8351 1 C33 0.1F C37 0.1F 5 RPG2 R49 0 C39 0.1F AMPINB 7 COMM 6 GND R48 0 C40 0.1F AMPIN R46 1.2k Figure 70. Evaluation Board Schematic--LVDS (continued) Rev. C | Page 37 of 40 02607-070 R22 100 JN00158 AD9430 Figure 73. PCB Ground Layer--LVDS 02607-074 02607-072 Figure 71. PCB Top Side Silkscreen--LVDS 02607-073 02607-071 F Figure 74. PCB Split Power Plane--LVDS Figure 72. PCB Top Side Copper--LVDS Rev. C | Page 38 of 40 02607-075 02607-076 AD9430 Figure 75. PCB Bottom Side Copper--LVDS Figure 76. PCB Bottom Side Silkscreen--LVD S Rev. C | Page 39 of 40 AD9430 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 SQ 1.20 MAX 14.00 SQ 100 1 76 76 75 100 1 75 SEATING PLANE TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 25 26 0.20 0.09 51 50 25 50 1.05 1.00 0.95 7 3.5 0 0.27 0.22 0.17 0.50 BSC 0.15 0.05 26 6.50 NOM COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MS-026AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE AD9411 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 77.100-Lead Thin Quad Flat Package, Exposed Pad [TQFP/EP] (SV-100-1) Dimensions shown in millimeters ORDERING GUIDE Model AD9430BSV-170 AD9430BSVZ-1701 AD9430BSV-210 AD9430BSVZ-210 AD9430-CMOS/PCB AD9430-LVDS/PCB 1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP/EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP/EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP/EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP/EP] Evaluation Board (CMOS Mode) Shipped with -210 Grade Evaluation Board (LVDS Mode) Shipped with -210 Grade Z = PB-free part. (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02607-0-11/04(C) Rev. C | Page 40 of 40 Package Option SV-100-1 SV-100-1 SV-100-1 SV-100-1