W256
Rev 1.0, November 25, 2006 Page 3 of 7
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 — Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 — Bits 7, 6, 5, 4, 3, 2, 1, 0
.–
.
Byte N — Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• SMBus Address for the W256 is:
Table 1.
A6 A5 A4 A3 A2 A1 A0 R/W
1101001––
Byte 6: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description Default
Bit 7 –Reserved, drive to 0 0
Bit 6 –Reserved, drive to 0 0
Bit 5 –Reserved, drive to 0 0
Bit 4 1FBOUT 1
Bit 3 27, 26 DDR5T_SDRAM10,
DDR5C_SDRAM11
1
Bit 2 –Reserved, drive to 0 1
Bit 1 23, 22 DDR4T_SDRAM8,
DDR4C_SDRAM9
1
Bit 0 –Reserved, drive to 0 1
Byte 7: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description Default
Bit 7 –Reserved, drive to 0 1
Bit 6 19, 18 DDR3T_SDRAM6,
DDR3C_SDRAM7
1
Bit 5 12, 13 DDR2T_SDRAM4,
DDR2C_SDRAM5
1
Bit 4 –Reserved, drive to 0 1
Bit 3 –Reserved, drive to 0 1
Bit 2 7, 8 DDR1T_SDRAM2,
DDR1C_SDRAM3
1
Bit 1 –Reserved, drive to 0 1
Bit 0 3, 4 DDR0T_SDRAM0,
DDR0C_SDRAM1
1