MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 D D D D D D D D Low Supply Voltage Range 2.5 V - 5.5 V Ultra Low-Power Consumption Low Operation Current, 330 A at 1 MHz,3 V Two Power Saving Modes: - Standby Mode: 1.5 A - RAM Retention Off Mode: 0.1 A Wake-up From Standby Mode in 6 s Maximum 16-Bit RISC Architecture, 200 ns Instruction Cycle Time Basic Clock Module Configurations: - Various Internal Resistors - Single External Resistor - 32 kHz Crystal - High Frequency Crystal - Resonator - External Clock Source D D D D D D Single Slope A/D Converter With External Components 16-Bit Timer With 3 Capture/Compare Registers Serial Onboard Programming Program Code Protection by Security Fuse Family Members Include: MSP430C111: 2k Byte ROM, 128 Byte RAM MSP430C112: 4k Byte ROM, 256 Byte RAM MSP430P112: 4k Byte OTP, 256 Byte RAM EPROM Version Available for Prototyping: - PMS430E112: 4k Byte EPROM, 256 Byte RAM Available in a 20-Pin Plastic Small-Outline Wide Body (SOWB) Package, 20-Pin Ceramic Dual-In-Line (CDIP) Package (EPROM Only) description The Texas Instruments MSP430 series is an ultra low-power microcontroller family consisting of several devices featuring different sets of modules targeted to various applications. The microcontroller is designed to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16 bit integrated registers on the CPU, and the constant generator, the MSP430 achieves maximum code efficiency. The digitallycontrolled oscillator provides fast wake-up from all low-power modes to active mode in less than 6 ms. DW PACKAGE (TOP VIEW) TEST/VPP VCC P2.5/ROSC VSS Xout/TCLK Xin RST/NMI P2.0/ACLK P2.1/INCLK P2.2/TA0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2 P2.3/TA1 Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. Stand alone RF sensor front-end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. The MSP430x11x series is an ultra low-power mixed signal microcontroller with a built in 16-bit timer and fourteen I/O pins. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 AVAILABLE OPTIONS PACKAGED DEVICES CDIP 20-Pin (JL) SOWB 20-Pin (DW) TA - 40C to 85C MSP430C111IDW MSP430C112IDW MSP430P112IDW 25C -- PMS430E112JL functional block diagram XIN VCC XOut VSS RST/NMI P1.0-7 8 Rosc Oscillator System Clock 2/4 kB ROM 4 kB OTP 'C': ROM 'P': OTP 'E': EPROM ACLK SMCLK 128/256B RAM Power-onReset Outx CCIxA TACLK SMCLK I/O Port 8 I/O's, All With Interrupt Capabililty JTAG MCLK MAB, 16 Bit CPU Incl. 16 Reg. MAB, 4 Bit Test JTAG MCB MDB, 16 Bit MDB, 8 Bit Bus Conv. TEST/VPP Watchdog Timer Timer_A 3 CC Register 15/16 Bit CCR0/1/2 x = 0, 1, 2 TACLK or INCLK INCLK Outx ACLK SMCLK CCIxA CCIxB Out0 CCI0B CCI1B I/O Port 2 6 I/O's All With Interrupt Capabililty 6 P2.0-5 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 DCOR ACLK MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 Terminal Functions TERMINAL NAME I/O DESCRIPTION NO. P1.0/TACLK 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 14 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI0A input, Compare: Out0 output P1.2/TA1 15 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI1A input, Compare: Out1 output P1.3/TA2 16 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI2A input, Compare: Out2 output P1.4/SMCLK/TCK 17 I/O General-purpose digital I/O pin/SMCLK signal output/Test clock, input terminal for device programming and test P1.5/TA0/TMS 18 I/O General-purpose digital I/O pin/Timer_A, Compare: Out0 output/test mode select, input terminal for device programming and test. P1.6/TA1/TDI 19 I/O General-purpose digital I/O pin/Timer_A, Compare: Out1 output/test data input terminal. P1.7/TA2/TDO/TDI 20 I/O General-purpose digital I/O pin/Timer_A, Compare: Out2 output/test data output terminal or data input during programming. P2.0/ACLK 8 I/O General-purpose digital I/O pin/ACLK output P2.1/INCLK 9 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/TA0 10 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI0B input, Compare: Out0 output P2.3/TA1 11 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI1B input, Compare: Out1 output P2.4/TA2 12 I/O General-purpose digital I/O pin/Timer_A, Compare: Out2 output P2.5/ROSC RST/NMI 3 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency 7 I Reset or nonmaskable interrupt input TEST/VPP 1 I Select of test mode for JTAG pins on Port1/programming voltage input during EPROM programming VCC 2 Supply voltage VSS 4 Ground reference Xin 6 I Xout/TCLK 5 I/O Input terminal of crystal oscillator Output terminal of crystal oscillator or test clock input detailed description processing unit The processing unit is based on a consistent, and orthogonally designed CPU and instruction set. This design structure results in a RISC-like architecture, highly transparent to the application development and distinguished by ease of programming. All operations other than program-flow instructions are consequently performed as register operations in conjunction with seven addressing modes for source and four modes for destination operations. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 detailed description (continued) CPU All sixteen registers are located inside the CPU, providing reduced instruction execution time. This reduces a register-register operation execution time to one cycle of the processor. Program Counter PC/R0 Stack Pointer SP/R1 SR/CG1/R2 Status Register CG2/R3 Constant Generator Four registers are reserved for special use as a program counter, a stack pointer, a status register, and a constant generator. The remaining twelve registers are available as general-purpose registers. Peripherals are connected to the CPU using a data address and control buses and can be handled easily with all instructions for memory manipulation. General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R14 General-Purpose Register R15 instruction set The instructions set for this register-register architecture provides a powerful and easy-to-use assembly language. The instruction set consists of 51 instructions with three formats and seven addressing modes. Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are listed in Table 2. Table 1. Instruction Word Formats Dual operands, source-destination e.g. ADD R4, R5 R4 + R5 R5 Single operands, destination only e.g. CALL R8 PC (TOS), R8 PC Relative jump, un-/conditional e.g. JNE Jump-on equal bit = 0 Most instructions can operate on both word and byte data. Byte operations are identified by the suffix B. Examples: Instructions for word operation Instructions for byte operation MOV ADD PUSH SWPB MOV.B ADD.B PUSH.B -- EDE,TONI #235h,&MEM R5 R5 EDE,TONI #35h,&MEM R5 Table 2. Address Mode Descriptions s d Register ADDRESS MODE MOV Rs, Rd MOV R10, R11 R10 R11 Indexed MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2 + R5) M(6 + R6) Symbolic (PC relative) MOV EDE, TONI M(EDE) M(TONI) Absolute MOV &MEM, &TCDAT M(MEM) M(TCDAT) Indirect MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) M(Tab + R6) Indirect autoincrement MOV @Rn+, RM MOV @R10+, R11 M(R10) R11, R10 + 2 R10 Immediate MOV #X, TONI MOV #45, TONI #45 M(TONI) NOTE: s = source 4 d = destination SYNTAX EXAMPLE Rs/Rd = source register/destination register POST OFFICE BOX 655303 OPERATION Rn = register number * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 instruction set (continued) Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and calls. The full use of this programming capability permits a program structure different from conventional 8- and 16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks instead of using flag type programs for flow control. operation modes and interrupts The MSP430 operating modes support various advanced requirements for ultra low-power and ultra low-energy consumption. This is achieved by the intelligent management of the operations during the different module operation modes and CPU states. The advanced requirements are fully supported during interrupt event handling. An interrupt event awakens the system from each of the various operating modes and returns with the RETI instruction to the mode that was selected before the interrupt event. The different requirements of the CPU and modules, which are driven by system cost and current consumption objectives, necessitate the use of different clock signals (see Figure 1): D D D Auxiliary clock ACLK (from LFXTCLK/crystal's frequency), used by the peripheral modules Main system clock MCLK, used by the CPU and system Subsystem clock SMCLK, used by the peripheral modules. DIVA 2 LFXTCLK /1, /2, /4, /8 OSCOff ACLK Auxiliary Clock XTS XIN ACLKGEN SELM High Frequency XT Oscillator, XTS=1 2 DIVM CPUOff 2 3 XOUT /1, /2, /4, /8, Off Low Power LF Oscillator, XTS = 0 MCLK Main System Clock 2 MCLKGEN VCC VCC Rsel SCG0 DCO 3 MOD SELS 5 DCOCLK 0 P2.5/ROSC DC Generator Digital Controlled Oscillator (DCO) + Modulator (MOD) 1 DCOR DIVS SCG1 2 0 /1, /2, /4, /8, Off DCOMOD SMCLK Sub-System Clock 1 SMCLKGEN The DCO-Generator is connected to pin P2.5/ROSC if DCOR control bit is set. The port pin P2.5/ROSC is selected if DCOR control bit is reset (initial state). P2.5 Figure 1. Clock Signals POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 operation modes and interrupts (continued) Two clock sources, LFXTCLK and DCOCLK, can be used to drive the MSP430 system. The LFXTCLK is defined by connecting a low power, low frequency crystal to the oscillator, by connecting a high frequency crystal to the oscillator, or by applying an external clock source. The high frequency crystal oscillator is used if the control bit XTS is set. The crystal oscillator may be switched off when the LFXTCLK oscillator is not needed for the present operation mode. The DCOCLK is active and the frequency is selected or adjusted by the software. The DCOCLK is inactive or stopped when it is not used by the CPU or peripheral modules. The dc-generator can be stopped when SCG0 is reset and DCOCLK is not needed. The dc-generator defines the basic DCO frequency and can be defined by one external resistor or it is adjusted in eight steps with the integrated resistors. NOTE: The system clock generator always starts with the DCOCLK selected for MCLK (CPU clock) to ensure proper start of program execution. The software then defines the final system clock, via control bit manipulation. low-power consumption capabilities The various operating modes are controlled by the software through controlling the operation of the internal clock system. This clock system provides many combinations of hardware and software capabilities to run the application with the lowest power consumption and with optimized system costs: D D D D Use the internal clock (DCO) generator without any external components. Select an external crystal or ceramic resonator for lowest frequency or cost. Select and activate the proper clock signals (LFXTCLK and/or DCOCLK) and clock pre-divider function. Apply an external clock source. Four of the control bits that influence the operation of the clock system and support fast turnon from low power operating modes are located in the status register SR. The four bits that control the CPU and the system clock generator are SCG1, SCG0, OscOff, and CPUOff: status register R2 15 9 Reserved For Future Enhancements rw-0 8 7 6 5 4 3 2 1 0 C V SCG1 SCG0 OscOff CPUOff GIE N Z rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-power control bits when the basic function of the system clock generator is established. They are pushed onto the stack whenever an interrupt is accepted and thereby saved so that the previous mode of operation can be retrieved after the interrupt request. During execution of an interrupt handler routine, the bits can be manipulated via indirect access of the data on the stack. That allows the program to resume execution in another power operating mode after the return from interrupt (RETI). SCG1: The clock signal SMCLK, used for peripherals, is enabled when the bit is reset or disabled if the bit is set. SCG0: The dc-generator is active when it is reset. The DCO can be deactivated only if the SCG0 bit is set and the DCOCLK signal is not used for MCLK or SMCLK. The current consumed by the dc-generator defines the basic frequency of the DCOCLK. It is a dc current. NOTE: When the current is switched off (SCG0=1) the start of the DCOCLK is delayed slightly. The delay is in the s-range. See device parameters for the specified values. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 status register R2 (continued) OscOff: The LFXT crystal oscillator is active when the OscOff bit is reset. The LFXT oscillator can only be deactivated if the OscOff bit is set and it is not used for MCLK or SMCLK. The setup time to start a crystal oscillation needs consideration when the oscillator off option is used. Mask programmable (ROM) devices can disable this feature so that the oscillator can never be switched off by software. CPUOff: The clock signal MCLK, used for the CPU, is active when the bit is reset or stopped if it is set. DCOCLK: The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCG0 bit is set. There are two situations when the SCG0 bit cannot switch off the DCOCLK signal: 1. DCOCLK frequency is used for MCLK (CPUOff=0 and SELM.1=0). 2. DCOCLK frequency is used for SMCLK (SCG1=0 and SELS=0). interrupt vector addresses The interrupt vectors and the power-up starting address are located in the ROM with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE Power-up, external reset, watchdog NMI, oscillator fault INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY WDTIFG (see Note1) Reset 0FFFEh 15, highest NMIIFG, OFIFG (see Note 1) (non)-maskable, (non)-maskable 0FFFCh 14 0FFFAh 13 0FFF8h 12 0FFF6h 11 WDTIFG maskable 0FFF4h 10 Timer_A CCIFG0 (see Note 2) maskable 0FFF2h 9 Timer_A CCIFG1, CCIFG2, TAIFG (see Notes 1 and 2) maskable 0FFF0h 8 Watchdog Timer 0FFEEh 7 0FFECh 6 0FFEAh 5 0FFE8h 4 I/O Port P2 (eight flags - see Note 3) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) maskable 0FFE6h 3 I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) maskable 0FFE4h 2 0FFE2h 1 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module 3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0-5) are implemented on the 11x devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 7 Address 6 5 0h 4 3 2 OFIE NMIIE rw-0 WDTIE: OFIE: NMIIE: 1 rw-0 0 WDTIE rw-0 Watchdog Timer enable signal Oscillator fault enable signal Non-maskable interrupt enable signal interrupt flag register 1 7 Address 02h 6 5 4 3 NMIIFG rw-0 WDTIFG: OFIFG: NMIIFG: Legend 8 Bit can be read and written. Bit can be read and written. It is reset by PUC SFR bit is not present in device. POST OFFICE BOX 655303 1 OFIFG rw-1 Set on overflow or security key violation OR Reset on VCC power-on or reset condition at RST/NMI-pin Flag set on oscillator fault Set via RST/NMI-pin rw: rw-0: 2 * DALLAS, TEXAS 75265 0 WDTIFG rw-0 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 memory organization MSP430C111 FFFFh FFE0h FFDFh Int. Vector 2 kB ROM FFFFh FFE0h FFDFh F800h 027Fh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430P112 PMS430E112 MSP430C112 Int. Vector FFFFh FFE0h FFDFh Int. Vector 4 kB EPROM 4 kB ROM 128B RAM 16b Per. 8b Per. SFR F000h F000h 02FFh 02FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h 256B RAM 16b Per. 8b Per. SFR 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h 256B RAM 16b Per. 8b Per. SFR peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled easily with instructions for memory manipulation. digital I/O There are two eight-bit I/O ports, Port P1 and Port P2 - implemented (11x parts only have six Port P2 I/O signals available on external pins). Both ports, P1 and P2, have seven control registers to give maximum flexibility of digital input/output to the application: * * * * All individual I/O bits are programmable independently. Any combination of input, output, and interrupt conditions is possible. Interrupt processing of external events is fully implemented for all eight bits of port P1 and for six bits of Port P2. Provides read/write access to all registers with all instructions. The seven registers are: * * * * * * * Input register 8 bits at Port P1/P2 contains information at the pins Output register 8 bits at Port P1/P2 contains output information Direction register 8 bits at Port P1/P2 controls direction Interrupt edge select 8 bits at Port P1/P2 input signal change necessary for interrupt Interrupt flags 8 bits at Port P1/P2 indicates if interrupt(s) are pending Interrupt enable 8 bits at Port P1/P2 contains interrupt enable bits Selection (Port or Mod.) 8 bits at Port P1/P2 determines if pin(s) have port or module function POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 digital I/O (continued) All these registers contain eight bits. Two interrupt vectors are implemented: one commonly used for any interrupt event on Port P1.0 to Port P1.7, and one commonly used for any interrupt event on Port P2.0 to P2.7. NOTE: Six bits of Port P2, P2.0 to P2.5, are available on external pins - but all control and data bits for Port P2 are implemented. Watchdog Timer The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a software problem has occurred. If the selected time interval expires, a system reset is generated. If this watchdog function is not needed in an application, the module can work as an interval timer, which generates an interrupt after the selected time interval. The Watchdog Timer counter (WDTCNT) is a 16-bit up-counter which is not directly accessible by S/W. The WDTCNT is controlled through the Watchdog Timer control register (WDTCTL), which is a 16-bit read/write register. Writing to WDTCTL is, in both operating modes (watchdog or timer), only possible by using the correct password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte must be the password 05Ah. If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When the password is read, its value is 069h. This minimizes accidental write operations to the WDTCTL register. In addition to the Watchdog Timer control bits, there are two bits included in the WDTCTL register that configure the NMI pin. Timer_A (3 capture/compare registers) The Timer_A module on 11x devices offers one sixteen bit counter and three capture/compare registers. The timer clock source can be selected to come from two external sources TACLK (SSEL=0) or INCLK (SSEL=3), or from two internal sources, the ACLK (SSEL=1) or SMCLK (SSEL=2). The clock source can be divided by one, two, four, or eight. The timer can be fully controlled (in word mode) since it can be halted, read, and written. It can be stopped, run continuously, counted up or up/down, using one compare block to determine the period. The three capture/compare blocks are configured by the application to run in capture or compare mode. The capture mode is primarily used to measure external or internal events using any combination of positive, negative, or both edges of the signal. Capture mode can be started and stopped by software. Three different external events TA0, TA1, and TA2 can be selected. At capture/compare register CCR2 the ACLK is the capture signal if CCI2B is selected. Software capture is chosen if CCISx=2 or CCISx=3 (see Figure 2). The compare mode is primarily used to generate timings for the software or application hardware, or to generate pulse-width modulated output signals for various purposes like D/A conversion functions or motor control. An individual output module is assigned to each of the three capture/compare registers. The output modules can run independently of the compare function, or can be triggered in several ways. 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 Timer_A (3 capture/compare registers) (continued) SSEL1 P1.0 TACLK P2.1 ACLK SMCLK INCLK 32 kHz to 8 MHz Timer Clock SSEL0 0 15 1 3 ID1 16-Bit Timer 0 16-Bit Timer CLK RC Input Divider 2 Data ID0 POR/CLR Mode Control Carry/Zero MC1 P1.1 P2.2 0 15 Capture Capture Mode Set_TAIFG MC0 Timer Bus CCIS01 CCIS00 0 CCI0A 1 CCI0B 2 GND 3 VCC Equ0 Capture/Compare Register CCR0 Capture/Compare Register CCR0 OM02 Out 0 0 15 P1.2 P2.3 P2.2 Comparator 0 EQU0 P1.3 ACLK TA0 0 15 Capture Capture Mode Capture/Compare Register CCR1 Capture/Compare Register CCR1 OM12 Out 1 P1.2 0 15 OM11 OM10 P1.6 P2.3 Output Unit 1 Comparator 1 EQU1 CCI1 CCM11 CCIS21 CCIS20 0 CCI2A 1 CCI2B 2 GND 3 VCC P1.1 P1.5 Output Unit 0 CCI0 CCM01 CCM00 CCIS11 CCIS10 0 CCI1A 1 CCI1B 2 GND 3 VCC OM01 OM00 CCM10 0 15 Capture Capture Mode Capture/Compare Register CCR2 Capture/Compare Register CCR2 OM22 Out 2 P1.3 0 15 OM21 OM20 Output Unit 2 P1.7 P2.4 Comparator 2 EQU2 CCI2 CCM21 CCM20 Figure 2. Timer_A, MSP430x11x Configuration Two interrupt vectors are used by the Timer_A module. One individual vector is assigned to capture/compare block CCR0, and one common interrupt vector is implemented for the timer and the other two capture/compare blocks. The three interrupt events using the same vector are identified by an individual interrupt vector word. The interrupt vector word is used to add an offset to the program counter to continue the interrupt handler software at the corresponding program location. This simplifies the interrupt handler and gives each interrupt event the same overhead of 5 cycles in the interrupt handler. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog/Timer Control WDTCTL 0120h Timer_A Timer_A Interrupt Vector Timer_A Control Cap/Com Control Cap/Com Control Cap/Com Control Reserved Reserved Reserved Reserved Timer_A Register Cap/Com Register Cap/Com Register Cap/Com Register Reserved Reserved Reserved Reserved TAIV TACTL CCTL0 CCTL1 CCTL2 012Eh 0160h 0162h 0164h 0166h 0168h 016Ah 016Ch 016Eh 0170h 0172h 0174h 0176h 0178h 017Ah 017Ch 017Eh TAR CCR0 CCR1 CCR2 PERIPHERALS WITH BYTE ACCESS 12 System Clock Basic Clock Sys. Control2 Basic Clock Sys. Control1 DCO Clock Freq. Control BCSCTL2 BCSCTL1 DCOCTL 058h 057h 056h EPROM EPROM Control EPCTL 054h Port P2 Port P2 Selection Port P2 Interrupt Enable Port P2 Interrupt Edge Select Port P2 Interrupt Flag Port P2 Direction Port P2 Output Port P2 Input P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 Selection Port P1 Interrupt Enable Port P1 Interrupt Edge Select Port P1 Interrupt Flag Port P1 Direction Port P1 Output Port P1 Input P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 026h 025h 024h 023h 022h 021h 020h Special Function SFR Interrupt Flag1 SFR Interrupt Enable1 IFG1 IE1 002h 000h POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 absolute maximum ratings Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Voltage applied to any pin (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Storage temperature, Tstg (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Storage temperature, Tstg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. recommended operating conditions MIN Supply voltage, VCC Supply voltage during programming, programming VCC MSP430P112 2.7 5.5 PMS430E112 2.7 5.5 V MSP430P112 4.5 5 5.5 V MSP430E112 4.5 5 5.5 V MSP430P112 -40 40 PMS430E112 85 Processor frequency f(system) ( t ) (MCLK signal) (MSP430C11x) Low-level input voltage (TCK, TMS, TDI, RST/NMI), VIL (excluding Xin, Xout) High-level input voltage (TCK, TMS, TDI, RST/NMI), VIH (excluding Xin, Xout) VIL(Xin, Xout) VIH(Xin, Xout) POST OFFICE BOX 655303 C Hz VCC = 3 V dc 2 VCC = 5 V VCC = 3 V dc 5.35 dc 2.73 VCC = 5 V dc 5.35 VCC = 3 V/5 V VSS 0.7VCC VSS+0.8 VCC VCC = 3 V/5 V VSS 0.8xVCC 0.2xVCC VCC * DALLAS, TEXAS 75265 V 25 32 768 Processor frequency f(system) ( t ) (PMS430P/E112) (MCLK signal) UNITS 5.5 XTAL frequency, f(XTAL),(ACLK signal) Input levels at Xin, Xin Xout MAX 2.5 MSP430C11x Operating free-air temperature range, TA NOM MSP430C11x MHz MHz V V V 13 MSP430x11x MIXED SIGNAL MICROCONTROLLERS f(system) - Maximum Processor Frequency - MHz SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 5 5.35 MHz at 5 V 4 3 2.2 MHz at 2.5 V 2 1 Minimum 0 0 1 2 3 4 5 6 7 VCC - Supply Voltage - V NOTE: Minimum processor frequency is defined by system clock. f(system) - Maximum Processor Frequency - MHz Figure 3. C Version Frequency vs Supply Voltage 5 5.35 MHz at 5 V 4 3 2 1.1 MHz at 2.7 V 1.1 Minimum 0 0 1 2 3 4 5 6 7 VCC - Supply Voltage - V NOTE: Minimum processor frequency is defined by system clock. Figure 4. P/E Version Frequency vs Supply Voltage 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current (into VCC) excluding external current (f(system) = 1 MHz) PARAMETER TEST CONDITIONS NOM MAX TA = -40C +85C, f(MCLK) = f(SMCLK) = 1 MHz, VCC = 3 V f(ACLK) = 32,768 Hz VCC = 5 V VCC = 3 V TA = -40C +85C, f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz VCC = 5 V TA = -40C +85C, VCC = 3 V fMCLK = f(SMCLK) = 1 MHz MHz, VCC = 5 V f(ACLK) = 32,768 Hz 330 400 630 700 3.4 4 7.8 10 400 500 730 900 TA = -40C +85C, f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz VCC = 3 V VCC = 5 V 3.4 4 7.8 10 C11x TA = -40C +85C, fMCLK = 0 MHz, f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz VCC = 3 V VCC = 5 V 51 60 120 150 P112 TA = -40C +85C, f(MCLK) = 0 MHz, f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz VCC = 3 V VCC = 5 V 70 85 125 170 TA = -40C +85C, f(MCLK) = f(SMCLK) = 0 MHz MHz, f(ACLK) = 32,768 Hz, SCG0 = 0, Rsel = 3 VCC = 3 V 8 22 VCC = 5 V 16 35 2 2.6 VCC = 3 V 1.5 2.2 1.85 2.2 6.3 8 5.1 7 5.1 7 0.1 0.8 0.1 0.8 0.4 1 C11x I(AM) Active mode P112 I(CPUOff) I(LPM2) Low power mode, (LPM0) Low power mode, mode (LPM2) TA = -40C TA = 25C I(LPM3) Low power mode, mode (LPM3) TA = 85C TA = -40C TA = 25C TA = 85C I((LPM4)) Low power mode, (LPM4) TA = -40C TA = 25C TA = 85C f(MCLK) = f(SMCLK) = 0 MHz, f((ACLK)) = 32,768 Hz, SCG = 1 SCG0 f(MCLK) = f(SMCLK) = 0 MHz MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 f(MCLK) = f(SMCLK) = 0 MHz, f((ACLK)) = 0 Hz, SCG = 1 SCG0 MIN VCC = 5 V VCC = 3 V/ 5V UNIT A A A A A A A A NOTE: All inputs are tied to VSS or VCC. Outputs do not source or sink any current. current consumption of active mode versus system frequency IAM = IAM[1 MHz] x fsystem [MHz] current consumption of active mode versus supply voltage IAM = IAM[3 V] + 175 A/V x (VCC-3 V) standard inputs RST/NMI PARAMETER VIL VIH Low-level input voltage High-level input voltage TEST CONDITIONS VCC = 3 V/5 V POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MIN VSS 0.7VCC NOM MAX UNIT VSS+0.8 VCC V 15 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5 PARAMETER TEST CONDITIONS MIN NOM MAX VIT IT+ Positive going input threshold voltage Positive-going VCC = 3 V VCC = 5 V 1.2 2.1 2.3 3.4 VIT IT- Negative going input threshold voltage Negative-going VCC = 3 V VCC = 5 V 0.7 1.5 1.4 2.3 Vh hys Input voltage hysteresis, hysteresis (VIT IT+ - VIT IT-) VCC = 3 V VCC = 5 V 0.3 1 0.6 1.4 UNIT V V V outputs Port 1 to P2; P1.0 to P1.7, P2.0 to P2.5 PARAMETER TEST CONDITIONS VOH High level output voltage High-level I(OH) = - 1.5 mA, I(OH) = - 4.5 mA, VOL Low level output voltage Low-level I(OL) = 1.5 mA, I(OL) = 4.5 mA, MIN VCC = 3 V/5 V, VCC = 3 V/5 V, See Note 4 VCC = 3 V/5 V, VCC = 3 V/5 V, See Note 4 See Note 5 MAX UNIT VCC-0.4 VCC-0.6 VCC VCC V VSS VSS VSS+0.4 VSS+0.6 V See Note 5 NOM NOTES: 4. The maximum total current, IOH and IOL, or all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. 5. The maximum total current, IOH and IOL, or all outputs combined, should not exceed 36 mA to hold the maximum voltage drop specified. leakage current (see Note 6) PARAMETER Ilkg(Px.x) lk (P ) TEST CONDITIONS High impendance leakage current High-impendance MIN NOM MAX Port P1: P1.x, 0 x 7 (see Note 7) VCC = 3 V/5 V, 50 Port P2: P2.x, 0 x 5 (see Note 7) VCC = 3 V/5 V, 50 UNIT nA NOTES: 6. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 7. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional pullup or pulldown resistor. optional resistors, individually programmable with ROM code (see Note 8) PARAMETER TEST CONDITIONS R(opt1) R(opt2) R(opt3) R(opt4) R(opt5) R(opt6) Resistors, individually y programmable g with ROM code, all port pins, values applicable for pulldown and pullup R(opt7) R(opt8) R(opt9) MIN NOM MAX UNIT VCC = 3 V/5 V VCC = 3 V/5 V 2.1 4.1 6.2 k 3.1 6.2 9.3 k VCC = 3 V/5 V VCC = 3 V/5 V 6 12 18 k 10 19 29 k VCC = 3 V/5 V VCC = 3 V/5 V 19 37 56 k 38 75 113 k VCC = 3 V/5 V VCC = 3 V/5 V 56 112 168 k 94 187 281 k VCC = 3 V/5 V VCC = 3 V/5 V 131 261 392 k R(opt10) 167 337 506 k NOTE 8: Optional resistors Roptx for pulldown or pullup are not programmed in standard OTP or EPROM devices MSP430P112 or PMS430E112. 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) inputs Px.x, TAx PARAMETER t((int)) t((cap)) External Interrupt timing Timer_A, capture timing TEST CONDITIONS VCC Port P2: P1 P1.x tto P2 P2.x, P t P1, P1 P2 External trigger signal for the interru interruptt flag, flag (see Note 9) TA0, TA1, TA2. (see Note 10) MIN 3 V/ 5 V 1.5 3V 540 5V 270 3 V/ 5 V 1.5 3V 540 5V 270 NOM MAX UNIT cycle ns cycle ns NOTES: 9. The external signal sets the interrupt flag every time the minimum tint cycle and time parameters are met. It may be set even with trigger signals shorter than tint. Both the cycle and timing specifications must be met to ensure the flag is set. 10. The external capture signal triggers the capture event every time when the minimum tcap cycles and time parameters are met. A capture may be triggered with capture signals even shorter than tcap. Both the cycle and timing specifications must be met to ensure a correct capture of the 16-bit timer value and to ensure the flag is set. internal signals TAx, SMCLK at Timer_A PARAMETER TEST CONDITIONS f(IN) Input frequency Internal TA0, TA0 TA1 TA1, TA2 TA2, tH = tL f(TAint) Timer_A clock frequency Internally, SMCLK signal applied VCC MIN NOM MAX 3V dc 10 5V dc 15 3 V/5 V dc fSystem UNIT MHz outputs P2x, TAx PARAMETER f(P20) f(TAx) Output frequency t((Xdc)) TEST CONDITIONS P2.0/ACLK, TA0, TA1, TA2, CL = 20 pF CL = 20 pF P2.0/ACLK, CL = 20 pF fP20 = 1.1 MHz fP20 = fXTCLK Duty cycle of O/P frequency MIN NOM 3 V/5 V 3 V/5 V fP20 = fXTCLK/n CL = 20 pF, TA0, TA1, TA2, Duty cycle = 50% t(TAdc) VCC 1.1 dc fSystem 60% 40% 3 V/ 5 V MAX 35% UNIT MHz 65% 50% 0 50 ns NOM MAX UNIT 150 250 s 1.5 2.4 V 1.2 2.1 V 0.9 1.8 V 0 0.4 3 V/ 5 V PUC/POR PARAMETER TEST CONDITIONS MIN t(POR_delay) V(POR) ( ) POR TA = -40C TA = 25C VCC = 3 V/5 V TA = 85C V(min) t(reset) PUC/POR Reset is accepted internally POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2 V s 17 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) V VCC V (POR) No POR POR V (min) POR t Figure 5. Power-On Reset (POR) vs Supply Voltage 3 2.4 V POR [V] 2.5 2.1 1.8 2 1.5 1.5 1 1.2 0.9 0.5 25C 0 -40 -20 0 20 40 60 80 Temperature [C] Figure 6. V(POR) vs Temperature crystal oscillator, Xin, Xout PARAMETER C(Xin) Capacitance at input C(Xout) Capacitance at output TEST CONDITIONS MIN VCC = 3 V/5 V VCC = 3 V/5 V NOM MAX UNIT 12 pF 12 pF RAM PARAMETER MIN NOM MAX UNIT V(RAMh) CPU halted (see Note 11) 1.8 V NOTE 11: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition. 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) DCO (MSP430P112) PARAMETER TEST CONDITIONS MIN NOM MAX f(DCO03) Rsell = 0 0, DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 0.12 f(DCO13) Rsell = 1 1, DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 0.19 f(DCO23) 3 MOD = 0, 0 DCOR = 0, 0 Rsell = 2 2, DCO = 3, TA = 25C VCC = 3 V VCC = 5 V 0.31 f(DCO33) Rsell = 3 3, DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V f(DCO43) Rsell = 4 4, DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 0.5 0.8 1.1 0.6 0.9 1.2 f(DCO53) Rsell = 5 5, DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 0.9 1.2 1.55 1.1 1.4 1.7 f(DCO63) Rsell = 6 6, DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 1.7 2 2.3 2.1 2.4 2.7 f(DCO73) Rsell = 7 7, DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 2.8 3.1 3.5 3.8 4.2 4.5 f(DCO47) Rsell = 4 4, DCO = 7, 7 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V/5 V S(Rsel) SR = fRsel+1/fRsel VCC = 3 V/5 V 1.4 1.65 1.9 S(DCO) SDCO = fDCO+1/fDCO VCC = 3 V/5 V 1.07 1.12 1.16 Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 12) VCC = 3 V -0.31 -0.36 -0.40 Dt VCC = 5 V -0.33 -0.38 -0.43 DV Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 12) 0 5 10 VCC = 3 V to 5 V UNIT MHz 0.13 MHz 0.21 MHz 0.34 0.5 MHz 0.55 FDCO40 FDCO40 FDCO40 x1.8 x2.2 x2.6 MHz MHz MHz MHz MHz ratio %/C %/V NOTE 12: These parameters are not production tested. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) DCO (MSP430C111, C112) PARAMETER TEST CONDITIONS MIN NOM MAX f(DCO03) Rsell = 0, 0 DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 0.04 0.07 0.10 0.04 0.07 0.10 f(DCO13) Rsell = 1, 1 DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 0.08 0.13 0.18 0.08 0.13 0.18 f(DCO23) 2 DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 Rsell = 2, TA = 25C VCC = 3 V VCC = 5 V 0.15 0.22 0.30 0.15 0.22 0.30 f(DCO33) Rsell = 3, 3 DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 0.26 0.36 0.47 0.26 0.36 0.47 f(DCO43) Rsell = 4, 4 DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 0.4 0.6 0.8 0.4 0.6 0.8 f(DCO53) Rsell = 5, 5 DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 0.8 1.1 1.4 0.8 1.1 1.4 f(DCO63) Rsell = 6, 6 DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 1.3 1.7 2.1 1.5 1.9 2.3 f(DCO73) Rsell = 7, 7 DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V VCC = 5 V 2.4 2.9 3.4 3.1 3.8 4.5 f(DCO47) Rsell = 4, 4 DCO = 7, 7 MOD = 0, 0 DCOR = 0, 0 TA = 25C VCC = 3 V/5 V S(Rsel) SR = fRsel+1/fRsel VCC = 3 V/5 V 1.4 1.65 1.9 S(DCO) SDCO = fDCO+1/fDCO VCC = 3 V/5 V 1.07 1.12 1.16 Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 12) VCC = 3 V -0.31 -0.36 -0.40 Dt VCC = 5 V -0.33 -0.38 -0.43 DV Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 12) 0 5 10 FDCO40 FDCO40 FDCO40 x1.8 x2.2 x2.6 VCC = 3 V to 5 V f(DCOx7) f(DCOx0) Max Min Max Min IIIIII IIIIII IIIIII IIIIII 3 1 f DCOCLK Frequency Variance NOTE 12. These parameters are not production tested. 5 0 1 VCC 3 4 5 6 DCO Steps Figure 7. DCO Characteristics 20 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 UNIT MHz MHz MHz MHz MHz MHz MHz MHz MHz ratio %/C %/V MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) principle characteristics of the DCO D D D Individual devices have a minimum and maximum operation frequency. The specified parameters for fDCOx0 to fDCOx7 are valid for all devices. The DCO control bits DCO0, DCO1 and DCO2 have a step size as defined in parameter SDCO. The modulation control bits MOD0 to MOD4 select how often fDCO+1 is used within the period of 32 DCOCLK cycles. fDCO is used for the remaining cycles. The frequency is an average = fDCO x (2MOD/32). wake-up from lower power modes (LPMx) PARAMETER t(LPM0)/ t(LPM2) t(LPM3) t(LPM4) Delay time TEST CONDITIONS RSel = 4, DCO = 3, MOD = 0 RSel = 4, DCO = 3, MOD = 0 MIN NOM MAX UNIT VCC = 3 V/5 V 100 ns VCC = 3 V/5 V VCC = 3 V/5 V 2.6 6 s 2.8 6 s NOM MAX JTAG/programming PARAMETER f(TCK) JTAG/test JTAG/fuse (see Note 13) Fuse blow voltage, E/P versions (see Note 14) 5 dc 10 5.5 6 11 13 Time to blow the fuse Programming voltage, applied to Test/VPP t(pps) t(ppf) Programming time, single pulse t(erase) VCC = 3 V/ 5 V VCC = 3 V/ 5 V dc Supply current on Test/VPP during fuse is blown V(PP) I(PP) P(n) MIN VCC = 3 V VCC = 5 V TCK frequency Fuse blow voltage, C versions (see Note 14) V(FB) I(FB) t(FB) TEST CONDITIONS 12 12.5 Current from programming voltage source EPROM PP and E E-versions versions only (see Note 15) Number of pulses for successful programming Erase time wave length 2537 A at 15 Ws/cm2 (UV lamp of 12 mW/ cm2) Write/erase cycles 30 V mA 1 ms 13 V 70 mA ms s 100 4 MHz 100 5 Programming time, fast algorithm UNIT 100 Pulse min 1000 Data retention Tj < 55C 10 Year NOTES: 13. Once the JTAG fuse is blown no further access to the MSP430 JTAG/test feature is possible. The JTAG block is switched to by-pass mode. 14. The power source to blow the fuse is applied to Test/VPP pin during blowing the fuse. 15. Refer to the Recommended Operating Conditions for the correct VCC during programing. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 APPLICATION INFORMATION input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-trigger VCC P1SEL.x 0 P1DIR.x (See Note 16) 1 Direction Control From Module (See Note 17) 0 P1OUT.x Pad Logic P1.0 - P1.3 1 Module X OUT (See Note 17) (See Note 16) P1IN.x GND EN D Module X IN P1IRQ.x P1IE.x P1IFG.x Q Interrupt Edge Select EN Set Interrupt Flag P1IES.x P1SEL.x NOTE: x = Bit Identifier, 0 to 3 For Port P1 PnSel.x PnDIR.x Dir. Control from module PnOUT.x Module X OUT PnIN.x P1Sel.0 P1DIR.0 P1DIR.0 P1Sel.1 P1DIR.1 P1DIR.1 P1OUT.0 VSS P1IN.0 P1OUT.1 P1IN.1 P1IN.3 P1Sel.2 P1DIR.2 P1DIR.2 P1OUT.2 Out0 signal Out1 signal P1Sel.3 P1DIR.3 P1DIR.3 P1OUT.3 Out2 signal P1IN.2 Module X IN PnIE.x PnIFG.x PnIES.x TACLK CCI0A P1IE.0 P1IFG.0 P1IES.0 P1IE.1 P1IFG.1 P1IES.1 CCI1A CCI2A P1IE.2 P1IFG.2 P1IES.2 P1IE.3 P1IFG.3 P1IES.3 Signal from or to Timer_A NOTES: 16. Optional selection of pullup or pulldown resistors with ROM (masked) versions. 17. Fuses for optional pullup and pulldown resistors can only be programmed at the factory. VCC (see Note 16) (see Note 17) (see Note 17) (see Note 16) GND CMOS INPUT (RST/NMI) 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 APPLICATION INFORMATION Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features P1SEL.x P1DIR.x Direction Control From Module P1OUT.x VCC 0 See Note 16 1 See Note 17 0 Pad Logic P1.4-P1.7 1 Module X OUT See Note 17 See Note 16 GND TS T P1IN.x Bus Keeper EN Module X IN P1IRQ.x D P1IE.x P1IFG.x Q Interrupt VPP_Internal Edge Select EN Set Interrupt Flag Test/VPP TST 60 k Typical Fuse P1IES.x Control By JTAG P1SEL.x Fuse GND Blow TST Control P1.x TDO Controlled By JTAG P1.7/TDI/TDO Controlled by JTAG NOTES:The test pin should be protected from potential EMI and TDI ESD voltage spikes. This may require a smaller external pulldown resistor in some applications. TST P1.x P1.6/TDI x = Bit identifier, 4 to 7 for port P1 During programming activity and during blowing the fuse, the pin TDO/TDI is used to apply the test input for JTAG circuitry. TST TMS P1.x P1.5/TMS TST TCK P1.x P1.4/TCK PnSel.x PnDIR.x Dir. Control from module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x P1Sel.4 P1DIR.4 P1DIR.4 P1OUT.4 SMCLK P1IN.4 unused P1IE.4 P1IFG.4 P1IES.4 Out0 signal Out1 signal P1IN.5 unused P1IE.5 P1IFG.5 P1IES.5 P1IN.6 unused P1IE.6 P1IFG.6 P1IES.6 P1Sel.7 P1DIR.7 P1DIR.7 P1OUT.7 P1IN.7 unused P1IE.7 Signal from or to Timer_A NOTES: 16. Optional selection of pullup or pulldown resistors with ROM (masked) versions. 17. Fuses for optional pullup and pulldown resistors can only be programmed at the factory. P1IFG.7 P1IES.7 P1Sel.5 P1DIR.5 P1DIR.5 P1OUT.5 P1Sel.6 P1DIR.6 P1DIR.6 P1OUT.6 Out2 signal POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 APPLICATION INFORMATION Port P2, P2.0 to P2.4, input/output with Schmitt-trigger P2SEL.x VCC 0 P2DIR.x 0: Input 1 Direction Control From Module See Note 17 Pad Logic 0 P2OUT.x See Note 16 1: Output P2.0 - P2.4 1 Module X OUT See Note 17 See Note 16 P2IN.x EN GND D Module X IN P2IRQ.x P2IE.x P2IFG.x Q EN Set Interrupt Flag Interrupt Edge Select P2IES.x P2SEL.x NOTE: x = Bit Identifier, 0 to 4 For Port P2 PnSel.x PnDIR.x Dir. Control from module PnOUT.x Module X OUT PnIN.x P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 ACLK P2IN.0 P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 VSS P2IN.1 P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out0 signal Out1 signal P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out2 signal Module X IN PnIE.x PnIFG.x PnIES.x P2IE.0 P2IFG.0 P1IES.0 P2IE.1 P2IFG.1 P1IES.1 P2IN.2 unused INCLK CCI0B P2IE.2 P2IFG.2 P1IES.2 P2IN.3 CCI1B P2IE.3 P2IFG.3 P1IES.3 P2IN.4 unused P2IE.4 P2IFG.4 P1IES.4 Signal from or to Timer_A NOTES: 16. Optional selection of pullup or pulldown resistors with ROM (masked) versions. 17. Fuses for optional pullup and pulldown resistors can only be programmed at the factory. 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 APPLICATION INFORMATION Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module VCC P2SEL.5 0: Input 1: Output 0 P2DIR.5 Pad Logic See Note 16 1 Direction Control From Module See Note 17 0 P2OUT.5 P2.5 1 Module X OUT See Note 17 See Note 16 GND Bus Keeper P2IN.5 EN Module X IN D VCC P2IRQ.5 P2IE.5 P2IFG.5 Q EN Set Interrupt Flag Internal to Basic Clock Module 0 1 Interrupt Edge Select P2IES.5 DC Generator DCOR P2SEL.5 NOTE: DCOR: Control bit from basic clock module if it is set, P2.5 is disconnected from P2.5 pad PnSel.x PnDIR.x Director Control from module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 VSS P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5 NOTES: 16. Optional selection of pullup or pulldown resistors with ROM (masked) versions. 17. Fuses for optional pullup and pulldown resistors can only be programmed at the factory. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 APPLICATION INFORMATION Port P2, un-bonded bits P2.6 and P2.7 P2SEL.x 0: Input 1: Output 0 P2DIR.x 1 Direction Control From Module 0 P2OUT.x 1 Module X OUT P2IN.x Node Is Reset With PUC EN Bus Keeper Module X IN P2IRQ.x D P2IE.x P2IFG.x Q Set Interrupt Flag PUC Interrupt Edge Select EN P2IES.x P2SEL.x NOTE: x = Bit identifier, 6 to 7 for Port P2 without external pins P2Sel.x P2DIR.x Dir. Control from module P2OUT.x Module X OUT P2IN.x Module X IN P2IE.x P2IFG.x P2IES.x P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 VSS P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6 P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 VSS P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7 NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal other than from software. They work then as soft interrupt. JTAG fuse check mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated. 26 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0- 8 A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) DIM 4040000 / D 02/98 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 MSP430C111IDW, MSP430C112IDW, MSP430P112IDW, pin out DW PACKAGE (TOP VIEW) TEST/VPP VCC P2.5/ROSC VSS Xout/TCLK Xin RST/NMI P2.0/ACLK P2.1/INCLK P2.2/TA0 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2 P2.3/TA1 PMS430E112 pin out JL PACKAGE (TOP VIEW) TEST/VPP VCC P2.5/ROSC VSS Xout/TCLK Xin RST/NMI P2.0/ACLK P2.1/INCLK P2.2/TA0 28 POST OFFICE BOX 655303 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/PMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2 P2.3/TA1 * DALLAS, TEXAS 75265 MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196B- DECEMBER 1998 - REVISED APRIL 2000 MECHANICAL DATA JL (R-GDIP-T20) CERAMIC DUAL-IN-LINE PACKAGE 0.975 (24,76) 0.930 (23,62) 11 20 0.300 (7,62) 0.245 (6,22) 1 10 0.050 (1,27) 0.015 (0,38) 0.050 (1,27) 0.015 (0,38) Window 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.100 (2,54) 0.023 (0,58) 0.015 (0,38) 0-15 0.014 (0,36) 0.008 (0,20) 4040109/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only Falls within MIL-STD-1835 GDIP1-T20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 29 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated