2001 Microchip Technology Inc. DS21204C-page 1
M25AA040/25LC040/25C040
DEVICE SELECTION TABLE
FEATURES
• Low power CMOS technology
- Write current: 3 mA typical
- Read current: 500 µA typical
- Standby current: 500 nA typical
• 512 x 8-bit organization
• 16 byte page
• Write cycle time: 5 ms max.
• Self-timed ERASE and WRITE cycles
• Block write protection
- Protect none, 1/4, 1/2 or all of array
• Built -in wri te prot ection
- Power on/off data protection circuitry
- Write enable latch
- Write protect pin
• Seque nti al read
• High reliability
- Endurance: 1M c ycles
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP, SOIC, and TSSOP packages
• Temperature ranges supported:
DESCRIPTION
The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25XX040*) is a 4 Kbit serial Electrically Eras-
able PROM. The memory is accessed via a simple
Serial Peripheral Interface™ (SPI™) compatible serial
bus. The bus signals required are a clock input (SCK)
plus separate data in (SI) and data out (SO) lines.
Access to the devi ce is cont roll ed thro ugh a chip selec t
(CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write protect pin (WP).
BLOCK DIAGRAM
PACKAGE TYPES
Part
Number VCC
Range Max. Clock
Frequency Temp.
Ranges
25AA040 1.8-5.5V 1 MHz I
25LC040 2.5-5.5V 2 MHz I
25C040 4.5-5.5V 3 MHz I,E
- Industrial (I): -40°Cto +85°C
- Automotive (E) (25C040): -40°C to +125°C
SI
SO
SCK
CS
HOLD
WP
Status
Register
I/O Control Memory
Control
Logic
X
Dec
HV Genera to r
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
CS
SO
WP
VSS
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
25XX040
PDIP
HOLD
VCC
CS
SO
1
2
3
4
8
7
6
5
SCK
SI
VSS
WP
TSSOP
25XX040
CS
SO
WP
VSS
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
25XX040
SOIC
4K SPI™ Bus Serial EEPROM
*25XX040 is used in this document as a generic part number for the 25AA040/25LC040/25C040 devices.
SPI™ is a trademark of Motorola Inc.
25AA040/25LC040/25C040
DS21204C-page 2 2001 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS .......... ...... ..... ...... ...................... ........................................ ................. - 0.6V to VCC+1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-65°C to 125°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on all pins.........................................................................................................................................4 KV
1.1 DC Characteristics
† NOTICE: Stresses above those listed under ‘Maximu m rati ngs’ may cause permanent damage to the device. This
is a stres s ra tin g on ly a nd functional ope r ati on of the d evice at those or an y other conditi ons abo ve those indi ca ted in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended
period of time may affect d evice rel i ability
DC CHARACTERISTICS Industrial (I): TAMB = -40 °C to +85°C VCC = 1.8V to 5.5V
Automotive (E): TAMB = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
D001 VIH1High level input
voltage 2.0 VCC+1 V VCC ≥ 2.7V (Note)
D002 VIH20.7 VCC VCC+1 V VCC< 2.7V (Note)
D003 VIL1Low level input
voltage -0.3 0.8 V VCC ≥ 2.7V (Note)
D004 VIL2-0.3 0.3 VCC VVCC < 2.7V (Note)
D005 VOL Low level output
voltage —0.4 V IOL = 2.1 mA
D006 VOL —0.2 V IOL = 1.0 mA, VCC < 2.5V
D007 VOH High level output
voltage VCC -0.5 —VIOH =-400 µA
D008 ILI Input leakage current -10 10 µACS = VCC, VIN = VSS TO VCC
D009 ILO Output leakage
current -10 10 µACS = VCC, VOUT = VSS TO VCC
D010 CINT Internal Capacitance
(all inputs and outputs) —7pFTAMB = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (No t e)
D011 ICC Read Operating Current —
—1
500 mA
µAVCC = 5.5V; FCLK = 3.0 MHz; SO = Open
VCC = 2.5V; FCLK = 2.0 MHz; SO = Open
D012 ICC Write —
—5
3mA
mA VCC = 5.5V
VCC = 2.5V
D013 ICCS Standby Current —
—5
1µA
µACS = VCC = 5.5 V, Inputs t ied to VCC or VSS
CS = VCC = 2.5V, Inputs tied to VCC or VSS
Note: This parameter is periodically sampled and not 100% tested.
2001 Microchip Technology Inc. DS21204C-page 3
25AA040/25LC040/25C040
1.2 AC Characteristics
AC CHARACTERISTICS Industrial (I): TAMB = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): TAMB = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)
Param.
No. Sym. Characte r istic Min. Max . Units Test Conditions
1F
CLK Clock Frequency —
—
—
3
2
1
MHz
MHz
MHz
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
2T
CSS CS Setup Time 100
250
500
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
3T
CSH CS Hold Time 150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
4T
CSD CS Disable T ime 500 —ns —
5T
SU Data Setup Time 30
50
50
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
6T
HD Data Hold Tim e 50
100
100
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
7T
RCLK Rise Time —2µs(Note 1)
8T
FCLK Fall T ime —2µs(Note 1)
9T
HI Clock High Time 150
230
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
10 TLO Clock Low Time 150
230
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
11 TCLD Clock Delay T ime 50 —ns —
12 TCLE Clock Enable Time 50 —ns —
13 TVOutput Valid from Clock Low —
—
—
150
230
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
14 THO Output Hold Time 0 —ns (Note 1)
15 TDIS Output Disable Time —
—
—
200
250
500
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
16 THS HOLD Setup Time 100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
17 THH HOLD Hold Time 100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
18 THZ HOLD Low to Output High-Z 100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
19 THV HOLD High to Output Valid 100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
20 TWC Internal Write Cycle T ime —5ms—
21 —Endurance 1M —E/W
Cycles (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on our website: www.microchip.com.
25AA040/25LC040/25C040
DS21204C-page 4 2001 Microchip Technology Inc.
FIGURE 1-1: HOLD TIMING
FIGURE 1-2: SERIAL INPUT TIMING
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
HOLD
17
16 16 17
19
18
don’t care 5
high impedance
n+2 n+1 n n-1
n
n+2 n+1 n nn-1
CS
SCK
SI
SO
65
8
711
3
LSB in
MSB in
high impedance
12
Mode 1,1
Mode 0,0
2
4
CS
SCK
SO
10
9
13
MSB out ISB out
3
15
don’t care
SI
Mode 1,1
Mode 0,0
14
2001 Microchip Technology Inc. DS21204C-page 5
25AA040/25LC040/25C040
1.3 AC Test Conditions FIGURE 1-4: AC TEST CIRCUIT AC
AC Waveform:
VLO = 0.2V —
VHI = VCC - 0.2V (Note 1)
VHI = 4.0V (Note 2)
Timing Measurement Reference Lev el
Input 0.5 VCC
Output 0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
VCC
SO
100 pF
1.8 KΩ
2.25 KΩ
25AA040/25LC040/25C040
DS21204C-page 6 2001 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into standby mode.
However, a programming cycle which is already initi-
ated or in progress w ill be co mplet ed, reg ardles s of th e
CS input sign al. If CS is brought high during a pro gram
cycle, the device will go in standby mode as soon as
the pr ogramming cyc le is complete . When the device is
deselected, SO goes into the high impedance state,
allowing multiple parts to share the same SPI bus. A
low t o high trans ition on CS after a valid write sequence
initiates an internal write cycle. After power-up, a low
level on CS is requi red prior to a ny seque nce be ing in i-
tiated.
2.2 Serial Output (SO)
The SO pin is used to transfer data out of the 25XX040.
During a read cy cl e, data is shif ted out on this pin after
the falling edge of the serial clock.
2.3 Write Protect (WP)
This pin is a hardware write prote ct input pin. When WP
is low, all writes to the array or status register are dis-
abled, but any other operation functions normally.
When WP is high, all functions, including nonvolatile
writes operate normally. WP going low at any time will
reset the write enable latch and inhibit programming,
except when an internal write has already begun. If an
internal write cycle has already begun, WP going low
will h ave no effect on the write. Se e Table 3-2 for Wr i te
Protect Functionality Matrix.
2.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
2.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX040. Instructions,
address es or data presen t on th e SI pin are la tc hed on
the risin g e dge of the clo ck in put, w hil e d at a on the SO
pin is updated after the falling edge of the clock input.
2.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX040 w hile in the middle of a seri al sequ ence wit h-
out hav ing to re trans m it the en tire s equ enc e aga in at a
later time. It must be held high any time this function is
not being used. Once the device is selected and a
serial sequence is underway, the HOLD pin may be
pulled low to pause further serial communication with-
out resetting the serial sequence. The HOLD pin must
be brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high to
low tr ansition. The 25XX0 40 must remain selected dur-
ing this sequence. The SI, SCK and SO pins are in a
high impedance st ate during the time the part is p aused
and transitions on these pins will be ignored. To resume
serial communication, HOLD must be brought high
while the SCK pin is low, otherwise serial communica-
tion will not resume. Lowering the HOLD line at any
time wil l tri-state the SO line.
Name PDIP SOIC TSSOP Description
CS 1 1 3 Chip Select Input
SO 2 2 4 Serial Data Output
WP 3 3 5 Write Protect Pin
VSS 4 4 6 Ground
SI 5 5 7 Serial Data Input
SCK 6 6 8 Serial Clock Input
HOLD 7 7 1 Hold Input
VCC 8 8 2 Supply Voltage
2001 Microchip Technology Inc. DS21204C-page 7
25AA040/25LC040/25C040
3.0 FUNCTIONAL DESCRIPTION
3.1 Principles of Operation
The 25XX040 is a 512 byte Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X micro-
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete
I/O lines programmed properly with the software.
The 25XX04 0 contain s an 8-bit instr uction regist er . The
part is acc ess ed v ia the SI pi n, with da t a be ing c loc ke d
in on the rising edge of SCK. The CS pin must be low
and the HOLD pin must be high for the entire opera tion.
The WP pin must be held high to allow writing to the
memory array.
Table 3-1 contains a list of the possible instruction
bytes and format for dev ice ope ration . The most si gnif-
icant address bit (A8) is located in the instruction byte.
All instructions, addresses, and data are transferred
MSB first, LSB last.
Dat a is sampled on the firs t rising edg e of SCK afte r CS
goes low. If the clock line is shared with other periph-
eral devices on the SPI bus, the user can assert the
HOLD input and place the 25XX040 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
3.2 Read Sequence
The part is selected by pulling CS low. The 8-bit read
instruction with the A8 address bit is transmitted to the
25XX040 followed by the lower 8-bit address (A7
through A0). After the correct read instruction and
address are sent, the data stored in the memory at the
select ed address is sh ifted out on the SO pin. The data
stored in the memory at the next address can be read
sequen tially by co nti nui ng to provide clock p uls es . Th e
internal address pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(01FFh), the address counter rolls over to address
0000h allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by raising the
CS pin (Figure 3-1).
3.3 Write Sequence
Prior to any attempt to write data to the 25XX040, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-4). This is done by setting C S low
and then clocking out the proper instruction into the
25XX040. Af ter all eight bits of the i nstruction are trans-
mitted, the CS must be brought high to set the write
enable latch. If the write operation is initiated immedi-
ately after the WREN instruction without CS being
brought high, the data will not be written to the array
becaus e the wri te enable latch w ill not h ave been prop-
erly se t.
Once the write enable latch is set, the user may pro-
ceed by setting the CS low, issu ing a writ e ins tru ction ,
followed by the address, and then the data to be writ-
ten. Keep in mind that the most significant address bit
(A8) is included in the instruction byte. Up to 16 bytes
of dat a can be sent to the 25 XX040 before a writ e cycle
is nece ss ary. The only restrict io n is th at a ll o f the bytes
must reside in the same page. A page address begins
with XXXX 0000 and ends with XXXX 1111. If the
internal address counter reaches XXXX 1111 and the
clock continues, the counter will roll back to the first
address of the p age and ov erwrite a ny data in the page
that may have been written.
For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the status register may
be read to check the status of the WIP, WEL, BP1 and
BP0 bits (Figure 3-6). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.
TABLE 3-1: INSTRUCTION SET
Instruction Name Instruction Format Description
READ 0000 A8011 Read data from memory array beginning at selected address
WRITE 0000 A8010 Write data to memory array beginning at selected address
WRDI 0000 0100 Reset the write enable latch (disable write operations)
WREN 0000 0110 Set the write enable latch (enable write operations)
RDSR 0000 0101 Read status register
WRSR 0000 0001 Write status register
Note: A8 is the 9th address bit necessary to fully address 512 bytes.
25AA040/25LC040/25C040
DS21204C-page 8 2001 Microchip Technology Inc.
FIGURE 3-1: READ SEQUENCE
FIGURE 3-2: BYTE WRITE SEQUENCE
FIGURE 3-3: PAGE WRITE SEQUENCE
SO
SI
SCK
CS
0 23456789101112131415161718192021221
01A800001A76541A0
76543210
instruction lower address byte
data out
high impedance
23
32 don’t care
SO
SI
SCK
CS
0 23456789101112131415161718192021221
00A80000A7654
1A076543210
instruction lower address byte data byte
high impedance
23
32
1
TWC
SI
CS
91011 1415161718192021222324
00A800001A7654
21076543210
instruction lower address byte data byte 1
SCK
0 23456718
SI
CS
34 35 36 39 40
76543210
data byte n (16 max)
SCK
25 27 28 29 30 31 3226 33
76543210
data byte 3
76543210
data byte 2
37 38
3
13
2001 Microchip Technology Inc. DS21204C-page 9
25AA040/25LC040/25C040
3.4 Wr it e Enable (WREN) and Write
Disable (WRDI)
The 25XX040 contains a write enable latch. See
Table 3-3 for the Write Protect Functionality Matrix.
This latch must be set before any write ope ration will be
comple ted in ternally. The WREN instructio n will s et the
latch, and the WRDI will reset the latch.
The following is a list of conditions under which the
write enab le latc h wi ll be reset:
•Power-up
•WRDI instru ction success fu lly exec ute d
•WRSR instruction successfully executed
•WRITE instruction successfully executed
•WP line is low
FIGURE 3-4: WRITE ENABLE SEQUENCE
FIGURE 3-5: WRITE DISABLE SEQUENCE
SCK 0 2345671
SI
high impedance
SO
CS
010000 01
SCK 0 2345671
SI
high impedance
SO
CS
010000 010
25AA040/25LC040/25C040
DS21204C-page 10 2001 Microchip Technology Inc.
3.5 Read Status Regist er (RDSR)
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even du ring a write cycl e. The s ta tus reg ister i s form at-
ted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX040 is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read only.
The W rite Enable La tch (WEL) bit indi cat es the st atu s
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array, when set to a ‘0’, the latch
prohibits writes to the array. The state of this bit can
always be updated vi a the WREN or WR DI comm ands
regardless of the state of write protection on the status
register. This bit is read only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are nonvolatile.
See Figure 3-6 for RDSR timing sequence.
3.6 Write Status Register (WRSR)
The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the status register. The array is
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg-
ments of the array. The partitioning is controlled as
illustrated in Table 3-2.
See Figure 3-7 for WRSR timing sequence.
TABLE 3-2: ARRAY PROTECTION
FIGURE 3-6: READ STATUS REGISTER SEQUENCE
FIGURE 3-7: WRITE STATUS REGISTER SEQUENCE
7654 3 2 1 0
XXXXBP1 BP0 WEL WIP
BP1 BP0 Array Addresses
Write Protected
00 none
01 upper 1/4
(0180h - 01FFh)
10 upper 1/2
(0100h - 01FFh)
11 all
(0000h - 01FFh)
SO
SI
CS
9101112131415
11000000
7654 210
instruction
data from status register
high impedance
SCK
0 23456718
3
SO
SI
CS
9101112131415
01000000
7654 210
instruction data to status register
high impedance
SCK
0 23456718
3
2001 Microchip Technology Inc. DS21204C-page 11
25AA040/25LC040/25C040
3.7 Data Protection
The foll ow in g pro tec tio n h as been implem en ted to p re-
vent inadvertent writes to the array:
•The write enable latch is reset on power-up
•A write enable instruction must be issued to set
the write enable latch
•After a byte write, page write or status register
write, the write enable latch is reset
•CS must be set high after the proper number of
clock cycles to start an internal write cycle
•Access to the array during an internal write cycle
is ignored and programming is continued
•The w rite e nable latc h is rese t when the WP pi n is
low
3.8 Power On State
The 25XX040 powers on in t he fo llowi ng stat e:
•The devic e is in low power sta ndb y m ode (CS=1)
•The write enable latch is reset
•SO is in high impedance state
•A low level on CS is required to enter active state
TABLE 3-3: WRITE PROTECT FUNCTIONALITY MATRIX
WP WEL Protected Blocks Unprotected Blocks Status Register
Low XProtected Protected Protected
High 0Protected Protected Protected
High 1Protected Writable Writable
25AA040/25LC040/25C040
DS21204C-page 12 2001 Microchip Technology Inc.
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead TSSOP Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
XXXX
XYWW
NNN
25AA040
I/PNNN
YYWW
25AA040
I/SNYYWW
NNN
5A4X
IYWW
NNN
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event th e full Mi crochi p pa rt numbe r cannot be ma rked on on e line, it will
be carried ov er to the ne xt li ne thus lim iti ng th e nu mb er of av ai lab le c hara ct ers
for customer specific information.
*Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2001 Microchip Technology Inc. DS21204C-page 13
25AA040/25LC040/25C040
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row S pacing §eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
25AA040/25LC040/25C040
DS21204C-page 14 2001 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC)
Foot A ngle f048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004
A1
Standoff §1.551.421.32.061.056.052A2M old ed Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45×
f
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
2001 Microchip Technology Inc. DS21204C-page 15
25AA040/25LC040/25C040
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1Molded Pa ckag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002
A1
Standoff §0.950.900.85.037.035.033A2Molded Pa ckag e Thick ness 1.10.043AOverall Height 0.65.026
p
Pitch 88
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits
α
A2
A
A1
L
c
β
f
1
2D
n
p
B
E
E1
Foot A ngle f048048
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side .
JEDEC Equivalent: MO-153
Drawing No. C04-086
§ Significant Characteristic
25AA040/25LC040/25C040
DS21204C-page 16 2001 Microchip Technology Inc.
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used b y Micr ochip as a me ans to mak e
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Connecting to the Microchip Internet Web Site
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The file transfer site is available by using an FTP ser-
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The web site and file transfer site provide a variety of
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2001 Microchip Technology Inc. DS21204C-page 17
25AA040/25LC040/25C040
READER RESPONSE
It is ou r intentio n to pro vi de you w it h th e b es t documentation po ss ib le to e ns ure suc c ess fu l u se of y ou r M ic roc hip pro d-
uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subject matter, and ways in wh ich our d ocument ation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-7578.
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DS21204C
25AA040/25LC040/25C040
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
25AA040/25LC040/25C040
DS21204C-page 18 2001 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X/XX
PackageTemperature
Range
Device
Device: 25AA040: 4096-bit 1.8V SPI Serial EEPROM
25AA040T: 4096-bit 1.8V SPI Serial EEPROM
(Tape and Reel)
25AA040X: 4096-bit 1.8V SPI Serial EEPRO M
in alternate pinout (ST only)
25AA040XT:4096-bit 1.8V SPI Serial EEPROM
in alternate pinout Tape and Reel
(ST only)
25LC040: 4096-bit 2.5V SPI Serial EEPROM
25LC040T: 4096-bit 2.5V SPI Serial EEPROM
(Tape and Reel)
25LC040X: 4096-bit 2.5V SPI Serial EEPROM
in alternate pinout (ST only)
25LC040XT:4096-bit 2.5V SPI Serial EEPROM
in alternate pinout Tape and Reel
(ST only)
25C040: 4096-bit 5.0V SPI Serial EEPROM
25C040T: 4096-bit 5.0V SPI Serial EEPROM
(Tape and Reel)
25C040X: 4096-bit 5.0V SPI Serial EEPROM
in alternate pinout (ST only)
25C040XT: 4096-bit 5.0V SPI Serial EEPROM
in alternate pinout Tape and Reel
(ST only)
Temperature
Range: I = -40 °C to+85 °C
E = -40 °C to+125 °C
Package: P = P lastic DIP (300 mil body), 8-lead
SN = P lastic SOIC (150 mil body), 8-lead
ST = Plastic TSSOP (4.4 mm body), 8-lead
Examples:
a) 25AA040-I/P: Industrial Temp.,
PDIP package
b) 25AA040-I/SN: Industrial Tem p.,
SOIC pack a ge
c) 25AA040T-I/SN: Tape and Reel,
Industrial Tem p., SOIC packag e
d) 25AA040X-I/ST: Alternate Pinout,
Industrial Tem p ., TSSOP package
e) 25AA040XT-I/ST: Alternate Pinout, Tape
and Reel, Industrial Temp., TSSOP
package
f) 25LC040-I /P: Industrial Temp.,
PDIP package
g) 25LC040-I/SN: Industrial Temp.,
SOIC pack a ge
h) 25LC040T-I/SN: Tape and Reel,
Industrial Tem p., SOIC packag e
i) 25LC040X-I/ST: Alternate Pinout,
Industrial Tem p ., TSSOP package
j) 25LC040XT-I/ST: Alternate Pinout, Tape
and Reel, Industrial Temp., TSSOP
package
k) 25C040-I/P: Industrial Tem p.,
PDIP package
l) 25C040-I/SN: Industrial Temp.,
SOIC pack a ge
m) 25C040T-I/SN: Tape and Reel,
Industrial Tem p., SOIC packag e
n) 25C040X-I/ST: Alternate Pinout,
Industrial Tem p ., TSSOP package
o) 25C040XT-I/ST: Alternate Pinout, Tape
and Reel, Industrial Temp., TSSOP
package
p) 25C040-E/P: Extended Temp.,
PDIP package
q) 25C040-E/SN: Extended Temp.,
SOIC pack a ge
r) 25C040T-E/SN: Tape and Reel,
Extended Tem p ., SOIC package
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2001 Microchip Technology Inc. DS21204C-page 19
25AA040/25LC040/25C040
“All rights reserved. Copyright © 2001, Microchip
Technology Incorporated, USA. Information contained
in this publication regarding device applications and the
like is intended through suggestion only and may be
superse ded by updates . No repr esent ati on or warrant y
is given and no liabil ity is assume d by Microchip
Technology Incorporated with respect to the accuracy
or use of such information, or infringement of patent s or
other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized
except with express written approval by Microchip. No
licenses are conveyed, implicitly or otherwise, under
any int ell ectual pro per ty righ ts. The Mi croch ip log o and
name are registered trademarks of Microchip
Technology Inc. in the U.S.A. and other countries. All
rights reserve d. Al l other trade ma rks m enti one d h erei n
are the property of their respective companies. No
licenses are conveyed, implicitly or otherwise, under
any intellectual property rights.”
Trademarks
The Microchip name, logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, KEELOQ,
SEEVAL, MPLAB and The Embedded Contr ol
Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and
other countries.
Total Endurance, ICSP, In-Circuit Serial Programming,
FilterLab, MXDEV, microID, FlexROM, fuzzyLAB,
MPASM, MPLINK, MPLIB, PICDEM, ICEPIC,
Migratable Memory, FanSense, ECONOMONITOR,
SelectMode and microPort are trademarks of
Microchip Technology Incorporated in the U.S.A.
Serializ ed Q ui ck Term Programm in g (SQ TP) is a
service mark of Microchip Technology Incorporated in
the U.S.A.
All other trademarks mentioned herein are property of
their respec tiv e com p a ni es.
© 2001, M icr oc hip Techn olo gy Inco rpo rate d, Prin ted in
the U.S.A., All Rights Reserved.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
update s. It i s your respo nsibilit y to en sure t hat you r app licatio n mee ts with y our sp ecifica tions. N o re presen tation or warra nty is given and n o liability is
assumed by M icroc hip Te chnolog y Incor porate d wi th re spect t o the accur acy or use of such in formati on, o r infrin gemen t of patents or other intellectua l
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-
tual p roperty rights. The M icrochip logo an d name are reg istered tradema rks of Microchip Technol ogy Inc. in the U.S .A. and other count ries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21204C-page 20 2001 Microchip Technology Inc.
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 5/01 Printed on recycled paper.
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