19-4121; Rev 2; 6/09 KIT ATION EVALU E L B AVAILA Quad-Output Controller for Low-Power Architecture Features The MAX17017 is a quad-output controller for ultramobile portable computers (UMPCs) that rely on a lowpower architecture. The MAX17017 provides a compact, low-cost controller capable of providing four independent regulators--a main stage, a 3AP-P internal stepdown, a 5AP-P internal step-down, and a 2A source/sink linear regulator. o Fixed-Frequency, Current-Mode Controllers o 5.5V to 28V Input Range (Step-Down) or 3V to 5V Input Range (Step-Up) o 1x Step-Up or Step-Down Controller o 1x Internal 5AP-P Step-Down Regulator o 1x Internal 3AP-P Step-Down Regulator o 1x 2A Source/Sink Linear Regulator with Dynamic REFIN o Internal BST Diodes o Internal 5V, 50mA Linear Regulator o Fault Protection--Undervoltage, Overvoltage, Thermal, Peak Current Limit o Independent Enable Inputs and Power-Good Outputs o Voltage-Controlled Soft-Start o High-Impedance Shutdown o 10A (typ) Shutdown Current Ordering Information PART TEMP RANGE PIN-PACKAGE MAX17017GTM+ -40C to +105C 48 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Pin Configuration POKB BSTB LXB LXB LXB DLA BSTA LXA DHA POKA FBA TOP VIEW FBB The main regulator can be configured as either a stepdown converter (for 2 to 4 Li+ cell applications) or as a step-up converter (for 1 Li+ cell applications). The internal switching regulators include 5V synchronous MOSFETs that can be powered directly from a single Li+ cell or from the main 3.3V/5V power stages. Finally, the linear regulator is capable of sourcing and sinking 2A to support DDR termination requirements or to generate a fixed output voltage. The step-down converters use a peak current-mode, fixed-frequency control scheme--an easy to implement architecture that does not sacrifice fast-transient response. This architecture also supports peak currentlimit protection and pulse-skipping operation to maintain high efficiency under light-load conditions. Separate enable inputs and independent open-drain power-good outputs allow flexible power sequencing. A soft-start function gradually ramps up the output voltage to reduce the inrush current. Disabled regulators enter high-impedance states to avoid negative output voltage created by rapidly discharging the output through the low-side MOSFET. The MAX17017 also includes output undervoltage, output overvoltage, and thermal-fault protection. The MAX17017 is available in a 48-pin, 6mm x 6mm thin QFN package. 36 35 34 33 32 31 30 29 28 27 26 25 ONB 37 24 CSPA SYNC 38 23 CSNA ONA 39 22 AGND 1-to-4 Li+ Cell Battery-Powered Devices INBC 40 21 REF Low-Power Architecture INBC 41 Ultra-Mobile PC (UMPC) INBC 42 Applications Portable Gaming Notebook and Subnotebook Computers PDAs and Mobile Communicators 20 FREQ MAX17017 19 UP/DN INBC 43 18 INA VDD 44 17 VCC POKD 45 16 BYP OND 46 15 LDO5 ONC 47 14 INLDO EXPOSED PAD = GND LXC 8 9 10 11 12 REFIND LXC 7 FBD LXC 6 VTTR 5 IND 4 OUTD 3 OUTD 2 13 SHDN LXC 1 BSTC + POKC FBC 48 THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX17017 General Description MAX17017 Quad-Output Controller for Low-Power Architecture ABSOLUTE MAXIMUM RATINGS INLDO, SHDN to GND............................................-0.3V to +28V LDO5, INA, VDD, VCC to GND ..................................-0.3V to +6V DHA to LXA .............................................-0.3V to (VBSTA + 0.3V) ONA, ONB, ONC, OND to GND ...............................-0.3V to +6V POKA, POKB, POKC, POKD to GND .........-0.3V to (VCC + 0.3V) REF, REFIND, FREQ, UP/DN, SYNC to GND ........................................-0.3V to (VCC + 0.3V) FBA, FBB, FBC, FBD to GND .....................-0.3V to (VCC + 0.3V) BYP to GND ............................................-0.3V to (VLDO5 + 0.3V) CSPA, CSNA to GND .................................-0.3V to (VCC + 0.3V) DLA to GND................................................-0.3V to (VDD + 0.3V) INBC, IND to GND....................................................-0.3V to +6V OUTD to GND............................................-0.3V to (VIND + 0.3V) VTTR to GND.............................................-0.3V to (VBYP + 0.3V) LXB, LXC to GND ....................................-1.0V to (VINBC + 0.3V) BSTB to GND ....................................(VDD - 0.3V) to (VLXB + 6V) BSTC to GND ....................................(VDD - 0.3V) to (VLXC + 6V) BSTA to GND ....................................(VDD - 0.3V) to (VLXA + 6V) REF Short-Circuit Current......................................................1mA Continuous Power Dissipation (TA = +70C) Multilayer PCB: 48-Pin 6mm x 6mm2 TQFN (T4866-2 derated 37mW/C above +70C) ....................2.9W Operating Temperature Range .........................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL Input Voltage Range INA Undervoltage Threshold VINA(UVLO) CONDITIONS TA = 0C to +85C MIN TYP UP/DN = GND (step-up), INA 3.0 5.0 UP/DN = LDO5 (step-down), INLDO, INA = LDO5 5.5 24 UP/DN = GND (step-up), INA = INLDO, rising edge hysteresis = 100mV 2.5 2.7 2.9 UP/DN = LDO5 (step-down), INA = VCC, rising edge, hysteresis = 160mV 4.0 4.2 4.4 INBC Input Voltage Range UP/DN = GND (step-up) UNITS V V 2.3 Minimum Step-Up Startup Voltage MAX 2.9 5.5 3.0 V V SUPPLY CURRENTS VIN = 5.5V to 26V, SHDN = GND 10 15 A VINLDO = 5.5V to 26V, ON_ = GND, SHDN = INLDO 50 80 A VCC Shutdown Supply Current SHDN = ONA = ONB = ONC = OND = GND, TA = +25C 0.1 1 A VDD Shutdown Supply Current SHDN = ONA = ONB = ONC = OND = GND, TA = +25C 0.1 1 A SHDN = ONA = ONB = ONC = OND = GND, UP/DN = VCC 7 10 A 210 300 A VINLDO Shutdown Supply Current IIN(SHDN) VINLDO Suspend Supply Current IIN(SUS) INA Shutdown Current VCC Supply Current Main Step-Down Only 2 IINA ONA = VCC, ONB = ONC = OND = GND; does not include switching losses, measured from VCC _______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture (Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS TA = 0C to +85C MIN TYP MAX UNITS VCC Supply Current Main Step-Down and Regulator B ONA = ONB = VCC, ONC = OND = GND; does not include switching losses, measured from VCC 280 350 A VCC Supply Current Main Step-Down and Regulator C ONA = ONC = VCC, ONB = OND = GND; does not include switching losses, measured from VCC 280 350 A VCC Supply Current Main Step-Down and Regulator D ONA = OND = VCC, ONB = ONC = GND; does not include switching losses; measured from VCC 2.2 3 mA INA Supply Current (Step-Down) IINA ONA = VCC, UP/DN = VCC (step-down) 40 60 A INA + VCC Step-Up Supply Current IINA ONA = VCC, UP/DN = GND (step-up) 320 410 A 5V LINEAR REGULATOR (LDO5) LDO5 Output Voltage VLDO5 LDO5 Short-Circuit Current Limit VINLDO = 5.5V to 26V, ILDO5 = 0 to 50mA, BYP = GND 4.8 5.0 5.2 V LDO5 = BYP = GND 70 160 250 mA BYP Switchover Threshold VBYP Rising edge 4.65 LDO5-to-BYP Switch Resistance RBYP LDO5 to BYP, VBYP = 5V, ILDO5 = 50mA 1.5 4 V Reference Output Voltage VREF No load 1.25 1.263 V Reference Load Regulation _VREF IREF = -1A to +50A 3 10 mV _ 1.25V REFERENCE Reference Undervoltage Lockout 1.237 VREF(UVLO) 1.0 V OSCILLATOR Oscillator Frequency fOSC FREQ = VCC 500 FREQ = REF 750 FREQ = GND Switching Frequency 0.9 1.0 fSWA Main step-up/step-down (regulator A) fSWB Regulator B fOSC fSWC Regulator C 1/2 fOSC Maximum Duty Cycle (All Switching Regulators) DMAX Minimum On-Time (All Switching Regulators) tON(MIN) kHz 1.1 MHz 1/2 fOSC 90 MHz 93.5 FREQ = VCC or GND 90 FREQ = REF 75 % ns REGULATOR A (Main Step-Up/Step-Down) Step-up configuration (UP/DN = GND) 3.0 VCC + 0.3 1.0 VCC + 0.3 V Output-Voltage Adjust Range Step-down configuration (UP/DN = VCC) _______________________________________________________________________________________ 3 MAX17017 ELECTRICAL CHARACTERISTICS (continued) MAX17017 Quad-Output Controller for Low-Power Architecture ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER FBA Regulation Voltage FBA Regulation Voltage (Overload) FBA Load Regulation SYMBOL VFBA VFBA VFBA CONDITIONS MIN TYP MAX Step-up configuration (UP/DN = GND), VCSPA - VCSNA = 0 to 20mV, 90% duty cycle 0.975 0.99 1.013 Step-down configuration (UP/DN = VCC), VCSPA - VCSNA = 0mV, 90% duty cycle 0.968 Step-up configuration (UP/DN = GND), VCSPA - VCSNA = 0mV, 90% duty cycle 0.959 Step-down configuration (UP/DN = VCC), VCSPA - VCSNA = 0 to 20mV, 90% duty cycle FBA Input Current IFBA Current-Sense Input CommonMode Range VCSA Current-Sense Input Bias Current ICSA Current-Limit Threshold (Positive) VILIMA Idle ModeTM Threshold VIDLEA Zero-Crossing Threshold VIZX DHA Gate Driver On-Resistance RDH 0.97 V 0.930 1.003 Step-down configuration (UP/DN = VCC), VCSPA - VCSNA = 0 to 20mV -40 Step-down (UP/DN = VCC) UP/DN = GND or VCC, TA = +25C mV 5 10 16 mV 10 16 22 -100 -5 +100 nA VCC + 0.3V V 0 TA = +25C 18 40 60 A 20 22 mV 4 mV 1 mV DHA forced high and low 2.5 5 DLA forced high 2.5 5 DLA forced low 1.5 3 DLA Gate Driver On-Resistance RDL DHA Gate Driver Source/Sink Current IDH DHA forced to 2.5V 0.7 DLA Gate Driver Source/Sink Current IDL(SRC) DLA forced to 2.5V 0.7 IDL(SNK) DLA forced to 2.5V 1.5 BSTA Switch On-Resistance RBSTA 5 Idle Mode is a trademark of Maxim Integrated Products, Inc. 4 1.003 1.013 -20 Step-up (UP/DN = GND) UNITS V Step-up configuration (UP/DN = GND), VCSPA - VCSNA = 0 to 20mV UP/DN = GND or VCC, 0 to 100% duty cycle FBA Line Regulation TA = 0C to +85C _______________________________________________________________________________________ A A Quad-Output Controller for Low-Power Architecture (Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS TA = 0C to +85C MIN TYP MAX ILXB = 0% duty cycle (Note 2) 0.747 0.755 0.762 ILXB = 0 to 2.5A, 0% duty cycle (Note 2) 0.720 UNITS REGULATOR B (Internal 3A Step-Down Converter) FBB Regulation Voltage FBB Regulation Voltage (Overload) FBB Load Regulation VFBB VFBB/ILXB ILXB = 0 to 2.5A FBB Line Regulation FBB Input Current 0 to 100% duty cycle IFBB Internal MOSFET On-Resistance LXB Peak Current Limit LXB Idle-Mode Trip Level LXB Zero-Crossing Trip Level LXB Leakage Current -5 V V mV/A 7 8 10 mV -100 -5 +100 nA High-side n-channel 75 150 Low-side n-channel 40 80 3.45 4.0 TA = +25C IPKB 3.0 IIDLEB IZXB ILXB 0.762 ONB = GND, VLXB = GND or 5V; VINBC = 5V at TA = +25C m A 0.8 A 100 mA -20 +20 A 0.762 V REGULATOR C (Internal 5A Step-Down Converter) FBC Regulation Voltage FBC Regulation Voltage (Overload) FBC Load Regulation VFBC Internal MOSFET On-Resistance LXC Idle-Mode Trip Level LXC Zero-Crossing Trip Level LXC Leakage Current ILXC = 0 to 4A, 0% duty cycle (Note 2) 0.710 0 to 100% duty cycle IFBC LXC Peak Current Limit 0.747 VFBC/ILXC ILXC = 0 to 4A FBC Line Regulation FBC Input Current ILXC = 0A, 0% duty cycle (Note 2) TA = +25C 0.762 -7 12 14 16 mV nA -5 +100 50 100 Low-side n-channel 25 40 5.75 6.5 IPKC -100 5.0 IZXC ONC = GND, VLXC = GND or 5V; VINBC = 5V at TA = +25C V mV/A High-side n-channel IIDLEC ILXC 0.755 m A 1.2 A 100 mA -20 +20 A 1 2.8 V REGULATOR D (Source/Sink Linear Regulator and VTTR Buffer) IND Input Voltage Range VIND IND Supply Current OND = VCC IND Shutdown Current OND = GND, TA = +25C 50 A 10 A 0.5 1.5 V -100 +100 nA 0.5 1.5 V VFBD with respect to VREFIND, OUTD = FBD, IOUTD = +50A (source load) -10 0 VFBD with respect to VREFIND, OUTD = FBD, IOUTD = -50A (sink load) 0 +10 REFIND Input Range REFIND Input Bias Current OUTD Output Voltage Range FBD Output Accuracy FBD Load Regulation VREFIND = 0 to 1.5V, TA = +25C VOUTD VFBD IOUTD = 1A 10 mV -17 -13 mV/A _______________________________________________________________________________________ 5 MAX17017 ELECTRICAL CHARACTERISTICS (continued) MAX17017 Quad-Output Controller for Low-Power Architecture ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS TA = 0C to +85C MIN TYP MAX FBD Line Regulation VIND = 1.0V to 2.8V, IOUTD = 200mA FBD Input Current VFBD = 0 to 1.5V, TA = +25C OUTD Linear Regulator Current Limit Source load +2 +4 Sink load -2 -4 Current-Limit Soft-Start Time Internal MOSFET On-Resistance VTTR Output Accuracy 1 0.1 mV 0.5 With respect to internal OND signal 160 High-side on-resistance 120 250 Low-side on-resistance 180 450 REFIND to VTTR A A s IVTTR = 0.5mA -10 +10 IVTTR = 3mA -20 +20 VTTR Maximum Current Rating UNITS 5 m mV mA FAULT PROTECTION SMPS POK and Fault Thresholds VTT LDO POKD and Fault Threshold Upper threshold rising edge, hysteresis = 50mV 9 12 14 Lower threshold falling edge, hysteresis = 50mV -14 -12 -9 Upper threshold rising edge, hysteresis = 50mV 6 12 16 Lower threshold falling edge, hysteresis = 50mV -16 -12 -6 % % POK Propagation Delay tPOK FB_ forced 50mV beyond POK_ trip threshold 5 s Overvoltage Fault Latch Delay tOVP FB_ forced 50mV above POK_ upper trip threshold 5 s SMPS Undervoltage Fault Latch Delay tUVP FBA, FBB, or FBC forced 50mV below POK_ lower trip threshold 5 s VTT LDO Undervoltage Fault Latch Delay tUVP FBD forced 50mV below POKD lower trip threshold 5000 s POK Output Low Voltage VPOK ISINK = 3mA IPOK VFBA = 1.05V, VFBB = VFBC = 0.8V, VFBD = VREFIND + 50mV (POK high impedance); POK_ forced to 5V, TA = +25C POK Leakage Currents Thermal-Shutdown Threshold TSHDN Hysteresis = 15C 0.4 V 1 A 160 C GENERAL LOGIC LEVELS SHDN Input Logic Threshold Hysteresis = 20mV 0.5 1.6 V SHDN Input Bias Current TA = +25C -1 +1 A ON_ Input Logic Threshold Hysteresis = 170mV 0.5 1.6 V ON_ Input Bias Current TA = +25C A UP/DN Input Logic Threshold UP/DN Input Bias Current 6 TA = +25C -1 +1 0.5 1.6 V -1 +1 A _______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture (Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS High (VCC) TA = 0C to +85C MIN TYP UNITS VCC - 0.4V FREQ Input Voltage Levels Unconnected/REF FREQ Input Bias Current TA = +25C 1.65 3.8 Low (GND) V 0.5 SYNC Input Logic Threshold SYNC Input Bias Current MAX TA = +25C -2 +2 A 1.5 3.5 V -1 +1 A ELECTRICAL CHARACTERISTICS (Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = -40C to +105C.) (Note 1) PARAMETER SYMBOL Input Voltage Range INA Undervoltage Threshold VINA(UVLO ) CONDITIONS TYP MAX UP/DN = GND (step-up), INA 3.0 5.0 UP/DN = LDO5 (step-down), INLDO, INA = LDO5 5.5 24 UP/DN = GND (step-up), INA = INLDO, rising edge, hysteresis = 100mV 2.4 3.0 UP/DN = LDO5 (step-down), INA = VCC, rising edge, hysteresis = 160mV 3.9 4.5 2.3 5.5 INBC Input Voltage Range UP/DN = GND (step-up) Minimum Step-Up Startup Voltage TA = -40C to +105C MIN UNITS V V 3.0 V V SUPPLY CURRENTS VIN = 5.5V to 26V, SHDN = GND 15 A VINLDO = 5.5V to 26V, ON_ = GND, SHDN = INLDO 80 A SHDN = ONA = ONB = ONC = OND = GND, UP/DN = VCC 10 A VCC Supply Current Main Step-Down Only ONA = VCC, ONB = ONC = OND = GND; does not include switching losses, measured from VCC 350 A VCC Supply Current Main Step-Down and Regulator B ONA = ONB = VCC, ONC = OND = GND; does not include switching losses, measured from VCC 400 A VCC Supply Current Main Step-Down and Regulator C ONA = ONC = VCC, ONB = OND = GND, does not include switching losses, measured from VCC 400 A VINLDO Shutdown Supply Current IIN(SHDN) VINLDO Suspend Supply Current IIN(SUS) INA Shutdown Current IINA _______________________________________________________________________________________ 7 MAX17017 ELECTRICAL CHARACTERISTICS (continued) MAX17017 Quad-Output Controller for Low-Power Architecture ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = -40C to +105C.) (Note 1) PARAMETER SYMBOL VCC Supply Current Main Step-Down and Regulator D CONDITIONS TA = -40C to +105C MIN TYP MAX ONA = OND = VCC, ONB = ONC = GND, does not include switching losses, measured from VCC 3.5 INA Supply Current (Step-Down) IINA ONA = VCC, UP/DN = VCC (step-down) 75 INA + VCC Step-Up Supply Current IINA ONA = VCC, UP/DN = GND (step-up) 475 UNITS mA A 5V LINEAR REGULATOR (LDO5) LDO5 Output Voltage VLDO5 LDO5 Short-Circuit Current Limit VINLDO = 5.5V to 26V, ILDO5 = 0 to 50mA, BYP = GND LDO5 = BYP = GND 4.75 5.25 55 V mA 1.25V REFERENCE Reference Output Voltage Reference Load Regulation VREF VREF No load 1.237 IREF = -1A to +50A 1.263 V 12 mV 1.1 MHz OSCILLATOR Oscillator Frequency fOSC Maximum Duty Cycle (All Switching Regulators) DMAX FREQ = GND 0.9 89 % REGULATOR A (Main Step-Up/Step-Down) 3.0 VCC + 0.3V 1.0 VCC + 0.3V Step-up configuration, VCSPA - VCSNA = 0mV, 90% duty cycle 0.970 1.018 Step-down configuration, VCSPA - VCSNA = 0mV, 90% duty cycle 0.963 1.008 Step-up configuration (UP/DN = GND), VCSPA - VCSNA = 0 to 20mV, 90% duty cycle 0.954 1.018 Step-down configuration (UP/DN = VCC), VCSPA - VCSNA = 0 to 20mV, 90% duty cycle 0.925 1.008 Step-up (UP/DN = GND) 5 19 Step-down (UP/DN = VCC) 10 23 Step-up configuration (UP/DN = GND) Output-Voltage Adjust Range Step-down configuration (UP/DN = VCC) FBA Regulation Voltage FBA Regulation Voltage (Overload) VFBA FBA Line Regulation V V V mV Current-Sense Input CommonMode Range VCSA 0 VCC + 0.3V V Current-Limit Threshold (Positive) VILIMA 17 23 mV 8 _______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture (Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = -40C to +105C.) (Note 1) PARAMETER SYMBOL CONDITIONS TA = -40C to +105C MIN TYP MAX UNITS REGULATOR B (Internal 3A Step-Down Converter) FBB Regulation Voltage FBB Regulation Voltage (Overload) VFBB ILXB = 0A, 0% duty cycle (Note 2) 0.742 0.766 V ILXB = 0 to 2.5A , 0% duty cycle (Note 2) 0.715 0.766 V FBB Line Regulation LXB Peak Current Limit 6 12 mV 2.7 4.2 A ILXC = 0A, 0% duty cycle (Note 2) 0.742 0.766 V ILXC = 0 to 4A, 0% duty cycle (Note 2) 0.705 0.766 V IPKB REGULATOR C (Internal 5A Step-Down Converter) FBC Regulation Voltage FBC Regulation Voltage (Overload) VFBC FBC Line Regulation LXC Peak Current Limit IPKC 11 20 mV 5.0 6.5 A 1 2.8 V 70 A 0.5 1.5 V 0.5 1.5 V -12 0 0 +12 REGULATOR D (Source/Sink Linear Regulator and VTTR Buffer) IND Input Voltage Range VIND IND Supply Current OND = VCC REFIND Input Range OUTD Output Voltage Range FBD Output Accuracy VOUTD VFBD VFBD with respect to VREFIND, OUTD = FBD, IOUTD = +50A (source load) VFBD with respect to VREFIND, OUTD = FBD, IOUTD = -50A (sink load) mV FBD Load Regulation IOUTD = 1A -20 OUTD Linear Regulator Current Limit Source load +2 +4 Sink load -2 -4 Internal MOSFET On-Resistance VTTR Output Accuracy mV/A High-side on-resistance 300 Low-side on-resistance 475 REFIND to VTTR IVTTR = 3mA -20 +20 A m mV _______________________________________________________________________________________ 9 MAX17017 ELECTRICAL CHARACTERISTICS (continued) MAX17017 Quad-Output Controller for Low-Power Architecture ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = -40C to +105C.) (Note 1) PARAMETER SYMBOL CONDITIONS TA = -40C to +105C MIN TYP MAX UNITS FAULT PROTECTION Upper threshold rising edge, hysteresis = 50mV 8 16 SMPS POK and Fault Thresholds % VTT LDO POKD and Fault Threshold POK Output Low Voltage VPOK Lower threshold falling edge, hysteresis = 50mV -16 -8 Upper threshold rising edge, hysteresis = 50mV 6 16 Lower threshold falling edge, hysteresis = 50mV -16 -6 % I SINK = 3mA 0.4 V GENERAL LOGIC LEVELS SHDN Input Logic Threshold Hysteresis = 20mV 0.5 1.6 V ON_ Input Logic Threshold Hysteresis = 170mV 0.5 1.6 V 0.5 1.6 V 1.65 3.8 V 1.5 3.5 UP/DN Input Logic Threshold High (VCC) FREQ Input Voltage Levels Unconnected/REF VCC - 0.4V Low (GND) SYNC Input Logic Threshold 0.5 V Note 1: Limits are 100% production tested at TA = +25C. Maximum and minimum limits are guaranteed by design and characterization. Note 2: Regulation voltage tested with slope compensation. The typical value is equivalent to 0% duty cycle. In real application, the regulation voltage is higher due to the line regulation times the duty cycle. 10 ______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture 80 5.00 VIN = 20V VIN = 12V 70 65 VIN = 20V 4.95 VIN = 12V 4.90 4.85 VIN = 2.5V 90 85 VIN = 3.3V 80 75 VIN = 5V 70 60 4.80 55 55 4.75 0.1 10 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOAD CURRENT (A) 50 0.001 0.01 SMPS REGULATOR B OUTPUT VOLTAGE vs. LOAD CURRENT 1 10 SMPS REGULATOR C EFFICIENCY vs. LOAD CURRENT 90 MAX17017 toc04 1.82 0.1 LOAD CURRENT (A) LOAD CURRENT (A) MAX17017 toc05 0.01 VIN = 2.5V 85 80 VIN = 5V EFFICIENCY (%) OUTPUT VOLTAGE (V) 1.77 VIN = 2.5V VIN = 3.3V 75 70 VIN = 5V 65 VIN = 3.3V 60 55 1.72 0 0.5 1.0 1.5 2.0 2.5 50 0.001 3.0 0.01 0.1 10 1 LOAD CURRENT (A) LOAD CURRENT (A) SMPS REGULATOR C OUTPUT VOLTAGE vs. LOAD CURRENT REGULATOR D VOLTAGE vs. SOURCE/SINK LOAD CURRENT 0.930 1.03 VIN = 5V 1.02 1.01 VIN = 2.5V 1.00 0.920 0.915 0.910 0.905 0.900 0.895 VIN = 3.3V 0.99 0.925 VTT VOLTAGE (V) 1.04 MAX17017 toc07 1.05 MAX17017 toc06 50 0.001 95 65 VIN = 8V 60 100 EFFICIENCY (%) 85 OUTPUT VOLTAGE (V) EFFICIENCY (%) 90 75 5.05 MAX17017 toc02 VIN = 8V OUTPUT VOLTAGE (V) 95 MAX17017 toc01 100 SMPS REGULATOR B EFFICIENCY vs. LOAD CURRENT SMPS REGULATOR A OUTPUT VOLTAGE vs. LOAD CURRENT MAX17017 toc03 SMPS REGULATOR A EFFICIENCY vs. LOAD CURRENT 0.890 0.885 0.880 0.98 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOAD CURRENT (A) -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 LOAD CURRENT (A) ______________________________________________________________________________________ 11 MAX17017 Typical Operating Characteristics (Circuit of Figure 1, TA = +25C, unless otherwise noted.) MAX17017 Quad-Output Controller for Low-Power Architecture Typical Operating Characteristics (continued) (Circuit of Figure 1, TA = +25C, unless otherwise noted.) REG A STARTUP WAVEFORM (HEAVY LOAD) REG B STARTUP WAVEFORM (HEAVY LOAD) REG A SHUTDOWN WAVEFORM MAX17017 toc09 MAX17017 toc08 MAX17017 toc10 ONA ONA OUTA ONB OUTA POKA OUTB POKB POKA ILA ILA ILB LXA LXB LXA 400s/div 400s/div ONA: 5V/div OUTA: 5V/div POKA: 5V/div ILA: 5A/div LXA: 10V/div ONA: 5V/div OUTA: 5V/div POKA: 5V/div ILA: 5A/div LXA: 10V/div RLOAD = 1.6 400s/div RLOAD = 2.5 ONB: 5V/div OUTB: 2V/div POKB: 5V/div ILB: 2A/div LXB: 5V/div REG C STARTUP WAVEFORM (HEAVY LOAD) REG B SHUTDOWN WAVEFORM RLOAD = 1.01 REG C SHUTDOWN MAX17017 toc12 MAX17017 toc11 MAX17017 toc13 ONC ONB OUTB ONC OUTC POKB OUTC POKC POKC ILB ILC ILC LXB LXC LXC 400s/div 400s/div ONB: 5V/div OUTB: 2V/div POKB: 5V/div ILB: 2A/div LXB: 5V/div 12 RLOAD = 0.8 ONC: 5V/div OUTC: 1V/div POKC: 5V/div ILC: 5A/div LXC: 5V/div 100s/div RLOAD = 0.25 ONC: 5V/div OUTC: 1V/div POKC: 5V/div ILC: 5A/div LXC: 5V/div ______________________________________________________________________________________ RLOAD = 0.25 Quad-Output Controller for Low-Power Architecture REG A LOAD TRANSIENT (1A TO 3.2A) REG B LOAD TRANSIENT (0.4A TO 2A) OUTA LXA REG C LOAD TRANSIENT (0.8A TO 3A) MAX17017 toc15 MAX17017 toc14 MAX17017 toc16 OUTB OUTC LXB LXC ILA ILC ILB IOUTA IOUTC IOUTB 20s/div 20s/div OUTA: 100mV/div LXA: 10V/div ILA: 2A/div IOUTA: 2A/div VINA = 12V, LOAD TRANSIENT IS FROM 1A TO 3.2A OUTB: 50mV/div LXB: 5V/div ILB: 1A/div IOUTB: 2A/div REG D LOAD TRANSIENT (SOURCE/SINK) 20s/div VINBC = 5V, 0.4A TO 2.0A LOAD TRANSIENT OUTC: 50mV/div LXC: 5V/div ILC: 2A/div IOUTC: 2A/div REG D LOAD TRANSIENT (SINK) MAX17017 toc17 VINBC = 5V, 0.8A TO 3.0A LOAD TRANSIENT REG D LOAD TRANSIENT (SOURCE) MAX17017 toc18 MAX17017 toc19 OUTD OUTD OUTD IOUTD IOUTD IOUTD 20s/div OUTD: 20mV/div IOUTD: 1A/div IND = 1.8V, REFIND = 0.9V, COUT = 2 x 10F, LOAD TRANSIENT IS FROM 1A SOURCING TO 1A SINKING 20s/div OUTD: 10mV/div IOUTD: 1A/div IND = 1.8V, REFIND = 0.9V, COUT = 2 x 10F, LOAD TRANSIENT IS FROM 0 TO 1A SINKING 20s/div OUTD: 10mV/div IOUTD: 1A/div IND = 1.8V, REFIND = 0.9V, COUT = 2 x 10F, LOAD TRANSIENT IS FROM 0 TO 1A SOURCING ______________________________________________________________________________________ 13 MAX17017 Typical Operating Characteristics (continued) (Circuit of Figure 1, TA = +25C, unless otherwise noted.) Quad-Output Controller for Low-Power Architecture MAX17017 Pin Description PIN NAME 1 POKC Open-Drain Power-Good Output for the Internal 5A Step-Down Converter. POKC is low if FBC is more than 12% (typ) above or below the nominal 0.75V feedback regulation threshold. POKC is held low during startup and in shutdown. POKC becomes high impedance when FBC is in regulation. 2 BSTC Boost Flying Capacitor Connection for the Internal 5A Step-Down Converter. The MAX17017 includes an internal boost switch/diode connected between VDD and BSTC. Connect to an external capacitor as shown in Figure 1. 3-6 LXC 7, 8 OUTD 9 IND Source/Sink Linear Regulator Input. Bypass IND with a 10F or greater ceramic capacitor to ground. 10 FBD Feedback Input for the Internal Source/Sink Linear Regulator. FBD tracks and regulates to the REFIND voltage. 11 VTTR Ouput of Reference Buffer. Bypass with 0.22F for 3mA of output current. 12 REFIND Dynamic Reference Input Voltage for the Source/Sink Linear Regulator and the Reference Buffer. The linear regulator feedback threshold (FBD) tracks the REFIND voltage. 13 SHDN Shutdown Control Input. The device enters its 5A supply current shutdown mode if VSHDN is less than the SHDN input falling edge trip level and does not restart until VSHDN is greater than the SHDN input rising edge trip level. Connect SHDN to VINLDO for automatic startup of LDO5. INLDO Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to GND with a 0.1F or greater ceramic capacitor close to the controller. In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply. Connect BYP and INLDO to the system's 5V supply to effectively disable the linear regulator. LDO5 5V Internal Linear Regulator Output. Bypass with a 4.7F or greater ceramic capacitor. The 5V linear regulator provides the bias power for the gate drivers (VDD) and analog control circuitry (VCC). The linear regulator sources up to 50mA (max guaranteed). When BYP exceeds 4.65V (typ), the MAX17017 bypasses the linear regulator through a 1.5_ bypass switch. When the linear regulator is bypassed, LDO5 supports loads up to 100mA. In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply. Bypass SHDN to ground and leave LDO5 unconnected. Connect BYP and INLDO to effectively disable the linear regulator. BYP Linear Regulator Bypass Input. When BYP exceeds 4.65V, the controller shorts LDO5 to BYP through a 1.5_ bypass switch and disables the linear regulator. When BYP is low, the linear regulator remains active. The BYP input also serves as the VTTR buffer supply, allowing VTTR to remain active even when the source/sink linear regulator (OUTD) has been disabled under system standby/suspend conditions. In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply. Bypass LDO5 to ground with a 1F capacitor and leave this output unconnected. Connect BYP and INLDO to the system's 5V supply to effectively disable the linear regulator. 14 15 16 14 FUNCTION Inductor Connection for the Internal 5A Step-Down Converter. Connect LXC to the switched side of the inductor. Source/Sink Linear Regulator Output. Bypass OUTD with 2x 10F or greater ceramic capacitors to ground. Dropout needs additional output capacitance (see the VTT LDO Output Capacitor Selection (COUTD) section). ______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture PIN NAME 17 VCC 5V Analog Bias Supply. VCC powers all the analog control blocks (error amplifiers, current-sense amplifiers, fault comparators, etc.) and control logic. Connect VCC to the 5V system supply with a series 10_ resistor, and bypass to analog ground using a 1F or greater ceramic capacitor. 18 INA Input to the Circuit in Reg A in Boost Mode. Connect INA to the input in step-up mode (UP/DN = GND) and connect INA to LDO5 in step-down mode (UP/DN = VCC). 19 UP/DN Converter Configuration Selection Input for Regulator A. When UP/DN is pulled high (UP/DN = VCC), regulator A operates as a step-down converter (Figure 1). When UP/DN is pulled low (UP/DN = GND), regulator A operates as a step-up converter. FREQ Trilevel Oscillator Frequency Selection Input. FREQ = VCC: RegA = 250kHz, RegB = 500kHz, RegC = 250kHz FREQ = REF: RegA = 375kHz, RegB = 750kHz, RegC = 375kHz FREQ = GND: RegA = 500kHz, RegB = 1MHz, RegC = 500kHz 20 FUNCTION 1.25V Reference-Voltage Output. Bypass REF to analog ground with a 0.1F ceramic capacitor. The reference sources up to 50A for external loads. Loading REF degrades output voltage accuracy according to the REF load-regulation error. The reference shuts down when the system pulls SHDN low in buck mode (UP/DN = GND) or when the system pulls ONA low in boost mode (UP/DN = VCC). 21 REF 22 AGND Analog Ground 23 CSNA Negative Current-Sense Input for the Main Switching Regulator. Connect to the negative terminal of the currentsense resistor. Due to the CSNA bias current requirements, limit the series impedance to less than 10. 24 CSPA Positive Current-Sense Input for the Main Switching Regulator. Connect to the positive terminal of the currentsense resistor. Due to the CSPA bias current requirements, limit the series impedance to less than 10. 25 FBA 26 POKA 27 DHA High-Side Gate-Driver Output for the Main Switching Regulator. DHA swings from LXA to BSTA. 28 LXA Inductor Connection of Converter A. Connect LXA to the switched side of the inductor. 29 BSTA Boost Flying Capacitor Connection of Converter A. The MAX17017 includes an internal boost switch/diode connected between VDD and BSTA. Connect to an external capacitor as shown in Figure 1. 30 DLA Low-Side Gate-Driver Output for the Main Switching Regulator. DLA swings from GND to VDD. 31, 32, 33 LXB Inductor Connection for the Internal 3A Step-Down Converter. Connect LXB to the switched side of the inductor. 34 BSTB Boost Flying Capacitor Connection for the Internal 3A Step-Down Converter. The MAX17017 includes an internal boost switch/diode connected between VDD and BSTB. Connect to an external capacitor as shown in Figure 1. 35 POKB Open-Drain Power-Good Output for the Internal 3A Step-Down Converter. POKB is low if FBB is more than 12% (typ) above or below the nominal 0.75V feedback-regulation threshold. POKB is held low during softstart and in shutdown. POKB becomes high impedance when FBB is in regulation. Feedback Input for the Main Switching Regulator. FBA regulates to 1.0V. Open-Drain Power-Good Output for the Main Switching Regulator. POKA is low if FBA is more than 12% (typ) above or below the nominal 1.0V feedback regulation point. POKA is held low during soft-start and in shutdown. POKA becomes high impedance when FBA is in regulation. ______________________________________________________________________________________ 15 MAX17017 Pin Description (continued) Quad-Output Controller for Low-Power Architecture MAX17017 Pin Description (continued) PIN NAME FUNCTION 36 FBB Feedback Input for the Internal 3A Step-Down Converter. FBB regulates to 0.75V. 37 ONB Switching Regulator B Enable Input. When ONB is pulled low, LXB is high impedance. When ONB is driven high, the controller enables the 3A internal switching regulator. 38 SYNC External Synchronization Input. Used to override the internal switching frequency. 39 ONA Switching Regulator A Enable Input. When ONA is pulled low, DLA and DHA are pulled low. When ONA is driven high, the controller enables the step-up/step-down converter. 40-43 INBC Input for Regulators B and C. Power INBC from a 2.5V to 5.5V supply. Internally connected to the drain of the high-side MOSFETs for both regulator B and regulator C. Bypass to PGND with 2x 10F or greater ceramic capacitors to support the RMS current. 44 VDD 5V Bias Supply Input for the Internal Switching Regulator Drivers. Bypass with a 1F or greater ceramic capacitor. Provides power for the BSTB and BSTC driver supplies. 45 POKD Open-Drain Power-Good Output for the Internal Source/Sink Linear Regulator. POKD is low if FBD is more than 10% (typ) above or below the REFIND regulation threshold. POKD is held low during soft-start and in shutdown. POKD becomes high impedance when FBD is in regulation. 46 OND Source/Sink Linear Regulator (Regulator D) and Reference Buffer Enable Input. When OND is pulled low, OUTD is high impedance. When OND is driven high, the controller enables the source/sink linear regulator. 47 ONC Switching Regulator C Enable Input. When ONC is pulled low, LXC is high impedance. When ONC is driven high, the controller enables the 5A internal switching regulator. 48 FBC Feedback Input for the Internal 5A Step-Down Converter. FBC regulates to 0.75V. EP PGND Power Ground. The source of the low-side MOSFETs (REG B and REG C), the drivers for all switching regulators, and the sink MOSFET of the VTT LDO are all internally connected to the exposed pad. Connect the exposed backside pad to system power ground planes through multiple vias. Detailed Description The MAX17017 standard application circuit (Figure 1) provides a 5V/5AP-P main stage, a 1.8V/3AP-P VDDQ and 0.9A/2A VTT outputs for DDR, and a 1.05V/5AP-P chipset supply. The MAX17017 supports four power outputs--one highvoltage step-down controller, two internal MOSFET step-down switching regulators, and one high-current source/sink linear regulator. The step-down switching regulators use a current-mode fixed-frequency architecture compensated by the output capacitance. An internal 50mA 5V linear regulator provides the bias supply and driver supplies, allowing the controller to power up from input supplies greater than 5.5V. Fixed 5V Linear Regulator (LDO5) An internal linear regulator produces a preset 5V lowcurrent output from INLDO. LDO5 powers the gate drivers for the external MOSFETs, and provides the bias 16 supply required for the SMPS analog controller, reference, and logic blocks. LDO5 supplies at least 50mA for external and internal loads, including the MOSFET gate drive, which typically varies from 5mA to 15mA per switching regulator, depending on the switching frequency. Bypass LDO5 with a 4.7F or greater ceramic capacitor to guarantee stability under the fullload conditions. The MAX17017 switch-mode step-down switching regulators require a 5V bias supply in addition to the mainpower input supply. This 5V bias supply is generated by the controller's internal 5V linear regulator (LDO5). This boot-strappable LDO allows the controller to power up independently. The gate-driver VDD input supply is typically connected to the fixed 5V linear regulator output (LDO5). Therefore, the 5V LDO supply must provide LDO5 (PWM controller) and the gatedrive power during power-up. ______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture C1 4.7F, 6V 0603 15 44 PWR 19 C2 1.0F, 6V 0402 SHDN INLDO BSTA LDO5 DHA VDD LXA UP/DN R1 10 5%, 0402 DLA 17 18 VCC INA 39 37 ON OFF 47 ON OFF 46 ON OFF 5V SMPS OUTPUT R9 100k 5%, 0402 ONA FBA ONB BYP ONC 4x INBC OND R11 100k 5%, 0402 R12 100k 5%, 0402 BSTB 26 35 1 45 38 3x LXB POKA FBB POKC 28 30 BSTC 4x LXC FREQ AGND R13 15k 1%, 0402 AGND 11 C23 0.1F, 6V 0402 FBC VTTR AGND PWR L1 3.3H, 6A, 30m 6.7mm x 7.7mm x 3.0mm R15 4m (NEC/TOKIN: NH1 1% MPLC0730L3R3) C16 OPEN 0402 AGND PWR AGND 25 5V, 4A C14 150F, 35m, 6V B2 CASE PWR R3 40k 1%, 0402 C21 OPEN 0402 C21 680pF, 6V 0402 16 AGND 40-43 34 PWR C12 1F, 16V 0402 R4 10k 1%, 0402 AGND C13 10F, 6V 0805 PWR PWR C5 L2 0.1F, 6V 1.0H, 6.8A, 14.2m 0402 5.8mm x 6.2mm x 3.0mm (NEC/TOKIN: MPLC0525L1RO) 31, 32, 33 R5 14k 1%, 0402 36 R6 10.0k 1%, 0402 C22 1000pF, 6V 0402 AGND L3 C6 1.0H, H6.8A, 14.2m 0.1F, 5.8mm x 8.2mm x 3.0mm 6V (NEC/TOKIN: MPLC0525L1R0) 0402 2 3-6 R7 3.01k 1%, 0402 48 6V TO 16V C10 22F, 16V C-CASE 16TQC22M PWR AGND R8 10.0k 1%, 0402 C23 2200pF, 6V 0402 AGND 1.8V, 2.5A C14 330F 18m, 2.5V, B2 CASE PWR C16 330F 18m, 2.5V, B2 CASE 1.05V, 4A AGND IND 9 2x OUTD R14 15.0k 1%, 0402 PWR C17 1F, 6V 0402 12 C9 4.7F, 16V 1206 NL1 POKD SYNC C3 AGND 0.1F, 6V 0402 21 REF 1.8V SMPS OUTPUT 23 C4 0.1F, 6V 0402 POKB AGND R2 0 1%, 0402 20 PWR 24 MAX17017 R10 100k 5%, 0402 C8 4.7F, 16V 1206 C7 1F, 16V 0603 29 CSPA 27 CSNA AGND ON OFF 14 MAX17017 13 7, 8 PWR PWR PGND PWR PWR C20 10F, 6V 0805 C19 10F, 6V 0805 FBD 10 AGND 22 REFIND C18 10F, 6V 0805 0.9A, 1A PWR AGND Figure 1. Standard Application Circuit ______________________________________________________________________________________ 17 MAX17017 Quad-Output Controller for Low-Power Architecture UP/DN UP/DN = VCC [BUCK], LOW BUCK MODE BYP VCC LDO5 VDD MAX17017 INLDO TSDN INA TSDN SHDN VCC BYP_OK BSTA VCC_OK REF_OK ONLDO SW EN DRV FB CSPA CSNA ONA EN LDO5 VCC VCCOK DHA LXA VDD REG A ANALOG UVLO *ONA (SHDN) BIAS DLA EN VCC REF VCC EN REF REFOK FBA SSDA+ SYNC OSC EN BSTB OND INBC IND VCC VCC CSB EN OUTD REG D ANALOG REG B ANALOG ONB INBC_OK PGND LXB VDD EN FBB REG D PWR FBD BSTC BYP VTTR INBC_OK + VCC ONA ONB ONC OND REFIND CSC POKX FAULTX ONX REG C ANALOG ONC INBC_OK LXC VDD EN FBC *BUCK REF ENABLED BY SHDN; BOOST REF ENABLED BY ONA. +SSDA ONLY USED IN STEP-UP MODE. SSDA = HIGH IN STEP-DOWN MODE. Figure 2. MAX17017 Block Diagram 18 INBC REFIND ON_VTTR PGOOD AND FAULT PROTECTION INBC UVLO ______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture SMPS Detailed Description Fixed-Frequency, Current-Mode PWM Controller The heart of each current-mode PWM controller is a multi-input, open-loop comparator that sums multiple signals: the output-voltage error signal with respect to the reference voltage, the current-sense signal, and the slope compensation ramp (Figure 3). The MAX17017 uses a direct-summing configuration, approaching ideal cycle-to-cycle control over the output voltage without a traditional error amplifier and the phase shift associated with it. Frequency Selection (FREQ) The FREQ input selects the PWM mode switching frequency. Table 1 shows the switching frequency based on the FREQ connection. High-frequency (FREQ = GND) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This might be acceptable in ultraportable devices where the load currents are lower. Low-frequency (FREQ = 5V) operation offers the best overall efficiency at the expense of component size and board space. Reference (REF) The 1.25V reference is accurate to 1% over temperature and load, making REF useful as a precision system reference. Bypass REF to GND with a 0.1F or greater ceramic capacitor. The reference sources up to 50A and sinks 5A to support external loads. If highly accurate specifications are required for the main SMPS output voltages, the reference should not be loaded. Loading the reference slightly reduces the output voltage accuracy because of the reference load-regulation error. VL R1 R2 TO PWM LOGIC UNCOMPENSATED HIGH-SPEED LEVEL TRANSLATOR AND BUFFER FB_ OUTPUT DRIVER I1 I2 I3 VBIAS REF CSH_ CSL_ SLOPE COMPENSATION Figure 3. PWM Comparator Functional Diagram ______________________________________________________________________________________ 19 MAX17017 LDO5 Bootstrap Switchover When the bypass input (BYP) exceeds the LDO5 bootstrap switchover threshold for more than 500s, an internal 1.5 (typ) p-channel MOSFET shorts BYP to LDO5, while simultaneously disabling the LDO5 linear regulator. This bootstraps the controller, allowing power for the internal circuitry and external LDO5 loading to be generated by the output of a 5V switching regulator. Bootstrapping reduces power dissipation due to driver and quiescent losses by providing power from a switch-mode source, rather than from a much-less-efficient linear regulator. The current capability increases from 50mA to 100mA when the LDO5 output is switched over to BYP. When BYP drops below the bootstrap threshold, the controller immediately disables the bootstrap switch and reenables the 5V LDO. MAX17017 Quad-Output Controller for Low-Power Architecture Table 1. FREQ Table REG A AND REG C REG B SWITCHING FREQUENCY SOFT-START TIME STARTUP BLANKING TIME SWITCHING FREQUENCY SOFT-START TIME STARTUP BLANKING TIME fSWA AND fSWC REG A: 1200/fSWA REG C: 900/fSWC 1500/fSWA fSWB 1800/fSWB 3000/fSWB LDO5 250kHz REG A: 4.8ms REG C: 3.6ms 6ms 500kHz 3.6ms 6ms REF 375kHz REG A: 3.2ms REG C: 2.4ms 4ms 750kHz 2.4ms 4ms GND 500kHz REG A: 2.4ms REG C: 1.8ms 3ms 1MHz 1.8ms 3ms SYNC 0.5 x fSYNC -- -- fSYNC -- -- PIN SELECT Light-Load Operation Control The MAX17017 uses a light-load pulse-skipping operating mode for all switching regulators. The switching regulators turn off the low-side MOSFETs when the current sense detects zero inductor current. This keeps the inductor from discharging the output capacitors and forces the switching regulator to skip pulses under light-load conditions to avoid overcharging the output. Idle-Mode Current-Sense Threshold When pulse-skipping mode is enabled, the on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle-mode currentsense threshold. Under light-load conditions, the ontime duration depends solely on the idle-mode current-sense threshold. This forces the controller to source a minimum amount of power with each cycle. To avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feedback threshold. Since the zero-crossing comparator prevents the switching regulator from sinking current, the MAX17017 switching regulators must skip pulses. Therefore, the controller regulates the valley of the output ripple under light-load conditions. Automatic Pulse-Skipping Crossover In skip mode, an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing 20 comparator senses the inductor current during the offtime. For regulator A, once VCSPA - VCSNA drops below the 1mV zero-crossing current-sense threshold, the comparator turns off the low-side MOSFET (DLA pulled low). For regulators B and C, once the current through the lowside MOSFET drops below 100mA, the zero-crossing comparator turns off the low-side MOSFET. The minimum idle-mode current requirement causes the threshold between pulse-skipping PFM operation and constant PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The load-current level at which PFM/PWM crossover occurs (ILOAD(SKIP)) is equivalent to half the idle-mode current threshold (see the Electrical Characteristics table for the idle-mode thresholds of each regulator). The switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). ______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture Regulator A Startup Once the 5V bias supply rises above this input UVLO threshold and ONA is pulled high, the main step-down controller (regulator A) is enabled and begins switching. The internal voltage soft-start gradually increments the feedback voltage by 10mV every 12 switching cycles. Therefore, OUTA reaches its nominal regulation voltage 1200/fSWA after regulator A is enabled (see the REG A Startup Waveform (Heavy Load) graph in the Typical Operating Characteristics). Regulator B and C Startup The internal step-down controllers start switching and the output voltages ramp up using soft-start. If the bias supply voltage drops below the UVLO threshold, the controller stops switching and disables the drivers (LX_ becomes high impedance) until the bias supply voltage recovers. Once the 5V bias supply and INBC rise above their respective input UVLO thresholds (SHDN must be pulled high to enable the reference), and ONB or ONC is pulled high, the respective internal step-down controller (regulator B or C) becomes enabled and begins switching. The internal voltage soft-start gradually increments the feedback voltage by 10mV every 24 switching cycles for regulator B or every 12 switching cycles for regulator C. Therefore, OUTB reaches its nominal regulation voltage 1800/fSWB after regulator B is enabled, and OUTC reaches its nominal regulation voltage 900/fSWC after regulator C is enabled (see the REG B Startup Waveform (Heavy Load) and REG C Startup Waveform (Heavy Load) graphs in the Typical Operating Characteristics). SMPS Power-Good Outputs (POK) POKA, POKB, and POKC are the open-drain outputs of window comparators that continuously monitor each output for undervoltage and overvoltage conditions. POK_ is actively held low in shutdown (SHDN = GND), standby (ONA = ONB = ONC = GND), and soft-start. Once the soft-start sequence terminates, POK_ becomes high impedance as long as the output remains within 8% (min) of the nominal regulation voltage set by FB_. POK_ goes low once its corresponding output drops 12% (typ) below its nominal regulation point, an output overvoltage fault occurs, or the output is shut down. For a logic-level POK_ output voltage, connect an external pullup resistor between POK_ and LDO5. A 100k pullup resistor works well in most applications. SMPS Fault Protection Output Overvoltage Protection (OVP) If the output voltage rises above 112% (typ) of its nominal regulation voltage, the controller sets the fault latch, pulls POK_ low, shuts down the respective regulator, and immediately pulls the output to ground through its low-side MOSFET. Turning on the low-side MOSFET with 100% duty cycle rapidly discharges the output capacitors and clamps the output to ground. However, this commonly undamped response causes negative output voltages due to the energy stored in the output LC at the instant the OVP occurs. If the load cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse-polarity clamp. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the input source also fails (short-circuit fault). Cycle VCC below 1V or toggle the respective enable input to clear the fault latch and restart the regulator. Output Undervoltage Protection (UVP) Each MAX17017 includes an output undervoltage (UVP)-protection circuit that begins to monitor the output once the startup blanking period has ended. If any output voltage drops below 88% (typ) of its nominal regulation voltage, the UVP protection immediately sets the fault latch, pulls the respective POK output low, forces the high-side and low-side MOSFETs into highimpedance states (DH = DL = low), and shuts down the respective regulator. Cycle VCC below 1V or toggle the respective enable input to clear the fault latch and restart the regulator. Thermal-Fault Protection The MAX17017 features a thermal-fault-protection circuit. When the junction temperature rises above +160C, a thermal sensor activates the fault latch, pulls all POK outputs low, and shuts down all regulators. Toggle SHDN to clear the fault latch and restart the controllers after the junction temperature cools by 15C. ______________________________________________________________________________________ 21 MAX17017 SMPS POR, UVLO, and Soft-Start Power-on reset (POR) occurs when VCC rises above approximately 1.9V, resetting the undervoltage, overvoltage, and thermal-shutdown fault latches. The POR circuit also ensures that the low-side drivers are pulled low until the SMPS controllers are activated. The VCC input undervoltage lockout (UVLO) circuitry prevents the switching regulators from operating if the 5V bias supply (VCC and VDD) is below its 4.2V UVLO threshold. MAX17017 Quad-Output Controller for Low-Power Architecture VTT LDO Detailed Description VTT LDO Power-Good Output (POKD) POKD is the open-drain output of a window comparator that continuously monitors the VTT LDO output for undervoltage and overvoltage conditions. POKD is actively held low when the VTT LDO is disabled (OND = GND) and soft-start. Once the startup blanking time expires, POKD becomes high impedance as long as the output remains within 6% (min) of the nominal regulation voltage set by REFIND. POKD goes low once its corresponding output drops or rises 12% (typ) beyond its nominal regulation point or the output is shut down. For a logic-level POKD output voltage, connect an external pullup resistor between POKD and LDO5. A 100k pullup resistor works well in most applications. VTT LDO Fault Protection LDO Output Overvoltage Protection (OVP) If the output voltage rises above 112% (typ) of its nominal regulation voltage, the controller sets the fault latch, pulls POKD low, shuts down the source/sink linear regulator, and immediately pulls the output to ground through its low-side MOSFET. Turning on the low-side MOSFET with 100% duty cycle rapidly discharges the output capacitors and clamps the output to ground. Cycle VCC below 1V or toggle OND to clear the fault latch and restart the linear regulator. LDO Output Undervoltage Protection (UVP) Each MAX17017 includes an output undervoltage protection (UVP) circuit that begins to monitor the output once the startup blanking period has ended. If the source/sink LDO output voltage drops below 88% (typ) of its nominal REFIND regulation voltage for 5ms, the UVP protection sets the fault latch, pulls the POKD output low, forces the output into a high-impedance state, and shuts down the linear regulator. Cycle VCC below 1V or toggle OND to clear the fault latch and restart the regulator. SMPS Design Procedure (Step Down Regulators) Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input voltage range. The maximum value (VIN(MAX)) must accommodate the worst-case, high ACadapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops 22 due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum load current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. * Switching frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. * Inductor operating point. This choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency, higher output ripple, and lower maximum load current, and due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (light loads), the inductor value also determines the loadcurrent value at which PFM/PWM switchover occurs. Step-Down Inductor Selection The switching frequency and inductor operating point determine the inductor value as follows: L= VOUT ( VIN - VOUT ) VINfSWILOAD(MAX)LIR Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Most inductor manufacturers provide inductors in standard values, such as 1.0H, 1.5H, 2.2H, 3.3H, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For ______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture Electrical Characteristics table, and fSW is the switching frequency selected by the FREQ setting (see Table 1). V (V - V ) IINDUCTOR = OUT IN OUT VINfSWL When using only polymer capacitors on the output, the additional ESR of the output (RESR) must be taken into consideration. Ferrite cores are often the best choice, although soft saturating molded core inductors are inexpensive and can work well at 500kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): I IPEAK = ILOAD(MAX) + INDUCTOR 2 SMPS Output Capacitor Selection The output filter capacitor selection requires careful evaluation of several different design requirements-- stability, transient response, and output ripple voltage--that place limits on the output capacitance and ESR. Based on these requirements, the typical application requires a low-ESR polymer capacitor (lower cost but higher output-ripple voltage) or bulk ceramic capacitors (higher cost but low output-ripple voltage). SMPS Loop Compensation Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the loop gain. This reduces the output capacitance requirement (stability and transient) and output power dissipation requirements as well. The load-line is generated by sensing the inductor current through the high-side MOSFET on-resistance, and is internally preset to -5mV/A (typ) for regulator B and -7mV/A (typ) for regulator C. The loadline ensures that the output voltage remains within the regulation window over the full-load conditions. The load line of the internal SMPS regulators also provides the AC ripple voltage required for stability. To maintain stability, the output capacitive ripple must be kept smaller than the internal AC ripple voltage, and crossover must occur before the Nyquist pole-- (2fSW)/(1+D) occurs. Based on these loop requirements, a minimum output capacitance can be determined from the following: When using only ceramic capacitors on the output, the required output capacitance is: VFB V 1 1 + OUT COUT > VIN 2fSW RDROOP VOUT where RDROOP is 2RSENSE for regulator A, 5mV/A for regulator B, or 7mV/A for regulator C as defined in the For duty cycles less than 40% using polymer capacitors: VFB VOUT 1 COUT > 1 + V 2fSW (RDROOP + RESR x VFB / VOUT) VOUT IN For duty cycles above 40% using polymer capacitors, the ESR and COUT must meet the conditions listed below: V RESR < RDROOP OUT VFB VFB V 1 1 + OUT COUT > VIN 2fSW RDROOP VOUT When the ESR condition described above is not satisfied, or when using a mix of ceramic and polymer capacitors on the output, an additional feedback polecapacitor from FB to analog ground (CFB) is necessary to cancel the output capacitor ESR zero: C R CFB > OUT ESR RFB where RFB is the parallel impedance of the FB resistive divider. SMPS Output Ripple Voltage With polymer capacitors, the effective series resistance (ESR) dominates and determines the output ripple voltage. The step-down regulator's output ripple voltage (V RIPPLE ) equals the total inductor ripple current (IINDUCTOR) multiplied by the output capacitor's ESR. Therefore, the maximum ESR to meet the output ripple voltage requirement is: VINfSWL RESR VRIPPLE (VIN - VOUT )VOUT where fSW is the switching frequency. The actual capacitance value required relates to the physical case size needed to achieve the ESR requirement, as well as to the capacitor chemistry. Thus, polymer capacitor selection is usually limited by ESR and voltage rating rather than by capacitance value. Alternatively, combining ceramics (for the low ESR) and polymers (for the bulk capacitance) helps balance the output capacitance vs. output ripple voltage requirements. ______________________________________________________________________________________ 23 MAX17017 the selected inductance value, the actual peak-to-peak inductor ripple current (IINDUCTOR) is defined by: MAX17017 Quad-Output Controller for Low-Power Architecture Internal SMPS Transient Response The load-transient response depends on the overall output impedance over frequency, and the overall amplitude and slew rate of the load step. In applications with large, fast load transients (load step > 80% of full load and slew rate > 10A/s), the output capacitor's high-frequency response--ESL and ESR--needs to be considered. To prevent the output voltage from spiking too low under a load-transient event, the ESR is limited by the following equation (ignoring the sag due to finite capacitance): VSTEP RESR - RPCB ILOAD(MAX) where VSTEP is the allowed voltage drop, ILOAD(MAX) is the maximum load step, and RPCB is the parasitic board resistance between the load and output capacitor. The capacitance value dominates the midfrequency output impedance and dominates the load-transient response as long as the load transient's slew rate is less than two switching cycles. Under these conditions, the sag and soar voltages depend on the output capacitance, inductance value, and delays in the transient response. Low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sudden load step, especially with low differential voltages across the inductor. The sag voltage (VSAG) that occurs after applying the load current can be estimated by the following: VSAG = ( )2 L ILOAD(MAX) ILOAD(MAX) (T - T) + COUT 2COUT (VIN x DMAX - VOUT ) where D MAX is the maximum duty factor (see the Electrical Characteristics table), T is the switching period (1/fOSC), and T equals VOUT/VIN x T when in PWM mode, or L x IIDLE/(VIN - VOUT) when in pulse-skipping mode. The amount of overshoot voltage (VSOAR) that occurs after load removal (due to stored inductor energy) can be calculated as: VSOAR 2 ILOAD(MAX) ) L ( 2COUT VOUT When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. 24 Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The IRMS requirements of an individual regulator can be determined by the following equation: I IRMS = LOAD VOUT (VIN - VOUT ) VIN The worst-case RMS current requirement occurs when operating with VIN = 2VOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD. However, the MAX17017 uses an interleaved fixed-frequency architecture, which helps reduce the overall input RMS current on the INBC input supply. For the MAX17017 system (INA) supply, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. For the MAX17017 INBC input supply, ceramic capacitors are preferred on input due to their low parasitic inductance, which helps reduce the high-frequency ringing on the INBC supply when the internal MOSFETs are turned off. Choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit longevity. BST Capacitors The boost capacitors (CBST) must be selected large enough to handle the gate charging requirements of the high-side MOSFETs. For these low-power applications, 0.1F ceramic capacitors work well. Regulator A Power-MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D2PAK), ______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture Power-MOSFET Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage: V 2 PD(NH Re sistive) = OUT (ILOAD ) RDS(ON) VIN Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board (PCB) layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD (NH Switching) = ILOADQG(SW) COSS VIN(MAX) + VIN(MAX)fSW IGATE 2 where COSS is the output capacitance of NH, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL) the worst-case power dissipation always occurs at maximum battery voltage: V 2 PD(NL Re sistive) = 1 - OUT (ILOAD ) RDS(ON) VIN(MAX) The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX), but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, "overdesign" the circuit to tolerate: I ILOAD = ILIMIT - INDUCTOR 2 where ILIMIT is the peak current allowed by the currentlimit circuit, including threshold tolerance and senseresistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage drop low enough to prevent the low-side MOSFET's body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current. This diode is optional and can be removed if efficiency is not critical. Regulator A Step-Up Converter Configuration Regulator A can be configured as a step-up converter (Figure 4). When UP/DN is pulled low, regulator A operates as a step-up converter (for 1 Li+ cell applications). It typically generates a 5V output voltage from a 3V to 5V battery input voltage. The step-up converter uses a current-mode architecture; the difference between the feedback voltage and a 1V reference signal generates an error signal that programs the peak inductor current to regulate the output voltage. The step-up converter is internally compensated, reducing external component requirements. When regulator A is configured as a step-up converter, SHDN should be connected to GND. ONA is the master enable switch. ONA rising enables REF and the bias block. Connect LDO5 and INLDO together with OUTA and connect BYP to either OUTA or INA. At light loads, efficiency is enhanced by an idle mode in which switching occurs only as needed to service the load. This idle-mode threshold is determined by comparing the current-sense signal to an internal reference. In idle mode, the synchronous rectifier shuts off once the current-sense voltage (CSPA - CSNA) drops below 1mV, preventing negative inductor current. ______________________________________________________________________________________ 25 MAX17017 and is reasonably priced. Ensure that the MAX17017 DLA gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems might occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology. MAX17017 Quad-Output Controller for Low-Power Architecture 13 38 19 15 AGND 14 INA SHDN 18 C7 1F, 16V 0603 SYNC UP/DN CSPA LDO5 PWR 24 R15 0.01 1%, 0612 CSNA 23 R1 C1 10 PWR 4.7F, 6V 0603 5%, 0402 AGND DLA 17 C2 1.0F, 6V 0402 39 ON OFF 37 ON OFF 47 ON OFF 46 ON OFF 5V SMPS OUTPUT R9 100k 5%, 0402 R10 100k 5%, 0402 R11 100k 5%, 0402 R12 100k 5%, 0402 VCC ONA BYP ONB ONC 1 45 R2 0 1%, 0402 20 NL1 30 PWR C11 680pF, 6V 0402 4x INBC 40-43 3x LXB POKA C12 1F, 16V 0402 34 FBB 31, 32, 33 BSTC 4x LXC C3 10nF , 6V 0402 21 REF FBC 36 1.8V SMPS OUTPUT AGND R13 15k 1%, 0402 C4 0.1F, 6V 0402 R14 15.0k 1%, 0402 AGND VTTR AGND L3 C6 1.0H, 6.8A, 14.2m 0.1F, 6V 5.8mm x 8.2mm x 3.0mm 0402 (NEC/TOKIN: MPLC0525L1R0) 2 3-6 R7 6.04k 1%, 0402 48 AGND C14 220F 18m, 2.5V, B2 CASE PWR C16 C17 220F 10F, 6V 18m, 0805 2.5V, B2 PWR CASE PWR 1.05V, 4A AGND IND 9 C20 10F, 6V 0805 2x OUTD 7, 8 PWR C21 10F, 6V 0805 FBD 10 22 AGND REFIND PWR PGND PWR PWR C22 10F, 6V 0805 PWR AGND Figure 4. Standard Application Circuit 2, Regulator A Configured as Step-Up Converter 26 1.8V, 2.5A AGND R8 15.0k 1%, 0402 C18 2200pF, 6V 0402 AGND C19 1F, 6V 0402 12 R6 15.0k 1%, 0402 C15 1000pF, 6V 0402 AGND 11 AGND PWR 5V, 1A C13 10F, 6V 0805 R5 21.0k 1%, 0402 POKD FREQ R3 40k 1%, 0402 R4 10k 1%, 0402 C11 220F, 35m 6V B2 C4SE PWR PWR C5 L2 0.1F, 6V 1.0H, 6.8A, 14.2m 0402 6.7mm x 7.7mm x 3.0mm (NEC/TOKIN: MPLC0730L3R3) POKB POKC C10 NH1 0.1F, 6V, 0402 16 OND BSTB 26 28 29 BSTA 27 DHA 25 FBA MAX17017 35 AGND LXA VDD PWR 3V TO 4.5V C9 150F, 35m 6V B2 CASE L1 3.3H, 6.8A, 14.2m 5.8mm x 6.2mm x 3.0mm (NEC/TOKIN: MPLC0525L1R0) INLDO 5V SMPS OUTPUT 44 C8 4.7F, 16V 1206 PWR ______________________________________________________________________________________ 0.9A, 1A Quad-Output Controller for Low-Power Architecture VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) 2 V VOUT - VVIN L = IN VOUT ILOAD(MAX)fSWLIR Choose an available inductor value from an appropriate inductor family. Calculate the maximum DC input current at the minimum input voltage VIN(MIN) using conservation of energy: IVIN(DC,MAX) = ILOAD(MAX) VOUT VIN(MIN) Calculate the ripple current at that operating point and the peak current required for the inductor: -V ) V (V IINDUCTOR = IN OUT IN VOUT fSWL I IPEAK = ILOAD(MAX) + INDUCTOR 2 The inductor's saturation current rating and the MAX17017's LXA current limit should exceed IPEAK and the inductor's DC current rating should exceed IVIN(DC,MAX). For good efficiency, choose an inductor with less than 0.1 series resistance. Step-Up Configuration Output Capacitor Selection For boost converter, during continuous operation, the output capacitor has a trapezoidal current profile. The large RMS ripple current in the output capacitor must be rated to handle the current. The RMS current is greatest at ILOAD(MAX) and minimum input working voltage. Therefore, the output capacitor should be chosen with a rating at least ICOUT(RMS).The RMS current into the capacitor is then given by: ICOUT(RMS) ILOAD VOUT - VIN VIN The total output voltage ripple has two components: the capacitive ripple caused by the charging and discharging of the output capacitance, and the resistive ripple due to the capacitor's equivalent series resistance (ESR): V I -V VRIPPLE(C) OUT OUT IN COUT VOUT fSW and: VRIPPLE(ESR) IPEAKRESR where IPEAK is the peak inductor current. For polymer capacitors, the output voltage ripple is typically dominated by resistive ripple voltage. The voltage rating and temperature characteristics of the output capacitor must also be considered. The output ripple voltage due to the frequency-dependent term can be compensated by using capacitors of very low ESR to maintain low ripple voltage. Note that all ceramic capacitors typically have large temperature coefficient and bias voltage coefficients. The actual capacitor value in circuit is typically significantly less than the stated value. Step-Up Configuration Loop Compensation The boost converter small-signal model contains a right half-plane (RHP) zero. The presence of an RHP zero tends to destabilize wide-bandwidth feedback loop because during a transient, the output initially changes in the wrong direction. Also when an RHP zero is present, it is difficult to obtain an adequate phase margin. RHP is determined by inductance L, duty cycle Dup, and load R. The RHP is: fRHP = (1 - DUP )2 R 2L To maintain stability, crossover must occur before the RHP. To make sure the phase margin is big enough to stabilize the circuit, the converter crossover must be kept 4 ~ 10 times slower than the RHP zero. A minimum output capacitance is determined from the following: A VREF COUT > 4 STEP -UP L R V 1 D R ( ) OUT CS UP where ASTEP-UP is equal to 1.25, which is the error amplifier gain divided by the current-sense gain; RCS is the current-sensing resistor. Additionally, an additional feedback pole--capacitor from FB to analog ground (CFB)--might be necessary to cancel the unwanted ESR zero of the output capacitor. ______________________________________________________________________________________ 27 MAX17017 Step-Up Configuration Inductor Selection The switching frequency and inductor operating point determine the inductor value as follows: MAX17017 Quad-Output Controller for Low-Power Architecture In general, if the ESR zero occurs before the Nyquist pole, then canceling the ESR zero is recommended: If: G V ESR > CS OUT ( 1 D ) AV REF then: C ESR CFB > OUT R FB where RFB is the parallel impedance of the FB resistive divider. Step-Up Configuration Input Capacitor Selection The current in the boost converter input capacitor does not contain large square-wave currents as found in the output capacitor. Therefore, the input capacitor selection is less critical due to the output capacitor. However, a low ESR is recommended. feature makes the MAX17017 ideal for memory applications in which the termination supply must track the supply voltage. VTT LDO Output Capacitor Selection (COUTD) A minimum value of 20F or greater ceramic is needed to stabilize the VTT output (OUTD). This value of capacitance limits the switching regulator's unity-gain bandwidth frequency to approximately 1.2MHz (typ) to allow adequate phase margin for stability. To keep the capacitor acting as a capacitor within the switching regulator's bandwidth, it is important that ceramic capacitors with low ESR and ESL be used. Since the gain bandwidth is also determined by the transconductance of the output MOSFETs, which increases with load current, the output capacitor might need to be greater than 20F if the load current exceeds 1.5A, but can be smaller than 20F if the maximum load current is less than 1.5A. As a guideline, choose the minimum capacitance and maximum ESR for the output capacitor using the following: The RMS input ripple current for a boost converter is: ICIN(RMS) 0.3VIN(MIN)DMAX COUT _ MIN = 20F x ILOAD 1.5A RESR _ MAX = 5m x ILOAD 1.5A and: LfSW VTT LDO Design Procedure IND Input Capacitor Selection (CIND) The value of the IND bypass capacitor is chosen to limit the amount of ripple and noise at IND, and the amount of voltage sag during a load transient. Typically, IND connects to the output of a step-down switching regulator, which already has a large bulk output capacitor. Nevertheless, a ceramic capacitor equivalent to half the VTT output capacitance should be added and placed as close as possible to IND. The necessary capacitance value must be increased with larger load current, or if the trace from IND to the power source is long and results in relatively high input impedance. RESR value is measured at the unity-gain-bandwidth frequency given by approximately: VTT LDO Output Voltage (FBD) The VTTR buffer is a scaled-down version of the VTT regulator, with much smaller output transconductance. Therefore, the VTTR compensation requirements also scale. For typical applications requiring load currents up to 3mA, a 0.22F or greater ceramic capacitor is recommended (RESR < 0.3). The VTT output stage is powered from the IND input. The VTT output voltage is set by the REFIND input. REFIND sets the VTT LDO feedback regulation voltage (VFBD = VREFIND) and the VTTR output voltage. The VTT LDO (FBD voltage) and VTTR track the REFIND voltage over a 0.5V to 1.5V range. This reference input 28 fGBW = I 36 x LOAD COUT 1.5A Once these conditions for stability are met, additional capacitors, including those of electrolytic and tantalum types, can be connected in parallel to the ceramic capacitor (if desired) to further suppress noise or voltage ripple at the output. VTTR Output Capacitor Selection ______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture Applications Information Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the Electrical Characteristics table). For the best dropout performance, use the slowest switching frequency setting (FREQ = GND). However, keep in mind that the transient performance gets worse as the step-down regulators approach the dropout voltage, so bulk output capacitance must be added (see the voltage sag and soar equations in the Design Procedure section). The absolute point of dropout occurs when the inductor current ramps down during the off-time (IDOWN) as much as it ramps up during the on-time (IUP). This results in a minimum operating voltage defined by the following equation: 1 VIN(MIN) = VOUT + VCHG + h - 1 (VOUT + VDIS ) DMAX where VCHG and VDIS are the parasitic voltage drops in the charge and discharge paths, respectively. A reasonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. Maximum Input Voltage The MAX17017 controller includes a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the Electrical Characteristics table). Operation above this maximum input voltage results in pulse skipping to avoid overcharging the output. At the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, effectively skipping a cycle. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (VIN(SKIP)): 1 VIN(SKIP) = VOUT fOSCt ON(MIN) where f OSC is the switching frequency selected by FREQ. PCB Layout Guidelines Careful PCB layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow the MAX17017 Evaluation Kit layout and use the following guidelines for good PCB layout: * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PCBs (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. * Minimize current-sensing errors by connecting CSPA and CSNA directly across the current-sense resistor (RSENSE_). * When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. * Route high-speed switching nodes (BST_, LX_, DHA, and DLA) away from sensitive analog areas (REF, REFIND, FB_, CSPA, CSNA). ______________________________________________________________________________________ 29 MAX17017 VTT LDO Power Dissipation Power loss in the MAX17017 VTT LDO is significant and can become a limiting design factor in the overall MAX17017 design: PDVTT = 2A x 0.9V = 1.8W The 1.8W total power dissipation is within the 40-pin TQFN multilayer board power-dissipation specification of 2.9W. The typical DDR termination application does not actually continuously source or sink high currents. The actual VTT current typically remains around 100mA to 200mA under steady-state conditions. VTTR is down in the microampere range, though the Intel specification requires 3mA for DDR1 and 1mA for DDR2. True worst-case power dissipation occurs on an output short-circuit condition with worst-case current limit. MAX17017 does not employ any foldback current limiting, and relies on the internal thermal shutdown for protection. Both the VTT and VTTR output voltages are referenced to the same REFIND input. MAX17017 Quad-Output Controller for Low-Power Architecture Chip Information PROCESS: BiCMOS 30 Package Information For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 TQFN T4866-2 21-0141 ______________________________________________________________________________________ Quad-Output Controller for Low-Power Architecture REVISION NUMBER REVISION DATE 0 5/08 Initial release 1 9/08 Updated Electrical Characteristics and added Regulator Step-Up Converter Configuration section 2 6/09 Status changed from silent to public; added leakage current specification and updated Note 2 in Electrical Characteristics; updated Figures 1, 2, and 4; updated SMPS Loop Compensation section DESCRIPTION PAGES CHANGED -- 4, 5, 8, 9, 23, 25-29 1-6, 8-23, 25, 26, 29, 30 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX17017 Revision History