74HCT165D,652 - NEXPERIA

74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Rev. 5 — 21 August 2017 Product data sheet

1 General description

The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The

device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two

complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the

data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH

data enters the register serially at DS. When the clock enable input (CE) is LOW data is

shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the

CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in

HIGH-to-LOW level shifting applications.

2 Features and benefits

•Asynchronous 8-bit parallel load

•Synchronous serial input

•Complies with JEDEC standard no. 7A

•Input levels:

–For 74HC165: CMOS level

–For 74HCT165: TTL level

•ESD protection:

–HBM JESD22-A114F exceeds 2000 V

–MM JESD22-A115-A exceeds 200 V

•Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3 Applications

•Parallel-to-serial data conversion

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

2 / 22

4 Ordering information

Table 1. Ordering information

PackageType number

Temperature

range

Name Description Version

74HC165D

74HCT165D

-40 °C to +125 °C SO16 plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

74HC165DB

74HCT165DB

-40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;

body width 5.3 mm

SOT338-1

74HC165PW

74HCT165PW

-40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

74HC165BQ

74HCT165BQ

-40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 16 terminals;

body 2.5 × 3.5 × 0.85 mm

SOT763-1

5 Functional diagram

mna985

CP CE

152

Figure 1. Logic symbol

mna986

≥ 1

1C3/

C2[LOAD]

G1[SHIFT]

SRG8

Figure 2. IEC logic symbol

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

3 / 22

mna992

8-BIT SHIFT REGISTER

PARALLEL-IN/SERIAL-OUT

DS10

D0 D1 D2 D3 D4 D5 D6 D7

12 13 14 3 4 5 6

Figure 3. Functional diagram

6 Pinning information

6.1 Pinning

74HC165

74HCT165

PL VCC

CP CE

D4 D3

D5 D2

D6 D1

D7 D0

Q7 DS

GND Q7

001aah564

Figure 4. Pin configuration (SO16 and (T)SSOP16)

001aah565

74HC165

74HCT165

Q7 DS

GND(1)

D7 D0

D6 D1

D5 D2

D4 D3

CP CE

GND

Transparent top view

7 10

6 11

5 12

4 13

3 14

2 15

terminal 1

index area

(1) This is not a supply pin. The substrate is attached

to this pad using conductive die attach material. There

is no electrical or mechanical requirement to solder this

pad.However, if it is soldered, the solder land should remain

floating or be connected to GND.

Figure 5. Pin configuration (DHVQFN16)

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

4 / 22

6.2 Pin description

Table 2. Pin description

Symbol Pin Description

PL 1 asynchronous parallel load input (active LOW)

CP 2 clock input (LOW-to-HIGH edge-triggered)

Q7 7 complementary output from the last stage

GND 8 ground (0 V)

Q7 9 serial output from the last stage

DS 10 serial data input

D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn)

CE 15 clock enable input (active LOW)

VCC 16 positive supply voltage

7 Functional description

Table 3. Function table [1]

Inputs Qn registers OutputsOperating modes

PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7

L X X X L L L to L L Hparallel load

L X X X H H H to H H L

H L ↑ l X L q0 to q5 q6 q6

H L ↑ h X H q0 to q5 q6 q6

H ↑ L l X L q0 to q5 q6 q6

serial shift

H ↑ L h X H q0 to q5 q6 q6

H H X X X q0 q1 to q6 q7 q7hold "do nothing"

H X H X X q0 q1 to q6 q7 q7

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care;

↑ = LOW-to-HIGH clock transition.

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

5 / 22

mna993

inhibit serial shift

load

Figure 6. Timing diagram

8 Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +7 V

IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA

IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA

IOoutput current -0.5 V < VO < VCC + 0.5 V - ±25 mA

ICC supply current - 50 mA

IGND ground current -50 - mA

Tstg storage temperature -65 +150 °C

Ptot total power dissipation Tamb = -40 °C to +125 °C [2] - 500 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO16 Packages: Ptot derates linearly with 8 mW/K above 70 °C.

For (T)SSOP16 Packages: Ptot derates linearly with 5.5 mW/K above 60 °C.

For DHVQFN16 Packages: Ptot derates linearly with 4.5 mW/K above 60 °C.

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

6 / 22

9 Recommended operating conditions

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

74HC165 74HCT165Symbol Parameter Conditions

Min Typ Max Min Typ Max

Unit

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VIinput voltage 0 - VCC 0 - VCC V

VOoutput voltage 0 - VCC 0 - VCC V

Tamb ambient temperature -40 - +125 -40 - +125 °C

VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V

Δt/ΔV input transition rise and fall rate

VCC = 6.0 V - - 83 - - - ns/V

10 Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

25 °C -40 °C to

+85 °C

-40 °C to

+125 °C

Symbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

74HC165

VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VIH HIGH-level input

voltage

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

VIL LOW-level input

voltage

VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

VI = VIH or VIL

IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

VOH HIGH-level

output voltage

IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

7 / 22

25 °C -40 °C to

+85 °C

-40 °C to

+125 °C

Symbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

VI = VIH or VIL

IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

VOL LOW-level

output voltage

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current

VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA

ICC supply current VI = VCC or GND; IO = 0 A;

VCC = 6.0 V

- - 8.0 - 80 - 160 μA

CIinput

capacitance

- 3.5 - - - - - pF

74HCT165

VIH HIGH-level input

voltage

VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V

VIL LOW-level input

voltage

VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

VI = VIH or VIL; VCC = 4.5 V

IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V

VOH HIGH-level

output voltage

IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

VI = VIH or VIL

IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

VOL LOW-level

output voltage

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current

VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA

ICC supply current VI = VCC or GND; IO = 0 A;

VCC = 6.0 V

- - 8.0 - 80 - 160 μA

per input pin; VI = VCC - 2.1 V;

other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V

Dn and DS inputs - 35 126 - 157.5 - 171.5 μA

ΔICC additional supply

current

CP CE, and PL inputs - 65 234 - 292.5 - 318.5 μA

CIinput

capacitance

- 3.5 - - - - - pF

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

8 / 22

11 Dynamic characteristics

Table 7. Dynamic characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V);

CL = 50 pF unless otherwise specified; for test circuit, see Figure 12

25 °C -40 °C to

+85 °C

-40 °C to

+125 °C

Symbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

74HC165

CP or CE to Q7, Q7;

see Figure 7

[1]

VCC = 2.0 V - 52 165 - 205 - 250 ns

VCC = 4.5 V - 19 33 - 41 - 50 ns

VCC = 6.0 V - 15 28 - 35 - 43 ns

VCC = 5.0 V; CL = 15 pF - 16 - - - - - ns

PL to Q7, Q7; see Figure 8

VCC = 2.0 V - 50 165 - 205 - 250 ns

VCC = 4.5 V - 18 33 - 41 - 50 ns

VCC = 6.0 V - 14 28 - 35 - 43 ns

VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns

D7 to Q7, Q7; see Figure 9

VCC = 2.0 V - 36 120 - 150 - 180 ns

VCC = 4.5 V - 13 24 - 30 - 36 ns

VCC = 6.0 V - 10 20 - 26 - 31 ns

tpd propagation

delay

VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns

Q7, Q7 output; see Figure 7 [2]

VCC = 2.0 V - 19 75 - 95 - 110 ns

VCC = 4.5 V - 7 15 - 19 - 22 ns

tttransition time

VCC = 6.0 V - 6 13 - 16 - 19 ns

CP input HIGH or LOW;

see Figure 7

VCC = 2.0 V 80 17 - 100 - 120 - ns

VCC = 4.5 V 16 6 - 20 - 24 - ns

VCC = 6.0 V 14 5 - 17 - 20 - ns

PL input LOW; see Figure 8

VCC = 2.0 V 80 14 - 100 - 120 - ns

VCC = 4.5 V 16 5 - 20 - 24 - ns

tWpulse width

VCC = 6.0 V 14 4 - 17 - 20 - ns

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

9 / 22

25 °C -40 °C to

+85 °C

-40 °C to

+125 °C

Symbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

PL to CP, CE; see Figure 8

VCC = 2.0 V 100 22 - 125 - 150 - ns

VCC = 4.5 V 20 8 - 25 - 30 - ns

trec recovery time

VCC = 6.0 V 17 6 - 21 - 26 - ns

DS to CP, CE; see Figure 10

VCC = 2.0 V 80 11 - 100 - 120 - ns

VCC = 4.5 V 16 4 - 20 - 24 - ns

VCC = 6.0 V 14 3 - 17 - 20 - ns

CE to CP and CP to CE;

see Figure 10

VCC = 2.0 V 80 17 - 100 - 120 - ns

VCC = 4.5 V 16 6 - 20 - 24 - ns

VCC = 6.0 V 14 5 - 17 - 20 - ns

Dn to PL; see Figure 11

VCC = 2.0 V 80 22 - 100 - 120 - ns

VCC = 4.5 V 16 8 - 20 - 24 - ns

tsu set-up time

VCC = 6.0 V 14 6 - 17 - 20 - ns

DS to CP, CE and Dn to PL;

see Figure 10

VCC = 2.0 V 5 2 - 5 - 5 - ns

VCC = 4.5 V 5 2 - 5 - 5 - ns

VCC = 6.0 V 5 2 - 5 - 5 - ns

CE to CP and CP to CE;

see Figure 10

VCC = 2.0 V 5 -17 - 5 - 5 - ns

VCC = 4.5 V 5 -6 - 5 - 5 - ns

thhold time

VCC = 6.0 V 5 -5 - 5 - 5 - ns

CP input; see Figure 7

VCC = 2.0 V 6 17 - 5 - 4 - MHz

VCC = 4.5 V 30 51 - 24 - 20 - MHz

VCC = 6.0 V 35 61 - 28 - 24 - MHz

fmax maximum

frequency

VCC = 5.0 V; CL = 15 pF - 56 - - - - - MHz

CPD power

dissipation

capacitance

per package; VI = GND to VCC

[3] - 35 - - - - - pF

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

10 / 22

25 °C -40 °C to

+85 °C

-40 °C to

+125 °C

Symbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

74HCT165

CE, CP to Q7, Q7;

see Figure 7

[1]

VCC = 4.5 V - 17 34 - 43 - 51 ns

VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns

PL to Q7, Q7; see Figure 8

VCC = 4.5 V - 20 40 - 50 - 60 ns

VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns

D7 to Q7, Q7; see Figure 9

VCC = 4.5 V - 14 28 - 35 - 42 ns

tpd propagation

delay

VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns

Q7, Q7 output; see Figure 7 [2]

tttransition time

VCC = 4.5 V - 7 15 - 19 - 22 ns

CP input; see Figure 7

VCC = 4.5 V 16 6 - 20 - 24 - ns

PL input; see Figure 8

tWpulse width

VCC = 4.5 V 20 9 - 25 - 30 - ns

PL to CP, CE; see Figure 8trec recovery time

VCC = 4.5 V 20 8 - 25 - 30 - ns

DS to CP, CE; see Figure 10

VCC = 4.5 V 20 2 - 25 - 30 - ns

CE to CP and CP to CE;

see Figure 10

VCC = 4.5 V 20 7 - 25 - 30 - ns

Dn to PL; see Figure 11

tsu set-up time

VCC = 4.5 V 20 10 - 25 - 30 - ns

DS to CP, CE and Dn to PL;

see Figure 10

VCC = 4.5 V 7 -1 - 9 - 11 - ns

CE to CP and CP to CE;

see Figure 10

thhold time

VCC = 4.5 V 0 -7 - 0 - 0 - ns

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

11 / 22

25 °C -40 °C to

+85 °C

-40 °C to

+125 °C

Symbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

CP input; see Figure 7

VCC = 4.5 V 26 44 - 21 - 17 - MHz

fmax maximum

frequency

VCC = 5.0 V; CL = 15 pF - 48 - - - - - MHz

CPD power

dissipation

capacitance

per package;

VI = GND to VCC - 1.5 V

[3] - 35 - - - - - pF

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD × VCC

2 × fi + Σ (CL × VCC

2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

Σ (CL × VCC

2 × fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in V.

11.1 Waveforms and test circuit

mna987

CP or CE input

Q7 or Q7 output

90 %

10 % 10 %

90 %

tPHL

tTHL tTLH

tPLH

1/fmax

VOH

GND

VOL

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the

maximum clock frequency and the output transition times

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

12 / 22

mna988

PL input

CE, CP input

Q7 or Q7 output

tPHL

tWtrec

VOH

GND

VOL

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel

load to clock (CP) and clock enable (CE) recovery time

mna989

D7 input

Q7 output

tPHL

VOH

GND

VOH

VOL

tPLH

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

13 / 22

tsu tsu

GND

DS input

tsu

mna990

GND

CP, CE input

(1)

(1) CE may change only from HIGH-to-LOW while CP is LOW.

The shaded areas indicate when the input is permitted to change for predictable output performance

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE)

inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable

input (CE)

mna991

Dn input

PL input

tsu th

GND

tsu th

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)

Table 8. Measurement points

Input OutputType

VIVMVM

74HC165 VCC 0.5VCC 0.5VCC

74HCT165 3 V 1.3 V 1.3 V

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

14 / 22

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aad983

DUT

VCC VCC

VIVO

RLS1

open

Test data is given in Table 9.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch

Figure 12. Test circuit for measuring switching times

Table 9. Test data

Input Load S1 positionType

VItr, tfCLRLtPHL, tPLH

74HC165 VCC 6 ns 15 pF, 50 pF 1 kΩ open

74HCT165 3 V 6 ns 15 pF, 50 pF 1 kΩ open

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

15 / 22

12 Package outline

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpc D(1) E(1) (1)

e HEL LpQ Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Figure 13. Package outline SOT109-1 (SO16)

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

16 / 22

UNIT A1A2A3bpc D (1) E(1) e HEL LpQ Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05

1.80

1.65 0.25 0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2 0.65 1.25

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1 99-12-27

03-02-19

(1)

vMA

16 9

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

max.

Figure 14. Package outline SOT338-1 (SSOP16)

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

17 / 22

UNIT A1A2A3bpc D (1) E(2) (1)

e HEL LpQ Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3 0.65 6.6

6.2

0.4

0.3

0.40

0.06

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

1 8

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Figure 15. Package outline SOT403-1 (TSSOP16)

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

18 / 22

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT763-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT763-1

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

A(1)

max.

detail X

y1C

2 7

15 10

B A

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Figure 16. Package outline SOT763-1 (DHVQFN16)

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

19 / 22

13 Abbreviations

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

14 Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT165 v.5 20170821 Product data sheet - 74HC_HCT165 v.4

Modifications: •Hold time for 74HC165 has been updated. See Paragraph hold time.

•The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

74HC_HCT165 v.4 20151228 Product data sheet - 74HC_HCT165 v.3

Modifications: •Type numbers 74HC165N and 74HCT165N (SOT38-4) removed.

74HC_HCT165 v.3 20080314 Product data sheet - 74HC_HCT165_CNV v.2

Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Package SOT763-1 (DHVQFN16) added to Section 4 and Section 12.

•Family data added, see Section 10

74HC_HCT165_CNV v.2 December 1990 Product specification - -

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

20 / 22

15 Legal information

15.1 Data sheet status

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product

development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local Nexperia

sales office. In case of any inconsistency or conflict with the short data sheet,

the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation -

lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory. Notwithstanding any damages that

customer might incur for any reason whatsoever, Nexperia's aggregate and

cumulative liability towards customer for the products described herein shall

be limited in accordance with the Terms and conditions of commercial sale of

Nexperia.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification. Customers are responsible for the

design and operation of their applications and products using Nexperia

products, and Nexperia accepts no liability for any assistance with

applications or customer product design. It is customer’s sole responsibility

to determine whether the Nexperia product is suitable and fit for the

customer’s applications and products planned, as well as for the planned

application and use of customer’s third party customer(s). Customers should

provide appropriate design and operating safeguards to minimize the risks

associated with their applications and products. Nexperia does not accept

any liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using Nexperia products in order to avoid a default of the

applications and the products or of the application or use by customer’s third

party customer(s). Nexperia does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Product data sheet Rev. 5 — 21 August 2017

21 / 22

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications. In the event that customer

uses the product for design-in and use in automotive applications to

automotive specifications and standards, customer (a) shall use the product

without Nexperia's warranty of the product for such automotive applications,

use and specifications, and (b) whenever customer uses the product for

automotive applications beyond Nexperia's specifications such use shall be

solely at customer’s own risk, and (c) customer fully indemnifies Nexperia

for any liability, damages or failed product claims resulting from customer

design and use of the product for automotive applications beyond Nexperia's

standard warranty and Nexperia's product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

15.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Nexperia 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 21 August 2017

Document identifier: 74HC_HCT165

Contents

1 General description ............................................ 1

2 Features and benefits .........................................1

3 Applications .........................................................1

4 Ordering information .......................................... 2

5 Functional diagram ............................................. 2

6 Pinning information ............................................ 3

6.1 Pinning ............................................................... 3

6.2 Pin description ................................................... 4

7 Functional description ........................................4

8 Limiting values ....................................................5

9 Recommended operating conditions ................ 6

10 Static characteristics .......................................... 6

11 Dynamic characteristics .....................................8

11.1 Waveforms and test circuit .............................. 11

12 Package outline .................................................15

13 Abbreviations .................................................... 19

14 Revision history ................................................ 19

15 Legal information .............................................. 20