LPC1111FHN33/101,5 - NXP Semiconductors

UM10398

LPC111x/LPC11Cxx User manual

Rev. 11 — 26 July 2012 User manual

Document information

Info Content

Keywords ARM Cortex-M0, LPC1111, LPC1112, LPC1113, LPC1114, LPC11C12,

LPC11C14, LPC1100, LPC1100L, LPC11C00, LPC11C22, LPC11C24,

LPC11D14, LPC1100XL

Abstract LPC111x/LPC11Cxx User manual

User manual Rev. 11 — 26 July 2012 2 of 538

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors UM10398

LPC111x/LPC11Cxx User manual

Revision history

Rev Date Description

11 20120726 LPC111x/LPC11C1x/LPC11C2x User manual

Modifications: •Function SSEL1 added to pin PIO2_0 in Table 170 and Figure 28.

•BOD level 0 for reset and interrupt removed.

10 20120626 LPC111x/LPC11C1x/LPC11C2x User manual

Modifications: •LPC1112FHN24 pinout corrected in Table 161 and Figure 18.

•Description of BYPASS bit corrected in Table 12 “System oscillator control register (SYSOSCCTRL,

address 0x4004 8020) bit descri ption”.

9 20120517 LPC111x/LPC11C1x/LPC11C2x/LPC11D1 4 User manual

Modifications: •LPC11D14/PCF8576D block diagram updated (see Figure 5).

•Description of interrupt use with IAP calls updated (see Section 26.4 .7) .

•SYSRSTSTAT register access changed to R/W (Table 7).

•Frequency values for FREQSEL bits in the WDTOSCCTRL register corrected (see Table 13).

•Figure 9 updated (RESET changed to internal reset).

•Limit number of bytes copied in Copy RAM to flash ISP and IAP commands for parts with less than

4 kB SRAM (see Table 381 and Table 396).

•Figure 14 updated with pseudo open-drain mode .

•Part LPC1112FHN24/202 added.

•Part IDs added for parts LPC1110FD20, LPC1111FDH20/002, LPC1112FD20/102,

LPC1112FDH20/102, LPC1112F DH28/102, LPC1114FDH2 8/102, LPC1114F N28/102.

•SRAM use by bootloader specified in Section 26.3.1.

8 20120308 LPC111x/LPC11C1x/LPC11C2x User manual

7 20110919 LPC111x/LPC11C1x/LPC11C2x User manual

6 20110822 LPC111x/LPC11C1x/LPC11C2x User manual

5 20110621 LPC111x/LPC11C1x/LPC11C2x User manual

4 20110304 LPC111x/LPC11C1x/LPC11C2x User manual

3 20110114 LPC111x/LPC11C1x/LPC11C2x User manual

2 20101102 LPC111x/LPC11 C1x User manual

1 20100721 LPC111x/LPC11C1x User manual

User manual Rev. 11 — 26 July 2012 3 of 538

1.1 Introduction

The LPC111x/LPC11Cxx are a ARM Cortex-M0 based, low-cost 32-bit MCU family,

designed for 8/16-bit micr ocontroller applications, of fering performance, low power, simple

instruction set and memory addressing together with reduced code size compared to

existing 8/16-bit architectures.

The LPC111x/LPC11Cxx operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC111x/LPC11Cxx includes up to 32 kB of flash

memory, up to 8 kB of data memory, one C_CAN controller (LPC11Cxx), one Fast-mode

Plus I2C-bus interface, one RS-485/EIA-485 UART, up to two SPI interfaces with SSP

features, four general purpose timers, a 10-bit ADC, and up to 42 general purpose I/O

pins.

On-chip C_CAN drivers and flash In-System Programming tools via C_CAN are included

on the LPC11Cxx. In addition, parts LPC11C2x are equipped with an on-chip CAN

transceiver.

Remark: This user manual covers the LPC111x/LPC11Cxx parts and th e LPC11D14

dual-chip p art with PCF8576D LCD controller. The LPC111x/LPC11Cxx part s are grouped

by the following series and part names (see Table 1 for a feature overview):

•LPC1100 series (parts LPC111x/101/201/301)

•LPC1100L series (parts LPC111x/102/202/302) and part LPC11D14 with LCD

controller.

•LPC1100XL series (parts LPC111x/103/203/323/333)

•LPC11C00 series (parts LPC11C1x/301 and LPC11C2x/301) with C_CAN controller.

UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

Rev. 11 — 26 July 2012 User manual

User manual Rev. 11 — 26 July 2012 4 of 538

NXP Semiconductors UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

Table 1. LPC111x/LPC11Cxx feature changes

Series Features overv iew

LPC1100 series •I2C, SSP, UART, GPIO

•Timers and watch dog timer

•10-bit ADC

•Flash/SRAM memory

•For a full feature list, see Section 1.2.

LPC1100L series LPC1100 series features plus the following additional features:

•Power profiles with lower power consumption in Active and Sleep modes.

•Internal pull-up resistors pull up pin s to full VDD level.

•Programmable pseudo open-drain mode for GPIO pins.

•WWDT with clock source lock capability.

•Small packages (TSSOP, SO, DIP, HVQFN)

LPC1100XL

series LPC1100L series features plus the following new features:

•Flash page erase In-Application Programming (IAP) function.

•Timer, UART, and SSP functions pinned out on additional pins.

•One capture function added for each timer.

•Capture-clear feature on the 16-bit and 32-bit timers for easy pulse-width

measurements.

LPC11C00 series LPC1100 series features plus the following additional features:

•CAN controller.

•On-chip CAN drivers.

•On-chip CAN transceiver (LPC11C2x).

•WDT (not windowed) with clock source lock capability.

LPC11D14

(LPC1100L

series)

LPC1100L series with LCD controller PCF8576D in a dual-chip package.

User manual Rev. 11 — 26 July 2012 5 of 538

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Chapter 1: LPC111x/LPC11Cxx Introductory information

1.2 Features

•System:

–ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

–ARM Cortex-M0 bu ilt- in Ne ste d Vectored Interrupt Controller (NVIC).

–Serial Wire Debug.

–System tick timer.

•Memory:

–On-chip flash programming memory for LPC1100, LPC1100L, and LPC1100C

series: 32 kB (LPC1114/LPC11C14), 24 kB (LPC1113), 16 kB

(LPC1112/LPC11C12), or 8 kB (LPC1111), 4kB (LPC1110) .

–On-chip flash programmi ng memory for LPC1100XL series: 8 kB (LPC1111), 16 kB

(LPC1112) , 24 kB (LPC1113), 32 kB (LPC1114/203/303), 48 kB (LPC1114/323),

56 kB (LPC1114/333), 64 kB (LPC1115).

–8 kB, 4 kB, 2 kB, or 1 kB SRAM.

–In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

–LPC1100XL series only: page erase IAP command.

•Digital peripherals:

–Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors. Number of GPIO pins is reduced for sm alle r packages an d

LPC11C22/C24.

–GPIO pins can be used as edge and level sensitive interrupt sources.

–High-current output driver (20 mA) on one pin.

–High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.

–Four general purpose timers/counters with a total of four capture inputs and up to

13 match outputs.

–Programmable WatchDog Timer (WDT).

•Analog peripherals:

–10-bit ADC with input multiplexing among up to 8 pins.

•Serial interfaces:

–UART with fractional baud rate generation, internal FIFO, and RS-485 support.

–Two SPI controllers with SSP features and with FIFO and multi-protocol

capabilities (second SPI on LQFP48 packages only).

–I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monito r mode.

–C_CAN controller (LPC11Cxx only). On-chip CAN and CANopen drivers included.

–On-chip, high-speed CAN transceiver (parts LPC11C22/C24 only).

•Clock generation :

–12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used

as a system clock.

–Crystal oscillator with an operating range of 1 MHz to 25 MHz.

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Chapter 1: LPC111x/LPC11Cxx Introductory information

–Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

–PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

–Clock output function with div ider that can reflect the system oscillator clock, IRC

clock, CPU clock, and the Watchdog clock.

•Power control:

–Integrated PMU (Power Manag ement Unit) to minim ize po wer consump tion d uring

Sleep, Deep-sleep, and Deep power-down modes.

–Power profiles residing in boot ROM allowing to optimize performance and

minimize power consumption for a ny given applicatio n through one simp le function

call. (On LPC1100L and LPC1100XL parts only).

–Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

–Processor wake-up from Deep-sleep mode via a dedicated start logic using up to

13 of the functional pins.

–Power-On Reset (POR).

–Brownout detect with three separate thresholds for interrupt and forced reset.

•Unique device serial number for identification.

•Single 3.3 V power supply (1.8 V to 3.6 V).

•Available as LQFP48 package, HVQFN33 package.

•LPC1100L series also available as HVQFN24, TSSOP28 package, DIP28 p ackage,

TSSOP20 package, and SO20 package.

•Available as dual-chip module consisting of the LPC1114 single-chip microcontroller

combined with a PCF8576D Universal LCD driver in a 100-pin LQFP package (part

LPC11D14FBD100/302).1

1. For details on the PCF8576D operation, see Ref. 3.

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Chapter 1: LPC111x/LPC11Cxx Introductory information

1.3 Ordering information

Table 2. Ordering informatio n

Type number Package

Name Description Version

SO20, TSSOP20, TSSOP28, and DIP28 packages

LPC1110FD20 SO20 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

LPC1111FDH20/002 TSSOP20 TSSOP20: plastic thin shrink small outline package; 20 leads; body

widt h 4. 4 mm SOT360-1

LPC1112FD20/102 SO20 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

LPC1112FDH20/102 TSSOP20 TSSOP20: plastic thin shrink small outline package; 20 leads; body

widt h 4. 4 mm SOT360-1

LPC1112FDH28/102 TSSOP28 TSSOP28: plastic thin shrink small outline package; 28 leads; body

widt h 4. 4 mm SOT361-1

LPC1114FDH28/102 TSSOP28 TSSOP28: plastic thin shrink small outline package; 28 leads; body

widt h 4. 4 mm SOT361-1

LPC1114FN28/102 DIP28 DIP28: plastic dual in-line package; 28 leads (600 mil) SOT117-1

HVQFN24/33 and LQFP48 packages

LPC1111FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1111FHN33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1111FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1111FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1111FHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1111FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1112 FHN 33/101 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1112 FHN 33/102 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1112 FHN 33/201 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1112 FHN 33/202 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1112FHN24/202 HVQFN24 HVQFN24: plastic thermal enhanced very thin quad flat package; no

leads; 24 terminals; body 4 x 4 x 0.85 mm sot616-3

LPC1112FHI33/202 HVQFN33 HVQFN: plastic thermal en hanced very thin quad flat package; no

leads; 33 terminals; body 5  5  0.85 mm n/a

LPC1112 FHI33 /203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 5  5  0.85 mm n/a

LPC1112 FHN 33/103 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1112 FHN 33/203 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

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Chapter 1: LPC111x/LPC11Cxx Introductory information

LPC1113 FHN 33/201 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1113 FHN 33/202 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1113 FHN 33/301 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1113 FHN 33/302 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1113 FHN 33/203 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1113 FHN 33/303 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1114 FHN 33/201 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1114 FHN 33/202 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1114 FHN 33/301 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1114 FHN 33/302 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1114 FHI33 /302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 5  5  0.85 mm n/a

LPC1114 FHI33 /303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 5  5  0.85 mm n/a

LPC1114 FHN 33/203 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1114FHN33/303 HVQFN3 3 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1114 FHN 33/333 HVQFN33 HVQFN: plastic thermal enhance d very thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

LPC1113FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC1113FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC1113FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC1114FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC1114FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC1114FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

Table 2. Ordering informatio n …continued

Type number Package

Name Description Version

User manual Rev. 11 — 26 July 2012 9 of 538

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Chapter 1: LPC111x/LPC11Cxx Introductory information

LPC1114FBD48/323 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC1114FBD48/333 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC1115FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

Table 2. Ordering informatio n …continued

Type number Package

Name Description Version

Table 3. Ordering options

Type number Series Flash

Total SRAM

UART RS-485

I2C/ Fm+

SPI

Power profiles

ADC channels

GPIO

C_CAN

Package

LPC1110

LPC1110FD20 LPC1100L 4 kB 1 kB 1 1 1 yes 5 16 - SO20

LPC1111

LPC1111FDH20/002 LPC1100L 8 kB 2 kB 1 1 1 yes 5 16 - TSSOP20

LPC1111FHN33/101 LPC1100 8 kB 2 kB 1 1 1 no 8 28 - HVQFN33

LPC1111FHN33/102 LPC1100L 8 kB 2 kB 1 1 1 yes 8 28 - HVQFN33

LPC1111FHN33/103 LPC1100XL 8 kB 2 kB 1 1 2 yes 8 28 - HVQFN33

LPC1111FHN33/201 LPC1100 8 kB 4 kB 1 1 1 no 8 28 - HVQFN33

LPC1111FHN33/202 LPC1100L 8 kB 4 kB 1 1 1 yes 8 28 - HVQFN33

LPC1111FHN33/203 LPC1100XL 8 kB 4 kB 1 1 2 yes 8 28 - HVQFN33

LPC1112

LPC1112FD20/102 LPC1100L 16 kB 4 kB 1 1 1 yes 5 16 - SO20

LPC1112FDH20/102 LPC1100L 16 kB 4 kB 1 - 1 yes 5 14 - TSSOP20

LPC1112FDH28/102 LPC1100L 16 kB 4 kB 1 1 1 yes 6 22 - TSSOP28

LPC1112FHN33/101 LPC1100 16 kB 2 kB 1 1 1 no 8 28 - HVQFN33

LPC1112FHN33/102 LPC1100L 16 kB 2 kB 1 1 1 yes 8 28 - HVQFN33

LPC1112FHN33/103 LPC1100XL 16 kB 2 kB 1 1 2 yes 8 28 - HVQFN33

LPC1112FHN33/201 LPC1100 16 kB 4 kB 1 1 1 no 8 28 - HVQFN33

LPC1112FHN24/202 LPC1100L 16 kB 4 kB 1 1 1 yes 6 19 - HVQFN24

LPC1112FHN33/202 LPC1100L 16 kB 4 kB 1 1 1 yes 8 28 - HVQFN33

LPC1112FHN33/203 LPC1100XL 16 kB 4 kB 1 1 2 yes 8 28 - HVQFN33

LPC1112FHI33/202 LPC1100L 16 kB 4 kB 1 1 1 yes 8 28 - HVQFN33

LPC1112FHI33/203 LPC1100XL 16 kB 4 kB 1 1 2 yes 8 28 - HVQFN33

LPC1113

LPC1113FHN33/201 LPC1100 24 kB 4 kB 1 1 1 no 8 28 - HVQFN33

LPC1113FHN33/202 LPC1100L 24 kB 4 kB 1 1 1 yes 8 28 - HVQFN33

LPC1113FHN33/203 LPC1100XL 24 kB 4 kB 1 1 2 yes 8 28 - HVQFN33

LPC1113FHN33/301 LPC1100 24 kB 8 kB 1 1 1 no 8 28 - HVQFN33

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Chapter 1: LPC111x/LPC11Cxx Introductory information

LPC1113FHN33/302 LPC1100L 24 kB 8 kB 1 1 1 yes 8 28 - HVQFN33

LPC1113FHN33/303 LPC1100XL 24 kB 8 kB 1 1 2 yes 8 28 - HVQFN33

LPC1113FBD48/301 LPC1100 24 kB 8 kB 1 1 2 no 8 42 - LQFP48

LPC1113FBD48/302 LPC1100L 24 kB 8 kB 1 1 2 yes 8 42 - LQFP48

LPC1113FBD48/303 LPC1100XL 24 kB 8 kB 1 1 2 yes 8 42 - LQFP48

LPC1114

LPC1114FDH28/102 LPC1100L 32 kB 4 kB 1 1 1 yes 6 22 TSSOP28

LPC1114FN28/102 LPC1100L 32 kB 4 kB 1 1 1 yes 6 22 DIP28

LPC1114FHN33/201 LPC1100 32 kB 4 kB 1 1 1 no 8 28 - HVQFN33

LPC1114FHN33/202 LPC1100L 32 kB 4 kB 1 1 1 yes 8 28 - HVQFN33

LPC1114FHN33/203 LPC1100XL 32 kB 4 kB 1 1 2 yes 8

LPC1114FHN33/301 LPC1100 32 kB 8 kB 1 1 1 no 8 28 - HVQFN33

LPC1114FHN33/302 LPC1100L 32 kB 8 kB 1 1 1 yes 8 28 - HVQFN33

LPC1114FHN33/303 LPC1100XL 32 kB 8 kB 1 1 2 yes 8 28 - HVQFN33

LPC1114FHN33/333 LPC1100XL 56 kB 8 kB 1 1 2 yes 8 28 - HVQFN33

LPC1114FHI33/302 LPC1100L 32 kB 8 kB 1 1 1 yes 8 28 - HVQFN33

LPC1114FHI33/303 LPC1100XL 32 kB 8 kB 1 1 2 yes 8 28 - HVQFN33

LPC1114FBD48/301 LPC1100 32 kB 8 kB 1 1 2 no 8 42 - LQFP48

LPC1114FBD48/302 LPC1100L 32 kB 8 kB 1 1 2 yes 8 42 - LQFP48

LPC1114FBD48/303 LPC1100XL 32 kB 8 kB 1 1 2 yes 8 42 - LQFP48

LPC1114FBD48/323 LPC1100XL 48 kB 8 kB 1 1 2 yes 8 42 - LQFP48

LPC1114FBD48/333 LPC1100XL 56 kB 8 kB 1 1 2 yes 8 42 - LQFP48

LPC1115

LPC1115FBD48/303 LPC1100XL 64 kB 8 kB 1 1 2 yes 8 42 - LQFP48

LPC11C12/LPC11C14

LPC11C12FBD48/301 LPC11C00 16 kB 8 kB 1 1 2 no 8 40 1 LQFP48

LPC11C14FBD48/301 LPC11C00 32 kB 8 kB 1 1 2 no 8 40 1 LQFP48

LPC11C22/LPC11C24 with on-chip, high-speed CAN transceiver

LPC11C22FBD48/301 LPC11C00 16 kB 8 kB 1 1 2 no 8 36 1 LQFP48

LPC11C24FBD48/301 LPC11C00 32 kB 8 kB 1 1 2 no 8 36 1 LQFP48

LPC11D14 dual-chip module with PCF8576D LCD driver1

LPC11D14FBD100/302 LPC1100L 32 kB 8 kB 1 1 2 yes 8 42 - LQFP100

Table 3. Ordering options …continued

Type number Series Flash

Total SRAM

UART RS-485

I2C/ Fm+

SPI

Power profiles

ADC channels

GPIO

C_CAN

Package

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Chapter 1: LPC111x/LPC11Cxx Introductory information

1.4 Block diagram

(1) LQFP48 packages only.

(2) Not on LPC1112FDH20/102.

(3) All pins available on LQFP48 and HVQFN33 packages. CT16B1_MAT1 not available on TSSOP28/DIP28 packages.

CT32B1_MAT3, CT16B1_CAP0, CT16B1_MAT[1:0], CT32B0_CAP0 not available on TSSOP20/SO20 packages.

CT16B1_MAT[1:0], CT32B0_CAP0 not available on the HVQFN24 package. XTALOUT not available on LPC1112FHN24.

(4) AD[7:0] available on LQFP48 and HVQFN33 packages. AD[5:0] available on TSSOP28/DIP28/HVQFN24packages. AD[4:0]

available on TSSOP20/SO20 packages.

(5) All pins available on LQFP48 packages. RXD, TXD, DTR, CTS, RTS available on HVQFN 33 packages. RXD, TXD, CTS, RTS

available on TSSOP28/DIP28 packages. RXD, TXD available on TSSOP20/SO20 packages.

Fig 1. LPC111x block diagram (LPC1100 and LPC1100L series)

SRAM

1/2/4/8 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

4/8/16/24/32 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT(3) RESET

clocks and

controls

SWD

LPC1110/11/12/13/14

002aae696

slave

slave slave

ROM

slave

AHB-LITE BUS

GPIO ports

PIO0/1/2/3

CLKOUT

IRC

POR

SPI0

10-bit ADC

UART

32-bit COUNTER/TIMER 0

I2C-BUS(2)

WDT

IOCONFIG

CT32B0_MAT[3:0](3)

AD[7:0](4)

CT32B0_CAP0(3)

SDA

SCL

RXD

TXD

DTR, DSR, CTS(5),

DCD, RI, RTS(5)

SYSTEM CONTROL

PMU

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0](3)

CT32B1_CAP0(3)

16-bit COUNTER/TIMER 1

CT16B1_MAT[1:0](3)

CT16B1_CAP0(3)

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0](3)

CT16B0_CAP0(3)

SCK0, SSEL0

MISO0, MOSI

SCK1, SSEL1

MISO1, MOSI

SPI1(1)

system bus

User manual Rev. 11 — 26 July 2012 12 of 538

NXP Semiconductors UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

(1) Available on LQFP packages only.

Fig 2. LPC111x block diagram (LPC1100XL series)

SRAM

2/4/8 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

8/16/24/32/

48/56/64 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT

RESET

clocks and

controls

SWD

LPC1111/12/13/14/15XL

002aag780

slave

slave slave

ROM

slave

AHB-LITE BUS

GPIO ports

PIO0/1/2/3

CLKOUT

IRC

POR

SPI0

10-bit ADC

UART

32-bit COUNTER/TIMER 0

I2C-BUS

WWDT

IOCONFIG

CT32B0_MAT[3:0]

AD[7:0]

CT32B0_CAP[1:0]

SDA

SCL

RXD

TXD

DTR, DSR(1), CTS,

DCD(1), RI(1), RTS

SYSTEM CONTROL

PMU

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

CT32B1_CAP[1:0]

16-bit COUNTER/TIMER 1

CT16B1_MAT[1:0]

CT16B1_CAP[1:0]

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

CT16B0_CAP[1:0]

SCK0, SSEL0

MISO0, MOSI0

SCK1, SSEL1

MISO1, MOSI1

SPI1

system bus

User manual Rev. 11 — 26 July 2012 13 of 538

NXP Semiconductors UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

(1) Not available on LPC11C22/C24.

Fig 3. LPC11Cxx/LPC11D14 bloc k diagram (LPC1100C series and LPC11D14)

SRAM

8 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

16/32 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT

RESET

clocks and

controls

SWD

LPC11Cxx

LPC11D14

slave

slave slave

ROM

slave

AHB-LITE BUS

GPIO ports

PIO0/1/2/3

CLKOUT

IRC

POR

SPI0

10-bit ADC

UART

32-bit COUNTER/TIMER 0

I2C-BUS

WDT

IOCONFIG

CT32B0_MAT[3:0]

AD[7:0]

CT32B0_CAP0

SDA

SCL

RXD

TXD

DTR, DSR, CTS,

DCD, RI, RTS

SYSTEM CONTROL

PMU

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

CT32B1_CAP0

16-bit COUNTER/TIMER 1

CT16B1_MAT[1:0](1)

CT16B1_CAP0

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

CT16B0_CAP0

SCK0, SSEL0

MISO0, MOSI0

SCK1, SSEL1

MISO1, MOSI1

SPI1

system bus

C_CAN (LPC11C12/C14)

CAN_TXD

CAN_RXD

C_CAN/

ON-CHIP TRANSCEIVER

(LPC11C22/C24)

CANL, CANH

STB

VCC, VDD_CAN

User manual Rev. 11 — 26 July 2012 14 of 538

NXP Semiconductors UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

Fig 4. LPC11D14 block diagram

SCL, SDA

LCD_SCL, LCD_SDA

VLCD

LPC1114

MCU

PCF8576D

LCD

CONTROLLER

PIO0, PIO1, PIO2, PIO3

S[39:0]

BP[3:0]

002aag449

Fig 5. PCF8576D block diagram

002aag451

LCD BIAS

GENERATOR

LCD

VOLTAGE

SELECTOR

PCF8576D

BACKPLANE

OUTPUTS

DISPLAY

CONTROLLER

COMMAND

DECODER

WRITE DATA

CONTROL

DISPLAY RAM

40 x 4-BIT

OUTPUT BANK SELECT

AND BLINK CONTROL

DISPLAY

DISPLAY SEGMENT

OUTPUTS

DATA POINTER AND

AUTO INCREMENT

SUBADDRESS

COUNTER

CLOCK SELECT

AND TIMING

OSCILLATOR

INPUT

FILTERS

BLINKER

TIMEBASE

POWER-ON

RESET

I2C-BUS

CONTROLLER

BP0 BP2 BP1 BP3

VDD(LCD)

OSC

SYNC

S0 to S39

LCD_SDA

LCD_SCL

CLK

VSS(LCD)

VSS(LCD) VSS(LCD)

VSS(LCD)

VLCD

A0SA0 A1 A2

User manual Rev. 11 — 26 July 2012 15 of 538

NXP Semiconductors UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

1.5 ARM Cortex-M0 processor

The ARM Cortex-M0 processor is described in detail in Section 28.3 “About the

Cortex-M0 processor and core peripherals”. For the LPC 111 x/ LPC11Cxx, the ARM

Cortex-M0 processor core is configured as follows:

•System options :

–The Nested Vectored Interrup t Contro ller (NVIC) is included and suppo rt s up to 32

interrupts.

–The system tick timer is included.

•Debug options: Serial Wire Debug is included with two watchpoints and four

breakpoints.

User manual Rev. 11 — 26 July 2012 16 of 538

2.1 How to read this chapter

Table 4 and Table 5 show the memory con fig u ra tio ns for different LPC 111x/LPC 11Cxx

parts.

2.2 Memory map

Figure 6 and Figure 7 show the memory and peripheral address space of the

LPC111x/LPC11Cxx.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.

On the LPC111x/LPC11Cxx, the GPIO ports are the only AHB peripherals. The APB

peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each

peripheral of either type is allocated 16 kB of space. This allows simplifying the address

decoding for each peripheral.

All peripheral register addresses are 32-bit word aligned regardless of their size. An

implication of this is that word and half-word registers must be accessed all at once. For

example, it is not possible to read or write the upper byte of a word register separately.

UM10398

Chapter 2: LPC111x/LPC11Cxx Memory mapping

Rev. 11 — 26 July 2012 User manual

Table 4. LPC111x memory configuration

Part Flash SRAM

Suffix /101; /102; /103 /201; /202; /203 /301; /302;

/303; /323; /333

LPC1111 8 kB 2 kB 4 KB -

LPC1112 16 kB 2 kB 4 KB -

LPC1113 24 kB - 4 KB 8 kB

LPC1114/LPC11D14 32 kB - 4 KB 8 kB

LPC1114/323 48 kB - - 8 kB

LPC1114/333 56 kB - - 8 kB

LPC1115 64 kB - - 8 kB

Table 5. LPC11Cxx memory configuration

Part Flash SRAM

LPC11C12/301 16 kB 8 kB

LPC11C14/301 32 kB 8 kB

LPC11C22/301 16 kB 8 kB

LPC11C24/301 32 kB 8 kB

User manual Rev. 11 — 26 July 2012 17 of 538

NXP Semiconductors UM10398

Chapter 2: LPC111x/LPC11Cxx Memory mapping

(1) LQFP100/LQFP48 packages only.

(2) LPC11Cxxonly.

Fig 6. LPC111x/LPC11Cxx memory map (LPC1100 and LPC1100L series)

0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

16 - 127 reserved

GPIO PIO1

4-7

0x5003 0000

0x5004 0000

GPIO PIO2

GPIO PIO3

8-11

12-15

GPIO PIO0

0-3

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x0000 2000

0x1000 2000

0x1000 1000

0x1000 0800

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

8 kB SRAM (LPC1113/14/301/302; LPC11D14;

LPC11Cxx)

0x1000 0000

4 kB SRAM (LPC1111/12/13/14/201/202)

2 kB SRAM (LPC1111/12/101/102)

LPC1111/12/13/14

LPC11Cxx

LPC11D14

8 kB on-chip flash (LPC1111)

0x0000 4000

0x0000 6000

16 kB on-chip flash (LPC1112; LPC11Cx2)

0x0000 8000

32 kB on-chip flash (LPC1114; LPC11D14;

LPC11Cx4)

24 kB on-chip flash (LPC1113)

16 kB boot ROM

0x0000 0000

0x0000 00C0

active interrupt vectors

reserved

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 0000

0x4005 4000

0x4005 8000

0x4005 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

UART

PMU

I2C-bus

10 - 13 reserved

reserved

23 - 31 reserved

SPI0

16-bit counter/timer 1

16-bit counter/timer 0

IOCONFIG

system control

20 C_CAN(2)

reserved

22 SPI1(1)

flash controller

0xE000 0000

0xE010 0000

private peripheral bus

User manual Rev. 11 — 26 July 2012 18 of 538

NXP Semiconductors UM10398

Chapter 2: LPC111x/LPC11Cxx Memory mapping

Fig 7. LPC111x memory map (LPC1 100XL series)

0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

127-16 reserved

GPIO PIO1

4-7

0x5003 0000

0x5004 0000

GPIO PIO2

GPIO PIO3

8-11

12-15

GPIO PIO0

0-3

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 8000

0x4005 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WWDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

UART

PMU

I2C-bus

13-10 reserved

reserved

21-19 reserved

31-23 reserved

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x0000 2000

0x1000 2000

0x1000 1000

0x1000 0800

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

8 kB SRAM (LPC1113/14/15/303/323/333)

4 kB SRAM (LPC1111/12/13/14/203)

2 kB SRAM (LPC1111/12/103)

0x1000 0000

LPC1111/12/13/14/15XL

8 kB on-chip flash (LPC1111)

0x0000 4000

0x0000 6000

16 kB on-chip flash (LPC1112)

0x0000 8000

32 kB on-chip flash (LPC1114)

24 kB on-chip flash (LPC1113)

0x0000 C000

0x0000 E000

48 kB on-chip flash (LPC1114/323)

0x0001 0000

64 kB on-chip flash (LPC1115)

56 kB on-chip flash (LPC1114/333)

16 kB boot ROM

0x0000 0000

0x0000 00C0

active interrupt vectors 002aag788

reserved

SPI0

16-bit counter/timer 1

16-bit counter/timer 0

IOCONFIG

system control

22 SPI1

flash controller

0xE000 0000

0xE010 0000

private peripheral bus

User manual Rev. 11 — 26 July 2012 19 of 538

3.1 How to read this chapter

The following functions of the system configuration block depend on the specific part

number:

DEVICE_ID register

The DEVICE_ID register is valid 0x4004 83F4 for part s of the LPC1100, LPC1100C, and

LPC1100L series only.

The device ID cannot be read through the SYSCON block for the LPC1100XL series. Use

the ISP part ID command (Table 399) to obtain the device ID for the LPC1100XL parts.

C_CAN controller

The C_CAN clock control bit 17 in the SYSAHBCLKCTRL register (Table 21) and the

C_CAN reset control bit 3 in the PRESETCTRL register (Table 9) are only functional for

parts LPC11C xx /1 01 /2 01 /3 01 .

Entering Deep power-down mode

Status of the IRC before entering Deep power-down mode (see Section 3.9.4.2):

•IRC must be enabled for parts LPC111x/101/201/301 and parts

LPC11Cxx/101/201/301.

•IRC status has no effect for parts in the LPC1100L and LPC1100XL series.

Enabling se q uen ce fo r UART clock

Requirements for enabling the UART peripheral clock:

•The UART pins must be configured in the IOCON block before the UART clock can be enabled

in the in the SYSAHBCLKCTRL register (Table 21) for parts LPC111x/101/201/301.

•The sequence of configuring the UART pins and the UART clock has no effect for

parts in the LPC1100L and LPC1100XL series and parts LPC1100C series.

NMI source selection register

The NMI source selection register is only available on parts in the LPC1100XL series.

3.2 General description

The system configuration block controls oscillators, start logic, and clock generation of the

LPC111x/LPC11Cxx. Also included in this block are registers for setting the priority for

AHB access and a register for remapping flash, SRAM, and ROM memory areas.

3.3 Pin description

Table 6 shows pin s tha t ar e as soc i at ed with sys tem con tr o l blo ck functions.

UM10398

Chapter 3: LPC111x/LPC11Cxx System configuration

(SYSCON)

Rev. 11 — 26 July 2012 User manual

User manual Rev. 11 — 26 July 2012 20 of 538

NXP Semiconductors UM10398

Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.4 Clock generation

See Figure 8 for an overview of the LPC111x/LPC11Cxx Clock Generation Unit (CG U ).

The LPC111x/LPC11Cxx include three independent oscillators. These are the system

oscillator , the Internal RC oscillator (IRC), and the watchdog oscillator . Each oscillator can

be used for more than one purpose as required in a particular application.

Following reset, the LPC111x/LPC11Cxx will operate from the Internal RC oscillator until

switched by software. This allows systems to oper ate without any extern al cryst al and the

bootloader code to operate at a known frequency.

The SYSAHBCLKCTRL register gates the system clock to the various peripherals and

memories. UART, the WDT, and SPI0/1 have individual clock dividers to derive pe ripheral

clocks from the main clock.

The main clock and the clock outputs from the IRC, the system oscillator, and the

watchdog oscillator can be observed directly on the CLKOUT pin.

For details on power control see Section 3.9.

Table 6. Pin summary

Pin name Pin direction Pin descriptio n

CLKOUT O Clockout pin

PIO0_0 to PIO0_11 I Start logic wake-up pins port 0

PIO1_0 I Start logic wake-up pin port 1

User manual Rev. 11 — 26 July 2012 21 of 538

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers

appear in the description of each function.

See Section 3.12 for the flash access timing register, which can be re-configured as part

the system setup. This register is not part of the system configuration block.

Fig 8. LPC111x/LPC11Cxx CGU block diagram

SYSTEM PLL

IRC oscillator

system oscillator

watchdog oscillator

IRC oscillator

watchdog oscillator

MAINCLKSEL

(main clock select)

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM CLOCK

DIVIDER

SYSAHBCLKCTRL[1:18]

SPI0 PERIPHERAL

CLOCK DIVIDER SPI0_PCLK

SPI1 PERIPHERAL

CLOCK DIVIDER SPI1_PCLK

UART PERIPHERAL

CLOCK DIVIDER UART_PCLK

WDT CLOCK

DIVIDER WDCLK

WDTUEN

(WDT clock update enable)

watchdog oscillator

IRC oscillator

system oscillator CLKOUT PIN CLOCK

DIVIDER CLKOUT pin

CLKOUTUEN

(CLKOUT update enable)

main clock

system clock

IRC oscillator

AHB clocks

1 to 18

(memories

and peripherals)

sys_pllclkout

sys_pllclkin

ARM

CORTEX-M0

SYSAHBCLKDIV

Table 7. Register overview: system con t rol block (base address 0x4004 8000)

Name Access Address offset Description Reset

value Reference

SYSMEMREMAP R/W 0x000 System memory remap 0x002 Table 8

PRESETCTRL R/W 0x004 Peripheral reset control 0x000 Table 9

SYSPLLCTRL R/W 0x008 System PLL control 0x000 Table 10

SYSPLLSTAT R 0x00C System PLL status 0x000 Table 11

- - 0x010 - 0x01C Reserved - -

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 11 — 26 July 2012  22 of 538
NXP Semiconductors UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
SYSOSCCTRL R/W 0x020 System oscillator control 0x000 Table 12
WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x000 Table 13
IRCCTRL R/W 0x028 IRC control 0x080 Table 14
- - 0x02C Reserved - -
SYSRSTSTAT R/W 0x030 System reset status register 0x000 Table 15
- - 0x034 - 0x03C Reserved - -
SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0x000 Table 16
SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0x000 Table 17
- - 0x048 - 0x06C Reserved - -
MAINCLKSEL R/W 0x070 Main clock source select 0x000 Table 18
MAINCLKUEN R/W 0x074 Main clock source upd ate enable 0x000 Table 19
SYSAHBCLKDIV R/W 0x078 System AHB clock divider 0x001 Table 20
- - 0x07C Reserved - -
SYSAHBCLKCTRL R/W 0x080 System AHB clock control  0x85F Table 21
- - 0x084 - 0x090 Reserved - -
SSP0CLKDIV R/W 0x094 SPI0 clock divider 0x000 Table 22
UARTCLKDIV R/W 0x098 UART clock divder 0x000 Table 23
SSP1CLKDIV R/W 0x09C SPI1 clock divder 0x000 Table 24
- - 0x0A0-0x0CC Reserved - -
WDTCLKSEL R/W 0x0D0 WDT clock source select 0x000 Table 25
WDTCLKUEN R/W 0x0D4 WDT clock source update enable 0x000 Table 26
WDTCLKDIV R/W 0x0D8 WDT clock divider 0x000 Table 27
- - 0x0DC Reserved - -
CLKOUTCLKSEL R/W 0x0E0 CLKOUT clock source select 0x000 Table 28
CLKOUTUEN R/W 0x0E4 CLKOUT clock source update enable 0x00 0 Table 29
CLKOUTCLKDIV R/W 0x0E8 CLKOUT clock divider 0x000 Table 30
- - 0x0EC - 0x0FC Reserved - -
PIOPORCAP0 R 0x100 POR captured PIO status 0 user 
dependent Table 31
PIOPORCAP1 R 0x104 POR captured PIO status 1 user 
dependent Table 32
- R 0x108 - 0x14C Reserved - -
BODCTRL R/W 0x150 BOD control 0x000 Table 33
SYSTCKCAL R/W 0x154 System tick counter calibration 0x004 Table 34
- - 0x158 - 0x170 Reserved - -
NMISRC R/W 0x174 NMI source selection 0x000 Table 35
- - 0x178 - 0x1FC Reserved - -
STARTAPRP0 R/W 0x200 Start logic edge control register 0 Table 36
STARTERP0 R/W 0x204 Start logic signal enable register 0  Table 37
STARTRSRP0CLR W 0x208 Start logic reset register 0  n/a Table 38
STARTSRP0 R 0x20C Start logic status register 0 n/a Table 39
Table 7. Register overview: system con t rol block (base address 0x4004 8000)  …continued
Name Access Address offset Description Reset 
value Reference

User manual Rev. 11 — 26 July 2012 23 of 538

NXP Semiconductors UM10398

Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.1 System memory remap register

The system memory remap register selects whether the ARM interrupt vectors are read

from the boot ROM, the flash, or the SRAM. By default, the flash memory is mapped to

address 0x0000 0000. Whe n the MAP bit s in the SYSMEMREMAP regi ster are set to 0x0

or 0x1, the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the

memory map (addresses 0x0000 0000 to 0x0000 0200).

3.5.2 Peripheral reset control register

This register allows software to reset the SPI and I2C peripherals. Writing a zero to the

SSP0/1_RST_N or I2C_RST_N bits resets the SPI0/1 or I2C peripheral. Writing a one

de-asserts the reset.

Remark: Before accessing the SPI and I2C peripherals, write a one to this register to

ensure that the reset signals to the SPI and I2C are de-asserted.

- - 0x210 - 0x22C Reserved - -

PDSLEEPCFG R/W 0x230 Power-down states in Deep-sleep mode 0x0000

0000 Table 41

PDAWAKECFG R/W 0x234 Power-down states after wake-up from

Deep-sleep mode 0x0000

EDF0 Table 42

PDRUNCFG R/W 0x238 Power-down configuration register 0x0000

EDF0 Table 43

- - 0x23C - 0x3F0 Reserved - -

DEVICE_ID R 0x3F4 Device ID register 0 for parts LPC1100,

LPC1100C, LPC1100L. part

dependent Table 44

Table 7. Register overview: system con t rol block (base address 0x4004 8000) …continued

Name Access Address offset Description Reset

value Reference

Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit

description

Bit Symbol Value Description Reset

value

1:0 MAP System memory remap 10

0x0 Boot Loader Mode. Interrupt ve ctors are re-mapped to Boot

ROM.

0x1 User RAM Mode. Interrupt vectors are re-mapped to Static

RAM.

0x2 User Flash Mode. Interrupt vectors are no t re-mapped and

reside in Flash.

31:2 - - Reserved 0x00

Table 9. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit Symbol Value Description Reset

value

0 SSP0_RST_N SPI0 reset control 0

0 Resets the SPI0 peripheral.

1 SPI0 re set de-asserted.

User manual Rev. 11 — 26 July 2012 24 of 538

NXP Semiconductors UM10398

Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.3 System PLL control register

This register conne ct s and e nables the system PL L and configur es the PLL multiplie r and

divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various

clock sources. The input frequency is multiplie d up to a hig h frequency, then divided down

to provide the actual clock used by the CPU, peripherals, and memories. The PLL can

produce a clock up to the maximum allowed for the CPU.

3.5.4 System PLL status register

This register is a Read-only register and supplie s the PLL lock status (see Section 3.11.1).

1 I2C_RST_N I2C reset control 0

0 Resets the I2C peripheral.

1 I2C reset de-asserted.

2 SSP1_RST_N SPI1 reset control 0

0 Resets the SPI1 peripheral.

1 SPI1 re set de-asserted.

3 CAN_RST_N C_CAN reset control. See Section 3.1 for part specific

details. 0

0 Resets the C_CAN peripheral.

1 C_CAN reset de-asserted.

31:4 - - Reserved 0x00

Table 9. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit Symbol Value Description Reset

value

Table 10. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description

Bit Symbol Value Description Reset

value

4:0 MSEL Feedback divider value. The division value M is the

programmed MSEL value + 1.

00000: Division ratio M = 1

11111: Division ratio M = 32.

0x000

6:5 PSEL Post divider ratio P. The division ratio is 2  P. 0x00

0x0 P = 1

0x1 P = 2

0x2 P = 4

0x3 P = 8

31:7 - - Reserved. Do not write ones to reserved bits. 0x0

User manual Rev. 11 — 26 July 2012 25 of 538

NXP Semiconductors UM10398

Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.5 System oscillator control register

This register configures the frequency range for the system oscillator.

3.5.6 Watchdog oscillator control register

This register configures the watchdog oscillator . The oscillator consists of an analog and a

digital p art. The analog part contains the oscillator function and generates an analog clock

(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the

required output clock frequency wdt_osc_clk. The ana log outp ut frequency (Fclkan a) can

be adjusted with the FREQSEL bits between 600 kHz and 4.6 MHz. With the digital part

Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.

The output clock frequency of the watchdog oscillator can be calculated as

wdt_osc_clk = Fclkana/(2  (1 + DIVSEL)) = 9.3 kHz to 2.3 MHz (nominal values).

Remark: Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the

listed frequency value. The watchdog oscillator is the clock source with the lowest power

consumption. If accurate timing is required, use the IRC or system oscillator.

Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog

oscillator frequency must be programmed by writing to the WDTOSCCTRL register before

using the watchdog oscillator.

Table 11. S ystem PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description

Bit Symbol Value Description Reset

value

0 LOCK PLL lock status 0x0

0 PLL not locked

1 PLL locked

31:1 - - Reserved 0x00

Table 12. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description

Bit Symbol Value Description Reset

value

0 BYPASS Bypass system oscillator 0x0

0 Oscillator is not bypassed.

1 Bypass enabled. PLL input (sys_osc_clk) is fed

directly from the XTALIN pin bypassing the

oscillator. Use this mode when using an external

clock source instead of the crystal oscillator.

1 FREQRANGE Determines frequency range for Low-power

oscillator. 0x0

0 1 - 20 MHz frequency range.

1 15 - 25 MHz frequency range

31:2 - - Reserved 0x00

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3.5.7 Internal resonant crystal control register

This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset

and written by the boot code on start-up.

3.5.8 System reset status register

The SYSRSTSTAT register shows the source of the latest reset event. Write a one to

clear the reset.

The POR event clears all other bits in this register. If any reset signal - for example

EXTRST - remains asserted af ter the POR signal is ne gated, then it s bit is set to detected

in this register.

Table 13. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 80 24) bit

description

Bit Symbol Value Description Reset

value

4:0 DIVSEL Select divider for Fclkana.

wdt_osc_clk = Fclkana/ (2  (1 + DIVSEL))

00000: 2  (1 + DIVSEL) = 2

00001: 2  (1 + DIVSEL) = 4

11111: 2  (1 + DIVSEL) = 64

8:5 FREQSEL Select watchdog oscillator analog output frequency

(Fclkana). 0x00

0x1 0.6 MHz

0x2 1.05 MHz

0x3 1.4 MHz

0x4 1.75 MHz

0x5 2.1 MHz

0x6 2.4 MHz

0x7 2.7 MHz

0x8 3.0 MHz

0x9 3.25 MHz

0xA 3.5 MHz

0xB 3.75 MHz

0xC 4.0 MHz

0xD 4.2 MHz

0xE 4.4 MHz

0xF 4.6 MHz

31:9 - - Reserved 0x00

Table 14. Internal resonant crystal control register (IRCCTRL, address 0x400 4 8028) bit

description

Bit Symbol Description Re set value

7:0 TRIM Trim value 0x1000 0000, then

flash will reprogram

31:8 - Reserved 0x00

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The reset value given in Table 15 applies to the POR reset.

3.5.9 System PLL clock source select register

This register selects the clock source for the system PLL. The SYSPLLCLKUEN register

(see Section 3.5.10) must be toggled from LOW to HIGH for the update to take effect.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system

oscillator must be selected.

Table 15. System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description

Bit Symbol Value Description Reset

value

0 POR POR reset status 0x0

0 No POR detected.

1 POR detected. Writing a one clears this reset.

1 EXTRST Status of the external RESET pin. 0x0

0 No RESET event detected.

1 RESET detected. Writing a one clears this reset.

2 WDT Status of the Watchdog reset 0x0

0 No WDT reset detected.

1 WDT reset detected . Writing a one clears this reset.

3 BOD Status of the Brown-out detect reset 0x0

0 No BOD reset detected.

1 BOD reset detected. Writing a one clears this reset.

4 SYSRST Status of the software system reset 0x0

0 No System reset detected.

1 System reset dete cted. Writing a one clears this reset.

31:5 - - Reserved 0x0

Table 16. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)

bit description

Bit Symbol Value Description Reset

value

1:0 SEL System PLL clock source 0x00

0x0 IRC oscillator

0x1 System oscillator

0x2 Reserved

0x3 Reserved

31:2 - - Reserved 0x00

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3.5.10 System PLL clock source update enable register

This register updates the clock source of the system PLL with the new input clock after the

SYSPLLCLKSEL register has been written to. In order for the update to take effect, first

write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

3.5.11 Main clock source select register

This register selects the main system clock which can be either any input to the system

PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators

directly. The main system clock clocks the core, the peripherals, and the memories.

The MAINCLKUEN register (see Section 3.5.12) must be toggled from LOW to HIGH for

the update to take effect.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system

oscillator must be selected.

3.5.12 Main clock source update enable register

This register updates the clock source of the main clock with the new input clock after the

MAINCLKSEL register has been written to. In order for the update to take effect, first write

a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

Table 17. System PLL clock source update enable register (SYSPLLCLKUEN, address

0x4004 8044) bit description

Bit Symbol Value Description Reset value

0 ENA Enable system PLL clock source update 0x0

0 No change

1 Up date clock source

31:1 - - Reserved 0x00

Table 18. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit

description

Bit Symbol Value Description Reset value

1:0 SEL Clock source for main clock 0x00

0x0 IRC oscillator

0x1 Input clock to system PLL

0x2 WDT oscillator

0x3 System PLL clock out

31:2 - - Reserved 0x00

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3.5.13 System AHB clock divider register

This register divides the main clock to provide the system clock to the core, memories,

and the peripherals. The system clock can be shut down completely by setting the DIV

bits to 0x0.

3.5.14 System AHB clock control register

The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.

The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock

for the AHB to APB bridge, the AHB matrix, the ARM Co rte x- M 0, th e Sysc on block, and

the PMU. This clock cannot be disabled.

Table 19. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)

bit description

Bit Symbol Value Description Reset value

0 ENA Enable main clock source update 0x0

0 No change

1 Up date clock source

31:1 - - Reserved 0x00

Table 20. System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit

description

Bit Symbol Description Reset value

7:0 DIV System AHB clock divider values

0: System clock disabled.

1: Divide by 1.

255: Divid e by 25 5.

0x01

31:8 - Reserved 0x00

Table 21. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

description

Bit Symbol Value Description Reset

value

0 SYS Enables clock for AHB to APB bridge, to the AHB

matrix, to the Cortex-M0 FCLK and HCLK, to the

SysCon, and to the PMU. This bit is read only.

0 Reserved

1 Enable

1 ROM Enables clock for ROM. 1

0 Disable

1 Enable

2 RAM Enables clock for RAM. 1

0 Disable

1 Enable

3 FLASHREG Enables clock for flash register interface. 1

0 Disabled

1 Enabled

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4 FLASHARRAY Enables clock for flash array access. 1

0 Disabled

1 Enabled

5 I2C Enables clock for I2C. 0

0 Disable

1 Enable

6 GPIO Enables clock for GPIO. 1

0 Disable

1 Enable

7 CT16B0 Enables clock for 16-bit counter/timer 0. 0

0 Disable

1 Enable

8 CT16B1 Enables clock for 16-bit counter/timer 1. 0

0 Disable

1 Enable

9 CT32B0 Enables clock for 32-bit counter/timer 0. 0

0 Disable

1 Enable

10 CT3 2B1 Enables clock for 32-bit counter/timer 1. 0

0 Disable

1 Enable

11 SSP0 Enables clock for SPI0. 1

0 Disable

1 Enable

12 UART Enables clock for UART. See Section 3.1 for part

specific details. 0

0 Disable

1 Enable

13 ADC Enables clock for ADC. 0

0 Disable

1 Enable

14 - Reserved 0

15 WDT Enables clock for WDT. 0

0 Disable

1 Enable

16 IOCON Enables clock for I/O configuration block. 0

0 Disable

1 Enable

Table 21. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

description …continued

Bit Symbol Value Description Reset

value

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3.5.15 SPI0 clock divider register

This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be

shut down by setting the DIV bits to 0x0.

3.5.16 UART clock divider register

This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can

be shut down by setting the DIV bits to 0x0.

Remark: Note that for some pa rts the UART pins must be configured in the IOCON block

before the UART clock can be enabled. See Section 3.1 for part specific details.

3.5.17 SPI1 clock divider register

This register configures the SPI1 peripheral clock SPI1_PCLK. The SPI1_PCLK can be

shut down by setting the DIV bits to 0x0.

17 CAN Enables clock for C_CAN. See Section 3.1 for part

specific details. 0

0 Disable

1 Enable

18 SSP1 Enables clock for SPI1. 0

0 Disable

1 Enable

31:19 - - Reserved 0x00

Table 21. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

description …continued

Bit Symbol Value Description Reset

value

Table 22. SPI0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit de scription

Bit Symbol Description Reset value

7:0 DIV SPI0_PCLK clock divider values

0: Disable SPI0_PCLK.

1: Divide by 1.

255: Divid e by 25 5.

0x00

31:8 - Reserved 0x00

Table 23. UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description

Bit Symbol Description Reset value

7:0 DIV UART_PCLK clock divider values

0: Disable UART_PCLK.

1: Divide by 1.

255: Divid e by 25 5.

0x00

31:8 - Reserved 0x00

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3.5.18 WDT clock source select register

This register selects the clock source for the watchdog timer. The WDTCLKUEN register

(see Section 3.5.19) must be toggled from LOW to HIGH for the update to take effect.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

3.5.19 WDT clock source update enable register

This register upd ates the clock source of th e watchdog timer with the new input clock afte r

the WDTCLKSEL register has been written to. In order for the update to take effect at the

input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write

a one to WDTCLKUEN.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

3.5.20 WDT clock divider register

This register dete rm in es th e div ide r values for the watchdog clock wdt_clk.

Table 24. SPI1 clock divider register (SSP1CLKDIV, address 0x4004 809C) bit description

Bit Symbol Description Reset

value

7:0 DIV SPI1_PCLK clock divider values

0: Disable SPI1_PCLK.

1: Divide by 1.

255: Divid e by 25 5.

0x00

31:8 - Reserved 0x00

Table 25. WDT clock source sele ct register (WDTCLKSEL, address 0x4004 80D0) bit

description

Bit Symbol Value Description Reset

value

1:0 SEL WDT clock source 0x00

0x0 IRC oscillator

0x1 Main clock

0x2 Watchdog oscillator

0x3 Reserved

31:2 - - Reserved 0x00

Table 26. WDT clock source update enable register (WDTCLKUEN, address 0x4004 80D4)

bit description

Bit Symbol Value Description Reset value

0 ENA Enable WDT clock source update 0x0

0 No change

1 Up date clock source

31:1 - - Reserved 0x00

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3.5.21 CLKOUT clock source select register

This register configures the clkout_clk signal to be output on the CLKOUT pin. All three

oscillators and the main clock can be selected for the clkout_clk clock.

The CLKOUTCLKUEN register (see Section 3.5.22) must be toggled from LOW to HIGH

for the update to take effect.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

3.5.22 CLKOUT clock source update enable register

This register updates the clock source of the CLKOUT pin with the new clock after the

CLKOUTCLKSEL register has been written to. In order for the update to take effect at the

input of the CLKOUT pin, first write a zero to the CLKCLKUEN register a nd then write a

one to CLKCLKUEN.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

Table 27. WDT clock divider register (WDTCLKDIV, address 0x4004 80D8) bit description

Bit Symbol Description Reset value

7:0 DIV WDT clock divider values

0: Disable WDCLK.

1: Divide by 1.

255: Divid e by 25 5.

0x00

31:8 - Reserved 0x00

T able 28. CLKOUT clock source select register (CLKOUTCLKSEL, address 0x4004 80E0) bit

description

Bit Symbol Value Description Reset

value

1:0 SEL CLKOUT clock source 0x00

0x0 IRC oscillator

0x1 System oscillator

0x2 Watchdog oscillator

0x3 Main clock

31:2 - - Reserved 0x00

Table 29. CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004

80E4) bit description

Bit Symbol Value Description Reset value

0 ENA Enable CLKOUT clock source update 0x0

0 No change

1 Up date clock source

31:1 - - Reserved 0x00

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3.5.23 CLKOUT clock divider register

This register determines the divider value for the clock output signal on the CLKOUT pin.

3.5.24 POR captured PIO status register 0

The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports

0,1, and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state

of one GPIO pin. This register is a read-only status register.

3.5.25 POR captured PIO status register 1

The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2

(PIO2_8 to PIO2_11) and port 3 at power-on-reset. Each bit repr esents the reset state of

one PIO pin. This register is a read-only status register.

Table 30. CLKOUT clock divider re gisters (CLKOUTCLKDIV, address 0x4004 80E8) bit

description

Bit Symbol Description Reset value

7:0 DIV Clock output divider values

0: Disable CLKOUT.

1: Divide by 1.

255: Divid e by 25 5.

0x00

31:8 - Reserved 0x00

Table 31. POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 810 0) bit

description

Bit Symbol Description Reset value

11:0 CAPPIO0_n Raw reset status input PIO0_n:

PIO0_11 to PIO0_0 User implementation dependent

23:12 CAPPIO1_n Raw reset st atus input PIO1_n:

PIO1_11 to PIO1_0 User implementation dependent

31:24 CAPPIO2_n Raw reset st atus input PIO2_n:

PIO2_7 to PIO2_0 User implementation dependent

Table 32. POR captured PIO status registers 1 (PIOPORCAP1, address 0x4004 8104) bit

description

Bit Symbol Description Reset value

0 CAPPIO2_8 Raw reset status input PIO2_8 User implementation dependent

1 CAPPIO2_9 Raw reset status input PIO2_9 User implementation dependent

2 CAPPIO2_10 Raw reset status input PIO2_10 User implementation dependent

3 CAPPIO2_11 Raw reset status input PIO2_11 User implementation dependent

4 CAPPIO3_0 Raw reset status input PIO3_0 User implementation dependent

5 CAPPIO3_1 Raw reset status input PIO3_1 User implementation dependent

6 CAPPIO3_2 Raw reset status input PIO3_2 User implementation dependent

7 CAPPIO3_3 Raw reset status input PIO3_3 User implementation dependent

8 CAPPIO3_4 Raw reset status input PIO3_4 User implementation dependent

9 CAPPIO3_5 Raw reset status input PIO3_5 User implementation dependent

31:10 - Reserved -

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3.5.26 BOD control register

The BOD control register selects three separate threshold values for sending a BOD

interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed are

typical values.

3.5.27 System tick counter calibration register

This register determines the value of the SYST_CALIB register (see Table 360).

3.5.28 NMI source selection register

The NMI source selection register selects a peripheral interrupts as source for the NMI

interrupt of the ARM Cortex-M0 core. For a list of all peripheral interrupts and their IRQ

numbers see Table 54. For a description of the NMI functionality, see Section 28.4.3.2.

Remark: See Section 3.1 for LPC111x parts using this register.

Table 33. BOD control register (BODCTRL, address 0x4004 8150) bit descr iption

Bit Symbol Value Description Reset

value

1:0 BODRSTLEV BOD reset level 00

0x0 Level 0: Reserved.

0x1 Level 1: The reset assertion threshold voltage is 2.06 V ; the

reset de-assertion threshold voltage is 2.15 V.

0x2 Level 2: The reset assertion threshold voltage is 2.35 V ; the

reset de-assertion threshold voltage is 2.43 V.

0x3 Level 3: The reset assertion threshold voltage is 2.63 V ; the

reset de-assertion threshold voltage is 2.71 V.

3:2 BODINTVAL BOD interrupt level 00

0x0 Level 0: Reserved.

0x1 Level 1:The interrupt assertion threshold voltage is 2.22 V;

the interrupt de-assertion threshold voltage is 2.35 V.

0x2 Level 2: The interrupt assertion threshold voltage is 2.52 V;

the interrupt de-assertion threshold voltage is 2.66 V.

0x3 Level 3: The interrupt assertion threshold voltage is 2.80 V;

the interrupt de-assertion threshold voltage is 2.90 V.

4 BODRSTENA BOD reset enable 0

0 Disable reset function.

1 Enable reset function.

31:5 - - Reserved 0x00

Table 34. System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit

description

Bit Symbol Description Reset

value

25:0 CAL System tick timer calibration value 0x04

31:26 - Reserved 0x00

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Note: If the NMISRC re gister is used to select an interrupt as the source of Non-Maskable

interrupt s, and th e se lected inte rr upt is enabled , on e inter r upt reque st can r esult in bo th a

Non-Maskable and a normal interrupt. Avoid this situation by disabling the normal

interrupt in the NVIC, as described in Section 28.6.2.

3.5.29 Start logic edge control register 0

The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11)

and 1 (PIO1_0). This register selects a falling or rising edge on the corresponding PIO

input to produce a falling or rising clock edge, respectively, for the start logic (see

Section 3.10.2).

Every bit in the STARTAPRP0 register controls one port input and is connected to one

wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt

0, bit 1 to interrupt 1, etc. (see Table 54), up to a total of 13 interrupts.

Remark: Each interrupt connected to a st art logic input must be enabled in the NVIC if the

corresponding PIO pin is used to wake up the chip from Deep-sleep mode.

3.5.30 Start logic signal enable register 0

This STARTERP0 register enables or disa bles the start signal bits in the start logic. The

bit assignment is identical to Table 36.

Table 35. NMI source selectio n register (NMISRC, address 0x4004 8174) bit description

Bit Symbol Description Reset

value

4:0 IRQNO The IRQ number of the interrupt that acts as the Non-Maskable Interrupt

(NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt

sources and their IRQ numbers.

30:5 - Reserved -

31 NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source

selected by bits 4:0. 0

Table 36. Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit

description

Bit Symbol Description Reset

value

11:0 APRPIO0_n Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0

0 = Falling ed g e

1 = Rising edge

0x0

12 APRPIO1_0 Edge select for start logic input PIO1_0

0 = Falling ed g e

1 = Rising edge

0x0

31:13 - Reserved. Do not write a 1 to reserved bits in this register. 0x0

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3.5.31 Start logic reset register 0

Writing a one to a bit in the STARTRSRP0CLR register r eset s the st art lo gic st ate. The bit

assignment is identical to Table 36. The start-up logic uses the input signals to genera te a

clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt

for waking up from Deep-sleep mode. Therefore, the st art-up logic st ates must be cle ared

before being used.

3.5.32 Start logic status register 0

This register reflects the status of the enabled star t signal bits. The bit assignment is

identical to Table 36. Each bit (if enabled) reflects the state of the start logic, i.e. whether

or not a wake-up signal has been received for a given pin.

Table 37. Start logic signal enable register 0 (STARTERP0, address 0x4004 8204) bit

description

Bit Symbol Description Reset

value

11:0 ERPIO0_n Enable start signal for start logic input PIO0_n: PIO0_11 to

PIO0_0

0 = Disabled

1 = Enabled

0x0

12 ERPIO1_0 Enable start signal for start logic input PIO1_0

0 = Disabled

1 = Enabled

0x0

31:13 - Reserved. Do not write a 1 to reserved bits in this register. 0x0

Table 38. Start logic reset register 0 (STARTRSRP0CLR, address 0x4004 8208) bit

description

Bit Symbol Description Reset

value

11:0 RSRPIO0_n Start signal reset for start logic input PIO0_n:PIO0_11 to

PIO0_0

0 = Do nothing.

1 = Writing 1 resets the start signal.

n/a

12 RSRPIO1_0 Start signal reset for start logic input PIO1_0

0 = Do nothing.

1 = Writing 1 resets the start signal.

n/a

31:13 - Reserved. Do not write a 1 to reserved bits in this register. n/a

Table 39. Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description

Bit Symbol Description Reset

value

11:0 SRPIO0_ n Start signal status for start logic input PIO0_n: PIO0_11 to

PIO0_0

0 = No start signal received.

1 = Start signal pending.

n/a

12 SRPIO1_0 Start signal status for start logic input PIO1_0

0 = No start signal received.

1 = Start signal pending.

n/a

31:13 - Reserved n/a

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3.5.33 Deep-sleep mode configuration register

This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit

when the device enters Deep-sleep mode.

This register must be initialized at least once before entering Deep-sleep mode with

one of the four values shown in Table 40:

Remark: Failure to initialize and program this register correctly may result in undefined

behavior of the microcontroller. The values listed in Table 40 are the only value s allowed

for PDSLEEPCFG register.

To select the appropriate power configuration for Deep-sleep mode, consider the

following:

•BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event

occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an

additional current drain in Deep-sleep mode.

•WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to

provide a clock for the watchdog timer or a general purpose timer if they are needed

for timing a wake-up even t (se e Section 3.10.3 for details). In this case, the watchdog

oscillator analog output frequency must be set to its lowest value (bits FREQSEL in

the WDTOSCCTRL = 0001, see Table 13) and all peripheral clocks other than the

timer clock must be disabled in the SYSAHBCLKCTRL register (see Table 21) before

entering Deep-sleep mode.

The watchdog oscillator, if running, contributes an additional current drain in

Deep-sleep mode.

Remark: Reserved bits in this register must always be written as indicated. This register

must be initialized correctly before entering Deep-sleep mode.

Table 40. Allowed values for PDSLEEPCFG register

Configuration WD oscillator on WD oscillator off

BOD on PDSLEEPCFG = 0x0000 18B7 PDSLEEPCFG = 0x0000 18F7

BOD off PDSLEEPCFG = 0x0000 18BF PDSLEEPCFG = 0x0000 18FF

Table 41. Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit

description

Bit Symbol Value Description Reset

value

2:0 NOTUSED Reserved. Always write these b its as 111. 0

3 BOD_PD BOD power-down control in Deep-sleep mode, see

Table 40. 0

0 Powered

1 Powere d down

5:4 NOTUSED Reserved. Always write these b its as 11. 0

6 WDTOSC_PD Watchdog oscillator power control in Deep-sleep

mode, see Table 40.0

0 Powered

1 Powere d down

7 NOTUSED Reserved. Always write this bit as 1. 0

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3.5.34 Wake-up conf iguration register

The bits in this register determine the state the chip enters when it is waking up from

Deep-sleep mode.

By default, the IRC and flash memory are powered and running and the BOD circuit is

enabled when the chip wakes up from Deep-sleep mode.

Remark: Reserved bit s must be always written as indicated.

10:8 NOTUSED Reserved. Always write these bits as 000. 0

12:11 NOTUSED Reserved. Always write these b its as 11. 0

31:13 - 0 Reserved 0

Table 41. Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit

description …continued

Bit Symbol Value Description Reset

value

Table 42. Wake-up configurat ion register (PDAWAKECFG, address 0x4004 8234) bit

description

Bit Symbol Value Description Reset

value

0 IRCOUT_PD IRC oscillator output wake-up configuration 0

0 Powered

1 Powered down

1 IRC_PD IRC oscillator power-down wake-up configu ra tion 0

0 Powered

1 Powered down

2 FLASH_PD Flash wake-up configuration 0

0 Powered

1 Powered down

3 BO D _PD BOD wa ke -u p co nfiguration 0

0 Powered

1 Powered down

4 ADC_PD ADC wake-up configuration 1

0 Powered

1 Powered down

5 SYSOSC_PD System oscillator wake-up configuration 1

0 Powered

1 Powered down

6 WDTOSC_PD Watchdog oscillator wake-up configuration 1

0 Powered

1 Powered down

7 SYSPLL_PD System PLL wake-up configuration 1

0 Powered

1 Powered down

8 - Reserved. Always write this bit as 1. 1

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.35 Power-down configuration register

The bits in the PDRUNCFG register control the power to the various analog blocks. This

immediately with the exception of the power-down signal to the IRC.

To avoid glitches when powering down the IRC, the IRC clock is automatically switched

off at a clean point. Therefore, for the IRC a delay is possible before the power-down st ate

takes effect.

By default, the IRC and flash memory are powered and running and the BOD circuit is

enabled.

Remark: Reserved bit s must be always written as indicated.

9 - Reserved. Always write this bit as 0. 0

10 - Reserved. Always write this bit as 1. 1

11 - Reserved. Always write this bit as 1. 1

12 - Reserved. Always write this bit as 0. 0

15:13 - Reserved. Always write these bits as 111. 111

31:16 - - Reserved -

Table 42. Wake-up configurat ion register (PDAWAKECFG, address 0x4004 8234) bit

description …continued

Bit Symbol Value Description Reset

value

Table 43. Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit

description

Bit Symbol Value Description Reset

value

0 IRCOUT_PD IRC oscillator output power-down 0

0 Powered

1 Powered down

1 IRC_PD IRC oscillator power-do wn 0

0 Powered

1 Powered down

2 FLASH_PD Flash power-down 0

0 Powered

1 Powered down

3 BO D _PD BOD pow e r-down 0

0 Powered

1 Powered down

4 ADC_PD ADC power-down 1

0 Powered

1 Powered down

5 SYSOSC_PD System oscillator power-down 1

0 Powered

1 Powered down

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.36 Device ID register

This device ID register is a read-only register and contains the part ID for each

LPC111x/LPC11Cxx part. This register is also read by the ISP/IAP commands

(Section 26.5.11).

Remark: This register return s the part ID for parts of the LPC1100, LPC1100C, and

LPC1100L series only. Use ISP/IAP to obtain the part ID for the LPC1100XL series.

The part IDs for the various parts are shown in the following list. Some parts have two

valid part IDs.

•LPC1110

–0x0A07 102B = LPC1110FD20

–0x1A07 102B = LPC1110FD20

•LPC1111

–0x0A16 D02B = LPC1111F DH2 0/00 2

–0x1A16 D02B = LPC1111F DH2 0/00 2

–0x041E 502B = LPC1111FHN33/101

–0x2516 D02B = LPC1111FHN33/101; LPC1111FHN33/102

–0x0416 502B = LPC1111FHN33/201

–0x2516 902B = LPC1111FHN33/201; LPC1111FHN33/202

•LPC1112

–0x0A24 902B = LPC1112FD20/102; LPC1112FDH20/102; LPC1112FDH28/102

–0x1A24 902B = LPC1112FD20/102; LPC1112FDH20/102; LPC1112FDH28/102

–0x042D 502B = LPC1112FHN33/101

–0x2524 D02B = LPC1112FHN33/101; LPC1112FHN33/102

6 WDTOSC_PD Watchdog oscillator power-down 1

0 Powered

1 Powered down

7 SYSPLL_PD System PLL power-down 1

0 Powered

1 Powered down

8 - Reserved. Always write this bit as 1. 1

9 - Reserved. Always write this bit as 0. 0

10 - Reserved. Always write this bit as 1. 1

11 - Reserved. Always write this bit as 1. 1

12 - Reserved. Always write this bit as 0. 0

15:13 - Reserved. Always write these bits as 11 1. 111

31:16 - - Reserved -

Table 43. Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit

description …continued

Bit Symbol Value Description Reset

value

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

–0x0425 502B = LPC1112FHN33/201

–0x2524 902B = LPC1112FHN33/201; LPC1112FHN33/202; LPC1112FHI33/202;

LPC1112FHN24/202

•LPC1113

–0x0434 502B = LPC1113FHN33/201

–0x2532 902B = LPC1113FHN33/201; LPC1113FHN33/202

–0x0434 102B = LPC1113FHN33/301; LPC1113FBD48/301

–0x2532 102B = LPC1113FHN33/301; LPC1113FHN33/302; LPC1113FBD48/301;

LPC1113FBD48/302

•LPC1114

–0x0A40 902B = LPC1114FDH28/102; LPC1114FN28/102

–0x1A40 902B = LPC1114FDH28/102; LPC1114FN28/102

–0x0444 502B = LPC1114FHN33/201

–0x2540 902B = LPC1114FHN33/201; LPC1114FHN33/202

–0x0444 102B = LPC1114FHN33/301; LPC1114FBD48/301

–0x2540 102B = LPC1114FHN33/301; LPC1114FHN33/302; LPC1114FHI33/302;

LPC1114FBD 48/3 01 ; LPC1114FBD48 /3 02 ; LPC 11D14FBD100 /30 2

•LPC11Cxx

–0x1440 102B = LPC11C14/FBD48/301

–0x1431 102B = LPC11C22/FBD48/301

–0x1430 102B = LPC11C24/FBD48/301

3.6 Reset

Reset has four sources on the LPC111x/LPC11Cxx: the RESET pin, Watchdog Reset,

Power-On Reset (POR), and Brown Out Detect (BOD). In addition, there is an ARM

software reset.

The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by an y source, once

the operating voltage attains a usable level, starts the IRC causing reset to remain

asserted until the external Reset is de-asserted, the oscillator is running, and the flash

controller has completed its initialization.

On the assertion of any reset source (ARM software reset, POR, BOD reset, External

reset, and Watchdog reset), the following processes are initiated:

1. The IRC starts up. After the IRC-start-up time (maximum of 6 s on power-up), the

IRC provides a stable clock output.

2. The flash is powere d up. This takes approximately 100 s. Th en the flash initialization

sequence is started.

Table 44. Device ID register (DEVICE_ID, address 0x4004 83F4) bit description

Bit Symbol Description Reset value

31:0 DEVICEID Part ID numbers for LPC111x/LPC11Cxx parts part-dependent

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3. The boot code in the ROM starts. The boot code performs the boot tasks and may

jump to the flash.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predeter mined values.

3.7 Start-up behavior

See Figure 9 for the start-up timing after reset. The IRC is the default clock at Reset and

provides a clean system clock shortly af ter the supply volt age reaches the th reshold value

of 1.8 V.

3.8 Brown-out detection

The LPC111x/LPC11Cxx includes three levels for monitori ng the volt age on the V DD pin. If

this voltage falls below on e of the four selected levels, the BOD asserts an interrupt signal

to the NVIC. This signal can be enabled for interrupt in the Interr upt Enable Register in the

NVIC in order to cause a CPU interrupt; if not, so ftware can monitor the signal by readin g

the NVIC status register (see Table 54). An additional four threshold levels can be

selected to cause a forced reset of the chip (see Table 33).

Fig 9. Start-up timing

valid threshold

= 1.8V

processor status

VDD

IRC status

internal reset

GND

80 μs 101 μs

boot time

user code

boot code

execution

finishes;

user code starts

IRC

starts

supply ramp-up

time

55 μs

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.9 Power management

The LPC111x/LPC11Cxx support a variety of power control features. In Active mode,

when the chip is running, power and clocks to selected peripherals can be optimized for

power consumption. In addition, there are three special modes of processor power

reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode.

Remark: The Debug mode is not supported in Sleep, Deep-sleep, or Deep power-down

modes.

3.9.1 Active mode

In Active mode, the ARM Cortex-M0 core and memor ies are clocked by the syste m clock,

and peripherals are clocked by the system clock or a dedicated peripheral clock.

The chip is in Active mode after reset and the default power configuration is determined

by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power

configuration can be changed during run time.

3.9.1.1 Power configuration in Active mode

Power consumption in Active mode is determined by the following configuration choices:

•The SYSAHBCLKCTRL register controls which memories and peripherals are

running (Table 21).

•The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and

the flash block) can be controlled at any time individually through the PDRUNCFG

•The clock source for the system clock can be selected from the IRC (default), the

system oscillator, or the watchdog oscillator (see Figure 8 and related registers).

•The system clock frequency can be selected by the SYSPLLCTRL (Table 10) and the

SYSAHBCLKDIV register (Table 20).

•Selected peripherals (UART, SPI0/1, WDT) use individual peripheral clocks with their

own clock dividers. The peripheral clocks can be shut down through the

correspond in g clo ck divider registers (Table 22 to Table 24).

3.9.2 Sleep mode

In Sleep mode, the system clock to the ARM Cort ex-M0 core is stoppe d, and execution o f

instructions is suspended until either a reset or an enabled interrupt occurs.

Peripheral functions, if selected to be clocke d in the SYSAHBCLKCTRL register, continue

operation during Sleep mode and may generate interrupts to cause the processor to

resume execution. Sleep mode eliminates dynamic power used by the processor itself,

memory systems and their related controllers, and internal buses. The processor state

and registers , perip he ra l reg ist er s, an d int er nal SRAM va lue s ar e ma in tained, and th e

logic levels of the pins remain static.

3.9.2.1 Power configuration in Sleep mode

Power consumption in Sleep mode is configured by the same settings as in Active mode:

•The clock remains running.

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•The system clock frequency remains the sa me as in Active mode, but the processor is

not clocked.

•Analog and digital peripherals are selected as in Active mode.

3.9.2.2 Programming Sleep mode

The following steps must be performed to enter Sleep mode:

1. The DPDEN bit in the PCON register must be set to zero (Table 49).

2. The SLEEPDEEP bit in the ARM Cortex-M0 SCR register must be set to zero, see

(Table 452).

3. Use the ARM Cortex-M0 Wait-For-Interrupt (WFI) instruction.

3.9.2.3 Wake-up from Sleep mode

Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the

processor or a reset occu rs. After wake-up due to an inte rr upt, the micr ocontr olle r returns

to its original power configuration defined by the contents of the PDRUNCFG and the

SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default

configuration in Active mode.

3.9.3 Deep-sleep mode

In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All

analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,

which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG

Deep-sleep mode eliminates all power used by the flash and analog peripherals and all

dynamic power used by the processor itself, memory systems and their related

controllers, and internal buses. The processor state and registers, peripheral registers,

and internal SRAM values are maintained, and the logic levels of the pins remain static.

3.9.3.1 Power configuration in Deep-sleep mode

Power consumption in Deep-sleep mode is determined by the Deep-sleep power

configuration setting in the PDSLEEPCFG (Table 41) register:

•The only clock source available in Deep-sleep mode is the watchdog oscillator. The

watchdog oscillator can be left running in Deep-sleep mode if required for

timer-controlled wake-up (see Section 3.10.3). All other clock sources (the IRC and

system oscillator) and the system PLL are shut down. The watchdog oscillator analog

output frequency must be set to the lowest value of its analog clock output (bits

FREQSEL in the WDTOSCCTRL = 0001, see Table 13).

•The BOD circuit can be left runn ing in Deep -slee p mode if r eq uired b y th e a pplication .

•If the watchdog oscillator is running in Deep-sleep mode, only the watchdog timer or

one of the general-purpose timers should be enabled in SYSAHBCLKCTRL register

to minimize power consumption.

3.9.3.2 Programming Deep-sleep mode

The following steps must be performed to enter Deep-sleep mode:

1. The DPDEN bit in the PCON register must be set to zero (Table 49).

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG (Table 41) 
register.
a. If a timer-controlled wake-up is needed, ensure that the watchdog oscillator is 
powered in the PDRUNCFG register and switch the clock source to WD oscillator 
in the MAINCLKSEL register (Table 18).
b. If no timer-controlled wake-up is needed and the watchdog oscillator is shut down, 
ensure that the IRC is powered in the PDRUNCFG register and switch the clock 
source to IRC in the MAINCLKSEL register (Table 18). This ensures that the 
system clock is shut down glitch-free.
3. Select the power configuration after wake-up in the PDAWAKECFG (Table 42) 
register.
4. If an external pin is used for wake-up, enable and clear the wake-up pin in the start 
logic registers (Table 36 to Table 39), and enable the start logic interrupt in the NVIC.
5. In the SYSAHBCLKCTRL register (Table 21), disable all peripherals except 
counter/timer or WDT if needed.
6. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 452).
7. Use the ARM WFI instruction.
3.9.3.3 Wake-up from Deep-sleep mode
The microcontroller can wake up from Deep-sleep mode in the following ways:
•Signal on an external pin. For this purpo se , pins PIO0_0 to PIO0_11 and PIO1_0 can 
be enabled as input s to the st art logic. The st art logic does no t require any clocks and  
generates the interrupt if enabled in the NVIC to wake up from Deep-sleep mode.
•Input signal to the st a rt log ic cre ated by  a match event o n one of the g ene ra l purpo se  
timer external match outputs. The pin hold ing the timer match function must be 
enabled as start logic input in the NVIC, the corresponding timer must be enabled in 
the SYSAHBCLKCTRL register, and the watchdog oscillator must be running in 
Deep-sleep mode (for details see Section 3.10.3).
•Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the 
PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL 
register (Table 33).
•Reset from the watchdog timer. In this case, the watchdog oscillator must be running 
in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in 
the SYSAHBCLKCTRL register.
•A reset signal from the external RESET pin.
Remark: If the watchdog oscillator is running in Deep-sleep mode, its frequency 
determines the wake-up time causing the wake-up time to be longer than waking up with 
the IRC.
3.9.4 Deep power-down mode
In Deep power-down mode, power and clocks are shut off to the entire chip with the 
exception of the WAKEUP pin.
During Deep po wer-do wn  mo de ,  th e con tents of  the SRAM a nd  re gisters a re  no t  retained 
except for a small amount of data which can be stored in the five 32-bit general purpose 
registers of the PMU block.

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All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin.

3.9.4.1 Power configuration in Deep power-down mode

Deep power-d o wn m od e has no con fig ur at io n options. All clocks, the core, and all

peripherals are powered down. Only the WAKEUP pin is powered.

3.9.4.2 Programming Deep power-down mode

The following steps must be performed to enter Deep power-down mode:

1. Write one to the DPDEN bit in the PCON register (see Table 49).

2. Store data to be retained in the general purpose registers (Table 50).

3. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 452).

4. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in

the PDRUNCFG register before entering Deep power-down mode.

Remark: This step is part dependent. See Section 3.1 for part specific details.

5. Use the ARM WFI instruction.

Remark: The WAKEUP pin must be pulled HIGH externally before entering Deep

power-down mode.

3.9.4.3 Wake-up from Deep power-down mode

Pulling the W AKEUP pin LOW wakes up the LPC1 11x/LPC1 1Cxx from Deep power-down,

and the chip goes through the entire reset process (Section 3.6). The minimum pulse

width for the HIGH-to-LOW transition on the WAKEUP pin is 50 ns.

Follow these steps to wake up the chip from Deep power-down mode:

1. A wake-up signal is generated when a HIGH-to-LOW transition occurs externally on

the WAKEUP pin with a pulse length of at least 50 ns while the part is in Deep

power-down mode.

–The PMU will turn on the on-chip volt age regulator. When the core voltage reaches

the power-on-reset (POR) trip point, a system reset will be triggered and the chip

re-boots.

–All registers except the GPREG0 to GPREG4and PCON will be in their reset state.

2. Once the chip has booted, read the deep power-down flag in the PCON register

(Table 49) to verify that the reset was caused by a wake-up event from Deep

power-down.

3. Clear the deep power-down flag in the PCON register (Table 49).

4. (Optional) Read the stored data in the general purpose registers (Table 50 and

Table 51).

5. Set up the PMU for th e ne xt De ep pow er -do wn cycle.

Remark: The RESET pin has no functionality in Deep power-down mode.

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.10 Deep-sleep mode details

3.10.1 IRC oscillator

The IRC is the only oscillator on the LPC111x/LPC11Cxx that can always shut down

glitch-free. Therefore it is recommended that the user switches the clock source to IRC

before the chip enters Deep-sleep mode.

3.10.2 Start logic

The Deep-sleep mode is exited when the start logic indicates an interrupt to the ARM

core. The port pins PIO0_0 to PIO0_11 and PIO1_0 are connected to the start logic an d

serve as wake-up pins. The user must program the start logic registers for each input to

set the appropriate edge polarity for the corresponding wake-up event. Furthermore, the

interrupts corresponding to each input must be enabled in the NVIC. Interrupts 0 to 12 in

the NVIC correspond to 13 PIO pins (see Section 3.5.29).

The start logic does not require a clock to run because it uses the input signals on the

enabled pins to generate a clock edge when enabled. Therefore, the start logic signals

should be cleared (see Table 38) before use .

The start logic can also be used in Active mode to provide a vectored interrupt using the

LPC111x/LPC11Cxx’s input pins.

3.10.3 Using the general purpose counter/timers to create a self-wake-up

event

If enabled in Deep-sleep mode through the SYSAHBCLKCFG register, the counter/timers

can count clock cycles of the watchdog oscillator and create a match event when the

number of cycles equals a preset match value. The match event causes the

corresponding match output pin to go HIGH, LOW, or toggle. The state of the match

output pin is also monitored by the st art logic and can trigge r a wake-up interrupt if that pin

is enabled in the NVIC and the star t logic trigger is configured accordingly in the st art logic

edge control register (see Table 36).

The following steps must be performed to configure the counter/timer and create a timed

Deep-sleep self-wake-up event:

1. Configure the port pin as match output in the IOCONFIG block. Select from pins

PIO0_1 or PIO0_8 to PIO0_11, which are inputs to the start logic and also hold a

match output function.

2. In the corresponding counter/ timer, set the match value, and configure the match

output for the selected pin.

3. Select the watchdog oscillator to run in Deep-sleep mode in the PDSLEEPCFG

4. Switch the clock source to the watchdog oscillator in the MAINCLKSEL register

(Table 18) and ensure the watchdog oscillator is powered in the PDRUNCFG register.

5. Enable the pin, configure its edge detect function, and reset the start logic in the start

logic registers (Table 36 to Table 39), and enable the interrupt in the NVIC.

6. Disable all other peripherals in the SYSAHBCLKCTRL register.

7. Ensure that the DPDEN bit in the PCON register is set to zero (Table 49).

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8. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 452).

9. Start the counter/timer.

10. Use the ARM WFI instruction to enter Deep-sleep mode.

3.11 System PLL functional description

The LPC111x/LPC11Cxx uses the system PLL to create the clocks for the core and

peripherals.

The block diagram of this PLL is shown in Figure 10. The input frequency range is 10 MHz

to 25 MHz. The input c loc k is fed dir ec tly to th e Pha se -Fr eq ue n cy Det ec to r (PF D). This

block compares the phase and frequency of its inputs, and generates a control signal

when phase and/ or frequency do not match. The loop filter filters these control signals

and drives the current controlled oscillator (CCO), which generates the main clock and

optionally two additional phases. The CCO frequency range is 156 MHz to

320 MHz.These clocks are either divided by 2P by the programmable post divider to

create the output clock(s), or are sent directly to the output(s). The main output clock is

then divided by M by the programmable feedback divider to generate the feedback clock.

The output signal of the phase-frequency detector is also monitored by the lock detector,

to signal when the PLL has locked on to the input clock.

Remark: The divider values for P and M must be selected so that the PLL output clock

frequency FCLKOUT is lower than 100 MHz.

3.11.1 Lock detector

The lock detector measures the phase difference between the rising edges of the input

and feedback clocks. Only when this difference is smaller than the so called “lock

criterion” for more than eight consecutive input clock periods, the lock output switches

from low to high. A single too large phase difference immediately resets the counter and

causes the lock sign al to dro p (if it was high ). Re qu irin g eig h t phase me as ur em e nts in a

Fig 10. System PLL bl oc k diag ram

LOCK

DETECT

PFD

FCLKOUT

analog section

/2P

PSEL<1:0>

MSEL<4:0>

irc_osc_clk

sys_osc_clk

SYSPLLCLKSEL

FCLKIN FCCO

LOCK

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row to be below a certain figure ensures that the lock detector will not indicate lock until

both the phase and freq uency of the input and feedb ack clocks are very well aligned. This

effectively prevents false lock indications, and thus ensures a glitch free lock signal.

3.11.2 Power-down control

To reduce the power co nsumption when the PLL clock is not needed, a Power- down

mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bits to one

in the Power-down configuration register (Table 43). In this mode, the internal current

reference will be turned off, the oscillator and the phase-frequency detector will be

stopped and the dividers will enter a reset state. While in Power-down mode, the lock

output will be low to indicate that the PLL is not in lock. When the Power-down mode is

terminated by setting the SYSPLL_PD bits to zero, the PLL will resume its normal

operation and will make the lock signal high once it has regained lock on the input clock.

3.11.3 Divider ratio programming

Post divider

The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two

times the value of P selected by PSEL bits as shown in Table 10. Th is gu ar an te e s an

output clock with a 50% duty cycle.

Feedback divider

The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio

between the PLL’s outp ut clock and the input clock is the decim al value on MSEL bits pl us

one, as specified in Table 10.

Changing the divider values

Changing the divider ratio while the PLL is running is not re commended. As there is no

way to synchronize the change of the MSEL and PSEL values with the dividers, the risk

exists that the counter will read in an undefined value, which could lead to unwanted

spikes or drops in the frequency of the output clo ck. The recommended way of changing

between divider settings is to power down the PLL, ad just the divid er settings and the n let

the PLL start up again.

3.11.4 Frequency selection

The PLL frequency equations use the following parameters (also see Figure 8):

Table 45. PLL frequency parameters

Parameter System PLL

FCLKIN Frequency of sys_pllclkin (input clock to the system PLL) from the

SYSPLLCLKSEL multiplexer (see Section 3.5.9).

FCCO Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz.

FCLKOUT Frequency of sys_pllclkout. FCLKOUT must be < 100 MHz.

P System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see Section 3.5.3).

M System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see

Section 3.5.3).

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3.11.4.1 Normal mode

In normal mode the post divider is enabled, giving a 50% duty cycle clock with the

following frequency relations:

(1)

To select the appropriate va lues for M and P, it is recommended to follow these steps:

1. Specify the input clock frequency FCLKIN.

2. Calculat e M to ob tain the desired output frequency FCLKOUT with

M = FCLKOUT / FCLKIN.

3. Find a value so that FCCO = 2  P  FCLKOUT.

4. Verify that all frequencies and divider values conform to the limits specified in

Table 10.

5. Ensure that FCLKOUT < 100 MHz.

Table 46 shows how to configure the PLL for a 12 MHz crystal oscillator using the

SYSPLLCTRL register (Table 10). The main clock is equivalent to the system clock if the

system clock divider SYSAHBCLKDIV is set to one (see Table 20).

3.11.4.2 Power-down mode

In this mode, the internal current reference is turned off, the oscillator and the

phase-frequency detector are stopped, and the dividers enter a reset state. While in

Power-down mode, the lock ou tput is be LOW to indicate that th e PLL is not in lock. When

the Power-down mode is terminated by setting the SYSPLL_PD bit to zero in the

Power-down configuration register (Table 43), the PLL resumes its normal operation and

asserts the lock signal HIGH once it has regained lock on the input clock.

3.12 Flash memory access

Depending on the system clock freque ncy, access to the flash memory can be configured

with various access times by writing to the FLASHCFG register at address 0x4003 C010.

This register is part of the flash configuration block (see Figure 6).

Remark: Improper setting of this register may result in incorrect operation of the

LPC111x/LPC11Cxx flash memory.

Table 46. PLL configuration examples

PLL input

clock

sys_pllclkin

(FCLKIN)

Main clock

(FCLKOUT) MSEL bits

Table 10 M divider

value PSEL bits

Table 10 P divider

value FCCO

frequency

12 MHz 48 MHz 00011 4 01 2 192 MHz

12 MHz 36 MHz 00010 3 10 4 288 MHz

12 MHz 24 MHz 00001 2 10 4 192 MHz

FCLKOUT M FCLKINFCCO2P==

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

Table 47. Flash configuration register (F L ASHCFG, address 0x4003 C010) bit description

Bit Symbol Valu

eDescription Reset

value

1:0 FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the

number of system clocks used for flash access. 10

00 1 system clock flash access time (for system clock

frequencies of up to 20 MHz).

01 2 system clocks flash access time (for system clock

frequencies of up to 40 MHz).

10 3 system clocks flash access time (for system clock

frequencies of up to 50 MHz).

11 Reserved.

31:2 - - Reserved. User software must not change the value of

these bits. Bit s 31:2 must be written back exactly as read.-

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4.1 How to read this chapter

Remark: For parts LPC11(D)1x/102/202/302, also refer to Chapter 5 for power control.

4.2 Introduction

The PMU controls the Deep p ower-down mode. Four gene ral purpose register in the PMU

can be used to retain data during Deep power-down mode.

4.3 Register description

4.3.1 Power control register

The power control register selects whether one of the ARM Cortex-M0 controlled

power-down modes (Sleep mod e or Deep-sle ep m ode) o r the Deep power -d own mode is

entered and provides the flags for Sleep or Deep-sleep modes and Deep power-down

modes respectively. See Section 3.9 for details on how to enter the power-down modes.

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Chapter 4: LPC111x/LPC11Cxx Power Monitor Unit (PMU)

Rev. 11 — 26 July 2012 User manual

Table 48. Register overview: PMU (base address 0x4003 8000 )

Name Access Address

offset Description Reset

value

PCON R/W 0x000 Power control register 0x0

GPREG0 R/W 0x004 General purpose register 0 0x0

GPREG1 R/W 0x008 General purpose register 1 0x0

GPREG2 R/W 0x00C General purpose register 2 0x0

GPREG3 R/W 0x010 General purpose register 3 0x0

GPREG4 R/W 0x014 General purpose register 4 0x0

Table 49. Power control register (PCON, address 0x4003 800 0) bit description

Bit Symbol Value Description Reset

value

0 - - Reserved. Do not write 1 to this bit. 0x0

1 DPDEN Deep power-down mode enable 0

0 ARM WFI will enter Sleep or Deep-sleep mode (clock to

ARM Cortex-M0 core turned off).

1 ARM WF I will enter Deep-power down mode (ARM

Cortex-M0 core powered-down).

7:2 - - Reserved. Do not write ones to this bit. 0x0

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Chapter 4: LPC111x/LPC11Cxx Power Monitor Unit (PMU)

4.3.2 General purpose registers 0 to 3

The general purpose registers retain data through the Deep power-down mode when

power is still applied to the VDD pin but the chip has entered Deep power-do wn mode.

Only a “cold” boot when all power has been completely removed from the chip will reset

the general purp o se re gis te rs.

4.3.3 General purpose register 4

The general purpose register 4 retains data through the Deep power-down mode when

power is still applied to the VDD pin but the chip has entered Deep power-do wn mode.

Only a “cold” boot, when all power has been completely removed from the chip, will reset

the general purp o se re gis te rs.

Remark: If there is a possibility that the external voltage applied on pin VDD drops below

2.2 V during Deep power-down, the hysteresis of the WAKEUP input pin has to be

disabled in this register before entering Deep power-down mode in order for the chip to

wake up.

8 SLEEPFLAG Sleep mode flag 0

0 R ead: No power-down mode entered.

LPC111x/LPC11Cxx is in Active mode.

Write: No effect.

1 R ead: Sleep/Deep-sleep or Deep power-down mode

entered.

Write: Writing a 1 clears the SLEEPFLAG bit to 0.

10:9 - - Reserved. Do not write ones to this bit. 0x0

11 DPDFLAG Deep power-down flag 0x0

0 R ead: Deep power-down mode not entered.

Write: No effect. 0x0

1 Read: Deep power-down mode entered.

Write: Clear the Deep power-down flag. 0x0

31:12 - - Reserved. Do not write ones to this bit. 0x0

Table 49. Power control register (PCON, address 0x4003 800 0) bit description …continued

Bit Symbol Value Description Reset

value

Table 50. General purpose registers 0 to 3 (GPREG0 - GPREG3, address 0x4003 8004 to

0x4003 8010) bit description

Bit Symbol Description Reset

value

31:0 GPDATA Data retained during Deep power-down mode. 0x0

Table 51. General purpose register 4 (GPREG4, addres s 0x4003 8014) bit description

Bit Symbol Value Description Reset

value

9:0 - - Reserved. Do not write ones to this bit. 0x0

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Chapter 4: LPC111x/LPC11Cxx Power Monitor Unit (PMU)

4.4 Functional description

For details of entering and exiting Deep power-down mode, see Section 3.9.4.

10 WAKEUPHYS WAKEUP pin hysteresis enable 0x0

1 Hysteresis for WAKEUP pin enabled.

0 Hyster esis for WAKUP pin disabled.

31:11 GPDATA Data retained during Deep power-dow n mode. 0x0

Table 51. General purpose register 4 (GPREG4, addres s 0x4003 8014) bit description

Bit Symbol Value Description Reset

value

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5.1 How to read this chapter

The power profiles are available for parts LPC11(D)1x/102/202/302 only (LPC1100L

series).

5.2 Features

•Includes ROM-based application services

•Power Management services

•Clocking services

5.3 Description

The API calls to the ROM are performed by executing functions which are pointed by a

pointer within the ROM Driver Table. Figure 11 shows the pointer structure used to call the

Power Profiles API.

UM10398

Chapter 5: LPC111x/LPC11Cxx Power profiles

Rev. 11 — 26 July 2012 User manual

Fig 11. Power profiles pointer stru ct ure

Ptr to ROM Driver table

Ptr to Device Table 2

Ptr to Device Table 1

Ptr to Device Table 0

…

Ptr to Device Table n

set_pll

set_power

Ptr to Function 2

Ptr to Function 0

Ptr to Function 1

…

Ptr to Function n

Power API function table

Device n

ROM Driver Table

0x1FFF 2004

0x1FFF 1FF8

0x1FFF 1FFC

0x1FFF 2000

0x1FFF 2004

Ptr to PowerAPI Table

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Chapter 5: LPC111x/LPC11Cxx Power profiles

5.4 Definitions

The following elements have to be defined in an application that uses the power profiles:

typedef struct _PWRD {

void (*set_pll)(unsigned int cmd[], unsigned int resp[]);

void (*set_power)(unsigned int cmd[], unsigned int resp[]);

} PWRD;

typedef struct _ROM {

const PWRD * pWRD;

} ROM;

ROM ** rom = (ROM **) (0x1FFF1FF8 + 3 * sizeof(ROM**));

unsigned int command[4], result[2];

5.5 Clocking routine

5.5.1 set_pll

This routine sets up the system PLL according to the calling arguments. If the expected

clock can be obtained by simply dividing the system PLL input, set_pll bypasses the PLL

to lower system power consumption.

Remark: Before this routine is invoked, the PLL clock source (IRC/system oscillator) must

be selected (Table 16), the main clock source must be set to the input clock to the system

PLL (Table 18) and the system/AHB clock divider must be set to 1 (Table 20).

set_pll attempts to find a PLL setup that matches the calling parameters. Once a

combination of a feedback divider value (SYSPLLCTRL, M), a post divider ratio

(SYSPLLCTRL, P) and the system/AHB clock divider (SYSAHBCLKDIV) is found, set_pll

applies the selected values and switches the main clock source selection to the system

PLL clock out (if necessary).

Fig 12. LPC111x/102/202/302 clock configuration for power API use

SYS PLL

irc_osc_clk

sys_osc_clk

irc_osc_clk

wdt_osc_clk

MAINCLKSEL

SYSPLLCLKSEL

CLOCK

DIVIDER

SYSAHBCLKCTRL[1]

(ROM enable)

SYSAHBCLKCTRL[18]

(SPI1 enable)

CLOCK

DIVIDER Peripherals

main clock system clock

sys_pllclkin

sys_pllclkout

ARM

CORTEX-M0

ROM

SPI1

SYSAHBCLKDIV

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The routine returns a result code that indicates if the system PLL was successfully set

(PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong).

The current system frequency value is also returned. The application should use this

information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or

clockout).

The following definitions are needed when making set_pll power routine calls:

/* set_pll mode options */

#define CPU_FREQ_EQU 0

#define CPU_FREQ_LTE 1

#define CPU_FREQ_GTE 2

#define CPU_FREQ_APPROX 3

/* set_pll result0 options */

#define PLL_CMD_SUCCESS 0

#define PLL_INVALID_FREQ 1

#define PLL_INVALID_MODE 2

#define PLL_FREQ_NOT_FOUND 3

#define PLL_NOT_LOCKED 4

For a simplified clock configuration scheme see Figure 12. For more details see Figure 8.

5.5.1.1 Param0: system PLL input frequency and Param1: expected system clock

set_pll looks for a setup in which the system PLL clo ck does n ot exceed 50 MH z. It e asily

finds a solution when the ratio between the expected system clock and the system PLL

input frequency is an integer value, but it can also find solutions in other cases.

The system PLL input frequency (Param0) must be between 10000 to 25000 kHz (10

MHz to 25 MHz) inclusive. The expected system clock (Param1) must be between 1 and

50000 kHz inclusive. If either of these requirements is not met, set_pll returns

PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged.

5.5.1.2 Param2: mode

The first priority of set_pll is to find a setup that generates the system clock at exactly the

rate specified in Param1. If it is unlikely that an exact match can be found , input parameter

mode (Param2) should be used to specify if the actual system clock can be less than or

equal, greater than or equal or ap prox imately the value specified as the expected system

clock (Param1).

A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the

frequency requ e s ted in Param1.

Table 52. set_pll routine

Routine set_pll

Input Param0: system PLL input frequency (in kHz)

Param1: expected system clock (in kHz)

Param2: mode (CPU_FREQ_EQU, CPU_FREQ_LTE, CPU_FREQ_GTE,

CPU_FREQ_APPROX)

Param3: system PLL lock time-out

Result Result0: PLL_CMD_SUCCESS | PLL_INVALID_FREQ | PLL_INVALID_MODE |

PLL_FREQ_NOT_FOUND | PLL_NOT_LOCKED

Result1: system clock (in kHz)

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Chapter 5: LPC111x/LPC11Cxx Power profiles

CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such

as overall current consumption and/or power budget reasons).

CPU_FREQ_GTE helps applications that need a minimum level of CPU processing

capabilities.

CPU_FREQ_APPROX results in a system clock that is as close as possible to the

requested value (it may be greater than or less than the requested value).

If an illegal mode is specified, set_pll returns PLL_INVALID_MODE. If the expected

system clock is out of the range supported by this routine, set_pll returns

PLL_FREQ_NOT_FOUND. In these cases the current PLL setting is not changed and

Param0 is returned as Result1.

5.5.1.3 Param3: system PLL lock time-out

It should take no more than 100 s for the system PLL to lock if a valid configuration is

selected. If Param3 is zero, set_pll will wait indefinitely for the PLL to lock. A non-zero

value indicates how many times the code will check for a successful PLL lock event

before it returns PLL_NOT_LOCKED. In this case the PLL settings are unchanged and

Param0 is returned as Result1.

Remark: The time it takes the PLL to lock depends on the selected PLL input clock

source (IRC/system oscillator) and its characteristics. The selected source can

experience more or less jitter depending on the operating conditions such as power

supply and/or ambient temperature. This is why it is suggested that when a good known

clock source is used and a PLL_NOT_LOCKED response is received, the set_pll routine

should be invoked several times before declaring the selected PLL clock source invalid.

Hint: setting Param3 equal to the system PLL frequency [Hz] divided by 10000 will

provide more than enough PLL lock-polling cycles.

5.5.1.4 Code examples

The following examples illustrate some of the features of set_pll discussed above.

5.5.1.4.1 Invalid frequency (device maximum clock rate exceeded)

command[0] = 12000;

command[1] = 60000;

command[2] = CPU_FREQ_EQU;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock and a system clock of exactly

60 MHz. The application was ready to infinitely wait for the PLL to lock. But the expected

system clock of 60 MHz exceed s th e ma xim um of 50 MHz. Th er ef or e set_pll returns

PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing the PLL

settings.

5.5.1.4.2 Invalid frequency selection (system clock divider restrictions)

command[0] = 12000;

command[1] = 40;

command[2] = CPU_FREQ_LTE;

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command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of no more than

40 kHz and no time-out while waiting for the PLL to lock. Since the maximum divider value

for the system clock is 255 and running at 40 kHz would need a divide by value of 300,

set_pll returns PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing

the PLL settings.

5.5.1.4.3 Exact solution cannot be found (PLL)

command[0] = 12000;

command[1] = 25000;

command[2] = CPU_FREQ_EQU;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock and a system clock of exactly

25 MHz. The application was ready to infinitely wait for the PLL to lock. Since there is no

valid PLL setup within earlier mentioned restrictions, set_pll returns

PLL_FREQ_NOT_FOUND in result[0] and 12000 in result[1] without changing the PLL

settings.

5.5.1.4.4 System clock less than or equal to the expected value

command[0] = 12000;

command[1] = 25000;

command[2] = CPU_FREQ_LTE;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of no more than

25 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and

24000 in result[1]. The new system clock is 24 MHz.

5.5.1.4.5 System clock greater than or equal to the expected value

command[0] = 12000;

command[1] = 25000;

command[2] = CPU_FREQ_GTE;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of at least 25 MHz

and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 36000 in

result[1]. The new system clock is 36 MHz.

5.5.1.4.6 System clock approximately equal to the expected value

command[0] = 12000;

command[1] = 16500;

command[2] = CPU_FREQ_APPROX;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

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The above code specifies a 12 MHz PLL input clock, a system clock of approximately

16.5 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and

16000 in result[1]. The new system clock is 16 MHz.

5.6 Power routine

5.6.1 set_power

This routine configures the device’s internal power control settings according to the calling

argument s. T he goa l is to reduce active pow er consumption while maint aining the feature

of interest to the application close to its optimum.

Remark: The set_powe r routine was designed for syste ms employing the configur ation of

SYSAHBCLKDIV = 1 (System clock divider register, see Table 20 and Figure 12). Using

this routine in an application with the system cloc k divider not equal to 1 might no t improve

microcontroller’s performance as much as in setups when the main clock and the system

clock are running at th e sa me rat e.

set_power returns a result code that reports whether the power setting was successfully

changed or not.

Fig 13. Powe r profi le s usa ge

using power profiles and

changing system clock

current_clock,

new_clock , new_mode

use power routine call

to change mode to

DEFAULT

use either clocking routine call or

custom code to change system clock

from current_clock to new _clock

use power routine call

to change mode to

new_mode

end

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The following definitions are needed for set_power routine calls:

/* set_power mode options */

#define PWR_DEFAULT 0

#define PWR_CPU_PERFORMANCE 1

#define PWR_EFFICIENCY 2

#define PWR_LOW_CURRENT 3

/* set_power result0 options */

#define PWR_CMD_SUCCESS 0

#define PWR_INVALID_FREQ 1

#define PWR_INVALID_MODE 2

For a simplified clock configuration scheme see Figure 12. For more details see Figure 8.

5.6.1.1 Param0: main clock

The main clock is the clock rate the microcontroller uses to source the system’s and the

peripherals’ clock. It is configured by either a successful execution of the clocking routine

call or a similar code provided by the user. This operand must be an integer between 1 to

50 MHz inclusive. If a value out of this range is supplied, set_power returns

PWR_INVALID_FREQ and does not change the power control system.

5.6.1.2 Param1: mode

The input parameter mod e (Param1) specifies one of four available power settings. If an

illegal selection is provided, set_power returns PWR_INVALID_MODE and does not

change the power control system.

PWR_DEFAULT keeps the device in a baseline power setting similar to its reset state.

PWR_CPU_PERFORMANCE configures the microcontroller so that it can provide more

processing capability to the application. CPU performance is 30% better than the default

option.

PWR_EFFICIENCY setting was designed to find a balance between active current and

the CPU’s ability to execute code and process data. In this mode the device outperforms

the default mode both in terms of providing higher CPU performance and lowering active

current.

PWR_LOW_CURRENT is intended for those solutions that focus on lowering power

consumption rather than CPU performance.

5.6.1.3 Param2: system clock

The system clock is the clock rate at which the microcontroller core is running when

set_power is called. This parameter is an integer between from 1 and 50 MHz inclusive.

Table 53. set_power routine

Routine set_power

Input Param0: main clock (in MHz)

Param1: mode (PWR_DEFAULT, PWR_CPU_PERFORMANCE, PWR_

EFFICIENCY, PWR_LOW_CURRENT)

Param2: system clock (in MHz)

Result Result0: PWR_CMD_SUCCESS | PWR_INVALID_FREQ |

PWR_INVALID_MODE

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5.6.1.4 Code examples

The following examples illustrate some of the set_power featur es discussed abo ve.

5.6.1.4.1 Invalid frequency (device maximum clock rate exceeded)

command[0] = 60;

command[1] = PWR_CPU_PERFORMANCE;

command[2] = 60;

(*rom)->pWRD->set_power(command, result);

The above setup would be used in a system running at the main and system clock of

60 MHz, with a need for maximum CPU processing power. Since the specified 60 MHz

clock is above the 50 MHz maximum, set_power returns PWR_INVALID_FREQ in

result[0] without changing anything in the existing p ower setup.

5.6.1.4.2 An applicable power setup

command[0] = 24;

command[1] = PWR_CPU_EFFICIENCY;

command[2] = 24;

(*rom)->pWRD->set_power(command, result);

The above code specifies that an application is running at the ma in and system clock of

24 M Hz with emphasis on efficiency. set_power returns PWR_CMD_SUCCESS in

result[0] after config uring the microcontroller’s internal power control fe atures.

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6.1 How to read this chapter

The C_CAN controller interrupt is available on parts LPC11Cxx only.

6.2 Introduction

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

6.3 Features

•Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0

•Tightly coupled interrupt controller provides low interrupt latency

•Controls system exceptions and peripheral interrupts

•The NVIC supports 32 vectored interrupts

•4 programmable interrupt priority levels with hardware priority level masking

•Software interrupt generation

6.4 Interrupt sources

Table 54 lists the interrupt sources for each peripheral fu nction. Each peripheral device

may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may

represent more than one interrupt source. There is no significance or priority about what

line is connected where, except for certain standards from ARM.

See Section 28.6.2 for the NVIC register bit descriptions.

UM10398

Chapter 6: LPC111x/LPC11Cxx Nested Vectored Interrupt

Controller (NVIC)

Rev. 11 — 26 July 2012 User manual

Table 54. Connection of interrupt sources to the Vectored Interrupt Controller

Exception

Number Vector

Offset Function Flag(s)

12 to 0 start logic wake-up

interrupts Each interrupt is connected to a PIO input pin serving

as wake-up pin from Deep-sleep mode; Interrupt 0 to

11 correspond to PIO0_0 to PIO0_11 and interrupt

12 corresponds to PIO1_0; see Section 3.5.29.

13 C_CAN C_CAN interrupt

14 SPI/SSP1 Tx FIFO half empty

Rx FIFO half full

Rx Timeout

Rx Overrun

15 I2C SI (state change)

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Chapter 6: LPC111x/LPC11Cxx Nested Vectored Interrupt Controller

16 CT16B0 Match 0 - 2

Capture 0

17 CT16B1 Match 0 - 1

Capture 0

18 CT32B0 Match 0 - 3

Capture 0

19 CT32B1 Match 0 - 3

Capture 0

20 SPI/SSP0 Tx FIFO half empty

Rx FIFO half full

Rx Timeout

Rx Overrun

21 UART Rx Line Status (RLS)

Transmit Holding Register Empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

End of Auto-Baud (ABEO)

Auto-Baud Time-Out (ABTO)

22 - Reserved

23 - Reserved

24 ADC A/D Converter end of con ver sion

25 WDT Watchdog interrupt (WDINT)

26 BOD Brown-out detect

27 - Reserved

28 PIO_3 GPIO interrupt status of port 3

29 PIO_2 GPIO interrupt status of port 2

30 PIO_1 GPIO interrupt status of port 1

31 PIO_0 GPIO interrupt status of port 0

Table 54. Connection of interrupt sources to the Vectored Interrupt Controller

Exception

Number Vector

Offset Function Flag(s)

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7.1 How to read this chapter

Remark: This chapter applies to parts in the following series (see Table 1):

•LPC1100

•LPC1100L

•LPC1100C

•LPC11D14

Pin configuration

The implementation of the I/O configuration registers varies for different

LPC111x/LPC11Cxx parts and packages. Table 56 shows which IOCON registers are

used on the different packages.

C_CAN pins

•For the LPC11C12/C14, functions PIO3_4 and PIO3_5 are not available. Instead, two

pins are dedicated to the C_CAN receive and transmit functions (see Table 56)

without pull-up or pull-down resistors. The C_CAN pins have no programmable pin

configuration.

•For the LPC11C22/C24, pins PIO1_9, PIO2_4, PIO2 _5, and PIO2_9 are not available

and are replaced by the on-chip CAN transceiver pins. The CAN transceiver pins

have no programmable pin configuration.

Pseudo open-drain function

For the LPC11(D)1x/102/202/302, a p seudo open-drain mode can be selected in the

IOCON registers for each digital pin except the I2C pins (see Figure 14). The open-drain

mode is not available for the LPC111x/101/201/301 parts.

Pull-up level

If the pull-up resistor is enabled (default), all non-I2C pins are pulled up to 2.6 V for

LPC111x/101/201/301 parts and pulled up to 3.3 V for LPC11Cxx parts a nd

LPC111x/102/202/302 (VDD = 3.3 V).

7.2 Features

The I/O configura tio n re gis te rs co nt ro l the el ectrical characteristics of the pads. The

following features are programmable:

•Pin function.

•Internal pull-up/pull-down resistor or bus keeper function.

•Hysteresis.

•Analog input or digital mode for pads hosting the ADC inputs.

•I2C mode for pads hosting the I2C-bus function .

UM10398

Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O

configuration (IOCONFIG)

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

•Pseudo open-drain mode for non-I2C pins (see Section 7.1 for part specific details).

7.3 General description

The IOCON regis ter s con trol th e fu nct i on (GPI O or peripheral function), the input mode,

and the hysteresis of all PIOn_m pins. In addition, the I2C-bus pins can be configured for

different I2C-bus modes. If a pin is used as input pin for the ADC, an analog input mode

can be selected.

7.3.1 Pin function

The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a

peripheral function. If the pins are GPIO pins, the GPIOnDIR registers determine whether

the pin is configured as an input or output (see Section 12.3.2). For any peripheral

function, the pin direction is controlled automatically depending on the pin’s functionality.

The GPIOnD IR re gis ter s ha ve no effect for peripheral functions.

For open-drain mode, see Section 7.1.

Fig 14. S tandard I/O pin configuration

ESD

strong

pull-up

strong

pull-down

weak

pull-up

weak

pull-down

open-drain enable

output enable

repeater mode

enable

pull-up enable

pull-down enable

data output

data input

analog input

select analog input

002aah159

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.3.2 Pin mode

The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down

resistors for each pin or select the repeater mode.

The possible on-chip r esistor configurations are pull- up enabled, pull-down enabled, or no

pull-up/pull-down. The default value is pull-up enabled. See Section 7.1 for part specific

details.

The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables

the pull-down resist or if the pin is at a logic LO W. This causes the pin to retain its last

known state if it is configured as an input and is not driven exte rnally. The state retention is

not applicable to the Deep power-down mode. Repeater mode may typically be used to

prevent a pin from floating (and potentially using significant power if it floats to an

indeterminate state) if it is temporarily not driven.

7.3.3 Hysteresis

The input buffer for digital functions can be con fig ur ed with hy ste re sis or as pla i n buffer

through the IOCON registers (see the LPC111x and LPC11Cx data sheets for details).

If the external pad supply voltage VDD is between 2.5 V and 3.6 V, the hysteresis buffer

can be enabled or disabled. If VDD is below 2.5 V, the hysteresis buffer must be disabled

to use the pin in input mode.

7.3.4 A/D-mode

In A/D-mode, the digital receiver is disconnected to obtain an accurate input voltage for

analog-to-digital conversions. This mode can be selected in those IOCON registers that

control pins with an analog function. If A/D mode is selected, Hysteresis and Pin mode

settings have no effect.

For pins without analog functions, the A/D-mode setting has no effect.

7.3.5 I2C mode

If the I2C function is selected by the FUNC bits of registers IOCON_PIO0_4 (Table 67)

and IOCON_PIO0_5 (Table 68), then the I2C-bus pins can be configured for different

I2C-modes:

•Standard mode/Fast-mode I2C with input glitch filter (this includes an open-drain

output according to the I2C-bus specification).

•Fast-mode Plus with input glitch filter (this includes an open-dr ain outpu t acco rding to

the I2C-bus specification). In this mode, the pins function as high-current sinks.

•Standard open-drain I/O functionality without input filter.

Remark: Either Standard mode/Fast-mode I2C or Standard I/O functionality should be

selected if the pin is used as GPIO pin.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration
7.3.6 Open-drain Mode
When output is selected, either by selecting a special function in the FUNC field, or by 
selecting GPIO function for a pin having a 1 in its GPIODIR register, a 1 in the OD bit 
selects ope n-drain operation, that is, a 1 disables the high-drive tran sistor . This option has 
no effect on the primary I2C pins.
Remark: The open-drain mode is not available on all parts ( see Section 7.1).
7.4 Register description
The I/O configura tio n re gis te rs co nt ro l the PIO port pins, the inputs and outputs of all 
peripherals and functional blocks, the I2C-bus pins, and the ADC input pins. 
Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and 
electrical characteristics.
Some input functions (SCK0, DSR, DCD, and  RI) are multiplexed to several physical pins. 
The IOCON_LOC registers select the pin location for each of these functions.
Remark: The IOCON registers are listed in order of their memory locations in Table 55, 
which correspond to the order of their physical pin numbers in the LQFP48 package 
starting at the upper left corner with pin 1 (PIO2_6). See Table 56 for a listing of IOCON 
registers ordered by port number.
The IOCON location registers are used to select a physical pin for multiplexed functions. 
Remark: Note that once the pin location has been selected, the function still must be 
configured in the corresponding IOCON registers for the function to be usable on that pin.
 
Table 55. Register overview: I/O configurat ion (base address 0x4004 4000)
Name Access Address 
offset Description Reset 
value Reference
IOCON_PIO2_6 R/W 0x000 I/O configuration for pin PIO2_6 0xD0 Table 57
- R/W 0x004 Reserved - -
IOCON_PIO2_0 R/W 0x008 I/O configuration for pin 
PIO2_0/DTR/SSEL1 0xD0 Table 58
IOCON_RESET_PIO0_0 R/W 0x00C I/O configuration for pin RESET/PIO0_0 0xD0 Table 59
IOCON_PIO0_1 R/W 0x010 I/O configuration for pin 
PIO0_1/CLKOUT/CT32B0_MAT2 0xD0 Table 60
IOCON_PIO1_8 R/W 0x014 I/O configuration for pin 
PIO1_8/CT16B1_CAP0 0xD0 Table 61
- R/W 0x018 Reserved - -
IOCON_PIO0_2 R/W 0x01C I/O configuration for pin 
PIO0_2/SSEL0/CT16B0_CAP0 0xD0 Table 62
IOCON_PIO2_7 R/W 0x020 I/O configuration for pin PIO2_7 0xD0 Table 63
IOCON_PIO2_8 R/W 0x024 I/O configuration for pin PIO2_8 0xD0 Table 64
IOCON_PIO2_1 R/W 0x028 I/O configuration for pin 
PIO2_1/DSR/SCK1 0xD0 Table 65
IOCON_PIO0_3 R/W 0x02C I/O configuration for pin PIO0_3 0xD0 Table 66
IOCON_PIO0_4 R/W 0x030 I/O configuration for pin PIO0_4/SCL 0x00 Table 67

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User manual Rev. 11 — 26 July 2012  70 of 538
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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration
IOCON_PIO0_5 R/W 0x034 I/O configuration for pin PIO0_5/SDA 0x00 Table 68
IOCON_PIO1_9 R/W 0x038 I/O configuration for pin 
PIO1_9/CT16B1_MAT0 0xD0 Table 69
IOCON_PIO3_4 R/W 0x03C I/O configuration for pin PIO3_4  0xD0 Table 70
IOCON_PIO2_4 R/W 0x040 I/O configuration for pin PIO2_4 0xD0 Table 71
IOCON_PIO2_5 R/W 0x044 I/O configuration for pin PIO2_5 0xD0 Table 72
IOCON_PIO3_5 R/W 0x048 I/O configuration for pin PIO3_5  0xD0 Table 73
IOCON_PIO0_6 R/W 0x04C I/O configuration for pin PIO0_6/SCK0 0xD0 Table 74
IOCON_PIO0_7 R/W 0x050 I/O configuration for pin PIO0_7/CTS 0xD0 Table 75
IOCON_PIO2_9 R/W 0x054 I/O configuration for pin PIO2_9 0xD0 Table 76
IOCON_PIO2_10 R/W 0x058 I/O configuration for pin PIO2_10 0xD0 Table 77
IOCON_PIO2_2 R/W 0x05C I/O configuration for pin 
PIO2_2/DCD/MISO1 0xD0 Table 78
IOCON_PIO0_8 R/W 0x060 I/O configuration for pin 
PIO0_8/MISO0/CT16B0_MAT0 0xD0 Table 79
IOCON_PIO0_9 R/W 0x064 I/O configuration for pin 
PIO0_9/MOSI0/CT16B0_MAT1 0xD0 Table 80
IOCON_SWCLK_PIO0_10 R/W 0x068 I/O configuration for pin 
SWCLK/PIO0_10/
SCK0/CT16B0_MAT2
0xD0 Table 81
IOCON_PIO1_10 R/W 0x06C I/O configuration for pin 
PIO1_10/AD6/CT16B1_MAT1 0xD0 Table 82
IOCON_PIO2_11 R/W 0x070 I/O configuration for pin PIO2_11/SCK0 0xD0 Table 83
IOCON_R_P IO0_11 R/W 0x074 I/O config u ra ti on for pin 
R/PIO0_11/AD0/CT32B0_MAT3 0xD0 Table 84
IOCON_R_PIO1_0 R/W 0x078 I/O configuration for pin 
R/PIO1_0/AD1/CT32B1_CAP0 0xD0 Table 85
IOCON_R_PIO1_1 R/W 0x07C I/O configuration for pin 
R/PIO1_1/AD2/CT32B1_MAT0 0xD0 Table 86
IOCON_R_PIO1_2 R/W 0x080 I/O configuration for pin 
R/PIO1_2/AD3/CT32B1_MAT1 0xD0 Table 87
IOCON_PIO3_0 R/W 0x084 I/O configuration for pin PIO3_0/DTR 0xD0 Table 88
IOCON_PIO3_1 R/W 0x088 I/O configuration for pin PIO3_1/DSR 0xD0 Table 89
IOCON_PIO2_3 R/W 0x08C I/O configuration for pin 
PIO2_3/RI/MOSI1 0xD0 Table 90
IOCON_SWDIO _PIO1_3 R/W 0x090 I/O configu r a ti o n fo r pin 
SWDIO/PIO1_3/AD4/CT32B1_MAT2 0xD0 Table 91
IOCON_PIO1_4 R/W 0x094 I/O configuration for pin 
PIO1_4/AD5/CT32B1_MAT3 0xD0 Table 92
IOCON_PIO1_11 R/W 0x098 I/O configuration for pin PIO1_11/AD7 0xD0 Table 93
IOCON_PIO3_2 R/W 0x09C I/O configuration for pin PIO3_2/DCD 0xD0 Table 94
IOCON_PIO1_5 R/W 0x0A0 I/O configuration for pin 
PIO1_5/RTS/CT32B0_CAP0 0xD0 Table 95
Table 55. Register overview: I/O configurat ion (base address 0x4004 4000)
Name Access Address 
offset Description Reset 
value Reference

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration
 
IOCON_PIO1_6 R/W 0x0A4 I/O configuration for pin 
PIO1_6/RXD/CT32B0_MAT0 0xD0 Table 96
IOCON_PIO1_7 R/W 0x0A8 I/O configuration for pin 
PIO1_7/TXD/CT32B0_MAT1 0xD0 Table 97
IOCON_PIO3_3 R/W 0x0AC I/O configuration for pin PIO3_3/RI 0xD0 Table 98
IOCON_SCK_LOC R/W 0x0B0 SCK pin location select register 0x00 Table 99
IOCON_DSR_LOC R/W 0x0B4 DSR pin location select register 0x00 Table 100
IOCON_DCD_LOC R/W 0x0B8 DCD pin location select register 0x00 Table 101
IOCON_RI_LOC R/W 0x0BC RI pin location register 0x00 Table 102
Table 55. Register overview: I/O configurat ion (base address 0x4004 4000)
Name Access Address 
offset Description Reset 
value Reference
Table 56. I/O configuration registers ordered by port number
Port pin Register name LPC1112 LPC1111/
12/13/14 LPC1113/
14 LPC11C12
/
C14
LPC11C22/
C24 Reference
HVQFN24 HVQFN33 LQFP48 LQFP48 LQFP48
PIO0_0 IOCON_RESET_PIO0_0 yes yes yes yes yes Table 59
PIO0_1 IOCON_PIO0_1 yes yes yes yes yes Table 57
PIO0_2 IOCON_PIO0_2 yes yes yes yes yes Table 62
PIO0_3 IOCON_PIO0_3 no yes yes yes yes Table 66
PIO0_4 IOCON_PIO0_4 yes yes yes yes yes Table 67
PIO0_5 IOCON_PIO0_5 yes yes yes yes yes Table 68
PIO0_6 IOCON_PIO0_6 yes yes yes yes yes Table 74
PIO0_7 IOCON_PIO0_7 yes yes yes yes yes Table 75
PIO0_8 IOCON_PIO0_8 yes yes yes yes yes Table 79
PIO0_9 IOCON_PIO0_9 yes yes yes yes yes Table 80
PIO0_10 IOCON_SWCLK_PIO0_10 yes yes yes yes yes Table 81
PIO0_11 IOCON_R_PIO0_11 yes yes yes yes yes Table 84
PIO1_0 IOCON_R_PIO1_0 yes yes yes yes yes Table 85
PIO1_1 IOCON_R_PIO1_1 yes yes yes yes yes Table 86
PIO1_2 IOCON_R_PIO1_2 yes yes yes yes yes Table 87
PIO1_3 IOCON_SWDIO_PIO1_3 yes yes yes yes yes Table 91
PIO1_4 IOCON_PIO1_4 yes yes yes yes yes Table 92
PIO1_5 IOCON_PIO1_5 no yes yes yes yes Table 95
PIO1_6 IOCON_PIO1_6 yes yes yes yes yes Table 96
PIO1_7 IOCON_PIO1_7 yes yes yes yes yes Table 97
PIO1_8 IOCON_PIO1_8 yes yes yes yes yes Table 61
PIO1_9 IOCON_PIO1_9 no yes yes yes no Table 69
PIO1_10 IOCON_PIO1_10 no yes yes yes yes Table 82
PIO1_11 IOCON_PIO1_11 no yes yes yes yes Table 93
PIO2_0 IOCON_PIO2_0 no yes yes yes yes Table 58
PIO2_1 IOCON_PIO2_1 no no yes yes yes Table 65

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration
7.4.1 IOCON_PIO2_6
 
PIO2_2 IOCON_PIO2_2 no no yes yes yes Table 78
PIO2_3 IOCON_PIO2_3 no no yes yes yes Table 90
PIO2_4 IOCON_PIO2_4 no no yes yes no Table 71
PIO2_5 IOCON_PIO2_5 no no yes yes no Table 72
PIO2_6 IOCON_PIO2_6 no no yes yes yes Table 57
PIO2_7 IOCON_PIO2_7 no no yes yes yes Table 63
PIO2_8 IOCON_PIO2_8 no no yes yes yes Table 64
PIO2_9 IOCON_PIO2_9 no no yes yes no Table 76
PIO2_10 IOCON_PIO2_10 no no yes yes yes Table 77
PIO2_11 IOCON_PIO2_11 no no yes yes yes Table 83
PIO3_0 IOCON_PIO3_0 no no yes yes yes Table 88
PIO3_1 IOCON_PIO3_1 no no yes yes yes Table 89
PIO3_2 IOCON_PIO3_2 no yes yes yes yes Table 94
PIO3_3 IOCON_PIO3_3 no no yes yes yes Table 98
PIO3_4 IOCON_PIO3_4 no yes yes no no Table 70
PIO3_5 IOCON_PIO3_5 no yes yes no no Table 73
- IOCON_SCK_LOC no yes (SCKLOC 
= 01 
reserved)
yes yes yes Table 99
- IOCON_DSR_LOC no no yes yes yes Table 100
- IOCON_DCD_LOC no no yes yes yes Table 101
- IOCON_RI_LOC no no yes yes yes Table 102
Table 56. I/O configuration registers ordered by port number
Port pin Register name LPC1112 LPC1111/
12/13/14 LPC1113/
14 LPC11C12
/
C14
LPC11C22/
C24 Reference
HVQFN24 HVQFN33 LQFP48 LQFP48 LQFP48
Table 57. IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description 
Bit Symbol Value Description Reset 
value
2:0 FUNC Selects pin function. All other values are reserve d. 000
0x0 Selects function PIO2_6. 
4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor 
control). 10
0x0 Inactive (no pull-down/pull-up resistor enabled).
0x1 Pull-down resistor enabled.
0x2 Pull-up resistor enabled.
0x3 Repeater mode .
5 HYS Hysteresis. 0
0 Disable.
1 Enable. 
9:6 - - Reserved 0011

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.2 IOCON_PIO2_0

7.4.3 IOCON_PIO_RESET_PIO0_0

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 57. IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description

Bit Symbol Value Description Reset

value

Table 58. IOCON_PIO2_0 register (IOCON_PIO2_0, address 0x4004 4008) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_0.

0x1 Select function D TR.

0x2 Select function SSEL1 .

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 59. IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C)

bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function RESET.

0x1 Selects function PIO0_0.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.4 IOCON_PIO0_1

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 59. IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C)

bit description

Bit Symbol Value Description Reset

value

Table 60. IOCON_PIO0_1 register (IOCON_PIO0_1, address 0x4004 4010) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_1.

0x1 Selects function CLKOUT.

0x2 Selects function CT32B0_MAT2.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.5 IOCON_PIO1_8

7.4.6 IOCON_PIO0_2

Table 61. IOCON_PIO1_8 register (IOCON_PIO1_8, address 0x4004 4014) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_8.

0x1 Selects function CT16B1_CAP0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 62. IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_2.

0x1 Selects function SSEL0.

0x2 Selects function CT16B0_CAP0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.7 IOCON_PIO2_7

7.4.8 IOCON_PIO2_8

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 62. IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description

Bit Symbol Value Description Reset

value

Table 63. IOCON_PIO2_7 register (IOCON_PIO2_7, address 0x4004 4020) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_7.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 64. IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_8.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.9 IOCON_PIO2_1

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 64. IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description

Bit Symbol Value Description Reset

value

Table 65. IOCON_PIO2_1 register (IOCON_PIO2_1, address 0x4004 4028) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_1.

0x1 Select function D S R.

0x2 Select function SCK1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.10 IOCON_PIO0_3

7.4.11 IOCON_PIO0_4

Table 66. IOCON_PIO0_3 register (IOCON_PIO0_3, address 0x4004 402C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_3.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 67. IOCON_PIO0_4 register (IOCON_PIO0_4, address 0x4004 4030) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other va lues are reserved. 000

0x0 Selects function PIO0_4 (open-drain pin).

0x1 Selects I2C function SCL (open-drain pin).

7:3 - Reserved. 00000

9:8 I2CMODE Se lects I2C mode. Select Standard mode (I2CMODE = 00,

default) or Standard I/O functionality (I2CMODE = 01) if the

pin function is GPIO (FUNC = 000).

0x0 Standard mode/ Fast-mode I2C.

0x1 Standard I/O functionality

0x2 Fast-mode Plus I2C

0x3 Reserved.

31:10 - - Reserved. -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.12 IOCON_PIO0_5

7.4.13 IOCON_PIO1_9

Remark: See Section 7.1 for part specific details.

7.4.14 IOCON_PIO3_4

Remark: See Section 7.1 for part specific details.

Table 68. IOCON_PIO0_5 register (IOCON_PIO0_5, address 0x4004 4034) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserved. 000

0x0 Selects function PIO0_5 (open-d rain pin).

0x1 Selects I2C function SDA (open-drain pin).

7:3 - Reserved. 00000

9:8 I2CMODE Selects I2C mode. Select Standard mode (I2CMODE = 00,

default) or Standard I/O functionality (I2CMODE = 01) if the

pin function is GPIO (FUNC = 000).

0x0 Standard mode/ Fast-mode I2C.

0x1 Standard I/O functionality

0x2 Fast-mode Plus I2C

0x3 Reserved.

31:10 - - Reserved. -

Table 69. IOCON_PIO1_9 register (IOCON_PIO1_9, address 0x4004 4038) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_9.

0x1 Selects function CT16B1_MAT0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.15 IOCON_PIO2_4

Remark: See Section 7.1 for part specific details.

Table 70. IOCON_PIO3_4 register (IOCON_PIO3_4, address 0x4004 403C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_4.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 71. IOCON_PIO2_4 register (IOCON_PIO2_4, address 0x4004 4040) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_4.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.16 IOCON_PIO2_5

Remark: See Section 7.1 for part specific details.

7.4.17 IOCON_PIO3_5

Remark: See Section 7.1 for part specific details.

Table 72. IOCON_PIO2_5 register (IOCON_PIO2_5, address 0x4004 4044) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_5.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 73. IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_5.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.18 IOCON_PIO0_6

7.4.19 IOCON_PIO0_7

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 73. IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description

Bit Symbol Value Description Reset

value

Table 74. IOCON_PIO0_6 register (IOCON_PIO0_6, address 0x4004 404C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_6.

0x1 Reserved.

0x2 Selects function SCK0 (only if pin PIO0_6/SCK0 selected in

Table 99).

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 75. IOCON_PIO0_7 register (IOCON_PIO0_7, address 0x4004 4050) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_7.

0x1 Select function C TS.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.20 IOCON_PIO2_9

Remark: See Section 7.1 for part specific details.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 75. IOCON_PIO0_7 register (IOCON_PIO0_7, address 0x4004 4050) bit description

Bit Symbol Value Description Reset

value

Table 76. IOCON_PIO2_9 register (IOCON_PIO2_9, address 0x4004 4054) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_9.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.21 IOCON_PIO2_10

7.4.22 IOCON_PIO2_2

Table 77. IOCON_PIO2_10 register (IOCON_PIO2_10, address 0x4004 4058) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_10.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 78. IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_2.

0x1 Select function D C D.

0x2 Select function MISO 1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.23 IOCON_PIO0_8

7.4.24 IOCON_PIO0_9

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 78. IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description

Bit Symbol Value Description Reset

value

Table 79. IOCON_PIO0_8 register (IOCON_PIO0_8, address 0x4004 4060) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_8.

0x1 Selects function MISO0.

0x2 Selects function CT16B0_MAT0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 80. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_9.

0x1 Selects function MOSI0.

0x2 Selects function CT16B0_MAT1.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.25 IOCON_SWCLK_PIO0_10

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 80. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description

Bit Symbol Value Description Reset

value

Table 81. IOCON_SWCLK_PIO0_10 regis te r (IOCON_SWCLK_PIO0_10, address 0x4004

4068) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserved. 0 00

0x0 Selects function SWCLK.

0x1 Selects function PIO0_10.

0x2 Selects function SCK0 (only if pin

SWCLK/PIO0_10/SCK0/CT16B0_MAT 2 selected in Table 99).

0x3 Selects function CT16B0_MAT2.

4:3 M ODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 In active (no pull-down/p ull-up resistor enabled).

0x1 Pull-d own resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode.

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drai n output

31:11 - - Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.26 IOCON_PIO1_10

7.4.27 IOCON_PIO2_11

Table 82. IOCON_PIO1_10 register (IOCON_PIO1_10, address 0x4004 406C) bit des cription

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_10.

0x1 Selects function AD6.

0x2 Selects function CT16B1_MAT1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 83. IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_11.

0x1 Select function SCK0 (only if pin PIO2_11/SCK0 selected in

Table 99).

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.28 IOCON_R_PIO0_11

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 83. IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description

Bit Symbol Value Description Reset

value

Table 84. IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit

description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function R. This function is reserved. Select one of

the alternate functions below.

0x1 Selects function PIO0_11.

0x2 Selects function AD0.

0x3 Selects function CT32B0_MAT3.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.29 IOCON_R_PIO1_0

7.4.30 IOCON_R_PIO1_1

Table 85. IOCON_R_PIO1_0 register (IOCON_R_PIO1_0, address 0x4004 4078) bit

description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function R. This function is reserved. Select one of

the alternate functions below.

0x1 Selects function PIO1_0.

0x2 Selects function AD1.

0x3 Selects function CT32B1_CAP0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 86. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit

description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function R. This function is reserved. Select one of

the alternate functions below.

0x1 Selects function PIO1_1.

0x2 Selects function AD2.

0x3 Selects function CT32B1_MAT0.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.31 IOCON_R_PIO1_2

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 86. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit

description …continued

Bit Symbol Value Description Reset

value

Table 87. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit

description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function R. This function is reserved. Select one of

the alternate functions below.

0x1 Selects function PIO1_2.

0x2 Selects function AD3.

0x3 Selects function CT32B1_MAT1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.32 IOCON_PIO3_0

7.4.33 IOCON_PIO3_1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 87. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit

description …continued

Bit Symbol Value Description Reset

value

Table 88. IOCON_PIO3_0 register (IOCON_PIO3_0, address 0x4004 4084) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_0.

0x1 Selects function DTR.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 89. IOCON_PIO3_1 register (IOCON_PIO3_1, address 0x4004 4088) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_1.

0x1 Selects function DSR.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.34 IOCON_PIO2_3

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 89. IOCON_PIO3_1 register (IOCON_PIO3_1, address 0x4004 4088) bit description

Bit Symbol Value Description Reset

value

Table 90. IOCON_PIO2_3 register (IOCON_PIO2_3, address 0x4004 408C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_3.

0x1 Selects function RI.

0x2 Selects function MOSI1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.35 IOCON_SWDIO_PIO1_3

7.4.36 IOCON_PIO1_4

Table 91. IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090)

bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function SWDIO.

0x1 Selects function PIO1_3.

0x2 Selects function AD4.

0x3 Selects function CT32B1_MAT2.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 92. IOCON_PIO1_4 register (IOCON_PIO1_4, address 0x4004 4094) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. This pin functions as WAKEUP pin if the

LPC1 11x/LPC1 1Cxx is in Deep power-down mode regardless

of the value of FUNC. All other values are reserved.

000

0x0 Selects function PIO1_4.

0x1 Selects function AD5.

0x2 Selects function CT32B1_MAT3.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.37 IOCON_PIO1_11

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 92. IOCON_PIO1_4 register (IOCON_PIO1_4, address 0x4004 4094) bit description

Bit Symbol Value Description Reset

value

Table 93. IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_11.

0x1 Selects function AD7.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.38 IOCON_PIO3_2

7.4.39 IOCON_PIO1_5

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 93. IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description

Bit Symbol Value Description Reset

value

Table 94. IOCON_PIO3_2 register (IOCON_PIO3_2, address 0x4004 409C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_2.

0x1 Selects function DCD.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 95. IOCON_PIO1_5 register (IOCON_PIO1_5, address 0x4004 40A0) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_5.

0x1 Selects function RTS.

0x2 Selects function CT32B0_CAP0.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.40 IOCON_PIO1_6

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 95. IOCON_PIO1_5 register (IOCON_PIO1_5, address 0x4004 40A0) bit description

Bit Symbol Value Description Reset

value

Table 96. IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_6.

0x1 Selects function RXD.

0x2 Selects function CT32B0_MAT0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.41 IOCON_PIO1_7

7.4.42 IOCON_PIO3_3

Table 97. IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_7.

0x1 Selects function TXD.

0x2 Selects function CT32B0_MAT1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 98. IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_3.

0x1 Selects function RI.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.43 IOCON_SCK_LOC

7.4.44 IOCON_DSR_LOC

10 OD Selects pseudo open-drain mode. See Section 7.1 for part

specific details. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 98. IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description

Bit Symbol Value Description Reset

value

Table 99. IOCON SCK location register (IOCON_SCK_LOC, ad dress 0x4004 40B0) bit

description

Bit Symbol Value Description Reset

value

1:0 SCKLOC Selects pin location for SCK0 function. 00

0x0 Selects SCK0 function in pin location

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (see Table 81).

0x1 Selects SCK0 function in pin location PIO2_11/SCK0 (see

Table 83.

0x2 Selects SCK0 function in pin location PIO0_6/SCK0 (see

Table 74).

0x3 Reserved.

31:2 - - Reserved. -

Table 100. IOCON DSR location register (IOCON_DSR_LOC, address 0x4004 40B4) bit

description

Bit Symbol Value Description Reset

value

1:0 DSRLOC Selects pin location for DSR function. 00

0x0 Selects DSR function in pin location PIO2_1/DSR/SCK1.

0x1 Selects DSR function in pin location PIO3_1/DSR.

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.45 IOCON_DCD_LOC

7.4.46 IOCON_RI_LOC

Table 101. IOCON DCD location register (IOCON_DCD_LOC, address 0x4004 40B8) bit

description

Bit Symbol Value Description Reset

value

1:0 DCDLOC Selects pin location for DCD function. 00

0x0 Selects DCD function in pin location PIO2_2/DCD/MISO1.

0x1 Selects DCD function in pin location PIO3_2/DCD.

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

Table 102. IOCON RI location register (IOCON_RI_LOC, address 0x4004 40BC) bit

description

Bit Symbol Value Description Reset

value

1:0 RILOC Selects pin location for RI function. 00

0x0 Selects RI function in pin location PIO2_3/RI/MOSI1.

0x1 Selects RI function in pin location PIO3_3/RI.

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

User manual Rev. 11 — 26 July 2012 100 of 538

8.1 How to read this chapter

Remark: This chapter applies to parts in the following series (see Table 1):

•LPC1100XL

The implement ation of the I/O configuration registers varies for dif ferent LPC1100XL parts

and packages. Table 104 shows which IOCON re gis te rs ar e us ed on th e different

packages.

8.2 Features

The I/O configura tio n re gis te rs co nt ro l the el ectrical characteristics of the pads. The

following features are programmable:

•Pin function.

•Internal pull-up/pull-down resistor or bus keeper function.

•Hysteresis.

•Analog input or digital mode for pads hosting the ADC inputs.

•I2C mode for pads hosting the I2C-bus function .

•Pseudo open-drain mode for non-I2C pins.

8.3 General description

The IOCON regis ter s con trol th e fu nct i on (GPI O or peripheral function), the input mode,

and the hysteresis of all PIOn_m pins. In addition, the I2C-bus pins can be configured for

different I2C-bus modes. If a pin is used as input pin for the ADC, an analog input mode

can be selected.

UM10398

Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Rev. 11 — 26 July 2012 User manual

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.3.1 Pin function

The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a

peripheral function. If the pins are GPIO pins, the GPIOnDIR registers determine whether

the pin is configured as an input or output (see Section 12.3.2). For any peripheral

function, the pin direction is controlled automatically depending on the pin’s functionality.

The GPIOnD IR re gis ter s ha ve no effect for peripheral functions.

8.3.2 Pin mode

The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down

resistors for each pin or select the repeater mode.

The possible on-chip r esistor configurations are pull- up enabled, pull-down enabled, or no

pull-up/pull-down. The default value is pull-up enabled. If the pull-up resistor is enabled

(default), all non-I2C pins are pulled up to 3.3 V (VDD = 3.3 V).

The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables

the pull-down resist or if the pin is at a logic LO W. This causes the pin to retain its last

known state if it is configured as an input and is not driven exte rnally. The state retention is

Fig 15. S tandard I/O pin configuration

ESD

strong

pull-up

strong

pull-down

weak

pull-up

weak

pull-down

open-drain enable

output enable

repeater mode

enable

pull-up enable

pull-down enable

data output

data input

analog input

select analog input

002aah159

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

not applicable to the Deep power-down mode. Repeater mode may typically be used to

prevent a pin from floating (and potentially using significant power if it floats to an

indeterminate state) if it is temporarily not driven.

8.3.3 Hysteresis

The input buffer for digital functions can be con fig ur ed with hy ste re sis or as pla i n buffer

through the IOCON registers (see the LPC110 0 X L da ta sheet for details).

If the external pad supply voltage VDD is between 2.5 V and 3.6 V, the hysteresis buffer

can be enabled or disabled. If VDD is below 2.5 V, the hysteresis buffer must be disabled

to use the pin in input mode.

8.3.4 A/D-mode

In A/D-mode, the digital receiver is disconnected to obtain an accurate input voltage for

analog-to-digital conversions. This mode can be selected in those IOCON registers that

control pins with an analog function. If A/D mode is selected, Hysteresis and Pin mode

settings have no effect.

For pins without analog functions, the A/D-mode setting has no effect.

8.3.5 I2C mode

If the I2C function is selected by the FUNC bits of registers IOCON_PIO0_4 (Table 115)

and IOCON_PIO0_5 (Table 116), then the I2C-bus pins can be configured for different

I2C-modes:

•Standard mode/Fast-mode I2C with input glitch filter (this includes an open-drain

output according to the I2C-bus specification).

•Fast-mode Plus with input glitch filter (this includes an open-dr ain outpu t acco rding to

the I2C-bus specification). In this mode, the pins function as high-current sinks.

•Standard open-drain I/O functionality without input filter.

Remark: Either Standard mode/Fast-mode I2C or Standard I/O functionality should be

selected if the pin is used as GPIO pin.

8.3.6 Open-drain Mode

When output is selected, either by selecting a special function in the FUNC field, or by

selecting GPIO function for a pin having a 1 in its GPIODIR register, a 1 in the OD bit

selects ope n-drain operation, that is, a 1 disables the high-drive tran sistor . This option has

no effect on the primary I2C pins.

8.4 Register description

The I/O configura tio n re gis te rs co nt ro l the PIO port pins, the inputs and outputs of all

peripherals and functional blocks, the I2C-bus pins, and the ADC input pins.

Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and

electrical characteristics.

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User manual Rev. 11 — 26 July 2012  103 of 538
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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)
Some input func tion s (SC K0,  DSR, DC D , RI, SSEL1, CT16B0_CAP0, SCK1, MISO1, 
MOSI1, CT32B0_CAP0, and RXD) are multiplexed to several physical pins. The 
IOCON_LOC registers select the pin location for each of these functions.
Remark: The IOCON registers are listed in order of their memory locations in Table 103, 
which correspond to the order of their physical pin numbers in the LQFP48 package 
starting at the upper left corner with pin 1 (PIO2_6). See Table 104 for a listing of IOCON 
registers ordered by port number.
The IOCON location registers are used to select a physical pin for multiplexed functions. 
Remark: Note that once the pin location has been selected, the function still must be 
configured in the corresponding IOCON registers for the function to be usable on that pin.
 
Table 103. Register overview: I/O configuration (ba se address 0x4004 4000)
Name Access Address 
offset Description Reset 
value Reference
IOCON_PIO2_6 R/W 0x000 I/O configuration for pin PIO2_6/ 
CT32B0_MAT1 0xD0 Table 105
- R/W 0x004 Reserved - -
IOCON_PIO2_0 R/W 0x008 I/O configuration for pin 
PIO2_0/DTR/SSEL1 0xD0 Table 106
IOCON_RESET_PIO0_0 R/W 0x00C I/O configuration for pin RESET/PIO0_0 0xD0 Table 107
IOCON_PIO0_1 R/W 0x010 I/O configuration for pin 
PIO0_1/CLKOUT/CT32B0_MAT2 0xD0 Table 105
IOCON_PIO1_8 R/W 0x014 I/O configuration for pin 
PIO1_8/CT16B1_CAP0 0xD0 Table 109
IOCON_SSEL1_LOC R/W 0x018 SSEL1 pin location select register 0x0 Table 151
IOCON_PIO0_2 R/W 0x01C I/O configuration for pin 
PIO0_2/SSEL0/CT16B0_CAP0 0xD0 Table 110
IOCON_PIO2_7 R/W 0x020 I/O configuration for pin PIO2_7/ 
CT32B0_MAT2/RXD 0xD0 Table 111
IOCON_PIO2_8 R/W 0x024 I/O configuration for pin PIO2_8/ 
CT32B0_MAT3/TXD 0xD0 Table 112
IOCON_PIO2_1 R/W 0x028 I/O configuration for pin 
PIO2_1/DSR/SCK1 0xD0 Table 113
IOCON_PIO0_3 R/W 0x02C I/O configuration for pin PIO0_3 0xD0 Table 114
IOCON_PIO0_4 R/W 0x030 I/O configuration for pin PIO0_4/SCL 0x00 Table 115
IOCON_PIO0_5 R/W 0x034 I/O configuration for pin PIO0_5/SDA 0x00 Table 116
IOCON_PIO1_9 R/W 0x038 I/O configuration for pin 
PIO1_9/CT16B1_MAT0/ MOSI1 0xD0 Table 117
IOCON_PIO3_4 R/W 0x03C I/O configuration for pin PIO3_4/ 
CT16B0_CAP1/RXD  0xD0 Table 118
IOCON_PIO2_4 R/W 0x040 I/O configuration for pin PIO2_4/ 
CT16B1_MAT1/ SSEL1 0xD0 Table 119
IOCON_PIO2_5 R/W 0x044 I/O configuration for pin PIO2_5/ 
CT32B0_MAT0 0xD0 Table 120
IOCON_PIO3_5 R/W 0x048 I/O configuration for pin PIO3_5/ 
CT16B1_CAP1/TXD  0xD0 Table 121
IOCON_PIO0_6 R/W 0x04C I/O configuration for pin PIO0_6/SCK0 0xD0 Table 122

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)
IOCON_PIO0_7 R/W 0x050 I/O configuration for pin PIO0_7/CTS 0xD0 Table 123
IOCON_PIO2_9 R/W 0x054 I/O configuration for pin PIO2_9/ 
CT32B0_CAP0 0xD0 Table 124
IOCON_PIO2_10 R/W 0x058 I/O configuration for pin PIO2_10 0xD0 Table 125
IOCON_PIO2_2 R/W 0x05C I/O configuration for pin 
PIO2_2/DCD/MISO1 0xD0 Table 126
IOCON_PIO0_8 R/W 0x060 I/O configuration for pin 
PIO0_8/MISO0/CT16B0_MAT0 0xD0 Table 127
IOCON_PIO0_9 R/W 0x064 I/O configuration for pin 
PIO0_9/MOSI0/CT16B0_MAT1 0xD0 Table 128
IOCON_SWCLK_PIO0_10 R/W 0x068 I/O configuration for pin 
SWCLK/PIO0_10/
SCK0/CT16B0_MAT2
0xD0 Table 129
IOCON_PIO1_10 R/W 0x06C I/O configuration for pin 
PIO1_10/AD6/CT16B1_MAT1/ MISO1 0xD0 Table 130
IOCON_PIO2_1 1 R/W 0x070 I/O configuration for pin PIO2_1 1/SCK0/ 
CT32B0_CAP1 0xD0 Table 131
IOCON_R_P IO0_11 R/W 0x074 I/O config u ra ti on for pin 
R/PIO0_11/AD0/CT32B0_MAT3 0xD0 Table 132
IOCON_R_PIO1_0 R/W 0x078 I/O configuration for pin 
R/PIO1_0/AD1/CT32B1_CAP0 0xD0 Table 133
IOCON_R_PIO1_1 R/W 0x07C I/O configuration for pin 
R/PIO1_1/AD2/CT32B1_MAT0 0xD0 Table 134
IOCON_R_PIO1_2 R/W 0x080 I/O configuration for pin 
R/PIO1_2/AD3/CT32B1_MAT1 0xD0 Table 135
IOCON_PIO3_0 R/W 0x084 I/O configuration for pin 
PIO3_0/DTR/CT16B0_MAT0/TXD 0xD0 Table 136
IOCON_PIO3_1 R/W 0x088 I/O configuration for pin 
PIO3_1/DSR/CT16B0_MAT1/RXD 0xD0 Table 137
IOCON_PIO2_3 R/W 0x08C I/O configuration for pin 
PIO2_3/RI/MOSI1 0xD0 Table 138
IOCON_SWDIO _PIO1_3 R/W 0x090 I/O configu r a ti o n fo r pin 
SWDIO/PIO1_3/AD4/CT32B1_MAT2 0xD0 Table 139
IOCON_PIO1_4 R/W 0x094 I/O configuration for pin 
PIO1_4/AD5/CT32B1_MAT3 0xD0 Table 140
IOCON_PIO1_11 R/W 0x098 I/O configuration for pin 
PIO1_11/AD7/CT32B1_CAP1 0xD0 Table 141
IOCON_PIO3_2 R/W 0x09C I/O configuration for pin PIO3_2/DCD/ 
CT16B0_MAT2/SCK1 0xD0 Table 142
IOCON_PIO1_5 R/W 0x0A0 I/O configuration for pin 
PIO1_5/RTS/CT32B0_CAP0 0xD0 Table 143
IOCON_PIO1_6 R/W 0x0A4 I/O configuration for pin 
PIO1_6/RXD/CT32B0_MAT0 0xD0 Table 144
IOCON_PIO1_7 R/W 0x0A8 I/O configuration for pin 
PIO1_7/TXD/CT32B0_MAT1 0xD0 Table 145
Table 103. Register overview: I/O configuration (ba se address 0x4004 4000)
Name Access Address 
offset Description Reset 
value Reference

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)
 
IOCON_PIO3_3 R/W 0x0AC I/O configuration for pin PIO3_3/RI/ 
CT16B0_CAP0 0xD0 Table 146
IOCON_SCK0_LOC R/W 0x0B0 SCK0 pin location select register 0x00 Table 147
IOCON_DSR_LOC R/W 0x0B4 DSR pin location select register 0x00 Table 148
IOCON_DCD_LOC R/W 0x0B8 DCD pin location select register 0x00 Table 149
IOCON_RI_LOC R/W 0x0BC RI pin location select register 0x00 Table 150
IOCON_CT16B0_CAP0_LOC R/W 0x0C0 CT16B0_CAP0 pin location select 
register 0x00 Table 152
IOCON_SCK1_LOC R/W 0x0C4 SCK1 pin location select register 0x00 Table 153
IOCON_MISO1_LOC R/W 0x0C8 MISO1 pin location select register 0x00 Table 154
IOCON_MOSI1_LOC R/W 0x0CC MOSI1 pin location select register 0x00 Table 155
IOCON_CT32B0_CAP0_LOC R/W 0x0D0 CT32B0_CAP0 pin location select 
register 0x00 Table 156
IOCON_RXD_LOC R/W 0x0D4 RXD pin location sele ct register 0x00 Table 157
Table 103. Register overview: I/O configuration (ba se address 0x4004 4000)
Name Access Address 
offset Description Reset 
value Reference
Table 104 . I/O configuration registers ordered by port number
Port pin Register name LPC1111/
12/13/14 LPC1113/14/15 Reference
HVQFN33 LQFP48
PIO0_0 IOCON_RESET_PIO0_0 yes yes Table 107
PIO0_1 IOCON_PIO0_1 yes yes Table 105
PIO0_2 IOCON_PIO0_2 yes yes Table 110
PIO0_3 IOCON_PIO0_3 yes yes Table 114
PIO0_4 IOCON_PIO0_4 yes yes Table 115
PIO0_5 IOCON_PIO0_5 yes yes Table 116
PIO0_6 IOCON_PIO0_6 yes yes Table 122
PIO0_7 IOCON_PIO0_7 yes yes Table 123
PIO0_8 IOCON_PIO0_8 yes yes Table 127
PIO0_9 IOCON_PIO0_9 yes yes Table 128
PIO0_10 IOCON_SWCLK_PIO0_10 yes yes Table 129
PIO0_11 IOCON_R_PIO0_11 yes yes Table 132
PIO1_0 IOCON_R_PIO1_0 yes yes Table 133
PIO1_1 IOCON_R_PIO1_1 yes yes Table 134
PIO1_2 IOCON_R_PIO1_2 yes yes Table 135
PIO1_3 IOCON_SWDIO_PIO1_3 yes yes Table 139
PIO1_4 IOCON_PIO1_4 yes yes Table 140
PIO1_5 IOCON_PIO1_5 yes yes Table 143
PIO1_6 IOCON_PIO1_6 yes yes Table 144
PIO1_7 IOCON_PIO1_7 yes yes Table 145
PIO1_8 IOCON_PIO1_8 yes yes Table 109
PIO1_9 IOCON_PIO1_9 yes yes Table 117

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 11 — 26 July 2012  106 of 538
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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)
8.4.1 IOCON_PIO2_6
 
PIO1_10 IOCON_PIO1_10 yes yes Table 130
PIO1_11 IOCON_PIO1_11 yes yes Table 141
PIO2_0 IOCON_PIO2_0 yes yes Table 106
PIO2_1 IOCON_PIO2_1 no yes Table 113
PIO2_2 IOCON_PIO2_2 no yes Table 126
PIO2_3 IOCON_PIO2_3 no yes Table 138
PIO2_4 IOCON_PIO2_4 no yes Table 119
PIO2_5 IOCON_PIO2_5 no yes Table 120
PIO2_6 IOCON_PIO2_6 no yes Table 105
PIO2_7 IOCON_PIO2_7 no yes Table 111
PIO2_8 IOCON_PIO2_8 no yes Table 112
PIO2_9 IOCON_PIO2_9 no yes Table 124
PIO2_10 IOCON_PIO2_10 no yes Table 125
PIO2_11 IOCON_PIO2_11 no yes Table 131
PIO3_0 IOCON_PIO3_0 no yes Table 136
PIO3_1 IOCON_PIO3_1 no yes Table 137
PIO3_2 IOCON_PIO3_2 yes yes Table 142
PIO3_3 IOCON_PIO3_3 no yes Table 146
PIO3_4 IOCON_PIO3_4 yes yes Table 118
PIO3_5 IOCON_PIO3_5 yes yes Table 121
Table 104 . I/O configuration registers ordered by port number
Port pin Register name LPC1111/
12/13/14 LPC1113/14/15 Reference
HVQFN33 LQFP48
Table 105. IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description 
Bit Symbol Value Description Reset 
value
2:0 FUNC Selects pin function. All other values are reserve d. 000
0x0 Selects function PIO2_6. 
0x1 Selects function CT32B0_MAT1.
4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor 
control). 10
0x0 Inactive (no pull-down/pull-up resistor enabled).
0x1 Pull-down resistor enabled.
0x2 Pull-up resistor enabled.
0x3 Repeater mode .
5 HYS Hysteresis. 0
0 Disable.
1 Enable. 
9:6 - - Reserved 0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.2 IOCON_PIO2_0

8.4.3 IOCON_PIO_RESET_PIO0_0

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 105. IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description

Bit Symbol Value Description Reset

value

Table 106. IOCON_PIO2_0 register (IOCON_PIO2_0, address 0x4004 4008) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_0.

0x1 Select function D TR.

0x2 Select function SSEL1 .

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 107. IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C)

bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function RESET.

0x1 Selects function PIO0_0.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.4 IOCON_PIO0_1

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 107. IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C)

bit description

Bit Symbol Value Description Reset

value

Table 108. IOCON_PIO0_1 register (IOCON_PIO0_1, address 0x4004 4010) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_1.

0x1 Selects function CLKOUT.

0x2 Selects function CT32B0_MAT2.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.5 IOCON_PIO1_8

8.4.6 IOCON_PIO0_2

Table 109. IOCON_PIO1_8 register (IOCON_PIO1_8, address 0x4004 4014) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_8.

0x1 Selects function CT16B1_CAP0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 110. IOCON_PIO0_2 regi ster (IOCON_PIO0_2, address 0x4004 401C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_2.

0x1 Selects function SSEL0.

0x2 Selects function CT16B0_CAP0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.7 IOCON_PIO2_7

8.4.8 IOCON_PIO2_8

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 110. IOCON_PIO0_2 regi ster (IOCON_PIO0_2, address 0x4004 401C) bit description

Bit Symbol Value Description Reset

value

Table 111. IOCON_PIO2_7 register (IOCON_PIO2_7, address 0x4004 4020) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_7.

0x1 Selects function CT32B0_MAT2.

0x2 Selects function RXD.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 112. IOCON_PIO2_8 regi ster (IOCON_PIO2_8, address 0x4004 4024) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_8.

0x1 Selects function CT32B0_MAT3.

0x2 Selects function TXD.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.9 IOCON_PIO2_1

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 112. IOCON_PIO2_8 regi ster (IOCON_PIO2_8, address 0x4004 4024) bit description

Bit Symbol Value Description Reset

value

Table 113. IOCON_PIO2_1 regi ster (IOCON_PIO2_1, address 0x4004 4028) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_1.

0x1 Select function D S R.

0x2 Select function SCK1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.10 IOCON_PIO0_3

8.4.11 IOCON_PIO0_4

Table 114. IOCON_PIO0_3 regi ster (IOCON_PIO0_3, address 0x4004 402C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_3.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 115. IOCON_PIO0_4 regi ster (IOCON_PIO0_4, address 0x4004 4030) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other va lues are reserved. 000

0x0 Selects function PIO0_4 (open-drain pin).

0x1 Selects I2C function SCL (open-drain pin).

7:3 - Reserved. 00000

9:8 I2CMODE Se lects I2C mode. Select Standard mode (I2CMODE = 00,

default) or Standard I/O functionality (I2CMODE = 01) if the

pin function is GPIO (FUNC = 000).

0x0 Standard mode/ Fast-mode I2C.

0x1 Standard I/O functionality

0x2 Fast-mode Plus I2C

0x3 Reserved.

31:10 - - Reserved. -

User manual Rev. 11 — 26 July 2012 113 of 538

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.12 IOCON_PIO0_5

8.4.13 IOCON_PIO1_9

Remark: See Section 8.1 for part specific details.

8.4.14 IOCON_PIO3_4

Remark: See Section 8.1 for part specific details.

Table 116. IOCON_PIO0_5 regi ster (IOCON_PIO0_5, address 0x4004 4034) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserved. 000

0x0 Selects function PIO0_5 (open-d rain pin).

0x1 Selects I2C function SDA (open-drain pin).

7:3 - Reserved. 00000

9:8 I2CMODE Selects I2C mode. Select Standard mode (I2CMODE = 00,

default) or Standard I/O functionality (I2CMODE = 01) if the

pin function is GPIO (FUNC = 000).

0x0 Standard mode/ Fast-mode I2C.

0x1 Standard I/O functionality

0x2 Fast-mode Plus I2C

0x3 Reserved.

31:10 - - Reserved. -

Table 117. IOCON_PIO1_9 regi ster (IOCON_PIO1_9, address 0x4004 4038) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_9.

0x1 Selects function CT16B1_MAT0.

0x2 Selects function MOSI1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

User manual Rev. 11 — 26 July 2012 114 of 538

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.15 IOCON_PIO2_4

Remark: See Section 8.1 for part specific details.

Table 118. IOCON_PIO3_4 regi ster (IOCON_PIO3_4, address 0x4004 403C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_4.

0x1 Selects function CT16B0_CAP1.

0x2 Selects function RXD.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 119. IOCON_PIO2_4 regi ster (IOCON_PIO2_4, address 0x4004 4040) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_4.

0x1 Selects function CT16B1_MAT1.

0x2 Selects function SSEL1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.16 IOCON_PIO2_5

Remark: See Section 8.1 for part specific details.

8.4.17 IOCON_PIO3_5

Remark: See Section 8.1 for part specific details.

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 119. IOCON_PIO2_4 regi ster (IOCON_PIO2_4, address 0x4004 4040) bit description

Bit Symbol Value Description Reset

value

Table 120. IOCON_PIO2_5 register (IOCON_PIO2_5, address 0x4004 4044) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_5.

0x1 Selects function CT32B0_MAT0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 121. IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_5.

0x1 Selects function CT16B1_CAP1.

0x2 Selects function TXD.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.18 IOCON_PIO0_6

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 121. IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description

Bit Symbol Value Description Reset

value

Table 122. IOCON_PIO0_6 register (IOCON_PIO0_6, address 0x4004 404C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_6.

0x1 Reserved.

0x2 Selects function SCK0 (only if pin PIO0_6/SCK0 selected in

Table 147).

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

User manual Rev. 11 — 26 July 2012 117 of 538

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.19 IOCON_PIO0_7

8.4.20 IOCON_PIO2_9

Remark: See Section 8.1 for part specific details.

Table 123. IOCON_PIO0_7 register (IOCON_PIO0_7, address 0x4004 4050) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_7.

0x1 Select function C TS.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 124. IOCON_PIO2_9 register (IOCON_PIO2_9, address 0x4004 4054) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_9.

0x1 Selects function CT32B0_CAP0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.21 IOCON_PIO2_10

8.4.22 IOCON_PIO2_2

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 124. IOCON_PIO2_9 register (IOCON_PIO2_9, address 0x4004 4054) bit description

Bit Symbol Value Description Reset

value

Table 125. IOCON_PIO2_10 register (IOCON_PIO2_10, address 0x4004 4058) bit de scription

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_10.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 126. IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_2.

0x1 Select function D C D.

0x2 Select function MISO 1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.23 IOCON_PIO0_8

8.4.24 IOCON_PIO0_9

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 126. IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description

Bit Symbol Value Description Reset

value

Table 127. IOCON_PIO0_8 register (IOCON_PIO0_8, address 0x4004 4060) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_8.

0x1 Selects function MISO0.

0x2 Selects function CT16B0_MAT0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 128. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO0_9.

0x1 Selects function MOSI0.

0x2 Selects function CT16B0_MAT1.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.25 IOCON_SWCLK_PIO0_10

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 128. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description

Bit Symbol Value Description Reset

value

Table 129. IOCON_SWCLK_PIO0_10 register (IOCON_SWCLK_PIO0_10, addre ss 0x4004

4068) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserved. 0 00

0x0 Selects function SWCLK.

0x1 Selects function PIO0_10.

0x2 Selects function SCK0 (o nly if pin

SWCLK/PIO0_10/SCK0/CT16B0_MAT 2 selected in

Table 147).

0x3 Selects function CT16B0_MAT2.

4:3 M ODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 In active (no pull-down/p ull-up resistor enabled).

0x1 Pull-d own resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode.

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drai n output

31:11 - - Reserved -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.26 IOCON_PIO1_10

8.4.27 IOCON_PIO2_11

Table 130. IOCON_PIO1_10 register (IOCON_PIO1_10, address 0x4004 406C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_10.

0x1 Selects function AD6.

0x2 Selects function CT16B1_MAT1.

0x3 Selects function MISO1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 131. IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_11.

0x1 Select function SCK0 (only if pin PIO2_11/SCK0 selected in

Table 147).

0x2 Select function CT3 2B0 _ C AP1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.28 IOCON_R_PIO0_11

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 131. IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description

Bit Symbol Value Description Reset

value

Table 132. IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit

description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function R. This function is reserved. Select one of

the alternate functions below.

0x1 Selects function PIO0_11.

0x2 Selects function AD0.

0x3 Selects function CT32B0_MAT3.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.29 IOCON_R_PIO1_0

8.4.30 IOCON_R_PIO1_1

Table 133. IOCON_R_PIO1_0 register (IOCON_R_PIO1_0, address 0x4004 4078) bit

description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function R. This function is reserved. Select one of

the alternate functions below.

0x1 Selects function PIO1_0.

0x2 Selects function AD1.

0x3 Selects function CT32B1_CAP0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 134. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit

description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function R. This function is reserved. Select one of

the alternate functions below.

0x1 Selects function PIO1_1.

0x2 Selects function AD2.

0x3 Selects function CT32B1_MAT0.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.31 IOCON_R_PIO1_2

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 134. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit

description …continued

Bit Symbol Value Description Reset

value

Table 135. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit

description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function R. This function is reserved. Select one of

the alternate functions below.

0x1 Selects function PIO1_2.

0x2 Selects function AD3.

0x3 Selects function CT32B1_MAT1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.32 IOCON_PIO3_0

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 135. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit

description …continued

Bit Symbol Value Description Reset

value

Table 136. IOCON_PIO3_0 register (IOCON_PIO3_0, address 0x4004 4084) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_0.

0x1 Selects function DTR.

0x2 Selects function CT16B0_MAT0.

0x3 Selects function TXD.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.33 IOCON_PIO3_1

8.4.34 IOCON_PIO2_3

Table 137. IOCON_PIO3_1 register (IOCON_PIO3_1, address 0x4004 4088) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_1.

0x1 Selects function DSR.

0x2 Selects function CT16B0_MAT1.

0x3 Selects function RXD.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 138. IOCON_PIO2_3 register (IOCON_PIO2_3, address 0x4004 408C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO2_3.

0x1 Selects function RI.

0x2 Selects function MOSI1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.35 IOCON_SWDIO_PIO1_3

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 138. IOCON_PIO2_3 register (IOCON_PIO2_3, address 0x4004 408C) bit description

Bit Symbol Value Description Reset

value

Table 139. IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090)

bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function SWDIO.

0x1 Selects function PIO1_3.

0x2 Selects function AD4.

0x3 Selects function CT32B1_MAT2.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.36 IOCON_PIO1_4

8.4.37 IOCON_PIO1_11

Table 140. IOCON_PIO1_4 register (IOCON_PIO1_4, address 0x4004 4094) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. This pin functions as WAKEUP pin if the

LPC1 11x/LPC1 1Cxx is in Deep power-down mode regardless

of the value of FUNC. All other values are reserved.

000

0x0 Selects function PIO1_4.

0x1 Selects function AD5.

0x2 Selects function CT32B1_MAT3.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 141. IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_11.

0x1 Selects function AD7.

0x2 Selects function CT32B1_CAP1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.38 IOCON_PIO3_2

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

6 - - Reserved 1

7 ADMODE Selects Analog/Digital mode 1

0 Analog input mode

1 D igital functional mode

9:8 - - Reserved 00

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 141. IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description

Bit Symbol Value Description Reset

value

Table 142. IOCON_PIO3_2 register (IOCON_PIO3_2, address 0x4004 409C) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_2.

0x1 Selects function DCD.

0x2 Selects function CT16B0_MAT2.

0x3 Selects function SCK1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.39 IOCON_PIO1_5

8.4.40 IOCON_PIO1_6

Table 143. IOCON_PIO1_5 register (IOCON_PIO1_5, address 0x4004 40A0) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_5.

0x1 Selects function RTS.

0x2 Selects function CT32B0_CAP0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 144. IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_6.

0x1 Selects function RXD.

0x2 Selects function CT32B0_MAT0.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.41 IOCON_PIO1_7

8.4.42 IOCON_PIO3_3

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 144. IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description

Bit Symbol Value Description Reset

value

Table 145. IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO1_7.

0x1 Selects function TXD.

0x2 Selects function CT32B0_MAT1.

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 146. IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. All other values are reserve d. 000

0x0 Selects function PIO3_3.

0x1 Selects function RI.

0x2 Selects function CT16B0_CAP0.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.43 IOCON_SCK0_LOC

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor

control). 10

0x0 Inactive (no pull-down/pull-up resistor enabled).

0x1 Pull-down resistor enabled.

0x2 Pull-up resistor enabled.

0x3 Repeater mode .

5 HYS Hysteresis. 0

0 Disable.

1 Enable.

9:6 - - Reserved 0011

10 OD Selects pseudo open-drain mode. 0

0 Standard GPIO output

1 Open-drain output

31:11 - - Reserved -

Table 146. IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description

Bit Symbol Value Description Reset

value

Table 147. IOCON SCK0 location register (IOCON_SCK0_LOC, address 0x40 04 40B0) bit

description

Bit Symbol Value Description Reset

value

1:0 SCKLOC Selects pin location for SCK0 function. 00

0x0 Selects SCK0 function in pin location

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (see Table 129).

0x1 Selects SCK0 function in pin location PIO2_11/SCK0 (see

Table 131).

0x2 Selects SCK0 function in pin location PIO0_6/SCK0 (see

Table 122).

0x3 Reserved.

31:2 - - Reserved. -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.44 IOCON_DSR_LOC

8.4.45 IOCON_DCD_LOC

8.4.46 IOCON_RI_LOC

Table 148. IOCON DSR location register (IOCON_DSR_LOC, address 0x4004 40B4) bit

description

Bit Symbol Value Description Reset

value

1:0 DSRLOC Selects pin location for DSR function. 00

0x0 Selects DS R funct ion in pin location PIO 2_1/DSR /SCK1 (see

Table 113).

0x1 Selects DSR function in pin location PIO3_1/DSR (see

Table 137).

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

Table 149. IOCON DCD location register (IOCON_DCD_LOC, address 0x4004 40B8) bit

description

Bit Symbol Value Description Reset

value

1:0 DCDLOC Selects pin location for DCD function. 00

0x0 Selects DCD function in pin location PIO2_2/DCD/MISO1

(see Table 126).

0x1 Selects DCD function in pin location PIO3_2/DCD (see

Table 142).

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

Table 150. IOCON RI location register (IOCON_RI_LOC, address 0x4004 40BC) bit

description

Bit Symbol Value Description Reset

value

1:0 RILOC Selects pin location for RI function. 00

0x0 Selects RI function in pin location PIO2_3/RI/MOSI1 (see

Table 138).

0x1 Selects RI function in pin location PIO3_3/RI (see Table 146).

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.47 IOCON_SSEL1_LOC

8.4.48 IOCON_CT16B0_CAP0_LOC

8.4.49 IOCON_SCK1_LOC

Table 151. IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) bit

description

Bit Symbol Value Description Reset

value

1:0 SSEL1LOC Selects pin location for SSEL1 function. 00

0x0 Selects SSEL1 function in pin location

PIO2_2/DCD/MISO1 (see Table 126).

0x1 Selects SSEL1 function in pin location

PIO2_4/CT16B1_MAT1/SSEL1 (see Table 119).

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

Table 152. IOCON CT16B0_CAP0 location register (IOCON_CT16B0 _CAP0_LOC, address

0x4004 40C0) bit description

Bit Symbol Value Description Reset

value

1:0 CT16B0_CAP0LOC Selects pin location fo r CT16B0_CAP0 function. 00

0x0 Selects CT16B0_CAP0 function in pin location

PIO0_2/SSEL0/CT16B0_CAP0 (see Table 110).

0x1 Selects CT16B0_CAP0 function in pin location

PIO3_3/RI/CT16B0 (see Table 146).

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

Table 153. IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x40 04 40C4) bit

description

Bit Symbol Value Description Reset

value

1:0 SCK1LOC Selects pin location for SCK1 function. 00

0x0 Selects SCK1 function in pin location PIO2_1/DSR/SCK1

(see Table 113).

0x1 Selects SCK1 function in pin location

PIO3_2/DCD/CT16B0_MAT2/SCK1 (see Table 142).

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.50 IOCON_MISO1_LOC

8.4.51 IOCON_MOSI1_LOC

8.4.52 IOCON_CT32B0_CAP0_LOC

Table 154. IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) bit

description

Bit Symbol Value Description Reset

value

1:0 MISO1LOC Selects pin location for the MISO1 function. 00

0x0 Selects MISO1 function in pin location

PIO2_2/DCD/MISO1 (see Table 126).

0x1 Selects MISO1 function in pin location

PIO1_10/AD6/CT16B1_MAT1/MISO1 (see Table 130).

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

Table 155. IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) bit

description

Bit Symbol Value Description Reset

value

1:0 MOSI1LOC Selects pin location for the MOSI1 function. 00

0x0 Selects MOSI1 function in pin location PIO2_3/RI/MOSI1

(see Table 138).

0x1 Selects MOSI1 function in pin location

PIO1_9/CT16B1_MAT0/MOSI1 (see Table 117).

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

Table 156. IOCON CT32B0_CAP0 location register (IOCON_CT32B0 _CAP0_LOC, address

0x4004 40D0) bit description

Bit Symbol Value Description Reset

value

1:0 CT32B0_CAP0LOC Selects pin location for the CT32B0_CAP0

function. 00

0x0 Selects CT32B0_CAP0 function in pin location

PIO1_5/RTS/CT32B0_CAP0 (see Table 143).

0x1 Selects CT32B0_CAP0 function in pin location

PIO2_9/CT32B0_CAP0 (Table 124).

0x2 Reserved.

0x3 Reserved.

31:2 - - Reserved. -

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NXP Semiconductors UM10398

Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.53 IOCON_RXD_LOC

Table 157. IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) bit

description

Bit Symbol Value Description Reset

value

1:0 RXDLOC Selects pin location for the RXD function. 00

0x0 Selects RXD function in pin location

PIO1_6/RXD/CT32B0_MAT0 (see Table 144).

0x1 Selects RXD function in pin location

PIO2_7/CT32B0_MAT2/RXD (see Table 111).

0x2 Selects RXD function in pin location

PIO3_1/DSR/CT16B0_MAT1/RXD (see Table 137).

0x3 Selects RXD function in pin location

PIO3_4/CT16B0_CAP1/RXD (see Table 118).

31:2 - - Reserved. -

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User manual Rev. 11 — 26 July 2012  137 of 538
 
9.1 How to read this chapter
Remark: This chapter applies to p ar t s in the LPC1100, LPC1100C, and LPC1100L series 
for LQFP and HVQFN packages.
The LPC111x are available in three packages: LQFP48 (LPC1113, LPC1114), and 
HVQFN33 (LPC1111, LPC1112, LPC1113, LPC1114).
The LPC11Cxx parts are available in a LQFP48 package.
The LPC11D14 part is available as a dual-chip module in a LQFP100 package.
 
UM10398
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, 
LPC1100C, and LPC1100L series, HVQFN/LQFP packages)
Rev. 11 — 26 July 2012 User manual
Table 158. LPC11(D)1x/LPC 11Cxx pin configur ations
Part LQFP48 HVQFN24 HVQFN33 LQFP100
LPC1111 Pin configuration - - Figure 17 -
Pin description - - Table 160 -
LPC1112 Pin configuration - Figure 18 Figure 17 -
Pin description - Table 161 Table 160 -
LPC1113 Pin configuration Figure 16 -Figure 17 -
Pin description Table 159 -Table 160 -
LPC1114 Pin configuration Figure 16 -Figure 17 -
Pin description Table 159 -Table 160 -
LPC11C12 Pin configuration Figure 19 ---
Pin description Table 159 ---
LPC11C14 Pin configuration Figure 19 ---
Pin description Table 159 ---
LPC11C22 Pin configuration Figure 20 ---
Pin description Table 162 ---
LPC11C24 Pin configuration Figure 20 ---
Pin description Table 162 ---
LPC11D14 Pin configuration - - - Figure 21
Pin description - - - Table 163

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NXP Semiconductors UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

9.2 LPC111x Pin configuration

Fig 16. Pin configuration LQFP48 package

LPC1113FBD48/301

LPC1113FBD48/302

LPC1114FBD48/301

LPC1114FBD48/302

PIO2_6 PIO3_0/DTR

PIO2_0/DTR/SSEL1 R/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

XTALIN PIO2_11/SCK0

XTALOUT PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0

PIO2_7 PIO2_2/DCD/MISO1

PIO2_8 PIO2_10

PIO2_1/DSR/SCK1 PIO3_3/RI

PIO0_3 PIO1_7/TXD/CT32B0_MAT1

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

PIO1_9/CT16B1_MAT0 V

PIO3_4 PIO3_2/DCD

PIO2_4 PIO1_11/AD7

PIO2_5 V

PIO3_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO0_6/SCK0 SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO0_7/CTS

PIO2_9

PIO2_3/RI/MOSI1

PIO3_1/DSR

002aae697

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NXP Semiconductors UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Fig 17. Pin configuration HVQF N33 package

002aae698

Transparent top view

PIO0_8/MISO0/CT16B0_MAT0

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO0_9/MOSI0/CT16B0_MAT1

VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2

XTALOUT PIO1_10/AD6/CT16B1_MAT1

XTALIN R/PIO0_11/AD0/CT32B0_MAT3

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

PIO1_9/CT16B1_MAT0

PIO3_4

PIO3_5

PIO0_6/SCK0

PIO0_7/CTS

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

PIO1_5/RTS/CT32B0_CAP0

VDD

PIO3_2

PIO1_11/AD7

PIO1_4/AD5/CT32B1_MAT3/WAKEUP

SWDIO/PIO1_3/AD4/CT32B1_MAT2

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

terminal 1

index area

33 VSS

Fig 18. Pin configuration HVQFN24 pa ckage

002aah173

LPC1112FHN24

Transparent top view

PIO0_9

PIO1_8

PIO0_10

XTALIN PIO0_11

PIO1_0

PIO0_1 PIO1_1

RESET/PIO0_0 PIO1_2

PIO0_2

PIO0_4

PIO0_5

PIO0_6

PIO0_7

PIO0_8

PIO1_7

PIO1_6

PIO1_4

PIO1_3

terminal 1

index area

613

514

415

316

217

118

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NXP Semiconductors UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

9.3 LPC11Cxx Pin configuration

Fig 19. Pin configuration LQFP48 package

LPC11C12FBD48/301

LPC11C14FBD48/301

PIO2_6 PIO3_0/DTR

PIO2_0/DTR/SSEL1 R/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

XTALIN PIO2_11/SCK0

XTALOUT PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0

PIO2_7 PIO2_2/DCD/MISO1

PIO2_8 PIO2_10

PIO2_1/DSR/SCK1 PIO3_3/RI

PIO0_3 PIO1_7/TXD/CT32B0_MAT1

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

PIO1_9/CT16B1_MAT0 V

PIO2_4 PIO3_2/DCD

CAN_RXD PIO1_11/AD7

CAN_TXD V

PIO2_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO0_6/SCK0 SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO0_7/CTS

PIO2_9

PIO2_3/RI/MOSI1

PIO3_1/DSR

002aaf266

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NXP Semiconductors UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Fig 20. Pin configuration (L PC11C22/C24)

LPC11C22FBD48/301

LPC11C24FBD48/301

PIO2_6 PIO3_0/DTR

PIO2_0/DTR/SSEL1 R/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

VSS R/PIO0_11/AD0/CT32B0_MAT3

XTALIN PIO2_11/SCK0

XTALOUT PIO1_10/AD6/CT16B1_MAT1

VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0

PIO2_7 PIO2_2/DCD/MISO1

PIO2_8 PIO2_10

PIO2_1/DSR/SCK1 PIO3_3/RI

PIO0_3 PIO1_7/TXD/CT32B0_MAT1

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

VDD_CAN VDD

CANL PIO3_2/DCD

CANH PIO1_11/AD7

VCC VSS

GND PIO1_4/AD5/CT32B1_MAT3/WAKEUP

STB SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO0_6/SCK0

PIO0_7/CTS

PIO2_3/RI/MOSI1

PIO3_1/DSR

002aaf909

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

9.4 LPC11D14 Pin configuration

Fig 21. Pin configuration LQFP100 package

LPC11D14FBD100/302

PIO1_7 S29

PIO3_3 S28

n.c. S27

PIO2_6 S26

PIO2_0 S25

RESET/PIO0_0 S24

PIO0_1 S23

VSS S22

XTALIN S21

XTALOUT S20

VDD S19

PIO1_8 S18

PIO0_2 S17

PIO2_7 S16

PIO1_9 S10

PIO3_4 S9

PIO2_4 S8

PIO2_5 S7

PIO3_5

PIO2_8

PIO2_1

PIO0_3

PIO0_4

PIO0_5

S15

S14

S13

S12

S11

PIO0_6 S5

PIO0_7 PIO1_6

PIO2_9 PIO1_5

PIO2_10 VDD

S34 PIO3_2

S35 PIO1_11

S36 VSS

S37 PIO1_4

S38 SWDIO/PIO1_3

S39 PIO2_3

LCD_ SDA PIO3_1

LCD_ SCL PIO3_0

SYNC R/PIO1_2

CLK R/PIO1_1

VDD(LCD) R/PIO1_0

BP3 PIO0_8

S0 PIO2_2

S1 S33

S2 S32

VSS(LCD)

VLCD

BP0

BP2

BP1

S31

R/PIO0_11

PIO2_11

PIO1_10

SWCLK/PIO0_10

PIO0_9

S4 S30

002aag450

100

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User manual Rev. 11 — 26 July 2012  143 of 538
NXP Semiconductors UM10398
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
9.5 LPC111x/LPC11Cxx Pin description
 
Table 159. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 p ackage)
Symbol Pin Type Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual directi on and function 
controls for each bit. The operation of port 0 pins depends on the function 
selected through the IOCONFIG register block.
RESET/PIO0_0 3[1][2] IRESET — External reset input: A LOW on this pin resets the device, 
causing I/O ports and peripherals to take on their default states, and 
processor execution to begin at address 0. 
I/O PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2 4[3][2] I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin 
during reset starts the flash ISP command handler via UART (if PIO0_3 is 
HIGH) or via C_CAN (if PIO0_3 is LOW).
OCLKOUT — Clockout pin.
OCT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 10[3][2] I/O PIO0_2 — General purpose digital input/output pin.
OSSEL0 — Slave Select for SPI0.
ICT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 14[3][2] I/O PIO0_3 — General purpose digital input/output pin. This pin is monitored 
during reset: Together with a LOW level on  pin PIO0_1, a LOW level starts 
the flash ISP command handler via C_CAN and a HIGH level starts the 
flash ISP command handler via UART.
PIO0_4/SCL 15[4][2] I/O PIO0_4 — General purpose digital input/output pin (open-drain).
I/O SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C 
Fast-mode Plus is selected in the I/O configuration register.
PIO0_5/SDA 16[4][2] I/O PIO0_5 — General purpose digital input/output pin (open-drain). 
I/O SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C 
Fast-mode Plus is selected in the I/O configuration register.
PIO0_6/SCK0 22[3][2] I/O PIO0_6 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO0_7/CTS 23[3][2] I/O PIO0_7 — General purpose digital input/output pin (hig h-current output 
driver).
ICTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 27[3][2] I/O PIO0_8 — General purpose digital input/output pin.
I/O MISO0 — Master In Slave Out for SPI0.
OCT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 28[3][2] I/O PIO0_9 — General purpose digital input/output pin.
I/O MOSI0 — Master Out Slave In for SPI0.
OCT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/CT16B0_MAT2 29[3][2] ISWCLK — Serial wire clock.
I/O PIO0_10 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
OCT16B0_MAT2 — Match output 2 for 16-bit timer 0.

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User manual Rev. 11 — 26 July 2012  144 of 538
NXP Semiconductors UM10398
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
R/PIO0_11/
AD0/CT32B0_MAT3 32[5][2] IR — Reserved. Configure for an alternate function in the IOCONFIG block.
I/O PIO0_11 — General purpose digital input/output pin.
IAD0 — A/D converter, input 0.
OCT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 1 pins depends on the function 
selected through the IOCONFIG register block.
R/PIO1_0/
AD1/CT32B1_CAP0 33[5][2] IR — Reserved. Configure for an alternate fu nction in the IOCONFIG block.
I/O PIO1_0 — General purpose digital input/output pin.
IAD1 — A/D converter, input 1.
ICT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 34[5] OR — Reserved. Configure for an alternate functi on in the IOCONFIG block.
I/O PIO1_1 — General purpose digital input/output pin.
IAD2 — A/D converter, input 2.
OCT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/
AD3/CT32B1_MAT1 35[5] IR — Reserved. Configure for an alternate functi on in the IOCONFIG block.
I/O PIO1_2 — General purpose digital input/output pin.
IAD3 — A/D converter, input 3.
OCT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/AD4/
CT32B1_MAT2 39[5] I/O SWDIO — Serial wire debug input/output.
I/O PIO1_3 — General purpose digital input/output pin.
IAD4 — A/D converter, input 4.
OCT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/WAKEUP 40[5] I/O PIO1_4 — General purpose digital input/output pin.
IAD5 — A/D converter, input 5.
OCT32B1_MAT3 — Match output 3 for 32-bit timer 1.
IWAKEUP — Deep power-down mode wake-up pin. This pin must be pulled 
HIGH externally to enter Deep power-down mode and pulled LOW to exit 
Deep power-down mode.
PIO1_5/RTS/
CT32B0_CAP0 45[3] I/O PIO1_5 — General purpose digital input/output pin.
ORTS — Request To Send output for UART.
ICT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 46[3] I/O PIO1_6 — General purpose digital input/output pin.
IRXD — Receiver input for UART.
OCT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 47[3] I/O PIO1_7 — General purpose digital input/output pin.
OTXD — Transmitter outp ut for UART.
OCT32B0_MAT1 — Match output 1 for 32-bit timer 0. 
PIO1_8/CT16B1_CAP0 9[3] I/O PIO1_8 — General purpose digital input/output pin.
ICT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/CT16B1_MAT0 17[3] I/O PIO1_9 — General purpose digital input/output pin.
OCT16B1_MAT0 — Match output 0 for 16-bit timer 1.
Table 159. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 p ackage) …continued
Symbol Pin Type Description

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User manual Rev. 11 — 26 July 2012  145 of 538
NXP Semiconductors UM10398
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
PIO1_10/AD6/
CT16B1_MAT1 30[5] I/O PIO1_10 — General purpose digital input/output pin.
IAD6 — A/D converter, input 6.
OCT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11/AD7 42[5] I/O PIO1_11 — General purpose digital input/output pin.
IAD7 — A/D converter, input 7.
PIO2_0 to PIO2_11 I/O Port 2 — Port 2 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 2 pins depends on the function 
selected through the IOCONFIG register block.
PIO2_0/DTR/SSEL1 2[3] I/O PIO2_0 — General purpose digital input/output pin.
ODTR — Data Terminal Ready output for UART.
OSSEL1 — Slave Select for SPI1.
PIO2_1/DSR/SCK1 13[3] I/O PIO2_1 — General purpose digital input/output pin.
IDSR — Data Set Ready input for UART.
I/O SCK1 — Serial clock for SPI1.
PIO2_2/DCD/MISO1 26[3] I/O PIO2_2 — General purpose digital input/output pin.
IDCD — Data Carrier Detect input for UART.
I/O MISO1 — Master In Slave Out for SPI1.
PIO2_3/RI/MOSI1 38[3] I/O PIO2_3 — General purpose digital input/output pin.
IRI — Ring Indicator input for UART.
I/O MOSI1 — Master Out Slave In for SPI1.
PIO2_4 19[3] I/O PIO2_4 — General purpose digital input/output pin. (LPC1113/14 only).
PIO2_4 18[3] I/O PIO2_4 — General purpose digital input/output pin. (LPC11C12/C14  only).
PIO2_5 20[3] I/O PIO2_5 — General purpose digital input/output pin. LPC1113/14 only).
PIO2_5 21[3] I/O PIO2_5 — General purpose digital input/output pin. (LPC11C12/C14  only).
PIO2_6 1[3] I/O PIO2_6 — General purpose digital input/output pin.
PIO2_7 11[3] I/O PIO2_7 — General purpose digital input/output pin.
PIO2_8 12[3] I/O PIO2_8 — General purpose digital input/output pin.
PIO2_9 24[3] I/O PIO2_9 — General purpose digital input/output pin.
PIO2_10 25[3] I/O PIO2_10 — General purpose digital input/output pin.
PIO2_11/SCK0 31[3] I/O PIO2_11 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual di rection and function 
controls for each bit. The operation of port 3 pins depends on the function 
selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 
are not available.
PIO3_0/DTR 36[3] I/O PIO3_0 — General purpose digital input/output pin.
ODTR — Data Terminal Ready output for UART.
PIO3_1/DSR 37[3] I/O PIO3_1 — General purpose digital input/output pin.
IDSR — Data Set Ready input for UART.
PIO3_2/DCD 43[3] I/O PIO3_2 — General purpose digital input/output pin.
IDCD — Data Carrier Detect input for UART.
Table 159. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 p ackage) …continued
Symbol Pin Type Description

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

[1] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up

from Deep power-down mode.

[2] Serves as Deep-sleep wake-up input pin to the start logic independently of selected pin function (see the LPC111x/11C1x user manual).

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.

[6] 5 V tolerant digital I/O pad without pull-up/pull-down resistors.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

PIO3_3/RI 48[3] I/O PIO3_3 — General purpose digital input/output pin.

IRI — Ring Indicator input for UART.

PIO3_4 18[3] I/O PIO3_4 — General purpose digital input/output pin. (LPC1113/14 onl y).

PIO3_5 21[3] I/O PIO3_5 — General purpose digital input/output pin. (LPC1113/14 only).

CAN_RXD 19[6] ICAN_RXD — C_CAN receive data input. (LPC11C12/14 only).

CAN_TXD 20[6] OCAN_TXD — C_CAN transmit data output. (LPC11C12/14 only).

VDD 8; 44 I 3.3 V supply volt age to the internal regulator , the external rail, and the ADC.

Also used as the ADC reference voltage.

XTALIN 6[7] I Input to the oscillator circuit and internal clock generator circuits. Input

voltage must not exceed 1.8 V.

XTALOUT 7[7] O Output from the oscill a to r amp li fier.

VSS 5; 41 I Ground.

Table 159. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 p ackage) …continued

Symbol Pin Type Description

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
 
Table 160. LPC1111/12/13/14 pin description table (HVQFN33 package) 
Symbol Pin Type Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 0 pins depends on the function 
selected through the IOCONFIG register block.
RESET/PIO0_0 2[1][2] IRESET — External reset input: A LOW on this pin resets the device, 
causing I/O ports and peripherals to take on their default states, and 
processor execution to begin at address 0. 
I/O PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2 3[3][2] I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin 
during reset starts the ISP command handler.
OCLKOUT — Clock out pin.
OCT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 8[3][2] I/O PIO0_2 — General purpose digital input/output pin.
OSSEL0 — Slave select for SPI0.
ICT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 9[3][2] I/O PIO0_3 — General purpose digital input/output pin. 
PIO0_4/SCL 10[4][2] I/O PIO0_4 — General purpose digital input/output pin (open-drain).
I/O SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C 
Fast-mode Plus is selected in the I/O configuration register.
PIO0_5/SDA 11[4][2] I/O PIO0_5 — General purpose digital input/output pin (ope n-drain).
I/O SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C 
Fast-mode Plus is selected in the I/O configuration register.
PIO0_6/SCK0 15[3][2] I/O PIO0_6 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO0_7/CTS 16[3][2] I/O PIO0_7 — General purpose digital input/output pin (high-current output 
driver).
ICTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 17[3][2] I/O PIO0_8 — General purpose digital input/output pin.
I/O MISO0 — Master In Slave Out for SPI0.
OCT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 18[3][2] I/O PIO0_9 — General purpose digital input/output pin.
I/O MOSI0 — Master Out Slave In for SPI0.
OCT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/SCK0/
CT16B0_MAT2 19[3][2] ISWCLK — Serial wire clock.
I/O PIO0_10 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
OCT16B0_MAT2 — Match output 2 for 16-bit timer 0.
R/PIO0_11/AD0/
CT32B0_MAT3 21[5][2] IR — Reserved. Configure for an alternate func tion in the IOCONFIG block.
I/O PIO0_11 — General purpose digital input/output pin.
IAD0 — A/D converter, input 0.
OCT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 1 pins depends on the function 
selected through the IOCONFIG register block.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
R/PIO1_0/AD1/
CT32B1_CAP0 22[5][2] IR — Reserved. Configure for an alternate function in the IOCONFIG block.
I/O PIO1_0 — General purpose digital input/output pin.
IAD1 — A/D converter, input 1.
ICT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/AD2/
CT32B1_MAT0 23[5] OR — Reserved. Configure for an alternate function in the IOCONFIG block.
I/O PIO1_1 — General purpose digital input/output pin.
IAD2 — A/D converter, input 2.
OCT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/AD3/
CT32B1_MAT1 24[5] IR — Reserved. Configure for an alternate function in the IOCONFIG block.
I/O PIO1_2 — General purpose digital input/output pin.
IAD3 — A/D converter, input 3.
OCT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/AD4/
CT32B1_MAT2 25[5] I/O SWDIO — Serial wire debug input/output.
I/O PIO1_3 — General purpose digital input/output pin.
IAD4 — A/D converter, input 4.
OCT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/WAKEUP 26[5] I/O PIO1_4 — General purpose digital input/output pin.
IAD5 — A/D converter, input 5.
OCT32B1_MAT3 — Match output 3 for 32-bit timer 1.
IWAKEUP — Deep power-down mode wake-up pin. This pin must be pulled 
HIGH externally to enter Deep power-down mode and pulled  LOW to exit 
Deep power-down mode.
PIO1_5/RTS/
CT32B0_CAP0 30[3] I/O PIO1_5 — General purpose digital input/output pin.
ORTS — Request To Send output for UART.
ICT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 31[3] I/O PIO1_6 — General purpose digital input/output pin.
IRXD — Receiver input for UART.
OCT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 32[3] I/O PIO1_7 — General purpose digital input/output pin.
OTXD — Transmitter output for UART.
OCT32B0_MAT1 — Match output 1 for 32-bit timer 0. 
PIO1_8/CT16B1_CAP0 7[3] I/O PIO1_8 — General purpose digital input/output pin.
ICT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/CT16B1_MAT0 12[3] I/O PIO1_9 — General purpose digital input/output pin.
OCT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO1_10/AD6/
CT16B1_MAT1 20[5] I/O PIO1_10 — General purpose digital input/output pin.
IAD6 — A/D converter, input 6.
OCT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11/AD7 27[5] I/O PIO1_11 — General purpose digital input/output pin.
IAD7 — A/D converter, input 7.
Table 160. LPC1111/12/13/14 pin description table (HVQFN33 package)  …continued
Symbol Pin Type Description

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
[1] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up 
from Deep power-down mode.
[2] Serves as Deep-sleep wake-up input pin to the start logic independently of selected pin function (see the LPC111x/11C1x user manual).
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. 
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. 
When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant.
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded 
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
 
PIO2_0 I/O Port 2 — Port 2 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 2 pins depends on the function 
selected through the IOCONFIG register block. Pins PIO2_1 to PIO2_11 
are not available.
PIO2_0/DTR 1[3] I/O PIO2_0 — General purpose digital input/output pin.
ODTR — Data Terminal Ready output for UART.
PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 3 pins depends on the function 
selected through the IOCONFIG register block. Pins PIO3_0, PIO3_1, 
PIO3_3 and PIO3_6 to PIO3_11 are not available.
PIO3_2 28[3] I/O PIO3_2 — General purpose digital input/output pin.
PIO3_4 13[3] I/O PIO3_4 — General purpose digital input/output pin.
PIO3_5 14[3] I/O PIO3_5 — General purpose digital input/output pin.
VDD 6; 29 I 3.3 V supply voltage to the internal regulator , the external rail, and the ADC. 
Also used as the ADC reference voltage.
XTALIN 4[6] I Input to the oscillator circuit and internal clock generator circuits. Input 
voltage must not exceed 1.8 V.
XTALOUT 5[6] O Output from the oscill ator amplif ie r.
VSS 33 - Thermal pad. Connect to ground.
Table 160. LPC1111/12/13/14 pin description table (HVQFN33 package)  …continued
Symbol Pin Type Description
Table 161. LPC1112FHN24 Pin description table (HVQFN24 package)
Symbol HVQFN 
pin Start 
logic 
input
Type Reset 
state
[1]
Description
RESET/PIO0_0 1[1] yes I I; PU RESET — External reset input with 20 ns glitch filter. A 
LOW-going pulse as short as 50 ns on this pin resets the 
device, causing I/O ports and peripherals to take on their 
default states, and processor execution to begin at address 0. 
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns 
glitch filter .
PIO0_1/CLKOUT/
CT32B0_MAT2 2[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW 
level on this pin during reset starts the ISP command handler.
O-CLKOUT — Clockout pin.
O-CT32B0_MAT2 — Match outpu t 2 fo r 32 -bi t timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 7[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
PIO0_4/SCL 8[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin 
(open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output. High-current 
sink only if I2C Fast-mode Plus is selected in the I/O 
configurati o n re gi ste r.
PIO0_5/SDA 9[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin 
(open-drain). 
I/O - SDA — I2C-bus, open-drain data input/output. High-current 
sink only if I2C Fast-mode Plus is selected in the I/O 
configurati o n re gi ste r.
PIO0_6/SCK0 10[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_7/CTS 11[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin 
(high-current output driver).
I-CTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 12[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O-CT16B0_MAT0 — Match outpu t 0 fo r 16 -bi t timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 13[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O-CT16B0_MAT1 — Match outpu t 1 fo r 16 -bi t timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
14[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pi n.
I/O - SCK0 — Serial clock for SPI0.
O-CT16B0_MAT2 — Match outpu t 2 fo r 16 -bi t timer 0.
R/PIO0_11/
AD0/CT32B0_MAT3 15[5] yes I I; PU R — Reserved. Configure for an alternate function in the 
IOCONFIG block.
I/O - PIO0_11 — General purpose digital input/output pin .
I-AD0 — A/D converter, input 0.
O-CT32B0_MAT3 — Match outpu t 3 fo r 32 -bi t timer 0.
R/PIO1_0/
AD1/CT32B1_CAP0 16[5] yes I I; PU R — Reserved. Configure for an alte rnate function in the 
IOCONFIG block.
I/O - PIO1_0 — General purpose digital input/output pin.
I-AD1 — A/D converter, input 1.
I-CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 17[5] no O I; PU R — Reserved. Configure for an alternate function in the 
IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
I-AD2 — A/D converter, input 2.
O-CT32B1_MAT0 — Match outpu t 0 fo r 32 -bi t timer 1.
Table 161. LPC1112FHN24 Pin description table (HVQFN24 package)
Symbol HVQFN 
pin Start 
logic 
input
Type Reset 
state
[1]
Description

User manual Rev. 11 — 26 July 2012 151 of 538

NXP Semiconductors UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level); IA = inactive,

no pull-up/down enabled.

[2] RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep

power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

[3] Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When

configured as a ADC input, digital section of the pad is disabled.

[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

R/PIO1_2/

AD3/CT32B1_MAT1 18[5] no I I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO1_2 — General purpose digital input/output pin.

I-AD3 — A/D converter, input 3.

O-CT32B1_MAT1 — Match outpu t 1 fo r 32 -bi t timer 1.

SWDIO/PIO1_3/

AD4/CT32B1_MAT2 19[5] no I/O I; PU SWDIO — Serial wire debug input/ou tput.

I/O - PIO1_3 — General purpose digital input/output pin.

I-AD4 — A/D converter, input 4.

O-CT32B1_MAT2 — Match outpu t 2 fo r 32 -bi t timer 1.

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

20[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns

glitch filter .

I-AD5 — A/D converter, input 5.

O-CT32B1_MAT3 — Match outpu t 3 fo r 32 -bi t timer 1.

I-WAKEUP — Deep power-down mode wake-up pin with 20 ns

glitch filter. This pin must be pulled HIGH externally to enter

Deep power-down mode and pulled LOW to exit Deep

power-down mode. A LOW-going pulse as short as 50 ns

wakes up the p a rt.

PIO1_6/RXD/

CT32B0_MAT0 23[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.

I-RXD — Receiver input for UART.

O-CT32B0_MAT0 — Match outpu t 0 fo r 32 -bi t timer 0.

PIO1_7/TXD/

CT32B0_MAT1 24[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.

O-TXD — Transmitter output for UART.

O-CT32B0_MAT1 — Match outpu t 1 fo r 32 -bi t timer 0.

PIO1_8/

CT16B1_CAP0 6[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin.

I-CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

XTALIN 4[7] - I - Input to the osci llator circuit and internal clock generator

circuits. Input voltage must not exceed 1.8 V.

VDD 5; 22 - I - 3.3 V supply vol tage to the internal regulator, the external rail,

and the ADC. Also used as the ADC reference voltage.

VSS 3; 21 - I - Ground.

Table 161. LPC1112FHN24 Pin description table (HVQFN24 package)

Symbol HVQFN

pin Start

logic

input

Type Reset

state

[1]

Description

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
 
Table 162. LPC11C24/C22 pin description table (LQFP48 package)
Symbol Pin Type Description
PIO0_0 to PIO0_11 Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for 
each bit. The operation of port 0 pins depends on the function selected through the 
IOCONFIG register block.
RESET/PIO0_0 3[1] IRESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 
50 ns on this pin resets the device, causing I/O ports and peripherals to take on their 
default states, and processor execution to begin at address 0. 
I/O PIO0_0 — General purpose dig i tal input/output pin with 10 ns glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 4[3] I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during 
reset starts the flash ISP command handler via UART (if PIO0_3 is HIGH) or via 
C_CAN (if PIO0_3 is LOW). 
OCLKOUT — Clockout pin.
OCT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 10[3] I/O PIO0_2 — General purpose digital input/output pin. 
I/O SSEL0 — Slave Select for SPI0.
ICT16B0_CAP0 — Ca pture input 0 for 16-bit timer 0.
PIO0_3 14[3] I/O PIO0_3 — General purpose digital input/output pin. This pin is monitored during reset: 
Together with a LOW level on pin PIO0_1, a LOW level starts the flash ISP command 
handler via C_CAN and a HIGH level starts the flash ISP command handler via UART. 
PIO0_4/SCL 15[4] I/O PIO0_4 — General purpose digital input/outp ut pin (open-drain). 
I/O SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode 
Plus is selected in the I/O configuration register.
PIO0_5/SDA 16[4] I/O PIO0_5 — General purpose digital input/outp ut pin (open-drain). 
I/O SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode 
Plus is selected in the I/O configuration register.
PIO0_6/SCK0 23[3] I/O PIO0_6 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO0_7/CTS 24[3] I/O PIO0_7 — General purpose digital input/output pin (high-current output dri ve r).
ICTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 27[3] I/O PIO0_8 — General purpose digital input/output pin.
I/O MISO0 — Master In Slave Out for SPI0.
OCT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 28[3] I/O PIO0_9 — General purpose digital input/output pin.
I/O MOSI0 — Master Out Slave In for SPI0.
OCT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
29[3] ISWCLK — Serial wire clock.
I/O PIO0_10 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
OCT16B0_MAT2 — Match output 2 for 16-bit timer 0.
R/PIO0_11/
AD0/
CT32B0_MAT3
32[5] -R — Reserved. Configure for an alternate function in the IOCONFIG block.
I/O PIO0_11 — General purpose digital input/output pin.
IAD0 — A/D converter, input 0.
OCT32B0_MAT3 — Match output 3 for 32-bit timer 0.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
PIO1_0 to PIO1_11 Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for 
each bit. The operation of port 1 pins depends on the function selected through the 
IOCONFIG register block.
R/PIO1_0/AD1/
CT32B1_CAP0 33[5] -R — Reserved. Configure for an alternate  function in the IOCONFIG block.
I/O PIO1_0 — General purpose digital input/ou tput pin.
IAD1 — A/D converter, input 1.
ICT32B1_CAP0 — Ca pture input 0 for 32-bit timer 1.
R/PIO1_1/AD2/
CT32B1_MAT0 34[5] -R — Reserved. Configure for an alternate function in the IOCONFIG block.
I/O PIO1_1 — General purpose digital input/ou tput pin.
IAD2 — A/D converter, input 2.
OCT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/AD3/
CT32B1_MAT1 35[5] -R — Reserved. Configure for an alternate function in the IOCONFIG block.
I/O PIO1_2 — General purpose digital input/ou tput pin.
IAD3 — A/D converter, input 3.
OCT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/
AD4/
CT32B1_MAT2
39[5] I/O SWDIO — Serial wire debug input/output.
I/O PIO1_3 — General purpose digital input/ou tput pin.
IAD4 — A/D converter, input 4.
OCT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/
WAKEUP
40[5] I/O PIO1_4 — General purpose dig i tal input/output pin with 10 ns glitch filter.
IAD5 — A/D converter, input 5.
OCT32B1_MAT3 — Match output 3 for 32-bit timer 1.
IWAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter. This pin 
must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to  
exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the 
part.
PIO1_5/RTS/
CT32B0_CAP0 45[3] I/O PIO1_5 — General purpose digital input/output pin.
ORTS — Request To Send outpu t for UART.
ICT32B0_CAP0 — Ca pture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 46[3] I/O PIO1_6 — General purpose digital input/output pin.
IRXD — Receiver input for UART.
OCT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 47[3] I/O PIO1_7 — General purpose digital input/output pin.
OTXD — Transmitter output for UART.
OCT32B0_MAT1 — Match output 1 for 32-bit timer 0. 
PIO1_8/
CT16B1_CAP0 9[3] I/O PIO1_8 — General purpose digital input/output pin.
ICT16B1_CAP0 — Ca pture input 0 for 16-bit timer 1.
PIO1_10/AD6/
CT16B1_MAT1 30[5] I/O PIO1_10 — General purpose digital input/output pin.
IAD6 — A/D converter, input 6.
OCT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11/AD7 42[5] I/O PIO1_11 — General purpose digital input/output pin.
IAD7 — A/D converter, input 7.
Table 162. LPC11C24/C22 pin description table (LQFP48 package)
Symbol Pin Type Description

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
PIO2_0 to PIO2_11 Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for 
each bit. The operation of port 2 pins depends on the function selected through the 
IOCONFIG register block.
PIO2_0/DTR/
SSEL1 2[3] I/O PIO2_0 — General purpose digital input/output pin.
I/O DTR — Data Terminal Ready output for UART.
I/O SSEL1 — Slave Select for SPI1.
PIO2_1/DSR/SCK1 13[3] I/O PIO2_1 — General purpose digital input/output pin.
IDSR — Data Set Ready input for UART.
I/O SCK1 — Serial clock for SPI1.
PIO2_2/DCD/
MISO1 26[3] I/O PIO2_2 — General purpose digital input/ou tput pin.
IDCD — Data Carrier Detect input for UART.
I/O MISO1 — Master In Slave Out for SPI1.
PIO2_3/RI/MOSI1 38[3] I/O PIO2_3 — General purpose digital input/output pin.
IRI — Ring Indicator input for UART.
I/O MOSI1 — Master Out Slave In for SPI1.
PIO2_6 1[3] I/O PIO2_6 — General purpose digital input/output pin.
PIO2_7 11[3] I/O PIO2_7 — General purpose digital input/output pin.
PIO2_8 12[3] I/O PIO2_8 — General purpose digital input/ou tput pin.
PIO2_10 25[3] I/O PIO2_10 — General purpose digital input/output pin.
PIO2_11/SCK0 31[3] I/O PIO2_11 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO3_0 to PIO3_3 Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for 
each bit. The operation of port 3 pins depends on the function selected through the 
IOCONFIG register block. Pins PIO3_4 to PIO3_11 are no t available.
PIO3_0/DTR 36[3] I/O PIO3_0 — General purpose dig ital input/ou tput pin.
ODTR — Data Terminal Ready output for UART.
PIO3_1/DSR 37[3] I/O PIO3_1 — General purpose digital input/ou tput pin.
IDSR — Data Set Ready input for UART.
PIO3_2/DCD 43[3] I/O PIO3_2 — General purpose digital input/ou tput pin.
IDCD — Data Carrier Detect input for UART.
PIO3_3/RI 48[3] I/O PIO3_3 — General purpose digital input/ou tput pin.
IRI — Ring Indicator input for UART.
CANL 18 I/O LOW-level CAN bus line.
CANH 19 I/O HIGH-level CAN bus line.
STB 22 I Silent mode control input for CAN transceiver (LOW = Normal mode, HIGH = silent 
mode).
VDD_CAN 17 - Supply voltage for I/O level of CAN transceiver.
VCC 20 - Supply voltage for CAN transceiver.
GND 21 - Ground for CAN transceiver.
VDD 8;44 I Supply voltage to the internal regulator, the external rail, and the ADC. Also used as 
the ADC reference voltage.
Table 162. LPC11C24/C22 pin description table (LQFP48 package)
Symbol Pin Type Description

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
[1] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up 
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.
[2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[3] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. 
[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. 
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.
[5] 5 V tolerant digital I/O pad without pull-up/pull-down resistors.
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded 
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
 
XTALIN 6[7] I Input to the oscillator circuit and internal clock generator circuits. Input voltage must 
not exceed 1.8 V.
XTALOUT 7[7] O Output fro m the oscil lator amplifie r.
VSS 5; 41 I Groun d.
Table 162. LPC11C24/C22 pin description table (LQFP48 package)
Symbol Pin Type Description
Table 163. LPC11D1 4 pi n description table (LQFP100 package)
Symbol Pin Start 
logic 
input
Type Reset 
state
[1]
Description
Microcontroller pins
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and 
function controls for each bit. The operation of port 0 pins 
depends on the function selected  through the IOCONFIG 
register block.
RESET/PIO0_0 6[1] yes I I; PU RESET — External reset input with 20 ns glitch filter. A 
LOW-going pulse as short as 50 ns on this pin resets the 
device, causing I/O ports and peripherals to take on their 
default states, and processor execution to begin at address 0. 
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns 
glitch filter .
PIO0_1/CLKOUT/
CT32B0_MAT2 7[3] yes I/O I; PU PIO0_1 — General purpose digi tal input/output pin. A LOW 
level on this pin during reset starts the ISP command handler.
O-CLKOUT — Clockout pin.
O-CT32B0_MAT2 — Match outpu t 2 fo r 32 -bi t timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 13[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 17[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. 
PIO0_4/SCL 18[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin 
(open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output. High-current 
sink only if I2C Fast-mode Plus is selected in the I/O 
configurati o n re gi ste r.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
PIO0_5/SDA 19[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin 
(open-drain). 
I/O - SDA — I2C-bus, open-drain data input/output. High-current 
sink only if I2C Fast-mode Plus is selected in the I/O 
configurati o n re gi ste r.
PIO0_6/SCK0 25[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_7/CTS 26[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin 
(high-current output driver).
I-CTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 81[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O-CT16B0_MAT0 — Match outpu t 0 fo r 16 -bi t timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 82[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O-CT16B0_MAT1 — Match outpu t 1 fo r 16 -bi t timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
83[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O-CT16B0_MAT2 — Match outpu t 2 fo r 16 -bi t timer 0.
R/PIO0_11/
AD0/CT32B0_MAT3 86[5] yes I I; PU R — Reserved. Configure for an alternate function in the 
IOCONFIG block.
I/O - PIO0_11 — General purpo se digital input/output pin.
I-AD0 — A/D converter, input 0.
O-CT32B0_MAT3 — Match outpu t 3 fo r 32 -bi t timer 0.
PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and 
function controls for each bit. The operation of port 1 pins 
depends on the function selected  through the IOCONFIG 
register block.
R/PIO1_0/
AD1/CT32B1_CAP0 87[5] yes I I; PU R — Reserved. Configure for an a lternate function in the 
IOCONFIG block.
I/O - PIO1_0 — General purpose digital input/output pin.
I-AD1 — A/D converter, input 1.
I-CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 88[5] no O I; PU R — Reserved. Configure for an alternate function in the 
IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
I-AD2 — A/D converter, input 2.
O-CT32B1_MAT0 — Match outpu t 0 fo r 32 -bi t timer 1.
Table 163. LPC11D1 4 pi n description table (LQFP100 package) …continued
Symbol Pin Start 
logic 
input
Type Reset 
state
[1]
Description

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
R/PIO1_2/
AD3/CT32B1_MAT1 89[5] no I I; PU R — Reserved. Configure fo r an alternate function in the 
IOCONFIG block.
I/O - PIO1_2 — General purpose digital input/output pin.
I-AD3 — A/D converter, input 3.
O-CT32B1_MAT1 — Match outpu t 1 fo r 32 -bi t timer 1.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 93[5] no I/O I; PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I-AD4 — A/D converter, input 4.
O-CT32B1_MAT2 — Match outpu t 2 fo r 32 -bi t timer 1.
PIO1_4/AD5/
CT32B1_MAT3/
WAKEUP
94[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns 
glitch filter .
I-AD5 — A/D converter, input 5.
O-CT32B1_MAT3 — Match outpu t 3 fo r 32 -bi t timer 1.
I-WAKEUP — Deep power-down mode wake-up pin with 20 ns 
glitch filter. This pin must be pulled HIGH externally to enter 
Deep power-down mode and pulled LOW to exit Deep 
power-down mode. A LOW-going pulse as short as 50 ns 
wakes up the p a rt.
PIO1_5/RTS/
CT32B0_CAP0 99[3] no I/O I; PU PIO1_5 — General purpose digital input/output pin.
O-RTS — Request To Send output for UART.
I-CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 100[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.
I-RXD — Receiver input for UART.
O-CT32B0_MAT0 — Match outpu t 0 fo r 32 -bi t timer 0.
PIO1_7/TXD/
CT32B0_MAT1 1[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.
O-TXD — Transmitter output for UART.
O-CT32B0_MAT1 — Match outpu t 1 fo r 32 -bi t timer 0. 
PIO1_8/
CT16B1_CAP0 12[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin.
I-CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/
CT16B1_MAT0 20[3] no I/O I; PU PIO1_9 — General purpose digital input/output pin.
O-CT16B1_MAT0 — Match outpu t 0 fo r 16 -bi t timer 1.
PIO1_10/AD6/
CT16B1_MAT1 84[5] no I/O I; PU PIO1_10 — General purpose digital input/ou tput pin.
I-AD6 — A/D converter, input 6.
O-CT16B1_MAT1 — Match outpu t 1 fo r 16 -bi t timer 1.
PIO1_11/AD7 96[5] no I/O I; PU PIO1_11 — General purpose digital input/output pin.
I-AD7 — A/D converter, input 7.
PIO2_0 to PIO2_11 I/O Port 2 — Port 2 is a 12-bit I/O port with individual direction and 
function controls for each bit. The operation of port 2 pins 
depends on the function selected  through the IOCONFIG 
register block.
Table 163. LPC11D1 4 pi n description table (LQFP100 package) …continued
Symbol Pin Start 
logic 
input
Type Reset 
state
[1]
Description

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
PIO2_0/DTR/SSEL1 5[3] no I/O I; PU PIO2_0 — General purpose digital input/output pin.
O-DTR — Data Terminal Ready output for UART.
I/O - SSEL1 — Slave Select for SPI1.
PIO2_1/DSR/SCK1 16[3] no I/O I; PU PIO2_1 — General purpose digital input/output pin.
I-DSR — Data Set Ready input for UART.
I/O - SCK1 — Serial clock for SPI1.
PIO2_2/DCD/MISO1 80[3] no I/O I; PU PIO2_2 — General purpose digital input/output pin.
I-DCD — Data Carrier Detect input for UART.
I/O - MISO1 — Master In Slave Out for SPI1.
PIO2_3/RI/MOSI1 92[3] no I/O I; PU PIO2_3 — General purpose digital input/output pin.
I-RI — Ring Indicator input for UART.
I/O - MOSI1 — Master Out Slave In for SPI1.
PIO2_4 22[3] no I/O I; PU PIO2_4 — General purpose digital input/output pin.
PIO2_5 23[3] no I/O I; PU PIO2_5 — General purpose digital input/output pin.
PIO2_6 4[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin.
PIO2_7 14[3] no I/O I; PU PIO2_7 — General purpose digital input/output pin.
PIO2_8 15[3] no I/O I; PU PIO2_8 — General purpose digital input/output pin.
PIO2_9 27[3] no I/O I; PU PIO2_9 — General purpose digital input/output pin.
PIO2_10 28[3] no I/O I; PU PIO2_10 — General purpose digital input/output pin.
PIO2_11/SCK0 85[3] no I/O I; PU PIO2_11 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and 
function controls for each bit. The operation of port 3 pins 
depends on the function selected  through the IOCONFIG 
register block. Pins PIO3_6 to PIO3_11 are not available.
PIO3_0/DTR 90[3] no I/O I; PU PIO3_0 — General purpose digital input/output pin.
O-DTR — Data Terminal Ready output for UART.
PIO3_1/DSR 91[3] no I/O I; PU PIO3_1 — General purpose digital input/output pin.
I-DSR — Data Set Ready input for UART.
PIO3_2/DCD 97[3] no I/O I; PU PIO3_2 — General purpose digital input/output pin.
I-DCD — Data Carrier Detect input for UART.
PIO3_3/RI 2[3] no I/O I; PU PIO3_3 — General purpose digital input/output pin.
I-RI — Ring Indicator input for UART.
PIO3_4 21[3] no I/O I; PU PIO3_4 — General purpose digital input/output pin.
PIO3_5 24[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin.
VDD 11; 98 - I - 3.3 V supply voltage to the internal regulator, the external rail, 
and the ADC. Also used as the ADC reference voltage.
XTALIN 9[7] - I - Input to the oscillator circuit and internal clock generator 
circuits. Input voltage must not exceed 1.8 V.
XTALOUT 10[7] - O - Output from the oscillator amplifier.
VSS 8; 95 - I - Ground.
Table 163. LPC11D1 4 pi n description table (LQFP100 package) …continued
Symbol Pin Start 
logic 
input
Type Reset 
state
[1]
Description

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
LCD display pins
S0 46 - O VLCD[7] LCD segment output.
S1 47 - O VLCD[7] LCD segment output.
S2 48 - O VLCD[7] LCD segment output.
S3 49 - O VLCD[7] LCD segment output.
S4 50 - O VLCD[7] LCD segment output.
S5 51 - O VLCD[7] LCD segment output.
S6 52 - O VLCD[7] LCD segment output.
S7 53 - O VLCD[7] LCD segment output.
S8 54 - O VLCD[7] LCD segment output.
S9 55 - O VLCD[7] LCD segment output.
S10 56 - O VLCD[7] LCD segment output.
S11 57 - O VLCD[7] LCD segment output.
S12 58 - O VLCD[7] LCD segment output.
S13 59 - O VLCD[7] LCD segment output.
S14 60 - O VLCD[7] LCD segment output.
S15 61 - O VLCD[7] LCD segment output.
S16 62 - O VLCD[7] LCD segment output.
S17 63 - O VLCD[7] LCD segment output.
S18 64 - O VLCD[7] LCD segment output.
S19 65 - O VLCD[7] LCD segment output.
S20 66 - O VLCD[7] LCD segment output.
S21 67 - O VLCD[7] LCD segment output.
S22 68 - O VLCD[7] LCD segment output.
S23 69 - O VLCD[7] LCD segment output.
S24 70 - O VLCD[7] LCD segment output.
S25 71 - O VLCD[7] LCD segment output.
S26 72 - O VLCD[7] LCD segment output.
S27 73 - O VLCD[7] LCD segment output.
S28 74 - O VLCD[7] LCD segment output.
S29 75 - O VLCD[7] LCD segment output.
S30 76 - O VLCD[7] LCD segment output.
S31 77 - O VLCD[7] LCD segment output.
S32 78 - O VLCD[7] LCD segment output.
S33 79 - O VLCD[7] LCD segment output.
S34 29 - O VLCD[7] LCD segment output.
S35 30 - O VLCD[7] LCD segment output.
S36 31 - O VLCD[7] LCD segment output.
S37 32 - O VLCD[7] LCD segment output.
Table 163. LPC11D1 4 pi n description table (LQFP100 package) …continued
Symbol Pin Start 
logic 
input
Type Reset 
state
[1]
Description

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
[1] Pin state at  reset for default function:  I =  Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD lev el (VDD = 3.3 V)); 
IA = inactive, no pull-up/down enabled.
[2] RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep 
power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. 
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. 
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. 
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded 
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
[7] See the LPC11D4 data sheet.
S38 33 - O VLCD[7] LCD segment output.
S39 34 - O VLCD[7] LCD segment output.
BP0 42 - O VLCD[7] LCD backplane output.
BP1 44 - O VLCD[7] LCD backplane output.
BP2 43 - O VLCD[7] LCD backplane output.
BP3 45 - O VLCD[7] LCD backplane output.
LCD_SDA 35 - I/O [7] I2C-bus serial data input/output.
LCD_SCL 36 - I/O [7] I2C-bus serial clock input.
SYNC 37 - I/O [7] Cascade synchronization input/output.
CLK 38 - I/O [7] External clock input/output.
VDD(LCD) 39 - - - 1.8 V to 5.5 V power supply: Power supply voltage for the 
PCF8576D.
VSS(LCD) 40 - - - LCD ground.
VLCD 41 - - - LCD power supply; LCD voltage.
n.c. 3 - - - Not connected.
Table 163. LPC11D1 4 pi n description table (LQFP100 package) …continued
Symbol Pin Start 
logic 
input
Type Reset 
state
[1]
Description

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User manual Rev. 11 — 26 July 2012  161 of 538
 
10.1 How to read this chapter
This chapter describes the small pin packages for the LPC111x parts in TSSOP, DIP, and 
SO packages.
 
10.2 Pin configuration (LPC1110/11/12)
 
UM10398
Chapter 10: LPC111x Pin configuration (LPC1100L series, 
TSSOP, DIP, SO packages)
Rev. 11 — 26 July 2012 User manual
Table 164. LPC11xx pin configurations for 20-pin and 28-pin packages
Part SO20 TSSOP20 TSSOP28 DIP28
LPC1110FD20 Pin configuration Figure 22 ---
Pin description Table 165 ---
LPC1111FDH20/002 Pin configuration - Figure 23 --
Pin description - Table 165 --
LPC1112FD20/102 Pin configuration Figure 22 ---
Pin description Table 165 ---
LPC1112 FDH 20/102 Pin configuration - Figure 24 --
Pin description - Table 166 --
LPC1112 FDH 28/102 Pin configuration - - Figure 25 -
Pin description - - Table 167 -
LPC1114 FDH 28/102 Pin configuration - - Figure 25 -
Pin description - - Table 167 -
LPC1114FN28/102 Pin configuration - - - Figure 26
Pin description - - - Table 167
Fig 22. Pin configuration SO20 package
LPC1110FD20
LPC1112FD20/
102
PIO0_8/MISO0/CT16B0_MAT0 PIO0_4/SCL
PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0
SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_1/CLKOUT/CT32B0_MAT2
R/PIO0_11/AD0/CT32B0_MAT3 RESET/PIO0_0
PIO0_5/SDA VSS
PIO0_6/SCK0 VDD
R/PIO1_0/AD1/CT32B1_CAP0 XTALIN
R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT
R/PIO1_2/AD3/CT32B1_MAT1 PIO1_7/TXD/CT32B0_MAT1
SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_6/RXD/CT32B0_MAT0
002aag595
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19

User manual Rev. 11 — 26 July 2012 162 of 538

NXP Semiconductors UM10398

Chapter 10: LPC111x Pin configuration (LPC1100L series , TSSOP, DIP,

Fig 23. Pin configuration TSSOP20 package with I2C-bus pins

LPC1111FDH20/002

PIO0_8/MISO0/CT16B0_MAT0 PIO0_4/SCL

PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_1/CLKOUT/CT32B0_MAT2

R/PIO0_11/AD0/CT32B0_MAT3 RESET/PIO0_0

PIO0_5/SDA VSS

PIO0_6/SCK0 VDD

R/PIO1_0/AD1/CT32B1_CAP0 XTALIN

R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT

R/PIO1_2/AD3/CT32B1_MAT1 PIO1_7/TXD/CT32B0_MAT1

SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_6/RXD/CT32B0_MAT0

002aag596

Table 165. LPC1110/11/12 pin des cription table (SO20 and TSSOP20 package with I2C-bus pins )

Symbol

Pin SO20/

TSSOP20

Start

logic

input

Type Reset

state

[1]

Description

PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual directi on and

function controls for each bit. The operation of port 0 pins depends

on the function selected through the IOCONFIG register block.

RESET/PIO0_0 17 [2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going

pulse as short as 50 ns on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and processor

execution to begin at address 0.

I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch

filter.

PIO0_1/CLKOUT/

CT32B0_MAT2 18 [3] ye s I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on

this pin during reset starts the ISP command handler.

O- CLKOUT — Clockout pin.

O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2/SSEL0/

CT16B0_CAP0 19 [3] yes I /O I; PU PIO0_2 — General purpose digital input/output pin.

I/O - SSEL0 — Slave Select for SPI0.

I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_4/SCL 20 [4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink

only if I2C Fast-mode Plus is selected in the I/O configuration

PIO0_5/SDA 5 [4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain).

I/O - SDA — I2C-bus, open-drain data input/output. High-current sink

only if I2C Fast-mode Plus is selected in the I/O configuration

PIO0_6/SCK0 6 [3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

PIO0_8/MISO0/

CT16B0_MAT0 1[3] ye s I/O I; PU PIO0_8 — General purpose digital input/output pin.

I/O - MISO0 — Master In Slave Out for SPI0.

O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

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User manual Rev. 11 — 26 July 2012  163 of 538
NXP Semiconductors UM10398
Chapter 10: LPC111x Pin configuration (LPC1100L series , TSSOP, DIP,
PIO0_9/MOSI0/
CT16B0_MAT1 2[3] ye s I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
3[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
R/PIO0_11/
AD0/CT32B0_MAT3 4[5] yes I I; PU R — Reserved. Configure for an alternate fu nction in the 
IOCONFIG block.
I/O - PIO0_11 — General purpose digital input/output pin.
I- AD0 — A/D converter, input 0.
O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_7 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and 
function controls for each bit. The operation of port 1 pins depends 
on the function selected through the IOCONFIG register block.
R/PIO1_0/
AD1/CT32B1_CAP0 7[5] yes I I; PU R — Reserved. Configure for an alternate function in the 
IOCONFIG block.
I/O - PIO1_0 — General purpose digital input/output pin.
I- AD1 — A/D converter, input 1.
I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 8[5] no O I; PU R — Reserved. Configure for an alternate function in the 
IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
I- AD2 — A/D converter, input 2.
O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/
AD3/CT32B1_MAT1 9[5] no I I; PU R — Reserved. Configure for an alternate function in the 
IOCONFIG block.
I/O - PIO1_2 — General purpose digital input/output pin.
I- AD3 — A/D converter, input 3.
O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 10 [5] no I/O I; PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I- AD4 — A/D converter, input 4.
O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_6/RXD/
CT32B0_MAT0 11 [3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.
I- RXD — Receiver input for UART.
O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 12 [3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.
O- TXD — Transmitter output for UART.
O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.  
Table 165. LPC1110/11/12 pin des cription  table (SO20 and TSSOP20 package with I2C-bus pins ) …continued
Symbol
Pin SO20/
TSSOP20 
Start 
logic 
input
Type Reset 
state
[1]
Description

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NXP Semiconductors UM10398

Chapter 10: LPC111x Pin configuration (LPC1100L series , TSSOP, DIP,

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level ); IA = inactive,

no pull-up/down enabled.

[2] RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep

power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant .

[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

10.3 Pin configuration (LPC1112)

VDD 15 - - 3.3 V supply voltage to the internal regulator, the external rail, and

the ADC. Also used as the ADC reference voltage.

XTALIN 14 [6] - I - Inpu t to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

XTALOUT 13 [6] - O - Output from the oscillator amplifier.

VSS 16 - - Ground.

Table 165. LPC1110/11/12 pin des cription table (SO20 and TSSOP20 package with I2C-bus pins ) …continued

Symbol

Pin SO20/

TSSOP20

Start

logic

input

Type Reset

state

[1]

Description

Fig 24. Pin configuration TSSOP20 package with VDDA and VSSA pins

LPC1112FDH20/102

PIO0_8/MISO0/CT16B0_MAT0 PIO0_3

PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_1/CLKOUT/CT32B0_MAT2

R/PIO0_11/AD0/CT32B0_MAT3 RESET/PIO0_0

VDDA VSS

VSSA VDD

R/PIO1_0/AD1/CT32B1_CAP0 XTALIN

R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT

R/PIO1_2/AD3/CT32B1_MAT1 PIO1_7/TXD/CT32B0_MAT1

SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_6/RXD/CT32B0_MAT0

002aag597

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User manual Rev. 11 — 26 July 2012  165 of 538
NXP Semiconductors UM10398
Chapter 10: LPC111x Pin configuration (LPC1100L series , TSSOP, DIP,
 
Table 166. LPC1112 pin description table (TSSOP20 with VDDA and VSSA pins)
Symbol
Pin TSSOP20
Start 
logic 
input
Type Reset 
state
[1]
Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with  individual direction 
and function controls for each bit. The operation of port 0 pins 
depends on the function selected throug h the IOCONFIG 
register block.
RESET/PIO0_0 17 [2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A 
LOW-going pulse as short as 50 ns on this pin resets the 
device, causing I/O ports and peripherals to take on their 
default states, and processor execution to begin at address 0. 
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns 
glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 18 [3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW 
level on this pin during reset starts the ISP command handler.
O-CLKOUT — Clockout pin.
O-CT32B0_MAT2 — Match ou tp ut 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 19 [3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 20 [3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. 
PIO0_8/MISO0/
CT16B0_MAT0 1[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O-CT16B0_MAT0 — Match ou tp ut 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 2[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O-CT16B0_MAT1 — Match ou tp ut 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
3[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O-CT16B0_MAT2 — Match ou tp ut 2 for 16-bit timer 0.
R/PIO0_11/
AD0/CT32B0_MAT3 4[4] yes I I; PU R — Reserved. Configure for an alternate function in the 
IOCONFIG block.
I/O - PIO0_11 — General purpose digital input/output pin.
I-AD0 — A/D con ve r ter, input 0.
O-CT32B0_MAT3 — Match ou tp ut 3 for 32-bit timer 0.
PIO1_0 to PIO1_7 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction 
and function controls for each bit. The operation of port 1 pins 
depends on the function selected throug h the IOCONFIG 
register block.

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 11 — 26 July 2012  166 of 538
NXP Semiconductors UM10398
Chapter 10: LPC111x Pin configuration (LPC1100L series , TSSOP, DIP,
[1] Pin state at reset for default function: I = Input; O =  Output; PU = internal pull-up enabled (pins pulled up to full VDD level ); IA  = inactive, 
no pull-up/down enabled.
[2] RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep 
power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. 
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
R/PIO1_0/
AD1/CT32B1_CAP0 7[4] yes I I; PU R — Reserved. Configure for an  a lternate function in the 
IOCONFIG block.
I/O - PIO1_0 — General purpose digital input/output pin.
I-AD1 — A/D con ve r ter, input 1.
I-CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 8[4] no O I; PU R — Reserved. Configure for an alternate function in the 
IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
I-AD2 — A/D con ve r ter, input 2.
O-CT32B1_MAT0 — Match ou tp ut 0 for 32-bit timer 1.
R/PIO1_2/
AD3/CT32B1_MAT1 9[4] no I I; PU R — Reserved. Configure for an alternate function in  the 
IOCONFIG block.
I/O - PIO1_2 — General purpose digital input/output pin.
I-AD3 — A/D con ve r ter, input 3.
O-CT32B1_MAT1 — Match ou tp ut 1 for 32-bit timer 1.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 10 [4] no I/O I; PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I-AD4 — A/D con ve r ter, input 4.
O-CT32B1_MAT2 — Match ou tp ut 2 for 32-bit timer 1.
PIO1_6/RXD/
CT32B0_MAT0 11 [3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.
I-RXD — Receiver input for UART.
O-CT32B0_MAT0 — Match ou tp ut 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 12 [3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.
O-TXD — T ransmitter output for UART.
O-CT32B0_MAT1 — Match ou tp ut 1 for 32-bit timer 0.  
VDD 15 - I - 3.3 V supply voltage to the internal regulator and the external 
rail.
VDDA 5 - I - 3.3 V supply voltage to the ADC. Also used as the ADC 
reference voltage.
XTALIN 14 [5] - I - Input to  the oscillator circuit and internal clock generator 
circuits. Input voltage must not exceed 1.8 V.
XTALOUT 13 [5] - O - Output from the oscillator amplifier.
VSS 16 - I - Ground.
VSSA 6 - I - Analog ground.
Table 166. LPC1112 pin description table (TSSOP20 with VDDA and VSSA pins) …continued
Symbol
Pin TSSOP20
Start 
logic 
input
Type Reset 
state
[1]
Description

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NXP Semiconductors UM10398

Chapter 10: LPC111x Pin configuration (LPC1100L series , TSSOP, DIP,

[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.

[5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

10.4 Pin configuration (LPC1112/14)

Fig 25. Pin configuration TSSOP28 package

LPC1112FDH28/102

LPC1114FDH28/102

PIO0_8/MISO0/CT16B0_MAT0 PIO0_7/CTS

PIO0_9/MOSI0/CT16B0_MAT1 PIO0_4/SCL

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_3

R/PIO0_11/AD0/CT32B0_MAT3 PIO0_2/SSEL0/CT16B0_CAP0

PIO0_5/SDA PIO0_1/CLKOUT/CT32B0_MAT2

PIO0_6/SCK0 RESET/PIO0_0

VDDA VSS

VSSA VDD

R/PIO1_0/AD1/CT32B1_CAP0 XTALIN

R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT

R/PIO1_2/AD3/CT32B1_MAT1 PIO1_9/CT16B1_MAT0

SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_8/CT16B1_CAP0

PIO1_4/AD5/CT32B1_MAT3/WAKEUP PIO1_7/TXD/CT32B0_MAT1

PIO1_5/RTS/CT32B0_CAP0 PIO1_6/RXD/CT32B0_MAT0

002aag598

Fig 26. Pin configuration DIP28 package

LPC1114FN28/

102

PIO0_8/MISO0/CT16B0_MAT0 PIO0_7/CTS

PIO0_9/MOSI0/CT16B0_MAT1 PIO0_4/SCL

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_3

R/PIO0_11/AD0/CT32B0_MAT3 PIO0_2/SSEL0/CT16B0_CAP0

PIO0_5/SDA PIO0_1/CLKOUT/CT32B0_MAT2

PIO0_6/SCK0 RESET/PIO0_0

DDA

SSA

R/PIO1_0/AD1/CT32B1_CAP0 XTALIN

R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT

R/PIO1_2/AD3/CT32B1_MAT1 PIO1_9/CT16B1_MAT0

SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_8/CT16B1_CAP0

PIO1_4/AD5/CT32B1_MAT3/WAKEUP PIO1_7/TXD/CT32B0_MAT1

PIO1_5/RTS/CT32B0_CAP0 PIO1_6/RXD/CT32B0_MAT0

002aag599

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User manual Rev. 11 — 26 July 2012  168 of 538
NXP Semiconductors UM10398
Chapter 10: LPC111x Pin configuration (LPC1100L series , TSSOP, DIP,
 
Table 167. LPC1112/14 pin description table (TSSOP28 and DIP28 packages)
Symbol
Pin TSSOP28/
DIP28
Start 
logic 
input
Type Reset 
state
[1]
Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and 
function controls for each bit. The operation of port 0 pins depends 
on the function selected through the IOCONFIG register block.
RESET/PIO0_0 23 [2] yes I I; PU RESET — External reset input with 20 ns glitch filter . A LOW-going 
pulse as short as 50 ns on this pin resets the device, causing I/O 
ports and peripherals to take on their default states, and processor 
execution to begin at address 0. 
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns 
glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 24 [3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level 
on this pin during reset starts the ISP command handler.
O- CLKOUT — Clockout pin.
O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 25 [3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit ti mer 0.
PIO0_3 26 [3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. 
PIO0_4/SCL 27 [4] yes I/O I; IA PIO0_4 — General  purpose digital input/output pin (open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink 
only if I2C Fast-mode Plus is selected in the I/O configuration 
register.
PIO0_5/SDA 5 [4] yes I/O I; IA PIO0_5 — General purpose di gital input/output pin (open-drain). 
I/O - SDA — I2C-bus, open-drain data input/output. High - current sink 
only if I2C Fast-mode Plus is selected in the I/O configuration 
register.
PIO0_6/SCK0 6 [3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_7/CTS 28 [3] yes I/O I; PU PIO0_7 — Ge neral purpose digital input/output pin (high-current 
output driver).
I-CTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 1[3] yes I/O I; PU PIO0_8 — General purpose digital input/o utput pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 2[3] yes I/O I; PU PIO0_9 — General purpose digital input/o utput pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
3[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_1 0 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

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Chapter 10: LPC111x Pin configuration (LPC1100L series , TSSOP, DIP,

R/PIO0_11/

AD0/CT32B0_MAT3 4[5] yes I I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO0_11 — General purpose di gital input/output pin.

I-AD0 — A/D converter, input 0.

O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

PIO1_0 to PIO1_9 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 1 pins depends

on the function selected through the IOCONFIG register block.

R/PIO1_0/

AD1/CT32B1_CAP0 9[5] yes I I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO1_0 — General purpose digital input/output pin.

I-AD1 — A/D converter, input 1.

I-CT32B1_CAP0 — Capture input 0 for 32-bit ti mer 1.

R/PIO1_1/

AD2/CT32B1_MAT0 10 [5] no O I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO1_1 — General purpose digital input/output pin.

I-AD2 — A/D converter, input 2.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2/

AD3/CT32B1_MAT1 11 [5] no I I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO1_2 — General purpose digital input/output pin.

I-AD3 — A/D converter, input 3.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/

AD4/CT32B1_MAT2 12 [5] no I/O I; PU SWDIO — Serial wire debug input/output.

I/O - PIO1_3 — General purpose digital input/output pin.

I-AD4 — A/D converter, input 4.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

13 [5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns

glitch filter.

I-AD5 — A/D converter, input 5.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

I-WAKEUP — Deep power-down mode wake-up pin with 20 ns

glitch filter. This pin must be pulled HIGH externally to enter Deep

power-down mode and pulled LOW to exit Deep power-down

mode. A LOW-going pulse as short as 50 ns wakes up the part.

PIO1_5/RTS/

CT32B0_CAP0 14 [3] no I/O I; PU PIO1_5 — General purpose digital input/output pin.

O- RTS — Request To Send output for UART.

I-CT32B0_CAP0 — Capture input 0 for 32-bit ti mer 0.

Table 167. LPC1112/14 pin description table (TSSOP28 and DIP28 packages) …continued

Symbol

Pin TSSOP28/

DIP28

Start

logic

input

Type Reset

state

[1]

Description

User manual Rev. 11 — 26 July 2012 170 of 538