1340-Type - Agere Systems, Inc.

Data Sh eet

Jan uary 2000

1340-Type Lightwave Receiver

Operating at 1.1 µm through 1.6 µm wavelengths and at

155 Mbit s/ s, 62 2 Mbits/s, or 1.25 G bit s /s , the vers a tile

1340-Type Rec eiver is ma nu fa ct u r ed in a 20-pin, pl as tic DIP

with a multimode fiber pigtail.

Features

■Backward compatible with 1310 receiver family

■Space-saving, self-contained, 20-pin plastic DIP

■Silicon-based ICs

■Single 5 V power su pply operation including photo-

current m onitor capability

■Exceeds all SONET (GR-253-CORE) and ITU-T

G.958 jitter requirements

■Wide dynam ic range

■Qualified to meet the intent of Telcordia Technolo-

gies * reliability practices

■Operates at data rates of 15 5 Mbits /s,

622 Mbits /s, or 1.25 Gbits/s

■Positive ECL (PECL) data outputs

■CMOS (TTL) link-status flag output

■Operation at 1.3 µ m or 1.55 µm wavelengths

■Operating case temperature range of

–40 °C to +85 °C

Applications

■Telecommunications:

—Inter- and intraoffice SONET/ITU-T SDH

—Subscr ib er loop

—Metropolitan area networks

■High-speed data communication s

Description

The 1340-Type receiver is designed for use in trans-

mission systems or medium- to high-speed data

communications appli c ations at data ra tes up to

1.25 Gbits/s. Compact pac kagi ng, along with wide

dynamic range, makes these receivers ideal for both

telecommunicat ions and data communications appli-

cations.

The following three versions of the receiver are avail-

able:

■SONET/SDH compliant with OC-3/STM-1

■SONET/SDH compliant with OC-12/STM-4

■1.25 Gbits for data applications.

* Telcordia Technologies is a trademark of Telcordia Technologies,

Inc.

22 Agere Systems Inc.

Data Sh eet

January 2000

1340-Type Lightwave Receiver

Description (continued)

The SONET/SDH versions of the receiver are fully

compliant with the latest issue o f Telcor dia Technolo-

gies GR-253- CORE and the most recent issues of ITU

recommendations G.957 and G.958. The 1340-Type

receiver requires only a single 5 V powe r suppl y for

operation. All versions of the receiv er are characteriz ed

for operati on over the case opera tin g range of –40 °C

to +85 °C at the appropriate data rate for each version.

Manufactured in a 20-pin DIP, the receivers us e a pla-

nar, rea r illuminated InGaAs P IN photodetector t hat

allows these receivers to be used at wavelength s fr om

1.1 µm to 1.6 µm. The photocurrent output of the PIN

detector is amplified and c onverted to a voltage by a

silic on amplifi er. A silicon quantizer prov id e s additional

signal amplification, data threshold detection, and

PECL data outputs. The inco ming optical signal is cou-

pled into the receiver through a 62.5 µm core multi-

mode fiber pigtail. T he outer j acket diameter of the

pigtail is 900 µm. The receiver can be ordered with the

pigtail terminated in an FC/PC, SC, or ST ® optical con-

nector . Other connectors are a v ailable on special order.

See your Agere account repres enta tive for orderi ng

conditi ons and informati on.

The rece ive r has differential PEC L data outputs and,

depending on the version selected, either differential

PECL link status flag or complement ary C MOS link

status flag outputs. The link status flag outputs indicate

the presence or absence of a minimum acceptable

level of optical input signal.

1-414(F)

Figure 1. Block Diagram

GaAs

PREAMPLIFIER

FILTER

InGaAs

PIN Si

COMPARATOR

DATA DATA

FLAG FLAGVCC

VPIN

FILTER

Data Sheet

Jan uary 2000 1340-Type Lightwave Receiver

Agere Systems Inc. 3

Description (continued)

To help ensure high product reliabili ty and custom er

satisfaction, Agere is committed to an intensive quality

program that starts in the design phase and proceeds

through the ma nufacturing and shipping process. Opto-

electronics subsystems are qualified to Agere internal

standards us ing MI L-STD-883 test methods and pro-

cedures a nd sampling techniques consistent with Tel-

cordia Technologies requirements. The 1340 receiver

qualification program meets the intent of Telcordia

Technologies TR-NWT-000468 and TA-TSY-000983.

Application Information

The 1340 re c eiver i s a hig h ly sensitive fiber-optic

receiver. Althoug h the data outp uts are digital logic lev-

els (PEC L) , the device shoul d be thought of as an ana-

log component. When laying out the printed-wiring

board (PW B), the 1340 receiver should be given the

same type of consideration one would give to a sensi-

tive analog component.

At a minimum, a double-sided printed-wiring board with

a large component-side ground plane beneath the

rec eiver must b e used . In applica tions that i nclude

many o ther high-speed devices, a multilayer PWB is

highly recom mended. T his perm its the placem ent of

power and gr ound connections on s eparate layers,

which help s minimize the coupling of unwanted signal

noise into the power supplies of the r eceiver.

Layout Considerations

A fiber-optic re ceiver employs a ver y h igh-gai n, wide-

bandwi dth transimpedance amplifier. The amplifier

detects and amplifies signals that are only tens of nA in

amplitude. Any unwanted signal currents that couple

into the receiver circuitry cause a decrease in the

receiver’s s ensitivity and can also degrade the perfor-

mance o f the receiver’s loss of signal (FLAG) circuit.

To minimize the c oupli ng of unwanted noise into the

receiver, route high-level, high-speed signals such as

transmitter inputs an d clock lines as far away as possi-

ble from the re c e iver pins. If this is not possible, then

the PWB layout engineer should consider interleaving

the receiver signal and flag traces with ground traces in

order to provide the required isolat ion.

Noise that couples into the receiver through t he power

supply pins can also degrade device per formance. The

application sc hematics, F igures 3—5, show recom-

mended power supply filte ring that helps min imize

noise coupling into the rece ive r. The bypass capacitors

should be high-quality ceramic devices rated for RF

applications. T hey sh ould be surface-mount compo-

nents placed as close as possible to the receiver pow er

supply pins. The ferrite bead shou ld have as high an

impedance as possible in the frequency range that is

most likely to cause prob lems. This will vary f or each

application and is dep endent on the signaling frequen-

cies p rese nt on the application circuit card. Surface-

mount , high-impedance beads are availabl e from sev-

eral manuf acturers.

Data and Flag Outputs

The data outputs of the 1340 receiver are driven by

open-emitt er NP N transisto rs which have an output

impedance of appro ximately 7 Ω. Each output can pro-

vide approximately 50 m A maximum output current.

Due to the high switching speeds of ECL outputs,

transmission line design must be us ed to interc onnect

components. To ensure o pti mum signal fidelity, both

data outputs (DATA and DATA) should be te rm inated

identically. The signal lines connecting the data outputs

to the next device should be equal in length and should

have matched impedan ces.

Controlled impedance stripline or micros trip cons truc-

tion must be used to preserve t he quali ty of the signal

into the next component and to minimize refle ctions

back into the rece iver. Excessive ringing due to r eflec-

tions cause d by improperly terminated signal l ines

makes it d ifficult for the component recei v ing these sig-

nals to decipher the proper logic levels an d may cause

transitions to occur where none were intended. Also , by

minimizing high frequency ringing due to reflections

caused by improperly design ed and terminated signa l

lines, possible EMI problems can be avoided. The

applications se ction s in the Signetics*ECL 10K/100K

Data Manual or the National Semiconductor† ECL

Logic Databook and Des ign Guide provide excellent

design information on ECL interfacing.

*Signetics is a registered trademark of Signetics Corp.

†National Semiconductor is a registered trademark of National

Semiconductor Corporation.

44 Agere Systems Inc.

Data Sh eet

January 2000

1340-Type Lightwave Receiver

Data and Flag Outputs (continued)

The FLAG and FLAG outputs of the OC-3/STM-1

155 Mbits/s version of the 1340 receiver are PECL

logic level s driven by open emitter t ransistors wi th the

same character istics as the data outputs. These out-

puts must be properly terminated in order to obtain the

correct logic levels. Since the FLAG function is basi-

cally a dc switch that indicates the loss of optical input

signal, i t can be inte rfaced to much slower TTL or

CMOS logic circuits.

The circuit shown in Figure 2 provides one example of

how to create a TTL logic output from the PECL FLAG

output signal. The outputs of the LT1016 are TTL-com-

patible and provide both true and inverted logic levels.

The Q output of this circuit will be a TTL high (>2.5 V)

when the 1340 i s receiving an optical signal greate r

than the FLAG switching thres hold and w ill be a TTL

low ( <0.4 V) wh e never t h e optical signal i s abs ent or is

below the FLAG switching threshold. The FLAG and

FLAG outputs of the OC-12/STM-4 and 1. 25 Gb i ts/s

receivers are 5 V TTL logic lev el compatib le. The FLA G

output is provided directly b y the comparator I C . How-

ever, the FLAG output is derived from the FLAG output

through an inverter. Excessive loading of the FLAG out-

put ca n c ause the FLAG output to malfunction.

1-800(C).a

* Part available from Linear Technology Corporation of Milpitas, CA 95035.

Figure 2. Converting PECL FLAG Outputs t o TT L

10 k•

TTL (TRUE)

TTL (INVERTED)

LT1016*

1340

FLAG

+5 V +5 V

10 k•

–

Agere Systems Inc. 5

Data Sheet

Jan uary 2000 1340-Type Lightwave Receiver

Pin 10

Pin 10 on the 1340-Type receiver is a not internally

connected (NIC) pin. T his definition allows the 1340 to

be used in most customer 20-pin receiver module

applications. Customer’ s printed-wiring boards that are

designed wi th ground, +5 V, –5 V, or no connection to

this pin are all accept able options. F or those applica-

tions t hat req uire monitoring the photocurrent of the

PIN photodetecto r for power monitoring purposes,

t here ar e v ersi ons of the 1340 that require +5 V or –5 V

applied to Pin 10. Check Tables 4 and 5 for ordering

information.

Recommended User Interface

The 1340 rec eiver is des igned to be operated from a

5 V power supply and provides raised or pseudo-ECL

(PECL) data outputs. Figu re s 3 and 4 show two possi-

ble application circuits for the 1340 receiv e r. Figure 3

represents an application for the version w ith PECL

FLAG outputs while Figure 4 shows a possible applica-

tion for the vers ion with the TTL-compatible FLAG

outputs.

In both instances, the DATA outputs are terminated with

a Thévenin equivalent circuit, which provides the equiv-

alent of a 50 Ω load terminated t o (VCC – 2 V).

A single 50 Ω resistor terminat ed to (VCC – 2 V) could

also be used, but this requi re s a se cond power supply.

Other methods of ter mina tin g ECL-type outputs are

discussed in the references previously mention ed.

Figure 5 shows an example of a ci rcui t that can be

used to interf ace the PECL outputs of the 1340 receiver

with a device which requires true, negativ e voltage ECL

inputs. The 100314 is an ECL line receiver and is

shown here only as an example to demonstrate this

coupling procedure. The D ATA lines are terminated in a

50 Ω equivalent impedance but are ac-coupled to the

100314. The capacitive coupling isolates and permits

level shifting of the positive DATA outputs of the

receiver to the proper negative level required by the

inputs of the 100314. The VBB output of the 100314

provide s the reference voltage required to center the

voltage swing of the DATA signals around the i nput

swit ching threshold of the 100314. The Thévenin

equivalent of the 166 Ω and 250 Ω resistor pai r is

100 Ω, whi ch, in parallel with t he 100 Ω resistor con-

nected t o V BB, re sults in a 5 0 Ω equivalent impedance

for the load on each of the data lines. Alternatively, if

there is no VBB referen ce available, a second pair of

166 Ω/250 Ω resistor networks could be used o n the

data lines on the 100314 s ide of the coupling capacitor.

* 50 Ω to (VCC – 2) V.

† DATA and DATA are 50 Ω impe danc e tr an sm i ss io n lines ; both line s ca n be ac- or dc-c o uple d int o the next devi c e.

‡ Fa ir- Rite Pr o du cts Corp orat io n pa rt numb er 2743 03 74 47 o r e q uivalent.

Note: All unused outputs must be terminated as shown. All resistors are 1/8 W, thin-film, ceramic chips. All capacitors are

25 Vdc, ceramic X7R, or equivalent.

Figure 3 . Interfacing to the 155 Mbits/s 1340 Receiver

1340

0.1 µF0.1 µF

124 •

0.1 µF0.1 µF

82 • 82 •

2.2 µF

†

FLAG*

124 • 124 •

FLAG*

+5.0 V

82 • 82 •

124 •

DATA

†

DATA

†

FERRITE

BEAD

‡

1-500(C).d

Data Sh eet

January 2000

1340-Type Lightwave Receiver

6Agere Systems Inc.

Recommended User Interfaces (continued)

* TTL (CMOS ) compatible level.

† DATA and DATA are 50 Ω impedance transmission lines; both lines can be ac- or dc-coupled into the next device.

‡Fair-Rite Products Corporation part number 2743037447 or equivalent.

Figure 4. Interfacing to th e 622 M bits/s and 1.25 Gbits/s 1340 Receivers

1-572(C).b

*50 Ω to (VCC – 2) V.

†50 Ω to –2 V. DATA and DATA are 50 Ω impedance transmission lines.

‡Fair-Rite Products Corporation part number 2743037447 or equivalent.

Figure 5. Interfa c ing the 155 Mbits/s 1340 Receiver to a True ECL Circuit

1340

0.1 µF 0.1 µF

124 •

2.2 µF

†

0.1 µF

FLAG*

+5.0 V

82 • 82 •

124 •

DATA

†

DATA

†

FERRITE

‡

BEAD

0.1 µF

124 •

100 • 100 •

1340

0.1 µF

82 •

124 •

82 •

124 •

0.1 µF

FLAG*

2.2 µF†

+5 V

0.1 µF 124 •

–

6, 7

100314

0.1 µF

0.1 µF 10 µF

0.1 µF

82 • 82 •

DATA†

166 •

250 •

166 •

250 •

FERRITE

BEAD‡

1-500(C).c

Data Sheet

Jan uary 2000 1340-Type Lightwave Receiver

Agere Systems Inc. 7

Pin Information

Table 1. Pi n Descriptions

* Pins desi gnate d as no user connect ion are not co nnecte d i ntern ally withi n the receiver. Howe ver , to allow for f ut ure fun ctional upgrades, it is

rec o mm e nded th at the us er no t m ake any c onne ction s to these pin positions.

† The l in k-s t a tu s flag is a log ic o ut put that in di cate s t he pre sence or ab s ence of a minimum acceptable level of optical input. A logic high on

FL AG in dica t e s t he pre sence o f a valid optical signa l.

Handling Precautions

Mounti ng and Connecti ons

The pigtai l consists of a 3 9 i n. ± 4 i n. (1 m ± 10 cm), 62.5 µm core / 125 µm cladding multimod e fiber. Th e standard

fiber has a 0.036 in. (914 µm) diameter tight-buffered outer jacket. The minimum fiber bending radius during opera-

tion is 1.0 in. (25.4 mm ).

Pin Number Description

1 Ground

2 Ground

3 Ground

4 Ground

5 N o Us er Connec t ion*

6 Ground

7DATA

8 Ground

9DATA

10 N IC or Optional VPIN

11 Vcc (5 V)

12 FLAG†

13 Ground

14 FLAG

15 Ground

16 Ground

17 N o Us er Connec t ion*

18 N o Us er Connec t ion*

19 N o Us er Connec t ion*

20 N o Us er Connec t ion*

Data Sh eet

January 2000

1340-Type Lightwave Receiver

8Agere Systems Inc.

Electrostatic Discharge

Caution: T his device is susceptible to damage as a result of electrostatic discharge (ESD). Take proper

precautions during both

handling and testing. Follo w EIA* Standard EIA-625.

Although protection circuitry is designed into the device, take proper precautions to avoid exposur e to ESD.

Agere e mpl oys a h uma n-body model (HBM) for ESD susceptibility testing and protection-design eva luation. ESD

v oltage thresholds are dependent on the critical parameters used to define the model. A standard HBM (r es istance

= 1.5 kΩ, capa citance = 100 pF) is widely used and, there fore, can be used for compari son purposes. The HBM

ESD threshold established for the 1340 receiver is ±1000 V.

Receiver Processing

The 1340-type receiver devices can withstand normal wave-soldering processes. The complete receiver module is

not hermetically sealed; therefore, it should not be immersed in or spray ed with any cleaning solution or solvents.

The process cap an d fiber pigtail jacket d ef ormation temperature is 85 °C. The receiver pins can be wave-soldered

at maximum temperat ure of 250 °C f or 10 seconds.

Installation Considerations

Although the receiver feat ures a robust design, care should be use d duri ng handling. The optical connector should

be kept free from dust, and the process cap should be kept in place as a dust cover whe n the device is not con-

nected to a cable. If contamination is present on the optical connector , the us e of canned air with an ext ension tube

should remove any debris. Other cleaning procedure s are identified in the technical note, Cleaning Fiber-Optic

Assemblies (TN95-010LWP).

* EIA is a registered trademark of Electronic Industries Association.

Data Sheet

Jan uary 2000 1340-Type Lightwave Receiver

Agere Systems Inc. 9

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can caus e permanent damage t o the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at th ese or any other conditions in excess

of those given in the operations section of the data sheet. Exposure to absolute maximum ratings for extended

per iods can adversely a ffect device reliab ili ty.

Operating Characteristics

Minimum and maximum values specified over operat ing case temperature range and end-of-life (EOL).

Typic al values are measured at beginning-of-life (BOL) room temperature unless otherwise noted.

Ta ble 2. Optical Characteristics

* For 1 x 10–10 BER with an optical input using a 223 – 1 pseudorandom word having a 50% average duty cycle.

Parameter Symbol Min Max Unit

Supply Voltage VCC —5.5 V

Operating Case Temperature Range TC–40 85 °C

Stora ge Cas e Temperature Range Tstg –40 85 °C

Lead Soldering Temperature/Time — — 250/10 °C/s

Operating Wavelength Range λ1.1 1.6 µm

Minimum Fibe r Bend Radius — 1.0 (25.4) — in. (m m)

Parameter Symbol Data Rate

(Mbits/s) Min Typ*Max Unit

Measure d Average Sensitivity*PR155

622

1250

—

–38

–32

–28

–36

–29

–24

dBm

Maximum Input Power *PMAX 155

622

1250

–3.0

–6.0

–3.0

–2.0

—

dBm

Link Status Sw itc hing Thresh old:

Decreasing Light Input

Increas ing Light Input

Hysteresis

LSTD

LSTI

HYS

155

622

1250

155

622

1250

All Data

Rates

–53.0

–45.0

–36.0

–52.5

–45.5

–35.5

0.5

–40

–34

–31.0

–38

–31

–29.0

3.0

–36.0

–28.0

–26.0

–35.5

–27.5

–25.5

6.0

dBm

Detector Responsivity R All Data

Rates 0.7 0.8 1.2 A/W

Data Sh eet

January 2000

1340-Type Lightwave Receiver

10 Agere Systems Inc.

Operating Characteristics (continued)

Table 3. El ectrical Characteristics

* Customers have the option for either a +5 V or –5 V supply.

† M easured from VCC with a 50 Ω load to (VCC – 2) V.

‡ Int er nal ly te rm ina t e d CMO S ou tp ut.

Qualification Tests and Reliability

To help ensure high product reliability and custo me r sa t isf a ct i on, Agere is comm itted to an intensive quality pro-

gram that starts in the design phase and proceeds through the manufacturing process. Optoelectronics modules

are qualifi ed to Agere internal standards using MIL-STD-883 test methods and procedures and using sampling

techniques consistent with Telcordia Technologie s requiremen ts. The 1340-Type receivers have undergone an

ex tensive and rigorous set of qualification tests. This qualification program fully meets the intent of Telcordia Te ch -

nologies reliability practices TR-NWT- 000468 and TA-NWT-000983. In addition, the design, development, and ma n-

ufacturing facility of Agere’s Optoelec tronics unit has been c ertified to be in full compliance with the late st ISO*-

9001 Quality System Standard s.

*ISO is a registered trademark of The International Organization for Standardization.

Parameter Symbol Min Typ Max Unit

dc Power Supply Voltage VCC 4.75 5.0 5.25 V

PIN P hotodetector Supply Voltage (Pin 10)* VPIN

VPIN 4.75

–5.25 5.0

–5.0 5.25

–4.75 V

Power Supply Current ICC

IPIN —

—80

—150

1mA

Output Data Volt age:†

Low

High VOL

VOH VCC – 1.81

VCC –1.025 VCC – 1.70

VCC – 0.95 VCC – 1.62

VCC – 0.88 V

Output Ri se Time/Fall Time:

OC-3/STM -1 Versions

OC-12/STM- 4 Versions tR/tF

tR/tF—

—700

350 1400

400 ps

Output Flag Voltage:

OC-3/STM-1 Versions:‡

Low

High

OC-12/STM- 4 Versions: ‡

Low

High

VFL

VFH

VFL

VFH

—

VCC – 1.025

VCC – 0.5

VCC – 1.90

VCC – 1.0

—

VCC – 1.65

—

0.5

VCC

Output Data Current:†

Low

High IOL

IOH —

—5

20 50

50 mA

Output F lag Current:

OC-3/STM-1 Versions:

Low

High

OC-12/STM- 4 Versions:

Low

High

IOL

IOH

IOL

IOH

—

Data Sheet

Jan uary 2000 1340-Type Lightwave Receiver

Agere Systems Inc. 11

Outline Diagram

Dimens ions are in inches and ( millimet er s). Unless noted otherwise, tolerances are 0.005 in. (0.127 mm).

1-988(C)

1.339

(34.01) 0.968

(24.58)

0.635

(16.14)

0.147

(3.73)

TOP V IEW

PIN 1 INDICATOR

0.125

(3.17)

0.110

(2.80)

0.100

(2.54)

0.900

(22.86)

0.350 (8.89)

0.400

(10.16)

PIN 20PIN 11

PIN 1

PIN 10

0.018

(0.46)

1340-Type Lightwave Receiver Advance Data Sheet

for OC -1,3/STM-1 January 2000

Agere Sys t e ms In c. re se rves t h e righ t t o make changes to the product(s) or information contained herein without notice. No liabi lity is assumed as a result of their use or application. ST is a

registered trademark of Agere Systems Inc.

A ll Rig hts Re serv ed

Print ed in U.S.A.

January 20 00

DS00-098OPTO (Replaces DS99-072LWP)

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERI CA : Age re Systems Inc ., 555 Uni on Boulevard, Room 30L-15P- BA, A llento wn, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)

JAP AN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIW AN: (886) 2-2725-5858 (Taipei)

EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045

Ordering Information

Table 4. OC-3/STM-1 Receiver Versions

Table 5. OC-12/STM- 4 Receiver Versions

Table 6. 1.25 Gbits/s Receiver Versions

Table 7. Related P rod uc ts

Device Code Conn ector Pin 10 Requirements C omcode

1340FMPC FC-PC No

Internal

Connection

108162322

1340CMPC SC 108354408

1340TMPC ST 108572264

1340FAPC FC-PC Requ ires + 5 V or –5 V

(Used for photocurrent

monitoring)

108468687

1340CAPC SC 108359175

1340TAPC ST 108572249

Device Code Connector Pin 10 Requirements Comcode

1340FNPC FC-PC No

Internal

Connection

108155680

1340CNPC SC 108354416

1340TNPC ST 108155755

1340FB P C FC-PC Req uires +5 V or –5 V

(Used for phot ocur rent

monitoring)

108155672

1340CBPC SC 108468679

1340TBPC ST 108572256

Device Code Connector Pin 10 Requirements Comcode

1340FCPC FC-PC Requires

+5 V or –5 V 108400342

1340CCPC SC 108400334

Description Documen t Number

1241/ 1243/ 1245-Type Receivers for SONET/SDH Applications DS99-073LWP

1345-Type Re ceiver with Clock Recove ry and Da ta Retiming DS00-099OPTO

Data Sh eet

January 2000

1340-Type Lightwave Receiver