HM628512A Series 4 M SRAM (512-kword x 8-bit) ADE-203-640B (Z) Rev. 2.0 Nov. 1997 Description The Hitachi HM628512A is a 4-Mbit static RAM organized 512-kword x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.5 m Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II or 600-mil plastic DIP, is available for high density mounting. The HM628512A is suitable for battery backup system. Features * Single 5 V supply * Access time: 55/70 ns (max) * Power dissipation Active: 50 mW/MHz (typ) Standby: 10 W (typ) * Completely static memory. No clock or timing strobe required * Equal access and cycle times * Common data input and output: Three state output * Directly TTL compatible: All inputs and outputs * Battery backup operation HM628512A Series Ordering Information Type No. Access time Package HM628512ALP-5 HM628512ALP-7 55 ns 70 ns 600-mil 32-pin plastic DIP (DP-32) HM628512ALP-5SL HM628512ALP-7SL 55 ns 70 ns HM628512ALFP-5 HM628512ALFP-7 55 ns 70 ns HM628512ALFP-5SL HM628512ALFP-7SL 55 ns 70 ns HM628512ALTT-5 HM628512ALTT-7 55 ns 70 ns HM628512ALTT-5SL HM628512ALTT-7SL 55 ns 70 ns HM628512ALRR-5 HM628512ALRR-7 55 ns 70 ns HM628512ALRR-5SL HM628512ALRR-7SL 55 ns 70 ns 2 525-mil 32-pin plastic SOP (FP-32D) 400-mil 32-pin plastic TSOP II (TTP-32D) 400-mil 32-pin plastic TSOP II reverse (TTP-32DR) HM628512A Series Pin Arrangement HM628512ALP Series HM628512ALFP Series A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 (Top view) HM628512ALTT Series A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS (Top view) HM628512ALRR Series VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top view) Pin Description Pin name Function A0 to A18 Address input I/O0 to I/O7 Data input/output CS Chip select OE Output enable WE Write enable VCC Power supply VSS Ground 3 HM628512A Series Block Diagram A12 V CC A7 V SS A1 A0 A2 A5 Row Decoder * * * * * Memory Matrix 1,024 x 4,096 A6 A3 A4 A18 I/O0 Column I/O * * Input Data Control Column Decoder I/O7 A13 A17A15A8 A9 A11A10A14A16 * * CS WE OE 4 Timing Pulse Generator Read/Write Control * * HM628512A Series Function Table WE CS OE Mode VCC current Dout pin Ref. cycle x H x Not selected I SB , I SB1 High-Z -- H L H Output disable I CC High-Z -- H L L Read I CC Dout Read cycle L L H Write I CC Din Write cycle (1) L L L Write I CC Din Write cycle (2) Note: x: H or L Absolute Maximum Ratings Parameter Symbol Value Power supply voltage VCC -0.5 to +7.0 1 Unit V 2 Voltage on any pin relative to V SS VT -0.5* to V CC + 0.3* V Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Storage temperature under bias Tbias -10 to +85 C Notes: 1. -3.0 V for pulse half-width 30 ns 2. Maximum voltage is 7.0 V Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.2 -- VCC + 0.3 V -- 0.8 V Input high voltage Input low voltage Note: VIL -0.3 *1 1. -3.0 V for pulse half-width 30 ns 5 HM628512A Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10% , VSS = 0 V) Parameter Symbol Min Typ*1 Max Unit Test conditions Input leakage current |ILI| -- -- 1 A Vin = VSS to V CC Output leakage current |ILO | -- -- 1 A CS = VIH or OE = VIH or WE = VIL, VI/O = VSS to V CC Operating power supply current: DC I CC -- 8 15 mA CS = VIL, others = VIH/VIL, I I/O = 0 mA HM628512A-5 I CC1 -- 45 70 mA Min cycle, duty = 100% CS = VIL, others = VIH/VIL I I/O = 0 mA HM628512A-7 I CC1 -- 40 60 mA mA Cycle time = 1 s, duty = 100% I I/O = 0 mA, CS 0.2 V VIH V CC - 0.2 V, VIL 0.2 V mA CS = VIH A Vin 0 V, CS V CC - 0.2 V Operating power supply current Operating power supply current I CC2 -- 10 20 Standby power supply current: DC I SB -- 1 3 Standby power supply current (1): DC I SB1 2* 2 -- 2* 3 -- 100* 50* 3 2 A Output low voltage VOL -- -- 0.4 V I OL = 2.1 mA Output high voltage VOH 2.4 -- -- V I OH = -1.0 mA Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and specified loading, and not guaranteed. 2. This characteristics is guaranteed only for L version. 3. This characteristics is guaranteed only for L-SL version. Capacitance (Ta = 25C, f = 1 MHz) Parameter 1 Input capacitance* Input/output capacitance* Note: 6 1 Symbol Typ Max Unit Test conditions Cin -- 8 pF Vin = 0 V CI/O -- 10 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. HM628512A Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.) Test Conditions * * * * Input pulse levels: 0.8 V to 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: 1 TTL Gate + CL (100 pF) (HM628512A-7) 1 TTL Gate + C L (50 pF) (HM628512A-5) (Including scope & jig) Read Cycle HM628512A -5 -7 Parameter Symbol Min Max Min Max Unit Notes Read cycle time t RC 55 -- 70 -- ns Address access time t AA -- 55 -- 70 ns Chip select access time t CO -- 55 -- 70 ns Output enable to output valid t OE -- 25 -- 35 ns Chip selection to output in low-Z t LZ 10 -- 10 -- ns 2 Output enable to output in low-Z t OLZ 5 -- 5 -- ns 2 Chip deselection to output in high-Z t HZ 0 20 0 25 ns 1, 2 Output disable to output in high-Z t OHZ 0 20 0 25 ns 1, 2 Output hold from address change t OH 10 -- 10 -- ns 7 HM628512A Series Write Cycle HM628512A -5 -7 Parameter Symbol Min Max Min Max Unit Notes Write cycle time t WC 55 -- 70 -- ns Chip selection to end of write t CW 50 -- 60 -- ns 4 Address setup time t AS 0 -- 0 -- ns 5 Address valid to end of write t AW 50 -- 60 -- ns Write pulse width t WP 40 -- 50 -- ns 3, 12 Write recovery time t WR 0 -- 0 -- ns 6 WE to output in high-Z t WHZ 0 20 0 25 ns 1, 2, 7 Data to write time overlap t DW 25 -- 30 -- ns Data hold from write time t DH 0 -- 0 -- ns Output active from output in high-Z t OW 5 -- 5 -- ns 2 Output disable to output in high-Z t OHZ 0 20 0 25 ns 1, 2, 7 Notes: 1. t HZ , t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later transition of CS going low or WE going low. A write ends at the earlier transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 4. t CW is measured from CS going low to the end of write. 5. t AS is measured from the address valid to the beginning of write. 6. t WR is measured from the earlier of WE or CS going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output remain in a high impedance state. 9. Dout is the same phase of the write data of this write cycle. 10. Dout is the read data of next address. 11. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. t WP tDW min + t WHZ max 8 HM628512A Series Timing Waveforms Read Timing Waveform (WE = VIH) tRC Address tAA tCO CS tLZ tHZ tOE tOLZ OE tOHZ Dout Valid Data tOH 9 HM628512A Series Write Timing Waveform (1) (OE Clock) tWC Address tAW tWR OE tCW CS *8 tWP tAS WE tOHZ Dout tDW Din 10 Valid Data tDH HM628512A Series Write Timing Waveform (2) (OE Low Fixed) tWC Address tCW tWR CS *8 tAW tWP WE tOH tAS tOW tWHZ *9 *10 Dout tDW tDH *11 Din Valid Data 11 HM628512A Series Low VCC Data Retention Characteristics (Ta = 0 to +70C) Parameter Symbol Min Typ Max Unit Test conditions*3 VCC for data retention VDR 2 -- -- Data retention current I CCDR 4 50* V CS V CC - 0.2 V, Vin 0 V 1 A VCC = 3.0 V, Vin 0 V CS V CC - 0.2 V -- 1* -- 1* 4 15* 2 A Chip deselect to data retention time t CDR 0 -- -- ns Operation recovery time tR 5 -- -- ms See retention waveform Notes: 1. For L-version and 20 A (max.) at Ta = 0 to 40C. 2. For SL-version and 3 A (max.) at Ta = 0 to 40C. 3. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = 25C and specified loading, and not guaranteed. Low V CC Data Retention Timing Waveform (CS Controlled) tCDR Data retention mode VCC 4.5 V 2.2 V VDR CS 0V 12 CS VCC - 0.2 V tR HM628512A Series Package Dimensions HM628512ALP Series (DP-32) Unit: mm 41.90 42.50 Max 17 13.4 13.7 Max 32 16 5.08 Max 1.20 2.30 Max 2.54 0.25 0.48 0.10 0.51 Min 2.54 Min 1 15.24 + 0.11 0.25 - 0.05 0 - 15 Hitachi Code JEDEC EIAJ Weight (reference value) DP-32 -- Conforms 5.1 g 13 HM628512A Series Package Dimensions (cont.) HM628512ALFP Series (FP-32D) Unit: mm 20.45 20.95 Max 17 11.30 32 1 1.27 0.40 0.08 0.38 0.06 0.10 0.15 M Dimension including the plating thickness Base material dimension 14 0.12 0.15 +- 0.10 1.00 Max 0.22 0.05 0.20 0.04 3.00 Max 16 14.14 0.30 1.42 0 - 8 0.80 0.20 Hitachi Code JEDEC EIAJ Weight (reference value) FP-32D Conforms -- 1.3 g HM628512A Series Package Dimensions (cont.) HM628512ALTT Series (TTP-32D) Unit: mm 20.95 21.35 Max 17 10.16 32 1.27 0.42 0.08 0.40 0.06 0.21 16 M 0.80 11.76 0.20 0.10 Dimension including the plating thickness Base material dimension 0.17 0.05 0.125 0.04 1.20 Max 1.15 Max 0.13 0.05 1 0 - 5 0.50 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-32D Conforms -- 0.51 g 15 HM628512A Series Package Dimensions (cont.) HM628512ALRR Series (TTP-32DR) Unit: mm 20.95 21.35 Max 16 10.16 1 1.27 0.42 0.08 0.40 0.06 0.21 17 M 0.80 11.76 0.20 0.10 Dimension including the plating thickness Base material dimension 16 0.17 0.05 0.125 0.04 1.20 Max 1.15 Max 0.13 0.05 32 0 - 5 0.50 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-32DR Conforms -- 0.51 g HM628512A Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright (c) Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 17 HM628512A Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Sep. 12, 1996 Initial issue K. Imato K. Imato 1.0 Dec. 2, 1996 Deletion of preliminary K. Imato K. Imato 2.0 Nov. 1997 Change of Subtitle 18