© Semiconductor Components Industries, LLC, 2009
October, 2017 − Rev. 1
1Publication Order Number:
SRDA3.3−4/D
SRDA3.3-4
ESD Protection Diode
Low Capacitance Surface Mount ESD
Protection for High−Speed Data
Interfaces
The SRDA3.3−4 surge protection is designed to protect equipment
attached to high speed communication lines from ESD and lightning.
Features
•Protects 4 I/O Lines
•Low Working Voltage: 3.3 V
•Low Clamping Voltage
•Low Capacitance (<15 pF) for High Speed Interfaces
•Peak Power − 500 W 8x20 ms
•Transient Protection for High Speed Lines to:
IEC61000−4−2 (ESD) ±15 kV (air), ±8 kV (contact)
IEC61000−4−4 (EFT) 40 A
IEC61000−4−5 (Lightning) 25 A
•UL Flammability Rating of 94 V−0
•This is a Pb−Free Device
Typical Applications
•High Speed Communication Line Protection
•T1/E1 Secondary Protection
•T3/E3 Secondary Protection
•Analog Video Protection
•Base Stations
•I2C Bus Protection
MAXIMUM RATINGS
Rating Symbol Value Unit
Peak Power Dissipation
8 x 20 mS @ TA = 25°C (Note 1)
Ppk 500 W
Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C
Lead Solder Temperature −
Maximum 10 Seconds Duration
TL260 °C
IEC 61000−4−2 Contact
Air
ESD ±8
±15
kV
IEC 61000−4−4 (5/50 ns) EFT 40 A
IEC 61000−4−5 (8 x 20 ms) −25 A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Non−repetitive current pulse 8 x 20 mS exponential decay waveform
Pin 2/3 to Pin 5/8
SO−8 LOW CAPACITANCE
VOLTAGE SUPPRESSOR
500 WATTS PEAK POWER
3.3 VOLTS
MARKING DIAGRAM
SOIC−8
CASE 751
PLASTIC
PIN CONFIGURATION
AND SCHEMATIC
I/O 1 1
REF 1 2
REF 1 3
I/O 2 4
8 GND
7 I/O 4
6 I/O 3
5 GND
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†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
8
P4106
AYWWG
G
1
8
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
Device Package
ORDERING INFORMATION
Shipping†
SRDA3.3−4DR2G SO−8
(Pb−Free)
2500/Tape & Reel
SRDA3.3−4
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2
ELECTRICAL CHARACTERISTICS
Characteristic Symbol Min Typ Max Unit
Reverse Stand−Off Voltage VRWM − − 3.3 V
Reverse Breakdown Voltage @ It = 1.0 mA VBR 5.0 − − V
Reverse Leakage Current @ VRWN = 3.3 V IRN/A 2.8 5.0 mA
Maximum Clamping Voltage @ IPP = 1.0 A, 8 x 20 mSVCN/A 5.9 7.0 V
Maximum Clamping Voltage @ IPP = 10 A, 8 x 20 mSVCN/A 7.1 10 V
Maximum Clamping Voltage @ IPP = 25 A, 8 x 20 mSVCN/A 9.0 15 V
Between I/O Pins and Ground @ VR = 0 V, 1.0 MHz CJ−8.0 15 pF
Between I/O Pins @ VR = 0 Volts, 1.0 MHz CJ−4.0 −pF
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VCClamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
IFForward Current
VFForward Voltage @ IF
Ppk Peak Power Dissipation
CCapacitance @ VR = 0 and f = 1.0 MHz
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Uni−Directional
IPP
IF
V
I
IR
IT
VRWM
VCVBR
VF
TYPICAL CHARACTERISTICS
Figure 1. 8 x 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
00204060
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
80
Figure 2. Clamping Voltage vs. Peak Pulse Current
(8 x 20 ms Waveform)
10
005
PEAK PULSE CURRENT (A)
CLAMPING VOLTAGE (V)
10 15 20 25
8
6
14
4
12
2
SRDA3.3−4
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3
APPLICATIONS INFORMATION
The SRDA3.3−4 is a low capacitance surge protection
diode array designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD events or transient
overvoltage conditions. Because of its low capacitance, it
can be used in high speed I/O data lines. The integrated
design of the SRDA3.3−4 offers surge rated, low
capacitance steering diodes and a surge protection diode
integrated in a single package (SO−8). If a transient
condition occurs, the steering diodes will drive the transient
to the positive rail of the power supply or to ground. The
surge protection device protects the power line against
overvoltage conditions avoiding damage to the power
supply and other downstream components.
SRDA3.3−4 Configuration Options
The SRDA3.3−4 is able to protect up to four data lines
against transient overvoltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
protected line exceeds the reference voltage (Vf or
VCC + Vf). The diodes will force the transient current to
bypass the sensitive circuit.
Data lines are connected at pins 1, 4, 6 and 7. The negative
reference is connected at pins 5 and 8. These pins must be
connected directly to ground using a ground plane to
minimize the PCB’s ground inductance. It is very important
to reduce the PCB trace lengths as much as possible to
minimize parasitic inductances.
Option 1
Protection of four data lines and the power supply using
VCC as reference.
8
7
6
5
1
2
3
4
I/O 1
I/O 2
I/O 3
I/O 4
VCC
Figure 3.
For this configuration, connect pins 2 and 3 directly to the
positive supply rail (VCC). The data lines are referenced to
the supply voltage. The internal surge protection diode
prevents overvoltage on the supply rail. Biasing of the
steering diodes reduces their capacitance.
Option 2
Protection of four data lines with bias and power supply
isolation resistor.
8
7
6
5
1
2
3
4
I/O 1
I/O 2
I/O 3
I/O 4
VCC
10 K
Figure 4.
The SRDA3.3−4 can be isolated from the power supply by
connecting a series resistor between pins 2 and 3 and VCC.
A 10 kW resistor is recommended for this application. This
will maintain a bias on the internal surge protection and
steering diodes, reducing their capacitance.
Option 3
Protection of four data lines using the internal surge
protection diode as reference.
8
7
6
5
1
2
3
4
I/O 1
I/O 2
I/O 3
I/O 4
NC
NC
Figure 5.
In applications lacking a positive supply reference or
those cases in which a fully isolated power supply is
required, the internal surge protection can be used as the
reference. For these applications, pins 2 and 3 are not
connected. In this configuration, the steering diodes will
conduct whenever the voltage on the protected line exceeds
the working voltage of the surge protection plus one diode
drop (Vc=Vf + VRWM).
SRDA3.3−4
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4
ESD Protection of Power Supply Lines
When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes reduces
their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:
VCC
D1
D2
Data Line
IESDpos
IESDneg
VF + VCC
−VF
IESDpos
IESDneg
Power
Supply
Protected
Device
Figure 6.
Looking at the figure above, it can be seen that when a
positive ESD condition occurs, diode D1 will be forward
biased while diode D2 will be forward biased when a negative
ESD condition occurs. For slower transient conditions, this
system may be approximated as follows:
For positive pulse conditions:
Vc = VCC + VfD1
For negative pulse conditions:
Vc = −VfD2
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect of
parasitic inductance must be considered. A pictorial
representation of this is shown below.
VCC
D1
D2
Data Line
IESDpos
IESDneg
VC = VCC + Vf + (L diESD/dt)
IESDpos
IESDneg
Power
Supply
Protected
Device
VC = −Vf − (L diESD/dt)
Figure 7.
An approximation of the clamping voltage for these fast
transients would be:
For positive pulse conditions:
Vc = VCC + Vf + (L diESD/dt)
For negative pulse conditions:
Vc = −Vf – (L diESD/dt)
As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
L diESD/dt factor. A relatively small trace inductance can result
in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached to
that rail. This highlights the importance of good board layout.
Taking care to minimize the effects of parasitic inductance
will provide significant benefits in transient immunity.
Even with good board layout, some disadvantages are still
present when discrete diodes are used to suppress ESD events
across datalines and the supply rail. Discrete diodes with good
transient power capability will have larger die and therefore
higher capacitance. This capacitance becomes problematic as
transmission frequencies increase. Reducing capacitance
generally requires reducing die size. These small die will have
higher forward voltage characteristics at typical ESD
transient current levels. This voltage combined with the
smaller die can result in device failure.
The ON Semiconductor SRDA3.3−4 was developed to
overcome the disadvantages encountered when using discrete
diodes for ESD protection. This device integrates a surge
protection diode within a network of steering diodes.
D1
D2
D3
D4
D5
D6
D7
D8
0
Figure 8. SRDA3.3−4 Equivalent Circuit
During an ESD condition, the ESD current will be driven
to ground through the surge protection diode as shown
below.
VCC
D1
D2
Data Line
IESDpos
Power
Supply
Protected
Device
Figure 9.
The resulting clamping voltage on the protected IC will
be: Vc = VFD1 + VRWM.
The clamping voltage of the surge protection diode is
provided in Figure 2 and depends on the magnitude of the
ESD current. The steering diodes are fast switching devices
with unique forward voltage and low capacitance
characteristics.
SRDA3.3−4
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5
TYPICAL APPLICATIONS
UPSTREAM
USB PORT
VBUS
VBUS
VBUS VBUS
VBUS
VBUS
VBUS
VBUS
DOWNSTREAM
USB PORT
DOWNSTREAM
USB PORT
D−
D+
D−
D+
GND
GND
D−
D+
GND
USB
Controller
RT
RT
RT
RT
CT
CT
CT
CT
NUP2201MR6
SRDA3.3−4
Figure 10. ESD Protection for USB Port
Figure 11. Protection for Ethernet 10/100 (Differential Mode)
PHY
Ethernet
(10/100)
Coupling
Transformers
SRDA3.3−4
RJ45
Connector
N/C N/C
TX+
TX−
RX+
RX−
TX+
TX−
RX+
RX−
GND
VCC
SRDA3.3−4
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7
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SRDA3.3−4
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8
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