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© 2005 Fairchild Semiconductor Corporation DS01 1616 www.fairchildsemi.com
June 1993
Revised April 2005
74LVX573 Low Voltage Octal Latch with 3-STATE Output s
74LVX573
Low Voltage Octal Latch with 3-STATE Outputs
General Descript ion
The LVX573 is a h i gh -spe ed o cta l la tch with b uffered com-
mon Latch Enable (LE) and buffered common Output
Enab l e (OE ) inpu ts. The LVX 573 is fu nctio nally id entic al to
the LVX 373 but wi th inputs and outputs o n opposite s ides
of the packa ge. The inputs tolera te up to 7V all owin g i nte r-
face of 5V systems to 3V systems.
Features
■Input voltage translation from 5V to 3V
■Ideal for low power/low noise 3.3V applications
■Guaranteed simultaneous switching noise level and
dynamic thresh ol d per for man ce
Ordering Code:
Devices also available in Tape and R eel. Sp ec if y by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74LVX573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVX573SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIA J TYPE II, 5.3mm Wide
74LVX573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
D0–D7Data Inputs
LE La tch Enable Input
OE 3-STAT E Output En ab le Input
O0–O73-STAT E Latch Outpu ts
www.fairchildsemi.com 2
74LVX573
Functional Description
The LVX573 contains eight D-type latches. When the
enable (LE) input is HIGH, data on the Dn inputs enters the
latche s. In this conditi on the latches are tra nsparent , i.e., a
latch output will change state each time its D input
changes. When LE is LOW the latche s store the informa-
tion that wa s pre sent o n the D in puts a se tup tim e pr eced-
ing the HIGH-to-LOW transition of LE. The 3-STATE
buffers are controlled by the Output Enable (OE) input.
When OE is LOW, the buffers are enabled. When OE is
HIGH th e buffers are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
H
HIG H Voltage
L
LOW Voltage
Z
High Impedance
X
Immaterial
O0
Previ ous O0 bef ore HIGH-to-LOW trans it ion of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Outputs
OE LE D On
LHH H
LHL L
LLX O
0
HXX Z
3 www.fairchildsemi.com
74LVX573
Absolute Maxim um Ratings(Note 1) Recommended Operating
Conditions (Note 2)
Note 1: The “Absolute Maximum Ratings” are those value s beyond whic h
the saf ety of the device cannot b e guaranteed . The device should not be
operated at these limits. The parametric values defined in the Electrical
Char ac teristics tables are not guar anteed at the absolute maxim um ratings .
The “R ecomm ended O peratin g Con ditions ” table will defin e the condition s
for actu al device operation.
Note 2: Unused inputs must b e held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteri stics (Note 3)
Note 3: (Input tr
tf
3ns)
Supply Voltage (VCC)
0.5V to
7.0V
DC Input Diode Current (IIK)
VI
0.5V
20 mA
DC Input Voltage (VI)
0.5V to 7V
DC Output Diode Current (IOK)
VO
0.5V
20 mA
VO
VCC
0.5V
20 mA
DC O utput Voltage (VO)
0.5V to VCC
0.5V
DC Output Source
or Sink Current (IO)
r
25 mA
DC VCC or Ground Current
(ICC or IGND)
r
75 mA
Storage Temperature (TSTG)
65
q
C to
150
q
C
Power Dissipation 180 mW
Supply Voltage (VCC) 2.0V to 3.6V
Input Voltage (VI) 0V to 5.5V
Output Voltage (VO)0V to V
CC
Operating Temperature (TA)
40
q
C to
85
q
C
Input Rise and Fall Time (
'
t/
'
V) 0 ns/V to 100 ns/V
Symbol Parameter VCC TA
25
q
CT
A
40
q
C to
85
q
CUnits Conditions
Min Typ Max Min Max
VIH HIGH Level 2.0 1.5 1.5
Input Voltage 3.0 2.0 2.0 V
3.6 2.4 2.4
VIL LOW Level 2.0 0.5 0.5
Input Voltage 3.0 0.8 0.8 V
3.6 0.8 0.8
VOH HIGH Level 2.0 1.9 2.0 1.9 VIN
VIH or VIL IOH
50
P
A
Output Voltage 3.0 2.9 3.0 2.9 V IOH
50
P
A
3.0 2.58 2.48 IOH
4 mA
VOL LOW Level 2.0 0.0 0.1 0.1 VIN
VIH or VIL IOL
50
P
A
Output Voltage 3.0 0.0 0.1 0.1 V IOL
50
P
A
3.0 0.36 0.44 IOL
4 mA
IOZ 3-STATE Output 3.6
r
0.25
r
2.5
P
AV
IN
VIH or VIL
Off-State Current VOUT
VCC or GND
IIN Input Leakage Current 3.6
r
0.1
r
1.0
P
AV
IN
5.5V or GND
ICC Quiescent Supply Current 3.6 4.0 40.0
P
AV
IN
VCC or GND
Symbol Parameter VCC TA
25
q
CUnits CL (pF )
(V) Typ Limit
VOLP Quiet Output Maximum Dynamic VOL 3.3 0.5 0.8 V 50
VOLV Quiet Output Minimum Dynamic VOL 3.3
0.5
0.8 V 50
VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50
VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50
www.fairchildsemi.com 4
74LVX573
AC Electrical Characteristics
Note 4: Parameter guaranteed by design. tOSLH
|tPLHm
tPLHn|, tOSHL
|tPHLm
tPHLn|.
Capacitance
Note 5: CPD is defined as the v alue of the int ernal equiv alent capacitanc e which is calculated from t he operatin g c urrent cons um ption without load.
Symbol Parameter VCC TA
25
q
CT
A
40
q
C to
85
q
CUnits Conditions
(V) Min Typ Max Min Max
tPLH Propagation 2.7 7.6 14.5 1.0 17.5
ns
CL
15 pF
tPHL Delay Time 10.1 18.0 1.0 21.0 CL
50 pF
Dn to On3.3
r
0.3 5.9 9.3 1.0 11.0 CL
15 pF
8.4 12.8 1.0 14.5 CL
50 pF
tPLH Propagation 2.7 8.2 15.6 1.0 18.5
ns
CL
15 pF
tPHL Delay Time 10.7 19.1 1.0 22.0 CL
50 pF
LE to On3.3
r
0.3 6.4 10.1 1.0 12.0 CL
15 pF
8.9 13.6 1.0 15.5 CL
50 pF
tPZL 3-STAT E Output 2.7 7.8 15.0 1.0 18.5
ns
CL
15 pF, RL
1 k
:
tPZH Enable Time 10.3 18.5 1.0 22.0 CL
50 pF, RL
1 k
:
3.3
r
0.3 6.1 9.7 1 .0 12.0 CL
15 pF, RL
1 k
:
8.6 13.2 1.0 15.5 CL
50 pF, RL
1 k
:
tPLZ 3-STAT E Output 2.7 12.1 19.1 1.0 22.0 ns CL
50 pF, RL
1 k
:
tPHZ Disable Time 3.3
r
0.3 10.1 13.6 1.0 15.5 CL
50 pF, RL
1 k
:
tWLE Pulse 2.7 6.5 7.5 ns
Width 3.3
r
0.3 5.0 5.0
tSSetup Time 2.7 5.0 5.0 ns
Dn to LE 3.3
r
0.3 3.5 3.5
tHHold Time 2.7 1.5 1.5 ns
Dn to LE 3.3
r
0.3 1.5 1.5
tOSHL Output to Output 2.7 1.5 1.5 ns CL
50 pF
tOSLH Skew (Note 4) 2.3 1.5 1.5
Symbol Parameter TA
25
q
CT
A
40
q
C to
85
q
CUnits
Min Typ Max Min Max
CIN Input Capacitance 4 10 10 pF
COUT Output Capacitance 6 pF
CPD Power Dissipation 27 pF
Capacitance (Note 5)
5 www.fairchildsemi.com
74LVX573
Physical Dim ensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
www.fairchildsemi.com 6
74LVX573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7 www.fairchildsemi.com
74LVX573 Low Voltage Octal Latch with 3-STATE Output s
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP), JED EC MO-1 53, 4.4mm Wide
Package Number MTC20
Fairchild does not assum e any responsibility for use of any circuitry described, no circuit patent lice nses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use provided in the labe li ng, can be re a-
sonably expected to result in a significant injury to the
user.
2. A crit ical com ponen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause the fa i lure of the life supp or t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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