1
Features
•Single Supply for Read and Write: 2.7 to 3.6V
•Fast Re ad Access Time – 55 ns
•Internal Program Control and Timer
•Sector Architecture
– One 16K Bytes Boot Block with Programming Lockout
– Two 8K Bytes Parameter Blocks
– Two Main Memory Blocks (32K Bytes, 64K Bytes)
•Fast Erase Cycle Time – 3 Seconds
•Byte-by-Byte Programming – 30 µs/Byte Typical
•Hardware Data Protection
•DATA Polling for End of Program Detection
•Low Power Dissipation
– 15 mA Active Current
– 50 µA CMOS Standby Current
•Typical 10,000 Write Cycles
Description
The AT49BV001A(N)(T) is a 2.7-volt-only in-system reprogrammable Flash Memor y.
Its 1 megab it of memor y is orga nized as 13 1,07 2 words by 8 bit s. Ma nufactured wi th
Atmel’s advanced nonvo latile CMOS technology, the device offe rs access times to
55 ns with power dissipation of just 54 mW over the industrial temperature range.
1-megabit
(128K x 8)
Single 2.7-volt
Battery-Voltage™
Flash Memory
AT49BV001A
AT49BV001AN
AT49BV001AT
AT49BV001ANT
Rev. 3364C– FLAS H– 9/0 3
PLCC Top View
Pin Configurations
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
RESET RESET
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
RESET*
VCC
WE
NC
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
VCC
*RESET
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Note: *This pin is a NC on the AT49BV001AN(T).
2AT49BV001A(N)(T) 3364C–FLASH–9/03
When the device is deselected, the CMOS standby current is less than 50 µA. For the
AT49 BV001 AN(T), pi n 1 for the PL CC packa ge and pin 9 for the T SOP packa ge are n o con-
nect pins. To allow for simple in-system reprogrammability, the AT49BV001A(N)(T) does not
require high input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to reading from
an EPROM; i t h as stan dar d CE , OE , a nd W E inputs to avoid bus contention. Reprogramming
the AT49BV001A(N)(T) is performed by erasing a block of data and then programming on a
byte by byte basis. The byte programming time is a fast 30 µs. The end of a program cycle can
be option ally dete cted by the DATA pol li ng fea tur e. Onc e the end of a byte program cycle has
been detected, a new access for a read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.
The device is erased by executing the erase command sequence; the device internally con-
trols the erase operations. There are two 8K byte parameter block sections, two main memory
blocks, and one boot block.
The devi ce has the c apa bil ity to pr ot ec t the da ta in th e boo t blo ck; thi s fe atur e is en abl ed by a
command sequence. The 16K-byte boot block section includes a reprogramming lock out fea-
ture to pr ovide data int egrity. The boot sector is designe d to contain user se cure code , and
when the feature is enabled, the boot sector is protected from being reprogrammed.
In the AT49BV001AN(T), once the boot block programming lockout feature is enabled, the
contents of the boot block are permanent and cannot be changed. In the AT49BV001A(T),
once the boot block programm ing lockout featur e is enabled, the c ontents of the b oot block
cannot be changed with input voltage levels of 5.5 volts or less.
Block Diag ram
CONTROL
LOGIC
Y DECODER
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
OE
WE
CE
RESET
ADDRESS
INPUTS
VCC
GND
AT49BV001A(N)
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
X DECODER
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
PROGRAM
DATA LATCHES
Y-GATING
INPUT/OUTPUT
BUFFERS
1FFFF
10000
0FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
AT49BV001A(N)T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
PROGRAM
DATA LATCHES
Y-GATING
INPUT/OUTPUT
BUFFERS
1FFFF
1C000
1BFFF
1A000
19FFF
18000
17FFF
10000
0FFFF
00000
3
AT49BV001A(N)(T)
3364C–FLASH–9/03
Device
Operation READ: The AT49BV001A(N)(T) is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is asserted
on the outputs. The outputs are put in the high impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
COMMAND S EQUENCES: W hen the d evi ce is first powe red on i t wil l be r ese t to the r ead or
standby mode depending upon the state of th e control line inputs. In or der to perform other
device fu nctio n s, a s er i es o f com mand se que nce s are en ter ed i nto th e dev ic e. The command
sequences are shown in the Command Definitions table. The command sequences are written
by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high.
The addres s is la tched on th e falling edge of CE or WE, whic hever occu rs last. The data is
latched b y the firs t rising edge of CE or W E. Stand ard micr opr ocess or write timing s are u sed.
The addres s lo ca tions used in the co mmand sequenc es are not affe cte d by enterin g the c om-
mand sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. If the RESET pin ma kes a hi gh t o lo w tr ansi tio n du rin g a pr ogr am or er as e oper ati on, the
operatio n may n ot be suc cessfu lly c omple ted and th e opera tion wi ll have to b e repea ted after
a high level is applied to the RESET pin. When a h igh lev el is re asser ted on th e RESET pin,
the device returns to the read or standby mode, depending upon the state of the control inputs.
By apply ing a 12V ± 0.5V inpu t signal to the RESET pin, the boot bloc k array can be repro-
grammed even if the boot block lockout feature has been enabled (see Boot Block
Programming Lockout Override section). The RESET feature is not available on the
AT49BV001AN(T).
ERASURE: Before a byte can be reprogrammed, the main memory blocks or parameter
blocks whi c h c onta ins th e by te m us t be er ased. T h e eras ed sta te o f the mem ory b its i s a log i-
cal “1”. The entire device can be erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load commands to specific address locations with
a specific data pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase opera-
tion so that no external clocks are requ ired. The maximu m time ne eded to e rase the w hole
chip is tEC. If the boot bloc k loc kou t feat ure has been enab led, the d ata i n the boo t sec tor wi ll
not be erased.
CHIP ERASE : If the boot block lockout has been enabled, the Chip Erase function will erase
Parameter Block 1, Parameter Block 2, Main Memory Block 1 - 2, but not the boot block. If the
Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip.
After the full chip erase the device will return back to read mode. Any command during c hip
erase will be ignored.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors
that can be individually erased. There are two 8K-byte parameter block sections and two main
memory blocks. The 8K-byte parameter block sections and the two main memory blocks can
be independently erased and reprogrammed. The Sector Erase command is a six bus cycle
operation. The sector ad dress is l atched on the falling WE edge of the sixth cy cle while t he
30H data in put co mma nd is lat che d at the ris ing edge of WE. The se ct or erase s tar ts after the
rising edge of WE of the sixth cycle. The erase operation is internally c ontrolled; it will auto-
matically time to completion.
4AT49BV001A(N)(T) 3364C–FLASH–9/03
BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a
logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to
a “1” ; only erase op eratio ns can conve rt “0”s t o “1”s . Prog ramming is ac compli shed v ia the
internal device command register and is a 4 bus cycle operation (please refer to the Command
Definitions table). The device will automatically generate the required internal program pulses.
The prog ram cycle has add resses latch ed on the fal ling edge of WE or CE, whic hever oc curs
last, and the data l atched on the rising edge of WE or CE, whichever occurs fir st. Program-
ming is co mpleted after the sp ecified tBP cycle time. The DATA polling fea ture may also be
used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The devic e has one desi gnated bl ock that has
a progra mmin g lockou t feature. This fe ature pre vents pr ogrammi ng of data in the des ignate d
block once the feature has been enab led. The size of the block is 16K bytes. This block,
refer red to as th e boot block , can cont ain secur e code that i s used to bri ng up the s ystem.
Enabling the lockout feature will allow the boot code to stay in the device while data in the rest
of the device is updated. This feature does not have to be activated; the boot block’s usage as
a write pr otected reg ion is opt ional to the use r. The addr ess range of the boot block is 00000
to 03FFF for the AT49BV001A(N) while the address range of the boot block is 1C000 to
1FFFF for the AT49BV001A(N)T.
Once the feature is enabled, the data in the boot block can no longer be erased or pro-
grammed with input voltage of 5.5V or less. Data in the main memory block can still be
changed through the regular programming method. To activate the lockout feature, a series of
six pro gram commands to specific addresses with specific data must b e performed. Pl ease
refer to the Command Definitions table.
BOOT BLOCK LO CKOUT DETECTIO N: A software method is available to determine if pro-
gramm ing of th e boot bl ock sec tion i s locke d out. Wh en th e device is in th e softwa re produ ct
identification mode (see Software Product Identification Entry and Exit sections) a read from
address location 00002H will show if programming the boot block is locked out for the
AT49BV001A(N), and a read from address location 1C002H will show if programming the boot
block i s locked ou t for th e AT49B V001A (N)T. If the data o n I/O0 is low, the boot blo ck can b e
programmed; if the data on I/O0 is high, the program lockout feature has been activated and
the b lock can not be p rogram med. The softwa re p roduct ident ifica tion code shou ld be use d to
return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot
block programming lockout by taking the RESET pin to 12 vol ts du ring th e enti re chip eras e,
sector erase or byte programming operation. When the RESET pin is brought back to TTL lev-
els the boot block programming lockout feature is again active. This feature is not available on
the AT49BV001AN(T).
PRODUCT IDENTIFICATION: The pr odu ct identificatio n mode ident ifies the de vi ce and m an-
ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For deta ils, see Ope rating Mod es (for hardwar e operation) or Software Pr oduct Ide ntificatio n.
The manufacturer and device code is the same for both modes.
5
AT49BV001A(N)(T)
3364C–FLASH–9/03
DATA POLLING: The AT 49 BV 001 A(N) (T ) featur e s DA TA p oll in g to i nd ic ate t he e nd of a pr o-
gram cycl e. Du ring a p ro gr am cyc le an att empted read of the las t byte l oade d wil l res ul t in th e
complem ent of the loaded d ata on I/O 7. Once the program cycle h as been completed, true
data is va li d on al l o utp uts an d th e next cy cle may b egi n. DAT A po ll ing ma y begin a t an y tim e
during the program cycle.
TOGGLE B IT: In addition to DATA polling the AT49BV001A(N)(T) provides another method
for determin ing the end of a program or erase cycle. During a program or erase operation,
success ive a ttempts to r ead da ta from the devi ce wil l result in I/O6 t ogglin g betwee n one an d
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION : Hardware featur es pr otect agai nst inad verte nt pro grams
to the AT4 9BV001A( N)(T) in the fo llowing way s: (a) VCC sense: if VCC is below 1 .8V (t ypical ),
the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or
WE high inh ib its program cyc les. (c ) Noi se fil ter : p ulses of les s tha n 15 ns (t yp ic al) on the WE
or CE inputs will not initiate a program cycle.
6AT49BV001A(N)(T) 3364C–FLASH–9/03
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex ). The address format in each bus cycle is as follows:
A11 - A0 (Hex); A11 - A16 (don’t care).
2. Since A11 is don’t care, AAA can be replaced with 2AA.
3. The 16K b yte boot s ector ha s the a ddress rang e 0000 0H to 03FFFH f o r the AT49BV001A(N) an d 1C000H to 1F FFFH for the
AT49BV001A(N)T
4. Either one of the Product ID Exit commands can be used.
5. SA = sector addresses:
For the AT49BV001A(N):
SA = 00000 to 03FFF for BOOT BLOCK
SA = 04000 to 05FFF for PARAMETER BLOCK 1
SA = 06000 to 07FFF for PARAMETER BLOCK 2
SA = 08000 to FFFF for MAIN MEMORY ARRAY BLOCK 1
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2
For the AT49BV001A(N)T:
SA = 1C000 to 1FFFF for BOOT BLOCK
SA = 1A000 to 1BFFF for PARAMETER BLOCK 1
SA = 18000 to 19FFF for PARAMETER BLOCK 2
SA = 10000 to 17FFF for MAIN MEMORY ARRAY BLOCK 1
SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 2
Command Definition (in Hex)(1)
Command
Sequence Bus
Cycles
1st Bus
Cycle 2nd Bus
Cycle 3rd Bus
Cycle 4th Bu s
Cycle 5th Bus
Cycle 6th Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read 1 Addr DOUT
Chip Erase 6 555 AA AAA(2) 55 555 80 555 AA AAA 55 555 10
Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA(5) 30
Byte Program 4 555 AA AAA 55 555 A0 Addr DIN
Boot Bloc k Lo c k out(3) 6 555 AA AAA 55 555 80 555 AA AAA 55 555 40
Product ID Entry 3 555 AA AAA 55 555 90
Product ID Exit(4) 3 555 AA AAA 55 555 F0
Product ID Exit(4) 1 XXXX F0
Absolute Maxim u m Ratings
Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affe ct de vice reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
7
AT49BV001A(N)(T)
3364C–FLASH–9/03
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programm ing Wavefor ms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 05H – AT49BV001A(N), 04H – AT49BV001A(N)T.
5. See details under Software Product Identification Entry/Exit.
6. This pin is not a vailable on the AT49BV001 AN(T).
Note: 1. In the erase mode, ICC is 50 mA.
DC and AC Operating Range
AT49BV001A(N)(T)-55
Operating Temperature (Case) Ind. -40°C - 85°C
VCC Power Supply 2.7V - 3.6V
Operating Modes
Mode CE OE WE RESET(6) Ai I/O
Read VIL VIL VIH VIH Ai DOUT
Program/Erase(2) VIL VIH VIL VIH Ai DIN
Standby/Write Inhibit VIH X(1) XV
IH X High Z
Program Inhibit X X VIH VIH
Program Inhibit X VIL XV
IH
Output Disable X VIH XV
IH High Z
Reset XXX V
IL X High Z
Product Identification
Hardware VIL VIL VIH
A1 - A16 = VIL, A9 = VH,(3), A0 = VIL Manufacturer Code(4)
A1 - A16 = VIL, A9 = VH,(3), A0 = VIH Device Code(4)
Software(5) A0 = VIL, A1 - A16=VIL Manufacturer Code(4)
A0 = VIH, A1 - A16=VIL Device Code(4)
DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10 µA
ILO Output Lea ka ge Cu rren t VI/O = 0V to VCC 10 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC 50 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 1mA
ICC(1) VCC Active Current f = 5 MHz; IOUT = 0 mA 15 mA
VIL Input Low Voltage 0.6 V
VIH Input High Voltage 2.0 V
VOL O utp ut Lo w Voltage IOL = 2.1 mA 0.45 V
VOH O utp ut Hi gh Voltage IOH = -400 µA 2.4 V
8AT49BV001A(N)(T) 3364C–FLASH–9/03
AC Read Waveforms (1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be de layed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol Parameter
AT49BV001A(N)(T)-55
UnitsMin Max
tACC Address to Output Delay 55 ns
tCE(1) CE to Output Delay 55 ns
tOE(2) OE to Output Delay 0 30 ns
tDF(3)(4) CE or OE to Output Float 0 25 ns
tOH Output Hold from OE, CE or
Address, whichever occurred first 0ns
ADDRESS
OUTPUT
HIGH Z
OUTPUT
OE
CE
t
ACC
t
OE
t
DF
t
OH
t
CE
VALID
ADDRESS VALID
9
AT49BV001A(N)(T)
3364C–FLASH–9/03
Input Test Waveform and Measurement Level
tR, tF < 5 ns
Output Load Test
Note: 1. This parameter is characterized and is not 100% tested.
AC
MEASUREMENT
LEVEL
AC
DRIVING
LEVELS 0.4V
2.4V
1.5V
OUTPUT
PIN
3.0V
30 pF
1.8K
1.3K
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 46pFV
IN = 0V
COUT 812pFV
OUT = 0V
10 AT49BV001A(N)(T) 3364C–FLASH–9/03
AC Byte Load Waveforms
WE Controlled
CE Controlled
AC Byte Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address H old Time 40 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Wi dth (WE or CE)30ns
tDS Data Set-up Time 40 ns
tDH, tOEH Data, OE Hold Time 0ns
tWPH Write Pulse Width High 30 ns
tDH
tDS
tAS tAH
tWP
CE
ADDRESS
DATA IN
OE tOES tOEH
WE tCS
tCH
tWPH
t
DH
t
DS
t
AS
t
AH
t
WP
WE
ADDRESS
DATA IN
OE t
OES
t
OEH
CE t
CS
t
CH
t
WPH
11
AT49BV001A(N)(T)
3364C–FLASH–9/03
Program Cycle Waveforms
Sector or Chip Erase Cycle Waveforms
Notes: 1. OE must be hi gh onl y when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
tBP Byte Progr am mi ng Time 30 50 µs
tAS Address Set-u p Time 0 ns
tAH Address H old Time 40 ns
tDS Data Set-up Time 40 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Widt h 30 ns
tWPH Write Pulse Width High 30 ns
tEC Erase Cy cle Tim e 3 5 seconds
A0 - A16
OE (1)
AA
80 Note 3
55 55
555 555 Note 2
AA
BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5
AAA AAA
t
WPH
tWP
CE
WE
A0 - A16
DATA
t
AS
tAH
tEC
tDH
tDS
555
12 AT49BV001A(N)(T) 3364C–FLASH–9/03
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling W aveforms
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Wavef orms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
Data Polling Characteristics
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tWR Write Recovery Time 0 ns
HIGH Z
An An An An An
WE
CE
OE
I/O7
A0-A16
t
OEH
t
OE
t
DH
t
WR
Toggle Bit Character istics
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tOEHP OE High Pulse 50 ns
tWR Write Recovery Time 0 ns
WE
CE
OE
I/O6
t
OEH
HIGH Z
t
DH
t
OE
t
WR
t
OEHP
13
AT49BV001A(N)(T)
3364C–FLASH–9/03
Software Product Identification Entry(1)
Software ProductIdentification Exit(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A16 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
Additional Device Code is read for address 000 3H
3. The device does not remain in identification mode if
pow e red do w n .
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 05H – AT49BV001A(N)
04H – AT49BV001A(N)T
Additional Device Code: 0FH – AT49BV001A(N)(T)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 90
TO
ADDRESS 555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA F0
TO
ADDRESS 555
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
OR
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
Boot Block Loc kout Feature Enable
Algorithm(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 80
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 40
TO
ADDRESS 555
PAUSE 1 second
(2)
14 AT49BV001A(N)(T) 3364C–FLASH–9/03
AT49BV001A Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Pa ckage Operation RangeActive Standby
55 15 0.05 AT49BV001A-55JI
AT49BV001A-55TI
AT49BV001A-55VI
32J
32T
32V
Industrial
(-40° to 85°C)
AT49BV001AN Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Pa ckage Operation RangeActive Standby
55 15 0.05 AT49BV001AN-55JI
AT49BV001AN-55TI
AT49BV001AN-55VI
32J
32T
32V
Industrial
(-40° to 85°C)
AT49BV001AT Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Pa ckage Operation RangeActive Standby
55 15 0.05 AT49BV001AT-55JI
AT49BV001AT-55TI
AT49BV001AT-55VI
32J
32T
32V
Industrial
(-40° to 85°C)
AT49BV001ANT Ordering Info rmation
tACC
(ns) ICC (mA) Ordering Code Package Operation Range
55 15 0.05 AT49BV001ANT-55JI
AT49BV001ANT-55TI
AT49BV001ANT-55VI
32J
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J 32-Lead, Plastic, J-Leaded Chip Car rier Package (PLCC )
32T 32-Lead, Thin Small Outl ine Package (TSOP)
32V 32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
15
AT49BV001A(N)(T)
3364C–FLASH–9/03
Pa ckaging Information
32J – PLCC
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B
32J
10/04/01
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER 1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 E2
B
e
E1 E
D1
D
D2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
16 AT49BV001A(N)(T) 3364C–FLASH–9/03
32T – TSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP) B
32T
10/18/01
PIN 1
D1 D
Pin 1 Identifier
b
e
EA
A1
A2
0º ~ 8º c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
17
AT49BV001A(N)(T)
3364C–FLASH–9/03
32V – VSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP) B
32V
10/18/01
PIN 1
D1 D
Pin 1 Identifier
b
e
EA
A1
A2
0º ~ 8º c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 13.80 14.00 14.20
D1 12.30 12.40 12.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
Printed on recycled paper.
© Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof are the registered trademarks, and Batter y-Voltage™ is the
trademark of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.
3364C–FLASH–9/03 /xM
Disclaimer: Atmel Cor poration makes no warranty for the use of its products, other than those expressly contained in the Comp any’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel produc ts, exp ressly or by implication. Atmel’s products are not aut horized for use
as critical components in life suppor t devices or systems.
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