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DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 1
Virtex-E Pin Definitions
0
Virtex™-E 1.8 V
Field Programmable Gate Arrays
DS022-4 (v2.3) November 15, 2001 00Preliminary Product Specification
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Pin Name Dedicated Pin Direction Description
GCK0, GCK1,
GCK2, GCK3
Yes Input Clock input pins that connect to Global Clock Buffers.
M0, M1, M2 Yes Input Mode pins are used to specify the configuration mode.
CCLK Yes Input or
Output
The configuration Clock I/O pin: it is an input for SelectMAP and
slave-serial modes, and output in master-serial mode. After
configuration, it is input only, logic level = Don’t Care.
PROGRAM Yes Input Initiates a configuration sequence when asserted Low.
DONE Yes Bidirectional Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output can be open drain.
INIT No Bidirectional
(Open-drain)
When Low, indicates that the configuration memory is being cleared.
The pin becomes a user I/O after configuration.
BUSY/DOUT No Output In SelectMAP mode, BUSY controls the rate at which configuration
data is loaded. The pin becomes a user I/O after configuration unless
the SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data
to downstream devices in a daisy-chain. The pin becomes a user I/O
after configuration.
D0/DIN,
D1, D2,
D3, D4,
D5, D6,
D7
No Input or
Output
In SelectMAP mode, D0-7 are configuration data pins. These pins
become user I/Os after configuration unless the SelectMAP port is
retained.
In bit-serial modes, DIN is the single data input. This pin becomes a
user I/O after configuration.
WRITE No Input In SelectMAP mode, the active-low Write Enable signal. The pin
becomes a user I/O after configuration unless the SelectMAP port is
retained.
CS No Input In SelectMAP mode, the active-low Chip Select signal. The pin
becomes a user I/O after configuration unless the SelectMAP port is
retained.
TDI, TDO,
TMS, TCK
Yes Mixed Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1.
DXN, DXP Yes N/A Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)
VCCINT Yes Input Power-supply pins for the internal core logic.
VCCO Yes Input Power-supply pins for the output drivers (subject to banking rules)
VREF No Input Input threshold voltage pins. Become user I/Os when an external
threshold voltage is not needed (subject to banking rules).
GND Yes Input Ground
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
2 1-800-255-7778 Preliminary Product Specification
Pinout Differences Between Virtex and Virtex-E Families
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
tions, listed in Table 1 .
XCV200E Device, FG456 Package
The Virtex-E XCV200E has two I/O pins swapped with the
Virtex XCV200 to accommodate differential clock pairing.
XCV300E Device, BG432 Package
The Virtex-E XCV300E has eight pins (B26, C7, F1, F30, S
AE29, AF1, AH8, and AH24) connected to VCCINT that are
not connected in the Virtex XCV300.
XCV400E Device, FG676 Package
The Virtex-E XCV400E has two I/O pins swapped with the
Virtex XCV400 to accommodate differential clock pairing.
All Devices, PQ240 and HQ240 Packages
The Virtex devices in PQ240 and HQ240 packages do not
have VCCO banking, but Virtex-E devices do. To achieve
this, eight Virtex I/O pins (P232, P207, P176, P146, P116,
P85, P55, and P25) are now VCCO pins in the Virtex-E fam-
ily. This change also requires one Virtex I/O or VREF pin to
be swapped with a standard I/O pin.
Additionally, accommodating differential clock input pairs in
Virtex-E caused some IO_VREF differences in the XCV400E
and XCV600E devices only. Virtex IO_VREF pins P215 and
P87 are Virtex-E IO_VREF pins P216 and P86, respectively.
Virtex-E pins P215 and P87 are IO_DLL.
Table 1: Pinout Differences Summary
Part Package Pins Virtex Virtex-E
XCV200 FG456 E11, U11 I/O No Connect
B11, AA11 No Connect IO_LVDS_DLL
XCV300 BG432 B26, C7, F1, F30, AE29, AF1, AH8, and AH24 No Connect VCCINT
XCV400 FG676 D13, Y13 I/O No Connect
B13, AF13 No Connect IO_LVDS_DLL
XCV400/600 PQ240/HQ240 P215, P87 IO_VREF IO_LVDS_DLL
P216, P86 I/O IO_VREF
All PQ240/HQ240 P232, P207, P176, P146, P116, P85, P55, and P25 I/O VCCO
P231 I/O IO_VREF
Virtex™-E 1.8 V Field Programmable Gate Arrays
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DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 3
Low Voltage Differential Signals
The Virtex-E family incorporates low-voltage signalling
(LVDS and LVPECL). Two pins are utilized for these signals
to be connected to a Virtex-E device. These are known as
differential pin pairs. Each differential pin pair has a Positive
(P) and a Negative (N) pin. These pairs are labeled in the
following manner.
IO_L#[P/N]
where
L = LVDS or LVPECL pin
# = Pin Pair Number
P = Positive
N = Negative
I/O pins for differential signals can either be synchronous or
asynchronous, input or output. The pin pairs can be used for
synchronous input and output signals as well as asynchro-
nous input signals. However, only some of the low-voltage
pairs can be used for asynchronous output signals.
DIfferential signals require the pins of a pair to switch almost
simultaneously. If the signals driving the pins are from IOB
flip-flops, they are synchronous. If the signals driving the
pins are from internal logic, they are asynchronous. Table 2
defines the names and function of the different types of
low-voltage pin pairs in the Virtex-E family.
Virtex-E Package Pinouts
The Virtex-E family of FPGAs is available in 12 popular
packages, including chip-scale, plastic and high heat-dissi-
pation quad flat packs, and ball grid and fine-pitch ball grid
arrays. Family members have footprint compatibility across
devices provided in the same package. The pinout tables in
this section indicate function, pin, and bank information for
each package/device combination. Following each pinout
table is an additional table summarizing information specific
to differential pin pairs for all devices provided in that pack-
age.
Ta b l e 2 : LVDS Pin Pairs
Pin Name Description
IO_L#[P/N]
Example: IO_L22N
Represents a general IO or a
synchronous input/output
differential signal. When used
as a differential signal, N
means Negative I/O and P
means Positive I/O.
IO_L#[P/N]_Y
Example: IO_L22N_Y
Represents a general IO or a
synchronous input/output
differential signal, or a
part-dependent asynchronous
output differential signal.
IO_L#[P/N]_YY
Example: O_L22N_YY
Represents a general IO or a
synchronous input/output
differential signal, or an
asynchronous output
differential signal.
IO_LVDS_DLL_L#[P/N]
Example:
IO_LVDS_DLL_L16N
Represents a general IO or a
synchronous input/output
differential signal, a differential
clock input signal, or a DLL
input. When used as a
differential clock input, this pin
is paired with the adjacent
GCK pin. The GCK pin is
always the positive input in the
differential clock input
configuration.
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
4 1-800-255-7778 Preliminary Product Specification
CS144 Chip-Scale Package
XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in CS144 Chip-scale packages have footprint com-
patibility. In the CS144 package, bank pairs that share a
side are internally interconnected, permitting four choices
for VCCO. See Ta bl e 3.
Pins labeled I0_VREF can be used as either in all parts
unless device-dependent, as indicated in the footnotes. If
the pin is not used as VREF
, it can be used as general I/O.
Immediately following Table 4, see Table 5 is Differential
Pair information.
Table 3: I/O Bank Pairs and Shared Vcco Pins
Paired Banks Shared VCCO Pins
Banks 0 & 1 A2, A13, D7
Banks 2 & 3 B12, G11, M13
Banks 4 & 5 N1, N7, N13
Banks 6 & 7 B2, G2, M2
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank Pin Description Pin #
0GCK3A6
0IOB3
0 IO_VREF_L0N_YY B42
0 IO_L0P_YY A4
0 IO_L1N_YY B5
0 IO_L1P_YY A5
0 IO_LVDS_DLL_L2N C6
0 IO_VREF A31
0IO_VREFC4
0IO_VREFD6
1GCK2A7
1IOA8
1 IO_LVDS_DLL_L2P B7
1 IO_L3N_YY C8
1IO_L3P_YYD8
1 IO_L4N_YY C9
1 IO_VREF_L4P_YY D92
1 IO_WRITE_L5N_YY C10
1 IO_CS_L5P_YY D10
1 IO_VREF A10
1 IO_VREF B8
1 IO_VREF B101
2IOD12
2IOF12
2 IO_DOUT_BUSY_L6P_YY C11
2 IO_DIN_D0_L6N_YY C12
2 IO_D1_L7N E10
2 IO_VREF_L7P D132
2 IO_L8N_YY E13
2 IO_D2_L8P_YY E12
2 IO_D3_L9N F11
2 IO_VREF_L9P F10
2 IO_L10P F13
2IO_VREFC13
1
2IO_VREFD11
3IOH13
3IOK13
3 IO_L10N G13
3 IO_VREF_L11N H11
3 IO_D4_L11P H12
3 IO_D5_L12N_YY J13
3 IO_L12P_YY H10
3 IO_VREF_L13N J102
3 IO_D6_L13P J11
3 IO_INIT_L14N_YY L13
3 IO_D7_L14P_YY K10
3 IO_VREF K111
3 IO_VREF K12
4GCK0K7
4IOM8
4IOM10
Ta b l e 4 : CS144 — XCV50E, XCV100E, XCV200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
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DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 5
4 IO_L15N_YY M11
4 IO_L15P_YY L11
4 IO_L16N_YY K9
4 IO_VREF_L16P_YY N102
4 IO_L17N_YY K8
4 IO_L17P_YY N9
4 IO_LVDS_DLL_L18P N8
4IO_VREFL8
4 IO_VREF L10
4IO_VREFN11
1
5GCK1M7
5IOM4
5 IO_LVDS_DLL_L18N M6
5 IO_L19N_YY N5
5 IO_L19P_YY K6
5 IO_VREF_L20N_YY N42
5 IO_L20P_YY K5
5 IO_L21N_YY M3
5 IO_L21P_YY N3
5 IO_VREF K41
5IO_VREFL4
5IO_VREFL6
6IOG4
6IOJ4
6 IO_L25P H1
6 IO_VREF_L25N H2
6 IO_L24P_YY H3
6 IO_L24N_YY H4
6 IO_L23P J2
6 IO_VREF_L23N J32
6 IO_VREF K1
6 IO_VREF K21
6 IO_L22N_YY L1
6 IO_L22P_YY K3
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank Pin Description Pin #
6 IO_L26N G1
7IOC2
7IOD3
7IOF3
7 IO_L26P F2
7 IO_L27N F4
7 IO_VREF_L27P E1
7 IO_L28N_YY E2
7 IO_L28P_YY E3
7 IO_L29N D1
7 IO_VREF_L29P D22
7IO_VREFC1
1
7IO_VREFD4
2 CCLK B13
3DONEM12
NA M0 M1
NA M1 L2
NA M2 N2
NA PROGRAM L12
NA TDI A11
NA TCK C3
2TDOA12
NA TMS B1
NA VCCINT A9
NA VCCINT B6
NA VCCINT C5
NA VCCINT G3
NA VCCINT G12
NA VCCINT M5
NA VCCINT M9
NA VCCINT N6
0VCCOA2
Ta b l e 4 : CS144 — XCV50E, XCV100E, XCV200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
6 1-800-255-7778 Preliminary Product Specification
CS144 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
1VCCOA13
1VCCOD7
2VCCOB12
3VCCOG11
3VCCOM13
4VCCON13
5VCCON1
5VCCON7
6VCCOM2
7VCCOB2
7VCCOG2
NA GND A1
NA GND B9
NA GND B11
NA GND C7
NA GND D5
NA GND E4
NA GND E11
NA GND F1
NA GND G10
NA GND J1
NA GND J12
NA GND L3
NA GND L5
NA GND L7
NA GND L9
NA GND N12
Notes:
1. VREF or I/O option only in the XCV200E; otherwise, I/O
option only.
2. VREF or I/O option only in the XCV100E, 200E; otherwise,
I/O option only.
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank Pin Description Pin #
Ta b l e 5 : CS144 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Global Differential Clock
0 4 K7 N8 NA IO_DLL_L18P
1 5 M7 M6 NA IO_DLL_L18N
2 1 A7 B7 NA IO_DLL_L2P
3 0 A6 C6 NA IO_DLL_L2N
IO LVDS
Total Pairs: 30, Asynchronous Output Pairs: 18
0 0 A4 B4
Ö
VREF
1 0 A5 B5
Ö
-
2 1 B7 C6 NA IO_LVDS_DLL
3 1 D8 C8
Ö
-
4 1 D9 C9
Ö
VREF
51D10C10
Ö
CS, WRITE
62C11C12
Ö
DIN, D0
7 2 D13 E10 1 D1, VREF
82E12E13
Ö
D2
92F10F111D3, VREF
10 3 F13 G13 NA -
11 3 H12 H11 1 D4, VREF
12 3 H10 J13
Ö
D5
13 3 J11 J10 1 D6, VREF
14 3 K10 L13
Ö
INIT
15 4 L11 M11
Ö
-
16 4 N10 K9
Ö
VREF
17 4 N9 K8
Ö
-
Virtex™-E 1.8 V Field Programmable Gate Arrays
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DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 7
PQ240 Plastic Quad Flat-Pack Packages
XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in PQ240 Plastic Flat-pack packages have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as VREF
, it can be used as gen-
eral I/O. Immediately following Table 6, see Table 7 for
Differential Pair information.
18 5 N8 M6 NA IO_LVDS_DLL
19 5 K6 N5
Ö
-
20 5 K5 N4
Ö
VREF
21 5 N3 M3
Ö
-
22 6 K3 L1
Ö
-
23 6 J2 J3 1 VREF
24 6 H3 H4
Ö
-
25 6 H1 H2 1 VREF
26 7 F2 G1 NA -
27 7 E1 F4 1 VREF
28 7 E3 E2
Ö
-
29 7 D2 D1 1 VREF
Note 1: AO in the XCV50E
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
Pin # Pin Description Bank
P238 IO 0
P237 IO_L0N_Y 0
P2362IO_VREF_L0P_Y 0
P235 IO_L1N_YY 0
P234 IO_L1P_YY 0
P231 IO_VREF 0
P230 IO 0
P2291IO_VREF_L2N_YY 0
P228 IO_L2P_YY 0
P224 IO_L3N_YY 0
P223 IO_L3P_YY 0
Table 5: CS144 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions P222 IO 0
P221 IO_L4N_Y 0
P220 IO_L4P_Y 0
P218 IO_VREF_L5N_Y 0
P217 IO_L5P_Y 0
P2163IO_VREF 0
P215 IO_LVDS_DLL_L6N 0
P213 GCK3 0
P210 GCK2 1
P209 IO_LVDS_DLL_L6P 1
P2083IO_VREF 1
P206 IO_L7N_Y 1
P205 IO_VREF_L7P_Y 1
P203 IO_L8N_Y 1
P202 IO_L8P_Y 1
P201 IO 1
P200 IO_L9N_YY 1
P199 IO_L9P_YY 1
P195 IO_L10N_YY 1
P1941IO_VREF_L10P_YY 1
P193 IO 1
P192 IO_L11N_YY 1
P191 IO_VREF_L11P_YY 1
P189 IO_L12N_YY 1
P188 IO_L12P_YY 1
P1872IO_VREF_L13N_Y 1
P186 IO_L13P_Y 1
P185 IO_WRITE_L14N_YY 1
P184 IO_CS_L14P_YY 1
P178 IO_DOUT_BUSY_L15P_YY 2
P177 IO_DIN_D0_L15N_YY 2
P1752IO_VREF 2
P174 IO_L16P_Y 2
Ta b l e 6 : PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
Pin # Pin Description Bank
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
8 1-800-255-7778 Preliminary Product Specification
P173 IO_L16N_Y 2
P171 IO_VREF_L17P_Y 2
P170 IO_L17N_Y 2
P169 IO 2
P1681IO_VREF_L18P_Y 2
P167 IO_D1_L18N_Y 2
P163 IO_D2_L19P_YY 2
P162 IO_L19N_YY 2
P161 IO 2
P160 IO_L20P_Y 2
P159 IO_L20N_Y 2
P157 IO_VREF_L21P_Y 2
P156 IO_D3_L21N_Y 2
P155 IO_L22P_Y 2
P1543IO_VREF_L22N_Y 2
P153 IO_L23P_YY 2
P152 IO_L23N_YY 2
P149 IO 3
P1473IO_VREF 3
P145 IO_D4_L24P_Y 3
P144 IO_VREF_L24N_Y 3
P142 IO_L25P_Y 3
P141 IO_L25N_Y 3
P140 IO 3
P139 IO_L26P_YY 3
P138 IO_D5_L26N_YY 3
P134 IO_D6_L27P_Y 3
P1331IO_VREF_L27N_Y 3
P132 IO 3
P131 IO_L28P_Y 3
P130 IO_VREF_L28N_Y 3
P128 IO_L29P_Y 3
P127 IO_L29N_Y 3
P1262IO_VREF_L30P_Y 3
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
Pin # Pin Description Bank
P125 IO_L30N_Y 3
P124 IO_D7_L31P_YY 3
P123 IO_INIT_L31N_YY 3
P118 IO_L32P_YY 4
P117 IO_L32N_YY 4
P1152IO_VREF 4
P114 IO_L33P_YY 4
P113 IO_L33N_YY 4
P111 IO_VREF_L34P_YY 4
P110 IO_L34N_YY 4
P109 IO 4
P1081IO_VREF_L35P_YY 4
P107 IO_L35N_YY 4
P103 IO_L36P_YY 4
P102 IO_L36N_YY 4
P101 IO 4
P100 IO_L37P_Y 4
P99 IO_L37N_Y 4
P97 IO_VREF_L38P_Y 4
P96 IO_L38N_Y 4
P95 IO_L39P_Y 4
P943IO_VREF_L39N_Y 4
P93 IO_LVDS_DLL_L40P 4
P92 GCK0 4
P89 GCK1 5
P87 IO_LVDS_DLL_L40N 5
P863IO_VREF 5
P84 IO_VREF_L41P_Y 5
P82 IO_L41N_Y 5
P81 IO 5
P80 IO 5
P79 IO_L42P_YY 5
P78 IO_L42N_YY 5
Ta b l e 6 : PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
Pin # Pin Description Bank
Virtex™-E 1.8 V Field Programmable Gate Arrays
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Preliminary Product Specification 1-800-255-7778 9
P74 IO_L43P_YY 5
P731IO_VREF_L43N_YY 5
P72 IO 5
P71 IO_L44P_YY 5
P70 IO_VREF_L44N_YY 5
P68 IO_L45P_YY 5
P67 IO_L45N_YY 5
P662IO_VREF_L46P_Y 5
P65 IO_L46N_Y 5
P64 IO_L47P_YY 5
P63 IO_L47N_YY 5
P57 IO_L48N_YY 6
P56 IO_L48P_YY 6
P542IO_VREF 6
P53 IO_L49N_Y 6
P52 IO_L49P_Y 6
P50 IO_VREF_L50N_Y 6
P49 IO_L50P_Y 6
P48 IO 6
P471IO_VREF_L51N_Y 6
P46 IO_L51P_Y 6
P42 IO_L52N_YY 6
P41 IO_L52P_YY 6
P40 IO 6
P39 IO_L53N_Y 6
P38 IO_L53P_Y 6
P36 IO_VREF_L54N_Y 6
P35 IO_L54P_Y 6
P34 IO_L55N_Y 6
P333IO_VREF_L55P_Y 6
P31 IO 6
P28 IO_L56N_YY 7
P27 IO_L56P_YY 7
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
Pin # Pin Description Bank
P263IO_VREF 7
P24 IO_L57N_Y 7
P23 IO_VREF_L57P_Y 7
P21 IO_L58N_Y 7
P20 IO_L58P_Y 7
P19 IO 7
P18 IO_L59N_YY 7
P17 IO_L59P_YY 7
P13 IO_L60N_Y 7
P121IO_VREF_L60P_Y 7
P11 IO 7
P10 IO_L61N_Y 7
P9 IO_VREF_L61P_Y 7
P7 IO_L62N_Y 7
P6 IO_L62P_Y 7
P52IO_VREF_L63N_Y 7
P4 IO_L63P_Y 7
P3 IO 7
P179 CCLK 2
P120 DONE 3
P60 M0 NA
P58 M1 NA
P62 M2 NA
P122 PROGRAM NA
P183 TDI NA
P239 TCK NA
P181 TDO 2
P2 TMS NA
P225 VCCINT NA
P214 VCCINT NA
P198 VCCINT NA
P164 VCCINT NA
P148 VCCINT NA
Ta b l e 6 : PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
Pin # Pin Description Bank
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
10 1-800-255-7778 Preliminary Product Specification
P137 VCCINT NA
P104 VCCINT NA
P88 VCCINT NA
P77 VCCINT NA
P43 VCCINT NA
P32 VCCINT NA
P16 VCCINT NA
P240 VCCO 7
P232 VCCO 0
P226 VCCO 0
P212 VCCO 0
P207 VCCO 1
P197 VCCO 1
P180 VCCO 1
P176 VCCO 2
P165 VCCO 2
P150 VCCO 2
P146 VCCO 3
P136 VCCO 3
P121 VCCO 3
P116 VCCO 4
P105 VCCO 4
P90 VCCO 4
P85 VCCO 5
P76 VCCO 5
P61 VCCO 5
P55 VCCO 6
P44 VCCO 6
P30 VCCO 6
P25 VCCO 7
P15 VCCO 7
P233 GND NA
P227 GND NA
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
Pin # Pin Description Bank
P219 GND NA
P211 GND NA
P204 GND NA
P196 GND NA
P190 GND NA
P182 GND NA
P172 GND NA
P166 GND NA
P158 GND NA
P151 GND NA
P143 GND NA
P135 GND NA
P129 GND NA
P119 GND NA
P112 GND NA
P106 GND NA
P98 GND NA
P91 GND NA
P83 GND NA
P75 GND NA
P69 GND NA
P59 GND NA
P51 GND NA
P45 GND NA
P37 GND NA
P29 GND NA
P22 GND NA
P14 GND NA
P8 GND NA
P1 GND NA
Notes:
1. VREF or I/O option only in the XCV100E, 200E, 300E, 400E;
otherwise, I/O option only.
2. VREF or I/O option only in the XCV200E, 300E, 400E;
otherwise, I/O option only.
3. VREF or I/O option only in the XCV400E; otherwise, I/O
option only.
Ta b l e 6 : PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
Pin # Pin Description Bank
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 11
PQ240 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
.
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
Pair Bank P Pin N Pin AO
Other
Functions
Global Differential Clock
0 4 P92 P93 NA IO_DLL_L40P
1 5 P89 P87 NA IO_DLL_L40N
2 1 P210 P209 NA IO_DLL_L6P
3 0 P213 P215 NA IO_DLL_L6N
IO LVDS
Total Pairs: 64, Asynchronous Outputs Pairs: 27
0 0 P236 P237 1 VREF
1 0 P234 P235
Ö
-
2 0 P228 P229
Ö
VREF
3 0 P223 P224
Ö
-
4 0 P220 P221 3 -
5 0 P217 P218 3 VREF
6 1 P209 P215 NA IO_LVDS_DLL
7 1 P205 P206 3 VREF
8 1 P202 P203 3 -
9 1 P199 P200
Ö
-
10 1 P194 P195
Ö
VREF
11 1 P191 P192
Ö
VREF
12 1 P188 P189
Ö
-
13 1 P186 P187 1 VREF
14 1 P184 P185
Ö
CS
15 2 P178 P177
Ö
DIN, D0
16 2 P174 P173 2 -
17 2 P171 P170 3 VREF
18 2 P168 P167 4 D1, VREF
19 2 P163 P162
Ö
D2
20 2 P160 P159 2 -
21 2 P157 P156 4 D3, VREF
22 2 P155 P154 5 VREF
23 2 P153 P152
Ö
-
24 3 P145 P144 4 D4, VREF
25 3 P142 P141 2 -
26 3 P139 P138
Ö
D5
27 3 P134 P133 4 VREF
28 3 P131 P130 3 VREF
29 3 P128 P127 2 -
30 3 P126 P125 6 VREF
31 3 P124 P123
Ö
INIT
32 4 P118 P117
Ö
-
33 4 P114 P113
Ö
-
34 4 P111 P110
Ö
VREF
35 4 P108 P107
Ö
VREF
36 4 P103 P102
Ö
-
37 4 P100 P99 3 -
38 4 P97 P96 3 VREF
39 4 P95 P94 7 VREF
40 5 P93 P87 NA IO_LVDS_DLL
41 5 P84 P82 8 VREF
42 5 P79 P78
Ö
-
43 5 P74 P73
Ö
VREF
44 5 P71 P70
Ö
VREF
45 5 P68 P67
Ö
-
46 5 P66 P65 1 VREF
47 5 P64 P63
Ö
-
Ta b l e 7 : PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
Pair Bank P Pin N Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
12 1-800-255-7778 Preliminary Product Specification
HQ240 High-Heat Quad Flat-Pack Packages
XCV600E and XCV1000E devices in High-heat dissipation
Quad Flat-pack packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF
, it can be used as general I/O. Immedi-
ately following Table 8, see Table 9 for Differential Pair infor-
mation.
48 6 P56 P57
Ö
-
49 6 P52 P53 2 -
50 6 P49 P50 3 VREF
51 6 P46 P47 4 VREF
52 6 P41 P42
Ö
-
53 6 P38 P39 2 -
54 6 P35 P36 4 VREF
55 6 P33 P34 5 VREF
56 7 P27 P28
Ö
-
57 7 P23 P24 4 VREF
58 7 P20 P21 2 -
59 7 P17 P18
Ö
-
60 7 P12 P13 4 VREF
61 7 P9 P10 3 VREF
62 7 P6 P7 2 -
63 7 P4 P5 6 VREF
Notes:
1. AO in the XCV50E.
2. AO in the XCV50E, 100E, 200E, 300E.
3. AO in the XCV50E, 200E, 300E, 400E.
4. AO in the XCV50E, 300E, 400E.
5. AO in the XCV100E, 200E, 400E.
6. AO in the XCV100E, 400E.
7. AO in the XCV50E, 200E, 400E.
8. AO in the XCV100E.
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
Pair Bank P Pin N Pin AO
Other
Functions
Ta b l e 8 : HQ240 — XCV600E, XCV1000E
Pin # Pin Description Bank
P240 VCCO 7
P239 TCK NA
P238 IO 0
P237 IO_L0N 0
P236 IO_VREF_L0P 0
P235 IO_L1N_YY 0
P234 IO_L1P_YY 0
P233 GND NA
P232 VCCO 0
P231 IO_VREF 0
P230 IO_VREF 0
P229 IO_VREF_L2N_YY 0
P228 IO_L2P_YY 0
P227 GND NA
P226 VCCO 0
P225 VCCINT NA
P224 IO_L3N_YY 0
P223 IO_L3P_YY 0
P222 IO_VREF 01
P221 IO_L4N_Y 0
P220 IO_L4P_Y 0
P219 GND NA
P218 IO_VREF_L5N_Y 0
P217 IO_L5P_Y 0
P216 IO_VREF 0
P215 IO_LVDS_DLL_L6N 0
P214 VCCINT NA
P213 GCK3 0
P212 VCCO 0
P211 GND NA
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 13
P210 GCK2 1
P209 IO_LVDS_DLL_L6P 1
P208 IO_VREF 1
P207 VCCO 1
P206 IO_L7N_Y 1
P205 IO_VREF_L7P_Y 1
P204 GND NA
P203 IO_L8N_Y 1
P202 IO_L8P_Y 1
P2011IO_VREF 1
P200 IO_L9N_YY 1
P199 IO_L9P_YY 1
P198 VCCINT NA
P197 VCCO 1
P196 GND NA
P195 IO_L10N_YY 1
P194 IO_VREF_L10P_YY 1
P193 IO_VREF 1
P192 IO_L11N_YY 1
P191 IO_VREF_L11P_YY 1
P190 GND NA
P189 IO_L12N_YY 1
P188 IO_L12P_YY 1
P187 IO_VREF_L13N 1
P186 IO_L13P 1
P185 IO_WRITE_L14N_YY 1
P184 IO_CS_L14P_YY 1
P183 TDI NA
P182 GND NA
P181 TDO 2
P180 VCCO 1
P179 CCLK 2
P178 IO_DOUT_BUSY_L15P_YY 2
P177 IO_DIN_D0_L15N_YY 2
P176 VCCO 2
P175 IO_VREF 2
Table 8: HQ240 — XCV600E, XCV1000E
Pin # Pin Description Bank
P174 IO_L16P_Y 2
P173 IO_L16N_Y 2
P172 GND NA
P171 IO_VREF_L17P_Y 2
P170 IO_L17N_Y 2
P169 IO_VREF 2
P168 IO_VREF_L18P_Y 2
P167 IO_D1_L18N_Y 2
P166 GND NA
P165 VCCO 2
P164 VCCINT NA
P163 IO_D2_L19P_YY 2
P162 IO_L19N_YY 2
P1611IO_VREF 2
P160 IO_L20P_Y 2
P159 IO_L20N_Y 2
P158 GND NA
P157 IO_VREF_L21P_Y 2
P156 IO_D3_L21N_Y 2
P155 IO_L22P_Y 2
P154 IO_VREF_L22N_Y 2
P153 IO_L23P_YY 2
P152 IO_L23N_YY 2
P151 GND NA
P150 VCCO 2
P149 IO 3
P148 VCCINT NA
P147 IO_VREF 3
P146 VCCO 3
P145 IO_D4_L24P_Y 3
P144 IO_VREF_L24N_Y 3
P143 GND NA
P142 IO_L25P_Y 3
P141 IO_L25N_Y 3
P1401IO_VREF 3
P139 IO_L26P_YY 3
Ta b l e 8 : HQ240 — XCV600E, XCV1000E
Pin # Pin Description Bank
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
14 1-800-255-7778 Preliminary Product Specification
P138 IO_D5_L26N_YY 3
P137 VCCINT NA
P136 VCCO 3
P135 GND NA
P134 IO_D6_L27P_Y 3
P133 IO_VREF_L27N_Y 3
P132 IO_VREF 3
P131 IO_L28P_Y 3
P130 IO_VREF_L28N_Y 3
P129 GND NA
P128 IO_L29P_Y 3
P127 IO_L29N_Y 3
P126 IO_VREF_L30P_Y 3
P125 IO_L30N_Y 3
P124 IO_D7_L31P_YY 3
P123 IO_INIT_L31N_YY 3
P122 PROGRAM NA
P121 VCCO 3
P120 DONE 3
P119 GND NA
P118 IO_L32P_YY 4
P117 IO_L32N_YY 4
P116 VCCO 4
P115 IO_VREF 4
P114 IO_L33P_YY 4
P113 IO_L33N_YY 4
P112 GND NA
P111 IO_VREF_L34P_YY 4
P110 IO_L34N_YY 4
P109 IO_VREF 4
P108 IO_VREF_L35P_YY 4
P107 IO_L35N_YY 4
P106 GND NA
P105 VCCO 4
P104 VCCINT NA
P103 IO_L36P_YY 4
Table 8: HQ240 — XCV600E, XCV1000E
Pin # Pin Description Bank
P102 IO_L36N_YY 4
P1011IO_VREF 4
P100 IO_L37P_Y 4
P99 IO_L37N_Y 4
P98 GND NA
P97 IO_VREF_L38P_Y 4
P96 IO_L38N_Y 4
P95 IO_L39P 4
P94 IO_VREF_L39N 4
P93 IO_LVDS_DLL_L40P 4
P92 GCK0 4
P91 GND NA
P90 VCCO 4
P89 GCK1 5
P88 VCCINT NA
P87 IO_LVDS_DLL_L40N 5
P86 IO_VREF 5
P85 VCCO 5
P84 IO_VREF_L41P 5
P83 GND NA
P82 IO_L41N 5
P81 IO 5
P801IO_VREF 5
P79 IO_L42P_YY 5
P78 IO_L42N_YY 5
P77 VCCINT NA
P76 VCCO 5
P75 GND NA
P74 IO_L43P_YY 5
P73 IO_VREF_L43N_YY 5
P72 IO_VREF 5
P71 IO_L44P_YY 5
P70 IO_VREF_L44N_YY 5
P69 GND NA
P68 IO_L45P_YY 5
P67 IO_L45N_YY 5
Ta b l e 8 : HQ240 — XCV600E, XCV1000E
Pin # Pin Description Bank
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 15
P66 IO_VREF_L46P 5
P65 IO_L46N 5
P64 IO_L47P_YY 5
P63 IO_L47N_YY 5
P62 M2 NA
P61 VCCO 5
P60 M0 NA
P59 GND NA
P58 M1 NA
P57 IO_L48N_YY 6
P56 IO_L48P_YY 6
P55 VCCO 6
P54 IO_VREF 6
P53 IO_L49N_Y 6
P52 IO_L49P_Y 6
P51 GND NA
P50 IO_VREF_L50N_Y 6
P49 IO_L50P_Y 6
P48 IO_VREF 6
P47 IO_VREF_L51N_Y 6
P46 IO_L51P_Y 6
P45 GND NA
P44 VCCO 6
P43 VCCINT NA
P42 IO_L52N_YY 6
P41 IO_L52P_YY 6
P401IO_VREF 6
P39 IO_L53N_Y 6
P38 IO_L53P_Y 6
P37 GND NA
P36 IO_VREF_L54N_Y 6
P35 IO_L54P_Y 6
P34 IO_L55N_Y 6
P33 IO_VREF_L55P_Y 6
P32 VCCINT NA
P31 IO 6
Table 8: HQ240 — XCV600E, XCV1000E
Pin # Pin Description Bank
P30 VCCO 6
P29 GND NA
P28 IO_L56N_YY 7
P27 IO_L56P_YY 7
P26 IO_VREF 7
P25 VCCO 7
P24 IO_L57N_Y 7
P23 IO_VREF_L57P_Y 7
P22 GND NA
P21 IO_L58N_Y 7
P20 IO_L58P_Y 7
P191IO_VREF 7
P18 IO_L59N_YY 7
P17 IO_L59P_YY 7
P16 VCCINT NA
P15 VCCO 7
P14 GND NA
P13 IO_L60N_Y 7
P12 IO_VREF_L60P_Y 7
P11 IO_VREF 7
P10 IO_L61N_Y 7
P9 IO_VREF_L61P_Y 7
P8 GND NA
P7 IO_L62N_Y 7
P6 IO_L62P_Y 7
P5 IO_VREF_L63N_Y 7
P4 IO_L63P_Y 7
P3 IO 7
P2 TMS NA
P1 GND NA
Notes:
1. VREF or I/O option only in the XCV1000E; otherwise, I/O
option only.
Ta b l e 8 : HQ240 — XCV600E, XCV1000E
Pin # Pin Description Bank
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
16 1-800-255-7778 Preliminary Product Specification
HQ240 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Global Differential Clock
0 4 P92 P93 NA IO _DLL_L40P
1 5 P89 P87 NA IO _DLL_L40N
2 1 P210 P209 NA IO _DLL_L6P
3 0 P213 P215 NA IO _DLL_L6N
IO LVDS
Total Pairs: 64, Asynchronous Output Pairs: 53
0 0 P236 P237 NA VREF
1 0 P234 P235
Ö
-
2 0 P228 P229
Ö
VREF
3 0 P223 P224
Ö
-
4 0 P220 P221
Ö
-
5 0 P217 P218
Ö
VREF
6 1 P209 P215 NA IO_LVDS_DLL
7 1 P205 P206
Ö
VREF
8 1 P202 P203
Ö
-
9 1 P199 P200
Ö
-
10 1 P194 P195
Ö
VREF
11 1 P191 P192
Ö
VREF
12 1 P188 P189
Ö
-
13 1 P186 P187 NA VREF
14 1 P184 P185
Ö
CS
15 2 P178 P177
Ö
DIN, D0
16 2 P174 P173
Ö
-
17 2 P171 P170
Ö
VREF
18 2 P168 P167
Ö
D1
19 2 P163 P162
Ö
D2
20 2 P160 P159
Ö
-
21 2 P157 P156
Ö
D3
22 2 P155 P154 1 VREF
23 2 P153 P152
Ö
-
24 3 P145 P144
Ö
D4, VREF
25 3 P142 P141
Ö
-
26 3 P139 P138
Ö
D5
27 3 P134 P133
Ö
VREF
28 3 P131 P130
Ö
VREF
29 3 P128 P127
Ö
-
30 3 P126 P125 1 VREF
31 3 P124 P123
Ö
INIT
32 4 P118 P117
Ö
-
33 4 P114 P113
Ö
-
34 4 P111 P110
Ö
VREF
35 4 P108 P107
Ö
VREF
36 4 P103 P102
Ö
-
37 4 P100 P99
Ö
-
38 4 P97 P96
Ö
VREF
39 4 P95 P94 NA VREF
40 5 P93 P87 NA IO_LVDS_DLL
41 5 P84 P82 NA VREF
42 5 P79 P78
Ö
-
43 5 P74 P73
Ö
VREF
44 5 P71 P70
Ö
VREF
45 5 P68 P67
Ö
-
46 5 P66 P65 NA VREF
47 5 P64 P63
Ö
-
Ta b l e 9 : HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 17
BG352 Ball Grid Array Packages
XCV100E, XCV200E, and XCV300E devices in BG352 Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF
, it can be used as general I/O. Immedi-
ately following Table 10, see Table 11 for Differential Pair
information.
48 6 P56 P57
Ö
-
49 6 P52 P53
Ö
-
50 6 P49 P50
Ö
VREF
51 6 P46 P47
Ö
VREF
52 6 P41 P42
Ö
-
53 6 P38 P39
Ö
-
54 6 P35 P36
Ö
VREF
55 6 P33 P34 1 VREF
56 7 P27 P28
Ö
-
57 7 P23 P24
Ö
VREF
58 7 P20 P21
Ö
-
59 7 P17 P18
Ö
-
60 7 P12 P13
Ö
VREF
61 7 P9 P10
Ö
VREF
62 7 P6 P7
Ö
-
63 7 P4 P5 1 VREF
Note 1: AO in the XCV600E.
Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
0 IO D22
0 IO C231
0 IO B241
0 IO C22
0 IO_VREF_0_L0N_YY D212
0 IO_L0P_YY B23
0 IO A241
0 IO_L1N_YY A23
0 IO_L1P_YY D20
0 IO_VREF_0_L2N_YY C21
0 IO_L2P_YY B22
0 IO B211
0 IO C201
0 IO_L3N B20
0 IO_L3P A21
0 IO D18
0 IO_VREF_0_L4N_YY C19
0 IO_L4P_YY B19
0 IO_L5N_YY D17
0 IO_L5P_YY C18
0 IO B181
0 IO_L6N C17
0 IO_L6P A18
0 IO D161
0 IO_L7N_Y B17
0 IO_L7P_Y C16
0 IO_VREF_0_L8N_Y A16
0 IO_L8P_Y D15
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
18 1-800-255-7778 Preliminary Product Specification
0 IO C15
0 IO B15
1
0 IO_LVDS_DLL_L9N A15
0 GCK3 D14
1 GCK2 B14
1 IO_LVDS_DLL_L9P A13
1 IO B13
1
1 IO_L10N C13
1 IO_L10P A12
1 IO_L11N_Y B12
1 IO_VREF_1_L11P_Y C12
1 IO_L12N_Y A11
1 IO_L12P_Y B11
1 IO B10
1
1 IO_L13N C11
1 IO_L13P D11
1 IO A91
1 IO_L14N_YY B9
1 IO_L14P_YY C10
1 IO_L15N_YY B8
1 IO_VREF_1_L15P_YY C9
1 IO_L16N _Y D9
1 IO_L16P _Y A7
1 IO B7
1 IO C81
1 IO D81
1 IO_L17N_YY A6
1 IO_VREF_1_L17P_YY B6
1 IO_L18N_YY C7
1 IO_L18P_YY A4
1 IO B51
1 IO_L19N_YY C6
1 IO_VREF_1_L19P_YY D62
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
1 IO B4
1 IO C5
1
1 IO A31
1 IO_WRITE_L20N_YY D5
1 IO_CS_L20P_YY C4
2 IO_DOUT_BUSY_L21P_YY E4
2 IO_DIN_D0_L21N_YY D3
2 IO C2
1
2 IO E31
2 IO F4
2 IO_VREF_2_L22P_YY D22
2 IO_L22N_YY C1
2 IO D1
1
2 IO_L23P_YY G4
2 IO_L23N_YY F3
2 IO_VREF_2_L24P_Y E2
2 IO_L24N_Y F2
2 IO G31
2 IO G21
2 IO_L25P F1
2 IO_L25N J4
2 IO H3
2 IO_VREF_2_L26P _Y H2
2 IO_D1_L26N _Y G1
2 IO_D2_L27P_YY J3
2 IO_L27N_YY J2
2 IO K31
2 IO_L28P J1
2 IO_L28N L4
2 IO K21
2 IO_L29P_YY L3
2 IO_L29N_YY L2
2 IO_VREF_2_L30P _Y M4
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 19
2 IO_D3_L30N _Y M3
2 IO_L31P M2
2 IO_L31N M1
2 IO N31
2 IO_L32P_YY N4
2 IO_L32N_YY N2
3 IO P1
3 IO P31
3 IO_L33P R1
3 IO_L33N R2
3 IO_D4_L34P _Y R3
3 IO_VREF_3_L34N _Y R4
3 IO_L35P_YY T2
3 IO_L35N_YY U2
3 IO T31
3 IO_L36P T4
3 IO_L36N V1
3 IO V21
3 IO_L37P_YY U3
3 IO_D5_L37N_YY U4
3 IO_D6_L38P _Y V3
3 IO_VREF_3_L38N _Y V4
3 IO_L39P _Y Y1
3 IO_L39N _Y Y2
3 IO W3
3 IO W41
3 IO AA11
3 IO_L40P_Y AA2
3 IO_VREF_3_L40N_Y Y3
3 IO_L41P_YY AC1
3 IO_L41N_YY AB2
3 IO AA31
3 IO_L42P_YY AA4
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
3 IO_VREF_3_L42N_YY AC22
3 IO AB3
3 IO AD11
3 IO AB41
3 IO_D7_L43P_YY AC3
3 IO_INIT_L43N_YY AD2
4 IO_L44P_YY AC5
4 IO_L44N_YY AD4
4 IO AE31
4 IO AD51
4 IO AC6
4 IO_VREF_4_L45P_YY AE42
4 IO_L45N_YY AF3
4 IO AF41
4 IO_L46P_YY AC7
4 IO_L46N_YY AD6
4 IO_VREF_4_L47P_YY AE5
4 IO_L47N_YY AE6
4 IO AD71
4 IO AE71
4 IO_L48P AF6
4 IO_L48N AC9
4 IO AD8
4 IO_VREF_4_L49P_YY AE8
4 IO_L49N_YY AF7
4 IO_L50P_YY AD9
4 IO_L50N_YY AE9
4 IO AD101
4 IO_L51P AF9
4 IO_L51N AC11
4 IO AE101
4 IO_L52P_Y AD11
4 IO_L52N_Y AE11
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
20 1-800-255-7778 Preliminary Product Specification
4 IO_VREF_4_L53P_Y AC12
4 IO_L53N_Y AD12
4 IO_L54P AE12
4 IO_L54N AF12
4 IO AD13
1
4 IO_LVDS_DLL_L55P AC13
4 GCK0 AE13
5 GCK1 AF14
5 IO_LVDS_DLL_L55N AD14
5 IO AF151
5 IO AE15
5 IO_L56P_Y AD15
5 IO_VREF_5_L56N_Y AC15
5 IO_L57P_Y AE16
5 IO_L57N_Y AE17
5 IO AD16
1
5 IO_L58P AC16
5 IO_L58N AF18
5 IO AE181
5 IO_L59P_YY AD17
5 IO_L59N_YY AC17
5 IO_L60P_YY AD18
5 IO_VREF_5_L60N_YY AC18
5 IO_L61P _Y AF20
5 IO_L61N _Y AE20
5 IO AD19
5 IO AC191
5 IO AF211
5 IO_L62P_YY AE21
5 IO_VREF_5_L62N_YY AD20
5 IO_L63P_YY AF23
5 IO_L63N_YY AE22
5 IO AD21
1
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
5 IO_L64P_YY AC21
5 IO_VREF_5_L64N_YY AE232
5 IO AD22
5 IO AF241
5 IO AC221
6 IO_L65N_YY AC24
6 IO_L65P_YY AD25
6 IO AB241
6 IO AA231
6 IO AC25
6 IO_VREF_6_L66N_YY AD262
6 IO_L66P_YY AC26
6 IO Y231
6 IO_L67N_YY AA24
6 IO_L67P_YY AB25
6 IO_VREF_6_L68N_Y AA25
6 IO_L68P_Y Y24
6 IO Y251
6 IO AA261
6 IO_L69N V23
6 IO_L69P W24
6 IO W25
6 IO_VREF_6_L70N _Y Y26
6 IO_L70P _Y U23
6 IO_L71N_YY V25
6 IO_L71P_YY U24
6 IO V261
6 IO_L72N T23
6 IO_L72P U25
6 IO T241
6 IO_L73N_YY T25
6 IO_L73P_YY T26
6 IO_VREF_6_L74N _Y R24
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 21
6 IO_L74P _Y R25
6 IO_L75N R26
6 IO_L75P P24
6 IO P23
1
6 IO N26
7 IO_L76N_YY N25
7 IO_L76P_YY N24
7 IO M261
7 IO_L77N M25
7 IO_L77P M24
7 IO_L78N _Y M23
7 IO_VREF_7_L78P _Y L26
7 IO_L79N_YY K25
7 IO_L79P_YY L24
7 IO L231
7 IO_L80N J26
7 IO_L80P J25
7 IO K24
1
7 IO_L81N_YY K23
7 IO_L81P_YY H25
7 IO_L82N _Y J23
7 IO_VREF_7_L82P _Y G26
7 IO_L83N _Y G25
7 IO_L83P _Y H24
7 IO H23
7 IO F261
7 IO F251
7 IO_L84N_Y G24
7 IO_VREF_7_L84P_Y D26
7 IO_L85N_YY E25
7 IO_L85P_YY F24
7 IO F231
7 IO_L86N_YY D25
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
7 IO_VREF_7_L86P_YY E242
7 IO C26
7 IO E231
7 IO D241
7 IO C25
NA TDI B3
NA TDO D4
NA CCLK C3
NA TCK C24
NA TMS D23
NA PROGRAM AC4
NA DONE AD3
NA DXN AD23
NA DXP AE24
NA M2 AC23
NA M0 AD24
NA M1 AB23
NA VCCINT A20
NA VCCINT B16
NA VCCINT C14
NA VCCINT D12
NA VCCINT D10
NA VCCINT K4
NA VCCINT L1
NA VCCINT P2
NA VCCINT T1
NA VCCINT W2
NA VCCINT AC10
NA VCCINT AF11
NA VCCINT AE14
NA VCCINT AF16
NA VCCINT AE19
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
22 1-800-255-7778 Preliminary Product Specification
NA VCCINT V24
NA VCCINT R23
NA VCCINT P25
NA VCCINT L25
NA VCCINT J24
0 VCCO D19
0 VCCO B25
0 VCCO A17
1 VCCO D13
1 VCCO D7
1 VCCO A10
2 VCCO K1
2 VCCO H4
2 VCCO B2
3 VCCO Y4
3 VCCO U1
3 VCCO P4
4 VCCO AF10
4 VCCO AE2
4 VCCO AC8
5 VCCO AF17
5 VCCO AC20
5 VCCO AC14
6 VCCO AE25
6 VCCO W23
6 VCCO U26
7 VCCO N23
7 VCCO K26
7 VCCO G23
NA GND A26
NA GND A25
NA GND A22
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
NA GND A19
NA GND A14
NA GND A8
NA GND A5
NA GND A2
NA GND A1
NA GND B26
NA GND B1
NA GND E26
NA GND E1
NA GND H26
NA GND H1
NA GND N1
NA GND P26
NA GND W26
NA GND W1
NA GND AB26
NA GND AB1
NA GND AE26
NA GND AE1
NA GND AF26
NA GND AF25
NA GND AF22
NA GND AF19
NA GND AF13
NA GND AF8
NA GND AF5
NA GND AF2
NA GND AF1
Notes:
1. No Connect in the XCV100E.
2. VREF or I/O option only in the XCV200E and XCV300E;
otherwise, I/O option only.
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 23
BG352 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
check (
Ö)
in the AO column indicates that the pin pair can be
used as an asynchronous output for all devices provided in
this package. Pairs with a note number in the AO column
are device dependent. They can have asynchronous out-
puts if the pin pair are in the same CLB row and column in
the device. Numbers in this column refer to footnotes that
indicate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates alter-
native function(s) not available when the pair is used as a
differential pair or differential clock
Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Global Differential Clock
0 4 AE13 AC13 NA IO LVDS 55
1 5 AF14 AD14 NA IO LVDS 55
2 1 B14 A13 NA IO LVDS 9
3 0 D14 A15 NA IO LVDS 9
IO LVDS
Total Outputs: 87, Asynchronous Output Pairs: 43
00B23 D21
Ö
VREF_0
10D20 A23
Ö
-
20B22 C21
Ö
VREF_0
30A21 B202 -
40B19 C19
Ö
VREF_0
50C18 D17
Ö
-
60A18 C172 -
70C16 B17
Ö
-
80D15 A16
Ö
VREF_0
91A13 A15
Ö
GCLK LVDS 3/2
10 1 A12 C13 2 -
11 1 C12 B12
Ö
VREF_1
12 1 B11 A11
Ö
-
13 1 D11 C11 2 -
14 1 C10 B9
Ö
-
15 1 C9 B8
Ö
VREF_1
16 1 A7 D9 1 -
17 1 B6 A6
Ö
VREF_1
18 1 A4 C7
Ö
-
19 1 D6 C6
Ö
VREF_1
20 1 C4 D5
Ö
CS
21 2 E4 D3
Ö
DIN_D0
22 2 D2 C1
Ö
VREF_2
23 2 G4 F3
Ö
-
24 2 E2 F2
Ö
VREF_2
25 2 F1 J4 2 -
26 2 H2 G1
Ö
D1
27 2 J3 J2
Ö
D2
28 2 J1 L4 1 -
29 2 L3 L2
Ö
-
30 2 M4 M3
Ö
D3
31 2 M2 M1 2 -
32 2 N4 N2
Ö
-
33 3 R1 R2 2 -
34 3 R3 R4
Ö
VREF_3
35 3 T2 U2
Ö
-
36 3 T4 V1 1 -
37 3 U3 U4
Ö
D5
38 3 V3 V4
Ö
VREF_3
39 3 Y1 Y2 1 -
40 3 AA2 Y3
Ö
VREF_3
41 3 AC1 AB2
Ö
-
42 3 AA4 AC2
Ö
VREF_3
43 3 AC3 AD2
Ö
INIT
44 4 AC5 AD4
Ö
-
45 4 AE4 AF3
Ö
VREF_4
46 4 AC7 AD6
Ö
-
47 4 AE5 AE6
Ö
VREF_4
48 4 AF6 AC9 2 -
49 4 AE8 AF7
Ö
VREF_4
50 4 AD9 AE9
Ö
-
51 4 AF9 AC11 2 -
52 4 AD11 AE11
Ö
-
53 4 AC12 AD12
Ö
VREF_4
54 4 AE12 AF12 2 -
Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
24 1-800-255-7778 Preliminary Product Specification
BG432 Ball Grid Array Packages
XCV300E, XCV400E, and XCV600E devices in BG432 Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF
, it can be used as general I/O. Immedi-
ately following Table 12, see Table 13 for Differential Pair
information.
55 5 AC13 AD14
Ö
GCLK LVDS 1/0
56 5 AD15 AC15
Ö
VREF_5
57 5 AE16 AE17
Ö
-
58 5 AC16 AF18 2 -
59 5 AD17 AC17
Ö
-
60 5 AD18 AC18
Ö
VREF_5
61 5 AF20 AE20 1 -
62 5 AE21 AD20
Ö
VREF_5
63 5 AF23 AE22
Ö
-
64 5 AC21 AE23
Ö
VREF_5
65 6 AD25 AC24
Ö
-
66 6 AC26 AD26
Ö
VREF_6
67 6 AB25 AA24
Ö
-
68 6 Y24 AA25
Ö
VREF_6
69 6 W24 V23 2 -
70 6 U23 Y26
Ö
VREF_6
71 6 U24 V25
Ö
-
72 6 U25 T23 1 -
73 6 T26 T25
Ö
-
74 6 R25 R24
Ö
VREF_6
75 6 P24 R26 2 -
76 7 N24 N25
Ö
-
77 7 M24 M25 2 -
78 7 L26 M23
Ö
VREF_7
79 7 L24 K25
Ö
-
80 7 J25 J26 1 -
81 7 H25 K23
Ö
-
82 7 G26 J23
Ö
VREF_7
83 7 H24 G25 1 -
84 7 D26 G24
Ö
VREF_7
85 7 F24 E25
Ö
-
86 7 E24 D25
Ö
VREF_7
Notes:
1. AO in the XCV100E.
2. AO in the XCV200E.
Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
0GCK3D17
0IOA22
0IOA26
0IOB20
0IOC23
0IOC28
0IO_L0N_YB29
0 IO_L0P_Y D27
0 IO_L1N_YY B28
0 IO_L1P_YY C27
0 IO_VREF_L2N_YY D26
0 IO_L2P_YY A28
0IO_L3N_YB27
0 IO_L3P_Y C26
0 IO_L4N_YY D25
0 IO_L4P_YY A27
0 IO_VREF_L5N_YY D24
0 IO_L5P_YY C25
0IO_L6N_YB25
0 IO_L6P_Y D23
0 IO_VREF_L7N_Y C241
0 IO_L7P_Y B24
0 IO_VREF_L8N_YY D22
0 IO_L8P_YY A24
0 IO_L9N_YY C22
0 IO_L9P_YY B22
0 IO_L10N_YY C21
0 IO_L10P_YY D20
0 IO_L11N_YY B21
0 IO_L11P_YY C20
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 25
0 IO_L12N_YY A20
0 IO_L12P_YY D19
0 IO_VREF_L13N_YY B19
0 IO_L13P_YY A19
0 IO_L14N_Y B18
0 IO_L14P_Y D18
0 IO_VREF_L15N_Y C182
0 IO_L15P_Y B17
0 IO_LVDS_DLL_L16N C17
1GCK2A16
1IOA12
1IOB9
1IOB11
1IOC16
1IOD9
1 IO_LVDS_DLL_L16P B16
1 IO_L17N_Y A15
1 IO_L17P_Y B152
1 IO_L18N_Y C15
1 IO_L18P_Y D15
1 IO_L19N_YY B14
1 IO_VREF_L19P_YY A13
1 IO_L20N_YY B13
1 IO_L20P_YY D14
1 IO_L21N_YY C13
1 IO_L21P_YY B12
1 IO_L22N_YY D13
1 IO_L22P_YY C12
1 IO_L23N_YY D12
1 IO_L23P_YY C11
1 IO_L24N_YY B10
1 IO_VREF_L24P_YY C10
1 IO_L25N_Y C9
1 IO_VREF_L25P_Y D101
1 IO_L26N_Y A8
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
1 IO_L26P_Y B8
1 IO_L27N_YY C8
1 IO_VREF_L27P_YY B7
1 IO_L28N_YY D8
1 IO_L28P_YY A6
1 IO_L29N_Y B6
1 IO_L29P_Y D7
1 IO_L30N_YY A5
1 IO_VREF_L30P_YY C6
1 IO_L31N_YY B5
1 IO_L31P_YY D6
1 IO_L32N_Y A4
1 IO_L32P_Y C5
1 IO_WRITE_L33N_YY B4
1 IO_CS_L33P_YY D5
2IOH4
2IOJ3
2IOL3
2IOM1
2IOR2
2 IO_DOUT_BUSY_L34P_YY D3
2 IO_DIN_D0_L34N_YY C2
2 IO_L35P D2
2 IO_L35N E4
2 IO_L36P_Y D1
2 IO_L36N_Y E3
2 IO_VREF_L37P_Y E2
2 IO_L37N_Y F4
2 IO_L38P E1
2 IO_L38N F3
2 IO_L39P_Y F2
2 IO_L39N_Y G4
2 IO_VREF_L40P_YY G3
2 IO_L40N_YY G2
2 IO_L41P_Y H3
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
26 1-800-255-7778 Preliminary Product Specification
2 IO_L41N_Y H2
2 IO_VREF_L42P_Y H11
2 IO_L42N_Y J4
2 IO_VREF_L43P_YY J2
2 IO_D1_L43N_YY K4
2 IO_D2_L44P_YY K2
2 IO_L44N_YY K1
2 IO_L45P_Y L2
2 IO_L45N_Y M4
2 IO_L46P_Y M3
2 IO_L46N_Y M2
2 IO_L47P_Y N4
2 IO_L47N_Y N3
2 IO_VREF_L48P_YY N1
2 IO_D3_L48N_YY P4
2 IO_L49P_Y P3
2 IO_L49N_Y P2
2 IO_VREF_L50P_Y R32
2 IO_L50N_Y R4
2 IO_L51P_YY R1
2 IO_L51N_YY T3
3IOAA2
3IOAC2
3IOAE2
3IOU3
3IOW1
3 IO_L52P_Y U4
3 IO_VREF_L52N_Y U22
3 IO_L53P_Y U1
3 IO_L53N_Y V3
3 IO_D4_L54P_YY V4
3 IO_VREF_L54N_YY V2
3 IO_L55P_Y W3
3 IO_L55N_Y W4
3 IO_L56P_Y Y1
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
3 IO_L56N_Y Y3
3 IO_L57P_Y Y4
3 IO_L57N_Y Y2
3 IO_L58P_YY AA3
3 IO_D5_L58N_YY AB1
3 IO_D6_L59P_YY AB3
3 IO_VREF_L59N_YY AB4
3 IO_L60P_Y AD1
3 IO_VREF_L60N_Y AC31
3 IO_L61P_Y AC4
3 IO_L61N_Y AD2
3 IO_L62P_YY AD3
3 IO_VREF_L62N_YY AD4
3 IO_L63P_Y AF2
3 IO_L63N_Y AE3
3 IO_L64P AE4
3 IO_L64N AG1
3 IO_L65P_Y AG2
3 IO_VREF_L65N_Y AF3
3 IO_L66P_Y AF4
3 IO_L66N_Y AH1
3 IO_L67P AH2
3 IO_L67N AG3
3 IO_D7_L68P_YY AG4
3 IO_INIT_L68N_YY AJ2
3IOT2
4 GCK0 AL16
4IOAH10
4IOAJ11
4IOAK7
4 IO AL12
4 IO AL15
4 IO_L69P_YY AJ4
4 IO_L69N_YY AK3
4 IO_L70P_Y AH5
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 27
4 IO_L70N_Y AK4
4 IO_L71P_YY AJ5
4 IO_L71N_YY AH6
4 IO_VREF_L72P_YY AL4
4 IO_L72N_YY AK5
4 IO_L73P_Y AJ6
4 IO_L73N_Y AH7
4 IO_L74P_YY AL5
4 IO_L74N_YY AK6
4 IO_VREF_L75P_YY AJ7
4 IO_L75N_YY AL6
4 IO_L76P_Y AH9
4 IO_L76N_Y AJ8
4 IO_VREF_L77P_Y AK81
4 IO_L77N_Y AJ9
4 IO_VREF_L78P_YY AL8
4 IO_L78N_YY AK9
4 IO_L79P_YY AK10
4 IO_L79N_YY AL10
4 IO_L80P_YY AH12
4 IO_L80N_YY AK11
4 IO_L81P_YY AJ12
4 IO_L81N_YY AK12
4 IO_L82P_YY AH13
4 IO_L82N_YY AJ13
4 IO_VREF_L83P_YY AL13
4 IO_L83N_YY AK14
4 IO_L84P_Y AH14
4 IO_L84N_Y AJ14
4 IO_VREF_L85P_Y AK152
4 IO_L85N_Y AJ15
4 IO_LVDS_DLL_L86P AH15
5GCK1AK16
5IOAH20
5IOAJ19
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
5IOAJ23
5IOAJ24
5 IO_LVDS_DLL_L86N AL17
5 IO_L87P_Y AK17
5 IO_VREF_L87N_Y AJ172
5 IO_L88P_Y AH17
5 IO_L88N_Y AK18
5 IO_L89P_YY AL19
5 IO_VREF_L89N_YY AJ18
5 IO_L90P_YY AH18
5 IO_L90N_YY AL20
5 IO_L91P_YY AK20
5 IO_L91N_YY AH19
5 IO_L92P_YY AJ20
5 IO_L92N_YY AK21
5 IO_L93P_YY AJ21
5 IO_L93N_YY AL22
5 IO_L94P_YY AJ22
5 IO_VREF_L94N_YY AK23
5 IO_L95P_Y AH22
5 IO_VREF_L95N_Y AL241
5 IO_L96P_Y AK24
5 IO_L96N_Y AH23
5 IO_L97P_YY AK25
5 IO_VREF_L97N_YY AJ25
5 IO_L98P_YY AL26
5 IO_L98N_YY AK26
5 IO_L99P_Y AH25
5 IO_L99N_Y AL27
5 IO_L100P_YY AJ26
5 IO_VREF_L100N_YY AK27
5 IO_L101P_YY AH26
5 IO_L101N_YY AL28
5 IO_L102P_Y AJ27
5 IO_L102N_Y AK28
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
28 1-800-255-7778 Preliminary Product Specification
6IOAA30
6IOAC30
6IOAD29
6IOU31
6IOW28
6 IO_L103N_YY AJ30
6 IO_L103P_YY AH30
6 IO_L104N AG28
6 IO_L104P AH31
6 IO_L105N_Y AG29
6 IO_L105P_Y AG30
6 IO_VREF_L106N_Y AF28
6 IO_L106P_Y AG31
6 IO_L107N AF29
6 IO_L107P AF30
6 IO_L108N_Y AE28
6 IO_L108P_Y AF31
6 IO_VREF_L109N_YY AE30
6 IO_L109P_YY AD28
6 IO_L110N_Y AD30
6 IO_L110P_Y AD31
6 IO_VREF_L111N_Y AC281
6 IO_L111P_Y AC29
6 IO_VREF_L112N_YY AB28
6 IO_L112P_YY AB29
6 IO_L113N_YY AB31
6 IO_L113P_YY AA29
6 IO_L114N_Y Y28
6 IO_L114P_Y Y29
6 IO_L115N_Y Y30
6 IO_L115P_Y Y31
6 IO_L116N_Y W29
6 IO_L116P_Y W30
6 IO_VREF_L117N_YY V28
6 IO_L117P_YY V29
6 IO_L118N_Y V30
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
6 IO_L118P_Y U29
6 IO_VREF_L119N_Y U282
6 IO_L119P_Y U30
6IOT30
7IOC30
7IOH29
7IOH31
7 IO L29
7IOM31
7IOR28
7 IO_L120N_YY T31
7 IO_L120P_YY R29
7 IO_L121N_Y R30
7 IO_VREF_L121P_Y R312
7 IO_L122N_Y P29
7 IO_L122P_Y P28
7 IO_L123N_YY P30
7 IO_VREF_L123P_YY N30
7 IO_L124N_Y N28
7 IO_L124P_Y N31
7 IO_L125N_Y M29
7 IO_L125P_Y M28
7 IO_L126N_Y M30
7 IO_L126P_Y L30
7 IO_L127N_YY K31
7 IO_L127P_YY K30
7 IO_L128N_YY K28
7 IO_VREF_L128P_YY J30
7 IO_L129N_Y J29
7 IO_VREF_L129P_Y J281
7 IO_L130N_Y H30
7 IO_L130P_Y G30
7 IO_L131N_YY H28
7 IO_VREF_L131P_YY F31
7 IO_L132N_Y G29
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 29
7 IO_L132P_Y G28
7 IO_L133N E31
7 IO_L133P E30
7 IO_L134N_Y F29
7 IO_VREF_L134P_Y F28
7 IO_L135N_Y D31
7 IO_L135P_Y D30
7 IO_L136N E29
7 IO_L136P E28
2 CCLK D4
3DONEAH4
NA DXN AH27
NA DXP AK29
NA M0 AH28
NA M1 AH29
NA M2 AJ28
NA PROGRAM AH3
NA TCK D28
NA TDI B3
2 TDO C4
NA TMS D29
NA VCCINT A10
NA VCCINT A17
NA VCCINT B23
NA VCCINT B26
NA VCCINT C7
NA VCCINT C14
NA VCCINT C19
NA VCCINT F1
NA VCCINT F30
NA VCCINT K3
NA VCCINT K29
NA VCCINT N2
NA VCCINT N29
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
NA VCCINT T1
NA VCCINT T29
NA VCCINT W2
NA VCCINT W31
NA VCCINT AB2
NA VCCINT AB30
NA VCCINT AE29
NA VCCINT AF1
NA VCCINT AH8
NA VCCINT AH24
NA VCCINT AJ10
NA VCCINT AJ16
NA VCCINT AK22
NA VCCINT AK13
NA VCCINT AK19
0 VCCO A21
0 VCCO C29
0 VCCO D21
1 VCCO A1
1 VCCO A11
1 VCCO D11
2 VCCO C3
2 VCCO L4
2 VCCO L1
3 VCCO AA1
3 VCCO AA4
3 VCCO AJ3
4 VCCO AH11
4 VCCO AL1
4 VCCO AL11
5 VCCO AH21
5 VCCO AL21
5 VCCO AJ29
6 VCCO AA28
6 VCCO AA31
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
30 1-800-255-7778 Preliminary Product Specification
6 VCCO AL31
7 VCCO A31
7 VCCO L28
7 VCCO L31
NA GND A2
NA GND A3
NA GND A7
NA GND A9
NA GND A14
NA GND A18
NA GND A23
NA GND A25
NA GND A29
NA GND A30
NA GND B1
NA GND B2
NA GND B30
NA GND B31
NA GND C1
NA GND C31
NA GND D16
NA GND G1
NA GND G31
NA GND J1
NA GND J31
NA GND P1
NA GND P31
NA GND T4
NA GND T28
NA GND V1
NA GND V31
NA GND AC1
NA GND AC31
NA GND AE1
NA GND AE31
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
NA GND AH16
NA GND AJ1
NA GND AJ31
NA GND AK1
NA GND AK2
NA GND AK30
NA GND AK31
NA GND AL2
NA GND AL3
NA GND AL7
NA GND AL9
NA GND AL14
NA GND AL18
NA GND AL23
NA GND AL25
NA GND AL29
NA GND AL30
Notes:
1. VREF or I/O option only in the XCV600E; otherwise, I/O
option only.
2. VREF or I/O option only in the XCV400E, XCV600E;
otherwise, I/O option only.
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 31
BG432 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also Vir-
tex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
Pair Bank P
Pin
N
Pin
AO Other
Functions
Global Differential Clock
0 4 AL16 AH15 NA IO_DLL_L86P
1 5 AK16 AL17 NA IO_DLL_L86N
2 1 A16 B16 NA IO_DLL_L16P
3 0 D17 C17 NA IO_DLL_L16N
IO LVDS
Total Outputs: 137, Asynchronous Output Pairs: 63
00D27B291 -
10C27B28
Ö
-
20A28D26
Ö
VREF
30C26B272 -
40A27D25
Ö
-
50C25D24
Ö
VREF
60D23B251 -
70B24C241 VREF
80A24D22
Ö
VREF
90B22C22
Ö
-
10 0 D20 C21
Ö
-
11 0 C20 B21
Ö
-
12 0 D19 A20
Ö
-
13 0 A19 B19
Ö
VREF
14 0 D18 B18 1 -
15 0 B17 C18 1 VREF
16 1 B16 C17 NA IO_LVDS_DLL
17 1 B15 A15 1 VREF
18 1 D15 C15 1 -
19 1 A13 B14
Ö
VREF
20 1 D14 B13
Ö
-
21 1 B12 C13
Ö
-
22 1 C12 D13
Ö
-
23 1 C11 D12
Ö
-
24 1 C10 B10
Ö
VREF
25 1 D10 C9 1 VREF
26 1 B8 A8 1 -
27 1 B7 C8
Ö
VREF
28 1 A6 D8
Ö
-
29 1 D7 B6 2 -
30 1 C6 A5
Ö
VREF
31 1 D6 B5
Ö
-
32 1 C5 A4 1 -
33 1 D5 B4
Ö
CS, WRITE
34 2 D3 C2
Ö
DIN, D0, BUSY
35 2 D2 E4 3 -
36 2 D1 E3 4 -
37 2 E2 F4 1 VREF
38 2 E1 F3 5 -
39 2 F2 G4 1 -
40 2 G3 G2
Ö
VREF
41 2 H3 H2 4 -
42 2 H1 J4 1 VREF
43 2 J2 K4
Ö
D1
44 2 K2 K1
Ö
D2
45 2 L2 M4 4 -
46 2 M3 M2 1 -
47 2 N4 N3 1 -
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
Pair Bank P
Pin
N
Pin
AO Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
32 1-800-255-7778 Preliminary Product Specification
48 2 N1 P4
Ö
D3
49 2 P3 P2 4 -
50 2 R3 R4 1 VREF
51 2 R1 T3
Ö
-
52 3 U4 U2 1 VREF
53 3 U1 V3 4 -
54 3 V4 V2
Ö
VREF
55 3 W3 W4 1 -
56 3 Y1 Y3 1 -
57 3 Y4 Y2 4 -
58 3 AA3 AB1
Ö
D5
59 3 AB3 AB4
Ö
VREF
60 3 AD1 AC3 1 VREF
61 3 AC4 AD2 4 -
62 3 AD3 AD4
Ö
VREF
63 3 AF2 AE3 1 -
64 3 AE4 AG1 5 -
65 3 AG2 AF3 1 VREF
66 3 AF4 AH1 4 -
67 3 AH2 AG3 3 -
68 3 AG4 AJ2
Ö
INIT
69 4 AJ4 AK3
Ö
-
70 4 AH5 AK4 1 -
71 4 AJ5 AH6
Ö
-
72 4 AL4 AK5
Ö
VREF
73 4 AJ6 AH7 2 -
74 4 AL5 AK6
Ö
-
75 4 AJ7 AL6
Ö
VREF
76 4 AH9 AJ8 1 -
77 4 AK8 AJ9 1 VREF
78 4 AL8 AK9
Ö
VREF
79 4 AK10 AL10
Ö
-
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
Pair Bank P
Pin
N
Pin
AO Other
Functions
80 4 AH12 AK11
Ö
-
81 4 AJ12 AK12
Ö
-
82 4 AH13 AJ13
Ö
-
83 4 AL13 AK14
Ö
VREF
84 4 AH14 AJ14 1 -
85 4 AK15 AJ15 1 VREF
86 5 AH15 AL17 NA IO_LVDS_DLL
87 5 AK17 AJ17 1 VREF
88 5 AH17 AK18 1 -
89 5 AL19 AJ18
Ö
VREF
90 5 AH18 AL20
Ö
-
91 5 AK20 AH19
Ö
-
92 5 AJ20 AK21
Ö
-
93 5 AJ21 AL22
Ö
-
94 5 AJ22 AK23
Ö
VREF
95 5 AH22 AL24 1 VREF
96 5 AK24 AH23 1 -
97 5 AK25 AJ25
Ö
VREF
98 5 AL26 AK26
Ö
-
99 5 AH25 AL27 2 -
100 5 AJ26 AK27
Ö
VREF
101 5 AH26 AL28
Ö
-
102 5 AJ27 AK28 1 -
103 6 AH30 AJ30
Ö
-
104 6 AH31 AG28 3 -
105 6 AG30 AG29 4 -
106 6 AG31 AF28 1 VREF
107 6 AF30 AF29 5 -
108 6 AF31 AE28 1 -
109 6 AD28 AE30
Ö
VREF
110 6 AD31 AD30 4 -
111 6 AC29 AC28 1 VREF
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
Pair Bank P
Pin
N
Pin
AO Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 33
BG560 Ball Grid Array Packages
XCV1000E, XCV1600E, and XCV2000E devices in BG560
Ball Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF
, it can be used as general I/O. Immedi-
ately following Table 14, see Table 15 for Differential Pair
information.
112 6 AB29 AB28
Ö
VREF
113 6 AA29 AB31
Ö
-
114 6 Y29 Y28 4 -
115 6 Y31 Y30 1 -
116 6 W30 W29 1 -
117 6 V29 V28
Ö
VREF
118 6 U29 V30 4 -
119 6 U30 U28 1 VREF
120 7 R29 T31
Ö
-
121 7 R31 R30 1 VREF
122 7 P28 P29 4 -
123 7 N30 P30
Ö
VREF
124 7 N31 N28 1 -
125 7 M28 M29 1 -
126 7 L30 M30 4 -
127 7 K30 K31
Ö
-
128 7 J30 K28
Ö
VREF
129 7 J28 J29 1 VREF
130 7 G30 H30 4 -
131 7 F31 H28
Ö
VREF
132 7 G28 G29 1 -
133 7 E30 E31 5 -
134 7 F28 F29 1 VREF
135 7 D30 D31 4 -
136 7 E28 E29 3 -
Notes:
1. AO in the XCV300E, 600E.
2. AO in the XCV300E.
3. AO in the XCV400E, 600E.
4. AO in the XCV300E, 400E.
5. AO in the XCV600E.
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
Pair Bank P
Pin
N
Pin
AO Other
Functions
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
0GCK3A17
0IOA27
0IOB25
0IOC28
0IOC30
0IOD30
0 IO_L0N E28
0 IO_VREF_L0P D29 3
0 IO_L1N_YY D28
0 IO_L1P_YY A31
0 IO_VREF_L2N_YY E27
0 IO_L2P_YY C29
0 IO_L3N_Y B30
0 IO_L3P_Y D27
0 IO_L4N_YY E26
0 IO_L4P_YY B29
0 IO_VREF_L5N_YY D26
0 IO_L5P_YY C27
0 IO_L6N_Y E25
0 IO_VREF_L6P_Y A28 1
0 IO_L7N_Y D25
0 IO_L7P_Y C26
0 IO_VREF_L8N_Y E24 4
0IO_L8P_YB26
0 IO_L9N_Y C25
0 IO_L9P_Y D24
0 IO_VREF_L10N_YY E23
0 IO_L10P_YY A25
0 IO_L11N_YY D23
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
34 1-800-255-7778 Preliminary Product Specification
0 IO_L11P_YY B24
0 IO_L12N_Y E22
0 IO_L12P_Y C23
0 IO_L13N_YY A23
0 IO_L13P_YY D22
0 IO_VREF_L14N_YY E21 3
0 IO_L14P_YY B22
0 IO_L15N_Y D21
0 IO_L15P_Y C21
0 IO_L16N_YY B21
0 IO_L16P_YY E20
0 IO_VREF_L17N_YY D20
0 IO_L17P_YY C20
0 IO_L18N_Y B20
0 IO_L18P_Y E19
0 IO_L19N_Y D19
0 IO_L19P_Y C19
0 IO_VREF_L20N_Y A19
0 IO_L20P_Y D18
0 IO_LVDS_DLL_L21N C18
0 IO_VREF E18 2
1GCK2D17
1IOA3
1IOD9
1IOE8
1IOE11
1 IO_LVDS_DLL_L21P E17
1 IO_VREF_L22N_Y C17 2
1 IO_L22P_Y B17
1 IO_L23N_Y B16
1 IO_VREF_L23P_Y D16
1 IO_L24N_Y E16
1 IO_L24P_Y C16
1 IO_L25N_Y A15
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
1 IO_L25P_Y C15
1 IO_L26N_YY D15
1 IO_VREF_L26P_YY E15
1 IO_L27N_YY C14
1 IO_L27P_YY D14
1 IO_L28N_Y A13
1 IO_L28P_Y E14
1 IO_L29N_YY C13
1 IO_VREF_L29P_YY D13 3
1 IO_L30N_YY C12
1 IO_L30P_YY E13
1 IO_L31N_Y A11
1 IO_L31P_Y D12
1 IO_L32N_YY B11
1 IO_L32P_YY C11
1 IO_L33N_YY B10
1 IO_VREF_L33P_YY D11
1 IO_L34N_Y C10
1 IO_L34P_Y A9
1 IO_L35N_Y C9
1 IO_VREF_L35P_Y D10 4
1 IO_L36N_Y A8
1 IO_L36P_Y B8
1 IO_L37N_Y E10
1 IO_VREF_L37P_Y C8 1
1 IO_L38N_YY B7
1 IO_VREF_L38P_YY A6
1 IO_L39N_YY C7
1 IO_L39P_YY D8
1 IO_L40N_Y A5
1 IO_L40P_Y B5
1 IO_L41N_YY C6
1 IO_VREF_L41P_YY D7
1 IO_L42N_YY A4
1 IO_L42P_YY B4
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 35
1 IO_L43N_Y C5
1 IO_VREF_L43P_Y E7 3
1 IO_WRITE_L44N_YY D6
1 IO_CS_L44P_YY A2
2IOD3
2IOF3
2IOG1
2IO J2
2 IO_DOUT_BUSY_L45P_YY D4
2 IO_DIN_D0_L45N_YY E4
2 IO_L46P_Y F5
2 IO_VREF_L46N_Y B3 3
2 IO_L47P_Y F4
2 IO_L47N_Y C1
2 IO_VREF_L48P_Y G5
2 IO_L48N_Y E3
2 IO_L49P_Y D2
2 IO_L49N_Y G4
2 IO_L50P_Y H5
2 IO_L50N_Y E2
2 IO_VREF_L51P_YY H4
2 IO_L51N_YY G3
2 IO_L52P_Y J5
2 IO_VREF_L52N_Y F1 1
2 IO_L53P_Y J4
2 IO_L53N_Y H3
2 IO_VREF_L54P_Y K5 4
2 IO_L54N_Y H2
2 IO_L55P_Y J3
2 IO_L55N_Y K4
2 IO_VREF_L56P_YY L5
2 IO_D1_L56N_YY K3
2 IO_D2_L57P_YY L4
2 IO_L57N_YY K2
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
2 IO_L58P_Y M5
2 IO_L58N_Y L3
2 IO_L59P_Y L1
2 IO_L59N_Y M4
2 IO_VREF_L60P_Y N5 3
2 IO_L60N_Y M2
2 IO_L61P_Y N4
2 IO_L61N_Y N3
2 IO_L62P_Y N2
2 IO_L62N_Y P5
2 IO_VREF_L63P_YY P4
2 IO_D3_L63N_YY P3
2 IO_L64P_Y P2
2 IO_L64N_Y R5
2 IO_L65P_Y R4
2 IO_L65N_Y R3
2 IO_VREF_L66P_Y R1
2 IO_L66N_Y T4
2 IO_L67P_Y T5
2 IO_VREF_L67N_Y T3 2
2 IO_L68P_YY T2
2 IO_L68N_YY U3
3IOAE3
3IOAF3
3IOAH3
3IOAK3
3 IO_VREF_L69P_Y U1 2
3 IO_L69N_Y U2
3 IO_L70P_Y V2
3 IO_VREF_L70N_Y V4
3 IO_L71P_Y V5
3 IO_L71N_Y V3
3 IO_L72P_Y W1
3 IO_L72N_Y W3
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
36 1-800-255-7778 Preliminary Product Specification
3 IO_D4_L73P_YY W4
3 IO_VREF_L73N_YY W5
3 IO_L74P_Y Y3
3 IO_L74N_Y Y4
3 IO_L75P_Y AA1
3 IO_L75N_Y Y5
3 IO_L76P_Y AA3
3 IO_VREF_L76N_Y AA4 3
3 IO_L77P_Y AB3
3 IO_L77N_Y AA5
3 IO_L78P_Y AC1
3 IO_L78N_Y AB4
3 IO_L79P_YY AC3
3 IO_D5_L79N_YY AB5
3 IO_D6_L80P_YY AC4
3 IO_VREF_L80N_YY AD3
3 IO_L81P_Y AE1
3 IO_L81N_Y AC5
3 IO_L82P_Y AD4
3 IO_VREF_L82N_Y AF1 4
3 IO_L83P_Y AF2
3 IO_L83N_Y AD5
3 IO_L84P_Y AG2
3 IO_VREF_L84N_Y AE4 1
3 IO_L85P_YY AH1
3 IO_VREF_L85N_YY AE5
3 IO_L86P_Y AF4
3 IO_L86N_Y AJ1
3 IO_L87P_Y AJ2
3 IO_L87N_Y AF5
3 IO_L88P_Y AG4
3 IO_VREF_L88N_Y AK2
3 IO_L89P_Y AJ3
3 IO_L89N_Y AG5
3 IO_L90P_Y AL1
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
3 IO_VREF_L90N_Y AH4 3
3 IO_D7_L91P_YY AJ4
3 IO_INIT_L91N_YY AH5
3IOU4
4 GCK0 AL17
4IOAJ8
4IOAJ11
4IOAK6
4IOAK9
4 IO_L92P_YY AL4
4 IO_L92N_YY AJ6
4 IO_L93P_Y AK5
4 IO_VREF_L93N_Y AN3 3
4 IO_L94P_YY AL5
4 IO_L94N_YY AJ7
4 IO_VREF_L95P_YY AM4
4 IO_L95N_YY AM5
4 IO_L96P_Y AK7
4 IO_L96N_Y AL6
4 IO_L97P_YY AM6
4 IO_L97N_YY AN6
4 IO_VREF_L98P_YY AL7
4 IO_L98N_YY AJ9
4 IO_L99P_Y AN7
4 IO_VREF_L99N_Y AL8 1
4 IO_L100P_Y AM8
4 IO_L100N_Y AJ10
4 IO_VREF_L101P_Y AL9 4
4 IO_L101N_Y AM9
4 IO_L102P_Y AK10
4 IO_L102N_Y AN9
4 IO_VREF_L103P_YY AL10
4 IO_L103N_YY AM10
4 IO_L104P_YY AL11
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 37
4 IO_L104N_YY AJ12
4 IO_L105P_Y AN11
4 IO_L105N_Y AK12
4 IO_L106P_YY AL12
4 IO_L106N_YY AM12
4 IO_VREF_L107P_YY AK13 3
4 IO_L107N_YY AL13
4 IO_L108P_Y AM13
4 IO_L108N_Y AN13
4 IO_L109P_YY AJ14
4 IO_L109N_YY AK14
4 IO_VREF_L110P_YY AM14
4 IO_L110N_YY AN15
4 IO_L111P_Y AJ15
4 IO_L111N_Y AK15
4 IO_L112P_Y AL15
4 IO_L112N_Y AM16
4 IO_VREF_L113P_Y AL16
4 IO_L113N_Y AJ16
4 IO_L114P_Y AK16
4 IO_VREF_L114N_Y AN17 2
4 IO_LVDS_DLL_L115P AM17
5GCK1AJ17
5 IO AL25
5 IO AL28
5 IO AL30
5IOAN28
5 IO_LVDS_DLL_L115N AM18
5 IO_VREF AL18 2
5 IO_L116P_Y AK18
5 IO_VREF_L116N_Y AJ18
5 IO_L117P_Y AN19
5 IO_L117N_Y AL19
5 IO_L118P_Y AK19
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
5 IO_L118N_Y AM20
5 IO_L119P_YY AJ19
5 IO_VREF_L119N_YY AL20
5 IO_L120P_YY AN21
5 IO_L120N_YY AL21
5 IO_L121P_Y AJ20
5 IO_L121N_Y AM22
5 IO_L122P_YY AK21
5 IO_VREF_L122N_YY AN23 3
5 IO_L123P_YY AJ21
5 IO_L123N_YY AM23
5 IO_L124P_Y AK22
5 IO_L124N_Y AM24
5 IO_L125P_YY AL23
5 IO_L125N_YY AJ22
5 IO_L126P_YY AK23
5 IO_VREF_L126N_YY AL24
5 IO_L127P_Y AN26
5 IO_L127N_Y AJ23
5 IO_L128P_Y AK24
5 IO_VREF_L128N_Y AM26 4
5 IO_L129P_Y AM27
5 IO_L129N_Y AJ24
5 IO_L130P_Y AL26
5 IO_VREF_L130N_Y AK25 1
5 IO_L131P_YY AN29
5 IO_VREF_L131N_YY AJ25
5 IO_L132P_YY AK26
5 IO_L132N_YY AM29
5 IO_L133P_Y AM30
5 IO_L133N_Y AJ26
5 IO_L134P_YY AK27
5 IO_VREF_L134N_YY AL29
5 IO_L135P_YY AN31
5 IO_L135N_YY AJ27
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
38 1-800-255-7778 Preliminary Product Specification
5 IO_L136P_Y AM31
5 IO_VREF_L136N_Y AK28 3
6IOAE33
6IOAF31
6IOAJ32
6 IO AL33
6 IO_L137N_YY AH29
6 IO_L137P_YY AJ30
6 IO_L138N_Y AK31
6 IO_VREF_L138P_Y AH30 3
6 IO_L139N_Y AG29
6 IO_L139P_Y AJ31
6 IO_VREF_L140N_Y AK32
6 IO_L140P_Y AG30
6 IO_L141N_Y AH31
6 IO_L141P_Y AF29
6 IO_L142N_Y AH32
6 IO_L142P_Y AF30
6 IO_VREF_L143N_YY AE29
6 IO_L143P_YY AH33
6 IO_L144N_Y AG33
6 IO_VREF_L144P_Y AE30 1
6 IO_L145N_Y AD29
6 IO_L145P_Y AF32
6 IO_VREF_L146N_Y AE31 4
6 IO_L146P_Y AD30
6 IO_L147N_Y AE32
6 IO_L147P_Y AC29
6 IO_VREF_L148N_YY AD31
6 IO_L148P_YY AC30
6 IO_L149N_YY AB29
6 IO_L149P_YY AC31
6 IO_L150N_Y AC33
6 IO_L150P_Y AB30
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
6 IO_L151N_Y AB31
6 IO_L151P_Y AA29
6 IO_VREF_L152N_Y AA30 3
6 IO_L152P_Y AA31
6 IO_L153N_Y AA32
6 IO_L153P_Y Y29
6 IO_L154N_Y AA33
6 IO_L154P_Y Y30
6 IO_VREF_L155N_YY Y32
6 IO_L155P_YY W29
6 IO_L156N_Y W30
6 IO_L156P_Y W31
6 IO_L157N_Y W33
6 IO_L157P_Y V30
6 IO_VREF_L158N_Y V29
6 IO_L158P_Y V31
6 IO_L159N_Y V32
6 IO_VREF_L159P_Y U33 2
6IOU29
7IOE30
7IOF29
7IOF33
7IOG30
7IOK30
7 IO_L160N_YY U31
7 IO_L160P_YY U32
7 IO_VREF_L161N_Y T32 2
7 IO_L161P_Y T30
7 IO_L162N_Y T29
7 IO_VREF_L162P_Y T31
7 IO_L163N_Y R33
7 IO_L163P_Y R31
7 IO_L164N_Y R30
7 IO_L164P_Y R29
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 39
7 IO_L165N_YY P32
7 IO_VREF_L165P_YY P31
7 IO_L166N_Y P30
7 IO_L166P_Y P29
7 IO_L167N_Y M32
7 IO_L167P_Y N31
7 IO_L168N_Y N30
7 IO_VREF_L168P_Y L33 3
7 IO_L169N_Y M31
7 IO_L169P_Y L32
7 IO_L170N_Y M30
7 IO_L170P_Y L31
7 IO_L171N_YY M29
7 IO_L171P_YY J33
7 IO_L172N_YY L30
7 IO_VREF_L172P_YY K31
7 IO_L173N_Y L29
7 IO_L173P_Y H33
7 IO_L174N_Y J31
7 IO_VREF_L174P_Y H32 4
7 IO_L175N_Y K29
7 IO_L175P_Y H31
7 IO_L176N_Y J30
7 IO_VREF_L176P_Y G32 1
7 IO_L177N_YY J29
7 IO_VREF_L177P_YY G31
7 IO_L178N_Y E33
7 IO_L178P_Y E32
7 IO_L179N_Y H29
7 IO_L179P_Y F31
7 IO_L180N_Y D32
7 IO_VREF_L180P_Y E31
7 IO_L181N_Y G29
7 IO_L181P_Y C33
7 IO_L182N_Y F30
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
7 IO_VREF_L182P_Y D31 3
2 CCLK C4
3DONEAJ5
NA DXN AK29
NA DXP AJ28
NA M0 AJ29
NA M1 AK30
NA M2 AN32
NA PROGRAM AM1
NA TCK E29
NA TDI D5
2TDOE6
NA TMS B33
NA NC C31
NA NC AC2
NA NC AK4
NA NC AL3
NA VCCINT A21
NA VCCINT B12
NA VCCINT B14
NA VCCINT B18
NA VCCINT B28
NA VCCINT C22
NA VCCINT C24
NA VCCINT E9
NA VCCINT E12
NA VCCINT F2
NA VCCINT H30
NA VCCINT J1
NA VCCINT K32
NA VCCINT M3
NA VCCINT N1
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
40 1-800-255-7778 Preliminary Product Specification
NA VCCINT N29
NA VCCINT N33
NA VCCINT U5
NA VCCINT U30
NA VCCINT Y2
NA VCCINT Y31
NA VCCINT AB2
NA VCCINT AB32
NA VCCINT AD2
NA VCCINT AD32
NA VCCINT AG3
NA VCCINT AG31
NA VCCINT AJ13
NA VCCINT AK8
NA VCCINT AK11
NA VCCINT AK17
NA VCCINT AK20
NA VCCINT AL14
NA VCCINT AL22
NA VCCINT AL27
NA VCCINT AN25
0VCCOA22
0VCCOA26
0VCCOA30
0VCCOB19
0VCCOB32
1VCCOA10
1VCCOA16
1VCCOB13
1VCCOC3
1VCCOE5
2VCCOB2
2VCCOD1
2VCCOH1
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
2VCCOM1
2VCCOR2
3VCCOV1
3VCCOAA2
3VCCOAD1
3VCCOAK1
3VCCOAL2
4VCCOAN4
4VCCOAN8
4VCCOAN12
4VCCOAM2
4VCCOAM15
5 VCCO AL31
5VCCOAM21
5VCCOAN18
5VCCOAN24
5VCCOAN30
6VCCOW32
6VCCOAB33
6VCCOAF33
6VCCOAK33
6VCCOAM32
7VCCOC32
7VCCOD33
7VCCOK33
7VCCON32
7VCCOT33
NA GND A1
NA GND A7
NA GND A12
NA GND A14
NA GND A18
NA GND A20
NA GND A24
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 41
NA GND A29
NA GND A32
NA GND A33
NA GND B1
NA GND B6
NA GND B9
NA GND B15
NA GND B23
NA GND B27
NA GND B31
NA GND C2
NA GND E1
NA GND F32
NA GND G2
NA GND G33
NA GND J32
NA GND K1
NA GND L2
NA GND M33
NA GND P1
NA GND P33
NA GND R32
NA GND T1
NA GND V33
NA GND W2
NA GND Y1
NA GND Y33
NA GND AB1
NA GND AC32
NA GND AD33
NA GND AE2
NA GND AG1
NA GND AG32
NA GND AH2
NA GND AJ33
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
NA GND AL32
NA GND AM3
NA GND AM7
NA GND AM11
NA GND AM19
NA GND AM25
NA GND AM28
NA GND AM33
NA GND AN1
NA GND AN2
NA GND AN5
NA GND AN10
NA GND AN14
NA GND AN16
NA GND AN20
NA GND AN22
NA GND AN27
NA GND AN33
Notes:
1. VREF or I/O option only in the XCV2000E; otherwise, I/O
option only.
2. VREF or I/O option only in the XCV1600E & 2000E;
otherwise, I/O option only.
3. VREF or I/O option only in the XCV1000E, 1600E, & 2000E;
otherwise, I/O option only.
4. VREF or I/O option only in the XCV600E, 1000E, 1600E, &
2000E; otherwise, I/O option only.
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank Pin Description Pin# See Note
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
42 1-800-255-7778 Preliminary Product Specification
BG560 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Global Differential Clock
0 4 AL17 AM17 NA IO_DLL_L15P
1 5 AJ17 AM18 NA IO_DLL_L15N
2 1 D17 E17 NA IO_DLL_L21P
3 0 A17 C18 NA IO_DLL_L21N
IO LVDS
Total Outputs: 183, Asynchronous Outputs: 87
0 0 D29 E28 8 VREF
10A31D28
Ö
-
20C29E27
Ö
VREF
30D27B303 -
40B29E26
Ö
-
50C27D26
Ö
VREF
60A28E259 VREF
70C26D257 -
80B26E247 VREF
90D24C252 -
10 0 A25 E23
Ö
VREF
11 0 B24 D23
Ö
-
12 0 C23 E22 8 -
13 0 D22 A23
Ö
-
14 0 B22 E21
Ö
VREF
15 0 C21 D21 3 -
16 0 E20 B21
Ö
-
17 0 C20 D20
Ö
VREF
18 0 E19 B20 9 -
19 0 C19 D19 7 -
20 0 D18 A19 7 VREF
21 1 E17 C18 NA IO_LVDS_DLL
22 1 B17 C17 2 VREF
23 1 D16 B16 7 VREF
24 1 C16 E16 7 -
25 1 C15 A15 9 -
26 1 E15 D15
Ö
VREF
27 1 D14 C14
Ö
-
28 1 E14 A13 3 -
29 1 D13 C13
Ö
VREF
30 1 E13 C12
Ö
-
31 1 D12 A11 8 -
32 1 C11 B11
Ö
-
33 1 D11 B10
Ö
VREF
34 1 A9 C10 10 -
35 1 D10 C9 7 VREF
36 1 B8 A8 7 -
37 1 C8 E10 5 VREF
38 1 A6 B7
Ö
VREF
39 1 D8 C7
Ö
-
40 1 B5 A5 11 -
41 1 D7 C6
Ö
VREF
42 1 B4 A4
Ö
-
43 1 E7 C5 12 VREF
44 1 A2 D6
Ö
CS
45 2 D4 E4
Ö
DIN, D0
46 2 F5 B3 17 VREF
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 43
47 2 F4 C1 14 -
48 2 G5 E3 15 VREF
49 2 D2 G4 16 -
50 2 H5 E2 15 -
51 2 H4 G3
Ö
VREF
52 2 J5 F1 17 VREF
53 2 J4 H3 14 -
54 2 K5 H2 18 VREF
55 2 J3 K4 19 -
56 2 L5 K3
Ö
D1
57 2 L4 K2
Ö
D2
58 2 M5 L3 17 -
59 2 L1 M4 14 -
60 2 N5 M2 15 VREF
61 2 N4 N3 16 -
62 2 N2 P5 15 -
63 2 P4 P3
Ö
D3
64 2 P2 R5 17 -
65 2 R4 R3 14 -
66 2 R1 T4 18 VREF
67 2 T5 T3 19 VREF
68 2 T2 U3
Ö
-
69 3 U1 U2 19 VREF
70 3 V2 V4 18 VREF
71 3 V5 V3 14 -
72 3 W1 W3 17 -
73 3 W4 W5
Ö
VREF
74 3 Y3 Y4 15 -
75 3 AA1 Y5 16 -
76 3 AA3 AA4 15 VREF
77 3 AB3 AA5 14 -
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
783AC1AB417 -
793AC3AB5
Ö
D5
803AC4AD3
Ö
VREF
81 3 AE1 AC5 4 -
82 3 AD4 AF1 18 VREF
83 3 AF2 AD5 14 -
84 3 AG2 AE4 20 VREF
85 3 AH1 AE5
Ö
VREF
86 3 AF4 AJ1 15 -
87 3 AJ2 AF5 14 -
88 3 AG4 AK2 15 VREF
89 3 AJ3 AG5 14 -
90 3 AL1 AH4 14 VREF
91 3 AJ4 AH5
Ö
INIT
92 4 AL4 AJ6
Ö
-
93 4 AK5 AN3 8 VREF
94 4 AL5 AJ7
Ö
-
95 4 AM4 AM5
Ö
VREF
96 4 AK7 AL6 3 -
97 4 AM6 AN6
Ö
-
98 4 AL7 AJ9
Ö
VREF
99 4 AN7 AL8 9 VREF
100 4 AM8 AJ10 7 -
101 4 AL9 AM9 7 VREF
102 4 AK10 AN9 2 -
103 4 AL10 AM10
Ö
VREF
104 4 AL11 AJ12
Ö
-
105 4 AN11 AK12 8 -
106 4 AL12 AM12
Ö
-
107 4 AK13 AL13
Ö
VREF
108 4 AM13 AN13 3 -
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
44 1-800-255-7778 Preliminary Product Specification
109 4 AJ14 AK14
Ö
-
110 4 AM14 AN15
Ö
VREF
111 4 AJ15 AK15 1 -
112 4 AL15 AM16 7 -
113 4 AL16 AJ16 7 VREF
114 4 AK16 AN17 2 VREF
115 5 AM17 AM18 NA IO_LVDS_DLL
116 5 AK18 AJ18 7 VREF
117 5 AN19 AL19 7 -
1185AK19AM209 -
119 5 AJ19 AL20
Ö
VREF
120 5 AN21 AL21
Ö
-
121 5 AJ20 AM22 3 -
1225AK21AN23
Ö
VREF
123 5 AJ21 AM23
Ö
-
1245AK22AM248 -
125 5 AL23 AJ22
Ö
-
126 5 AK23 AL24
Ö
VREF
127 5 AN26 AJ23 13 -
128 5 AK24 AM26 7 VREF
129 5 AM27 AJ24
Ö
-
130 5 AL26 AK25 5 VREF
131 5 AN29 AJ25
Ö
VREF
1325AK26AM29
Ö
-
133 5 AM30 AJ26 11 -
134 5 AK27 AL29
Ö
VREF
135 5 AN31 AJ27
Ö
-
136 5 AM31 AK28 12 VREF
137 6 AJ30 AH29
Ö
-
138 6 AH30 AK31 17 VREF
139 6 AJ31 AG29 14 -
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
140 6 AG30 AK32 15 VREF
141 6 AF29 AH31 16 -
142 6 AF30 AH32 15 -
143 6 AH33 AE29
Ö
VREF
144 6 AE30 AG33 17 VREF
145 6 AF32 AD29 14 -
146 6 AD30 AE31 18 VREF
147 6 AC29 AE32 19 -
148 6 AC30 AD31
Ö
VREF
149 6 AC31 AB29
Ö
-
150 6 AB30 AC33 17 -
151 6 AA29 AB31 14 -
152 6 AA31 AA30 15 VREF
153 6 Y29 AA32 16 -
154 6 Y30 AA33 15 -
155 6 W29 Y32
Ö
VREF
156 6 W31 W30 17 -
157 6 V30 W33 14 -
158 6 V31 V29 18 VREF
159 6 U33 V32 19 VREF
160 7 U32 U31
Ö
-
161 7 T30 T32 19 VREF
162 7 T31 T29 18 VREF
163 7 R31 R33 14 -
164 7 R29 R30 17 -
165 7 P31 P32
Ö
VREF
166 7 P29 P30 15 -
167 7 N31 M32 16 -
168 7 L33 N30 15 VREF
169 7 L32 M31 14 -
170 7 L31 M30 17 -
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 45
FG256 Fine-Pitch Ball Grid Array Packages
XCV50E, XCV100E, XCV200E, and XCV300E devices in
FG256 fine-pitch Ball Grid Array packages have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as VREF
, it can be used as gen-
eral I/O. Immediately following Ta bl e 1 6, see Table 17 for
Differential Pair information.
171 7 J33 M29
Ö
-
172 7 K31 L30
Ö
VREF
173 7 H33 L29 4 -
174 7 H32 J31 18 VREF
175 7 H31 K29 14 -
176 7 G32 J30 20 VREF
177 7 G31 J29
Ö
VREF
178 7 E32 E33 15 -
179 7 F31 H29 14 -
180 7 E31 D32 15 VREF
181 7 C33 G29 14 -
182 7 D31 F30 14 VREF
Notes:
1. AO in the XCV1600E.
2. AO in the XCV2000E.
3. AO in the XCV1600E, 2000E.
4. AO in the XCV1000E, 1600E.
5. AO in the XCV1000E, 2000E.
6. AO in the XCV1000E.
7. AO in the XCV1000E, 1600E, 2000E.
8. AO in the XCV600E, 1600E.
9. AO in the XCV400E, 600E, 1600E.
10. AO in the XCV400E, 600E, 1000E, 2000E.
11. AO in the XCV400E, 600E, 1000E.
12. AO in the XCV400E, 1000E, 2000E.
13. AO in the XCV400E, 600E, 1000E, 1600E.
14. AO in the XCV400E, 1000E, 1600E.
15. AO in the XCV600E, 1000E, 2000E.
16. AO in the XCV600E, 2000E.
17. AO in the XCV400E, 600E, 1600E, 2000E.
18. AO in the XCV600E, 1000E, 1600E, 2000E.
19. AO in the XCV400E, 600E, 2000E.
20. AO in the XCV400E, 1000E.
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
Bank Pin Description Pin #
0GCK3 B8
0IO B3
0IO E7
0IO D8
0 IO_L0N_Y C5
0 IO_VREF_L0P_Y A32
0 IO_L1N_YY D5
0 IO_L1P_YY E6
0 IO_VREF_L2N_YY B4
0 IO_L2P_YY A4
0 IO_L3N_Y D6
0IO_L3P_Y B5
0 IO_VREF_L4N_YY C61
0 IO_L4P_YY A5
0IO_L5N_YY B6
0 IO_L5P_YY C7
0 IO_L6N_Y D7
0IO_L6P_Y C8
0 IO_VREF_L7N_Y B7
0IO_L7P_Y A6
0 IO_LVDS_DLL_L8N A7
1GCK2 C9
1IOB10
1 IO_LVDS_DLL_L8P A8
1 IO_L9N_Y D9
1IO_L9P_Y A9
1 IO_L10N_Y E10
1 IO_VREF_L10P_Y B9
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
46 1-800-255-7778 Preliminary Product Specification
1 IO_L11N_Y A10
1 IO_L11P_Y D10
1 IO_L12N_YY C10
1 IO_L12P_YY A11
1 IO_L13N_YY B11
1 IO_VREF_L13P_YY E111
1 IO_L14N_Y A12
1 IO_L14P_Y D11
1 IO_L15N_YY A13
1 IO_VREF_L15P_YY C11
1 IO_L16N_YY B12
1 IO_L16P_YY D12
1 IO_VREF_L17N_Y A142
1 IO_L17P_Y C12
1 IO_WRITE_L18N_YY C13
1 IO_CS_L18P_YY B13
2 IO_DOUT_BUSY_L19P_YY C15
2 IO_DIN_D0_L19N_YY D14
2 IO_L20P B16
2 IO_VREF_L20N E132
2 IO_L21P_YY C16
2 IO_L21N_YY E14
2 IO_VREF_L22P_Y F13
2 IO_L22N_Y E15
2 IO_L23P F12
2 IO_L23N D16
2 IO_VREF_L24P_Y F141
2 IO_D1_L24N_Y E16
2 IO_D2_L25P_YY F15
2 IO_L25N_YY G13
2 IO_L26P F16
2 IO_L26N G12
2 IO_L27P_YY G15
2 IO_L27N_YY G14
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
Bank Pin Description Pin #
2 IO_VREF_L28P_Y H13
2 IO_D3_L28N_Y G16
2 IO_L29P J13
2 IO_L29N H15
2 IO_L30P_YY H14
2 IO_L30N_YY H16
3IOJ15
3 IO_L31P K15
3 IO_L31N J14
3 IO_D4_L32P_Y J16
3 IO_VREF_L32N_Y K16
3 IO_L33P_YY K12
3 IO_L33N_YY L15
3 IO_L34P K13
3 IO_L34N L16
3 IO_L35P_YY K14
3 IO_D5_L35N_YY M16
3 IO_D6_L36P_Y N16
3 IO_VREF_L36N_Y L131
3 IO_L37P P16
3 IO_L37N L12
3 IO_L38P_Y M15
3 IO_VREF_L38N_Y L14
3 IO_L39P_YY M14
3 IO_L39N_YY R16
3 IO_VREF_L40P M132
3 IO_L40N T15
3 IO_D7_L41P_YY N14
3 IO_INIT_L41N_YY N15
4GCK0 N8
4IOP10
4 IO_L42P_YY T14
4 IO_L42N_YY P13
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 47
4 IO_L43P_Y P12
4 IO_VREF_L43N_Y R132
4 IO_L44P_YY N12
4 IO_L44N_YY T13
4 IO_VREF_L45P_YY T12
4 IO_L45N_YY P11
4 IO_L46P_Y R12
4 IO_L46N_Y N11
4 IO_VREF_L47P_YY T111
4 IO_L47N_YY M11
4 IO_L48P_YY R11
4 IO_L48N_YY T10
4 IO_L49P_Y R10
4 IO_L49N_Y M10
4 IO_VREF_L50P_Y P9
4 IO_L50N_Y T9
4 IO_L51P_Y N10
4 IO_L51N_Y R9
4 IO_LVDS_DLL_L52P N9
5GCK1 R8
5IO N7
5IO T7
5 IO_LVDS_DLL_L52N T8
5 IO_L53P_Y R7
5 IO_VREF_L53N_Y P8
5 IO_L54P_Y P7
5 IO_L54N_Y T6
5 IO_L55P_YY M7
5 IO_L55N_YY R6
5 IO_L56P_YY P6
5 IO_VREF_L56N_YY R51
5 IO_L57P_Y N6
5 IO_L57N_Y T5
5 IO_L58P_YY M6
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
Bank Pin Description Pin #
5 IO_VREF_L58N_YY T4
5 IO_L59P_YY T3
5 IO_L59N_YY P5
5 IO_VREF_L60P_Y T22
5 IO_L60N_Y N5
6 IO_L61N_YY M3
6 IO_L61P_YY R1
6 IO_L62N M4
6 IO_VREF_L62P N22
6 IO_L63N_YY L5
6 IO_L63P_YY P1
6 IO_VREF_L64N_Y N1
6 IO_L64P_Y L3
6 IO_L65N M2
6 IO_L65P L4
6 IO_VREF_L66N_Y M11
6 IO_L66P_Y K4
6 IO_L67N_YY L2
6 IO_L67P_YY L1
6 IO_L68N K3
6 IO_L68P K1
6 IO_L69N_YY K2
6 IO_L69P_YY K5
6 IO_VREF_L70N_Y J3
6 IO_L70P_Y J1
6 IO_L71N J4
6 IO_L71P H1
6IO J2
7IO C2
7 IO_L72N_YY G1
7 IO_L72P_YY H4
7 IO_L73N G5
7 IO_L73P H2
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
48 1-800-255-7778 Preliminary Product Specification
7 IO_L74N_Y G4
7 IO_VREF_L74P_Y H3
7 IO_L75N_YY G2
7 IO_L75P_YY F5
7 IO_L76N F4
7 IO_L76P F1
7 IO_L77N_YY G3
7 IO_L77P_YY F2
7 IO_L78N_Y E1
7 IO_VREF_L78P_Y D11
7 IO_L79N E4
7 IO_L79P E2
7 IO_L80N_Y F3
7 IO_VREF_L80P_Y C1
7 IO_L81N_YY D2
7 IO_L81P_YY E3
7 IO_VREF_L82N B12
7 IO_L82P A2
2 CCLK D15
3DONER14
NA DXN R4
NA DXP P4
NA M0 N3
NA M1 P2
NA M2 R3
NA PROGRAM P15
NA TCK C4
NA TDI A15
2TDOB14
NA TMS D3
NA VCCINT C3
NA VCCINT C14
NA VCCINT D4
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
Bank Pin Description Pin #
NA VCCINT D13
NA VCCINT E5
NA VCCINT E12
NA VCCINT M5
NA VCCINT M12
NA VCCINT N4
NA VCCINT N13
NA VCCINT P3
NA VCCINT P14
0 VCCO F8
0 VCCO E8
1 VCCO F9
1 VCCO E9
2 VCCO H12
2 VCCO H11
3 VCCO J12
3 VCCO J11
4 VCCO M9
4 VCCO L9
5 VCCO M8
5 VCCO L8
6 VCCO J6
6 VCCO J5
7 VCCO H6
7 VCCO H5
NA GND T16
NA GND T1
NA GND R15
NA GND R2
NA GND L11
NA GND L10
NA GND L7
NA GND L6
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 49
FG256 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
NA GND K11
NA GND K10
NA GND K9
NA GND K8
NA GND K7
NA GND K6
NA GND J10
NA GND J9
NA GND J8
NA GND J7
NA GND H10
NA GND H9
NA GND H8
NA GND H7
NA GND G11
NA GND G10
NA GND G9
NA GND G8
NA GND G7
NA GND G6
NA GND F11
NA GND F10
NA GND F7
NA GND F6
NA GND B15
NA GND B2
NA GND A16
NA GND A1
Notes:
1. VREF or I/O option only in the XCV100E, 200E, 300E;
otherwise, I/O option only.
2. VREF or I/O option only in the XCV200E, 300E; otherwise,
I/O option only.
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
Bank Pin Description Pin #
Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Global Differential Clock
0 4 N8 N9 NA IO_DLL_L52P
1 5 R8 T8 NA IO_DLL_L52N
2 1 C9 A8 NA IO_DLL_L8P
3 0 B8 A7 NA IO_DLL_L8N
IO LVDS
Total Pairs: 83, Asynchronous Outputs: 35
00A3C57 VREF
10E6D5
Ö
-
2 0 A4 B4
Ö
VREF
30B5D62 -
40A5C6
Ö
VREF
50C7B6
Ö
-
6 0 C8 D7 1 -
7 0 A6 B7 1 VREF
8 1 A8 A7 NA IO_LVDS_DLL
91A9D92 -
10 1 B9 E10 1 VREF
11 1 D10 A10 1 -
12 1 A11 C10
Ö
-
13 1 E11 B11
Ö
VREF
14 1 D11 A12 2 -
15 1 C11 A13
Ö
VREF
16 1 D12 B12
Ö
-
17 1 C12 A14 7 VREF
18 1 B13 C13
Ö
CS
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
50 1-800-255-7778 Preliminary Product Specification
19 2 C15 D14
Ö
DIN, D0
20 2 B16 E13 6 VREF
21 2 C16 E14
Ö
-
22 2 F13 E15 1 VREF
23 2 F12 D16 5 -
24 2 F14 E16 3 D1
25 2 F15 G13
Ö
D2
26 2 F16 G12 6 -
27 2 G15 G14
Ö
-
28 2 H13 G16 3 D3
29 2 J13 H15 4 -
30 2 H14 H16
Ö
-
31 3 K15 J14 4 -
32 3 J16 K16 3 VREF
33 3 K12 L15
Ö
-
34 3 K13 L16 6 -
35 3 K14 M16
Ö
D5
36 3 N16 L13 3 VREF
37 3 P16 L12 5 -
38 3 M15 L14 1 VREF
39 3 M14 R16
Ö
-
40 3 M13 T15 6 VREF
41 3 N14 N15
Ö
INIT
42 4 T14 P13
Ö
-
43 4 P12 R13 7 VREF
44 4 N12 T13
Ö
-
45 4 T12 P11
Ö
VREF
46 4 R12 N11 2 -
47 4 T11 M11
Ö
VREF
48 4 R11 T10
Ö
-
49 4 R10 M10 1 -
50 4 P9 T9 1 VREF
51 4 N10 R9 1 -
52 5 N9 T8 NA IO_LVDS_DLL
53 5 R7 P8 1 VREF
54 5 P7 T6 1 -
Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
55 5 M7 R6
Ö
-
56 5 P6 R5
Ö
VREF
57 5 N6 T5 2 -
58 5 M6 T4
Ö
VREF
59 5 T3 P5
Ö
-
60 5 T2N57 VREF
61 6 R1 M3
Ö
-
62 6 N2 M4 6 VREF
63 6 P1 L5
Ö
-
64 6 L3 N1 1 VREF
65 6 L4 M2 5 -
66 6 K4 M1 3 VREF
67 6 L1 L2
Ö
-
68 6 K1 K3 6 -
69 6 K5 K2
Ö
-
70 6 J1 J3 3 VREF
71 6 H1 J4 4 -
72 7 H4 G1
Ö
-
73 7 H2 G5 4 -
74 7 H3 G4 3 VREF
75 7 F5 G2
Ö
-
76 7 F1 F4 6 -
77 7 F2 G3
Ö
-
78 7 D1 E1 3 VREF
79 7 E2 E4 5 -
80 7 C1 F3 1 VREF
81 7 E3 D2
Ö
-
82 7 A2 B1 6 VREF
Notes:
1. AO in the XCV50E, 200E, 300E.
2. AO in the XCV50E, 200E.
3. AO in the XCV50E, 300E.
4. AO in the XCV100E, 200E.
5. AO in the XCV200E.
6. AO in the XCV100E.
7. AO in the XCV50E.
Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 51
FG456 Fine-Pitch Ball Grid Array Packages
XCV200E and XCV300E devices in FG456 fine-pitch Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in both devices pro-
vided in this package. If the pin is not used as VREF
, it can be
used as general I/O. Immediately following Table 18, see
Table 19 for Differential Pair information.
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
0GCK3C11
0IOA2
1
0IOA3
0IOA6
1
0IOA10
0IOB5
0IOB9
0IOC5
0IOD8
0IOD10
0IOE11
1
0 IO_L0N D5
0 IO_L0P B3
0 IO_VREF_L1N_YY B4
0 IO_L1P_YY E6
0 IO_L2N A4
0 IO_L2P E7
0 IO_VREF_L3N_YY C6
0 IO_L3P_YY D6
0 IO_L4N_Y A5
0 IO_L4P_Y B6
0 IO_L5N_Y D7
0 IO_L5P_Y C7
0 IO_VREF_L6N_YY E8
0 IO_L6P_YY B7
0 IO_L7N_YY A7
0 IO_L7P_YY E9
0 IO_L8N_Y C8
0 IO_L8P_Y B8
0 IO_L9N_Y D9
0 IO_L9P_Y A8
0 IO_L10N C9
0 IO_L10P E10
0 IO_VREF_L11N_YY A9
0 IO_L11P_YY C10
0 IO_L12N_Y F11
0 IO_L12P_Y B10
0 IO_LVDS_DLL_L13N B11
1GCK2A11
1IOA12
1
1IOA14
1IOB16
1
1IOB19
1IOE13
1IOE15
1IOE16
1IOE17
1
1 IO_LVDS_DLL_L13P D11
1 IO_L14N_Y C12
1 IO_L14P_Y D12
1 IO_L15N_Y B12
1 IO_L15P_Y A13
1 IO_L16N_YY E12
1 IO_VREF_L16P_YY B13
1 IO_L17N_YY C13
1 IO_L17P_YY D13
1 IO_L18N_Y B14
1 IO_L18P_Y C14
1 IO_L19N_Y F12
1 IO_L19P_Y A15
1 IO_L20N_YY B15
1 IO_L20P_YY C15
1 IO_L21N_YY A16
1 IO_VREF_L21P_YY E14
1 IO_L22N_Y D14
1 IO_L22P_Y C16
1 IO_L23N_Y D15
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
52 1-800-255-7778 Preliminary Product Specification
1 IO_L23P_Y A17
1 IO_L24N_YY B17
1 IO_VREF_L24P_YY A18
1 IO_L25N_YY D16
1 IO_L25P_YY C17
1 IO_L26N_YY B18
1 IO_VREF_L26P_YY A19
1 IO_L27N_YY D17
1 IO_L27P_YY C18
1 IO_WRITE_L28N_YY A20
1 IO_CS_L28P_YY C19
2IOD18
1
2IOE19
1
2IOE20
2IOF20
2IOG21
2IOG22
1
2IOJ22
2IOL19
1
2IO_D3K20
2 IO_DOUT_BUSY_L29P_YY C21
2 IO_DIN_D0_L29N_YY D20
2 IO_L30P_YY C22
2 IO_L30N_YY D21
2 IO_VREF_L31P_YY D22
2 IO_L31N_YY E21
2 IO_L32P_YY E22
2 IO_L32N_YY F18
2 IO_VREF_L33P_YY F21
2 IO_L33N_YY F19
2 IO_L34P_Y F22
2 IO_L34N_Y G19
2 IO_L35P_Y G20
2 IO_L35N_Y G18
2 IO_VREF_L36P_Y H18
2 IO_D1_L36N_Y H22
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
2 IO_D2_L37P_YY H20
2 IO_L37N_YY H19
2 IO_L38P_YY H21
2 IO_L38N_YY J19
2 IO_L39P_YY J18
2 IO_L39N_YY J20
2 IO_L40P_Y K18
2 IO_L40N_Y J21
2 IO_L41P K22
2 IO_VREF_L41N K21
2 IO_L42P_Y K19
2 IO_L42N_Y L22
2 IO_L43P_YY L21
2 IO_L43N_YY L18
2 IO_L44P_YY L17
2 IO_L44N_YY L20
3IOM21
1
3IOP22
3IOR20
1
3IOR22
3IOT19
3IOU18
1
3IOV20
3IOV21
3IOY22
1
3 IO_L45P_YY M18
3 IO_L45N_YY M20
3 IO_L46P_Y M19
3 IO_L46N_Y M17
3 IO_D4_L47P_Y N22
3 IO_VREF_L47N_Y N21
3 IO_L48P_YY N20
3 IO_L48N_YY N18
3 IO_L49P_YY N19
3 IO_L49N_YY P21
3 IO_L50P_YY P20
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 53
3 IO_L50N_YY P19
3 IO_L51P_YY P18
3 IO_D5_L51N_YY R21
3 IO_D6_L52P_Y T22
3 IO_VREF_L52N_Y R19
3 IO_L53P_Y U22
3 IO_L53N_Y R18
3 IO_L54P_YY T21
3 IO_L54N_YY V22
3 IO_L55P_YY T20
3 IO_VREF_L55N_YY U21
3 IO_L56P_YY W22
3 IO_L56N_YY T18
3 IO_L57P_YY U19
3 IO_VREF_L57N_YY U20
3 IO_L58P_YY W21
3 IO_L58N_YY AA22
3 IO_D7_L59P_YY Y21
3 IO_INIT_L59N_YY V19
3IOM22
4GCK0W12
4IOW14
4IOY13
4IOY17
4IOAA16
1
4IOAA19
4IOAB12
1
4IOAB17
4IOAB21
1
4 IO_L60P_YY W18
4 IO_L60N_YY AA20
4 IO_L61P Y18
4 IO_L61N V17
4 IO_VREF_L62P_YY AB20
4 IO_L62N_YY W17
4 IO_L63P AA18
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
4 IO_L63N V16
4 IO_VREF_L64P_YY AB19
4 IO_L64N_YY AB18
4 IO_L65P_Y W16
4 IO_L65N_Y AA17
4 IO_L66P_Y Y16
4 IO_L66N_Y V15
4 IO_VREF_L67P_YY AB16
4 IO_L67N_YY Y15
4 IO_L68P_YY AA15
4 IO_L68N_YY AB15
4 IO_L69P_Y W15
4 IO_L69N_Y Y14
4 IO_L70P_Y V14
4 IO_L70N_Y AA14
4 IO_L71P AB14
4 IO_L71N V13
4 IO_VREF_L72P_YY AA13
4 IO_L72N_YY AB13
4 IO_L73P_Y W13
4 IO_L73N_Y AA12
4 IO_L74P_Y Y12
4 IO_L74N_Y V12
4 IO_LVDS_DLL_L75P U12
5IOU11
1
5IOV8
5IOW5
5IOAA3
1
5IOAA9
5IOAA10
5IOAB4
5IOAB7
1
5IOAB8
5GCK1Y11
5 IO_LVDS_DLL_L75N AA11
5 IO_L76P_Y AB11
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
54 1-800-255-7778 Preliminary Product Specification
5 IO_L76N_Y W11
5 IO_L77P_YY V11
5 IO_VREF_L77N_YY Y10
5 IO_L78P_YY AB10
5 IO_L78N_YY W10
5 IO_L79P_Y V10
5 IO_L79N_Y Y9
5 IO_L80P_Y AB9
5 IO_L80N_Y W9
5 IO_L81P_YY V9
5 IO_L81N_YY AA8
5 IO_L82P_YY Y8
5 IO_VREF_L82N_YY W8
5 IO_L83P_Y W7
5 IO_L83N_Y AA7
5 IO_L84P_Y AB6
5 IO_L84N_Y AA6
5 IO_L85P_YY AB5
5 IO_VREF_L85N_YY AA5
5 IO_L86P_YY Y7
5 IO_L86N_YY W6
5 IO_L87P_YY AA4
5 IO_VREF_L87N_YY Y6
5 IO_L88P_YY V7
5 IO_L88N_YY AB3
6IOM2
1
6IOM5
6IOP4
6IOR3
1
6IOT2
6IOT4
6IOU3
1
6IOW2
6IOAA1
1
6 IO_L89N_YY W3
6 IO_L89P_YY Y2
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
6 IO_L90N_YY V4
6 IO_L90P_YY V3
6 IO_VREF_L91N_YY Y1
6 IO_L91P_YY U4
6 IO_L92N_YY V2
6 IO_L92P_YY W1
6 IO_VREF_L93N_YY T3
6 IO_L93P_YY U2
6 IO_L94N_Y T5
6 IO_L94P_Y V1
6 IO_L95N_Y R5
6 IO_L95P_Y U1
6 IO_VREF_L96N_Y R4
6 IO_L96P_Y T1
6 IO_L97N_YY R2
6 IO_L97P_YY P3
6 IO_L98N_YY P5
6 IO_L98P_YY R1
6 IO_L99N_YY P2
6 IO_L99P_YY N5
6 IO_L100N_Y P1
6 IO_L100P_Y N4
6 IO_L101N N3
6 IO_VREF_L101P N2
6 IO_L102N_Y N1
6 IO_L102P_Y M4
6 IO_L103N_YY M3
6 IO_L103P_YY M6
6IOM1
7IOB1
7IOC2
1
7IOD1
1
7IOE4
7IOF4
7IOG2
1
7IOG4
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 55
7IOJ1
7IOJ4
7IOL2
1
7 IO_L104N_YY L3
7 IO_L104P_YY L4
7 IO_L105N_YY L5
7 IO_L105P_YY L1
7 IO_L106N_Y L6
7 IO_L106P_Y K2
7 IO_L107N_Y K4
7 IO_VREF_L107P_Y K3
7 IO_L108N_YY K1
7 IO_L108P_YY K5
7 IO_L109N_YY J3
7 IO_L109P_YY J2
7 IO_L110N_YY J5
7 IO_L110P_YY H1
7 IO_L111N_YY H2
7 IO_L111P_YY H3
7 IO_L112N_Y G1
7 IO_VREF_L112P_Y H4
7 IO_L113N_Y F1
7 IO_L113P_Y F2
7 IO_L114N_YY H5
7 IO_L114P_YY G3
7 IO_L115N_YY E1
7 IO_VREF_L115P_YY E2
7 IO_L116N_YY F3
7 IO_L116P_YY G5
7 IO_L117N_YY E3
7 IO_VREF_L117P_YY D2
7 IO_L118N_YY F5
7 IO_L118P_YY C1
2 CCLK B22
3DONEY19
NA DXN Y5
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
NA DXP V6
NA M0 AB2
NA M1 U5
NA M2 Y4
NA PROGRAM W20
NA TCK C4
NA TDI B20
2TDOA21
NA TMS D3
NA NC W19
NA NC W4
NA NC D19
NA NC D4
NA VCCINT E5
NA VCCINT E18
NA VCCINT F6
NA VCCINT F17
NA VCCINT G7
NA VCCINT G8
NA VCCINT G9
NA VCCINT G14
NA VCCINT G15
NA VCCINT H7
NA VCCINT G16
NA VCCINT H16
NA VCCINT J7
NA VCCINT J16
NA VCCINT P7
NA VCCINT P16
NA VCCINT R7
NA VCCINT R16
NA VCCINT T7
NA VCCINT T8
NA VCCINT T9
NA VCCINT T14
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
56 1-800-255-7778 Preliminary Product Specification
NA VCCINT T15
NA VCCINT T16
NA VCCINT U6
NA VCCINT U17
NA VCCINT V5
NA VCCINT V18
NA VCCO_7 L7
NA VCCO_7 K7
NA VCCO_7 K6
NA VCCO_7 J6
NA VCCO_7 H6
NA VCCO_7 G6
NA VCCO_6 N7
NA VCCO_6 M7
NA VCCO_6 T6
NA VCCO_6 R6
NA VCCO_6 P6
NA VCCO_6 N6
NA VCCO_5 U10
NA VCCO_5 U9
NA VCCO_5 U8
NA VCCO_5 U7
NA VCCO_5 T11
NA VCCO_5 T10
NA VCCO_4 U16
NA VCCO_4 U15
NA VCCO_4 U14
NA VCCO_4 U13
NA VCCO_4 T13
NA VCCO_4 T12
NA VCCO_3 T17
NA VCCO_3 R17
NA VCCO_3 P17
NA VCCO_3 N17
NA VCCO_3 N16
NA VCCO_3 M16
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
NA VCCO_2 K17
NA VCCO_2 J17
NA VCCO_2 H17
NA VCCO_2 G17
NA VCCO_2 L16
NA VCCO_2 K16
NA VCCO_1 G13
NA VCCO_1 G12
NA VCCO_1 F16
NA VCCO_1 F15
NA VCCO_1 F14
NA VCCO_1 F13
NA VCCO_0 G11
NA VCCO_0 G10
NA VCCO_0 F10
NA VCCO_0 F9
NA VCCO_0 F8
NA VCCO_0 F7
NA GND AB22
NA GND AB1
NA GND AA21
NA GND AA2
NA GND Y20
NA GND Y3
NA GND P14
NA GND P13
NA GND P12
NA GND P11
NA GND P10
NA GND P9
NA GND N14
NA GND N13
NA GND N12
NA GND N11
NA GND N10
NA GND N9
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 57
FG456 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
NA GND M14
NA GND M13
NA GND M12
NA GND M11
NA GND M10
NA GND M9
NA GND L14
NA GND L13
NA GND L12
NA GND L11
NA GND L10
NA GND L9
NA GND K14
NA GND K13
NA GND K12
NA GND K11
NA GND K10
NA GND K9
NA GND J14
NA GND J13
NA GND J12
NA GND J11
NA GND J10
NA GND J9
NA GND C20
NA GND C3
NA GND B21
NA GND B2
NA GND A22
NA GND A1
Note 1: NC in the XCV200E device.
Table 18: FG456 — XCV200E and XCV300E
Bank Pin Description Pin #
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Global Differential Clock
0 4 W12 U12 NA IO_DLL_L75P
1 5 Y11 AA11 NA IO_DLL_L75N
2 1 A11 D11 NA IO_DLL_L13P
3 0 C11 B11 NA IO_DLL_L13N
IO LVDS
Total Pairs: 119, Asynchronous Output Pairs: 69
0 0 B3 D5 NA -
1 0 E6 B4
Ö
VREF
2 0 E7 A4 NA -
3 0 D6 C6
Ö
VREF
4 0 B6 A5 1 -
5 0 C7 D7 1 -
6 0 B7 E8
Ö
VREF
7 0 E9 A7
Ö
-
80B8C81 -
90A8D91 -
10 0 E10 C9 NA -
11 0 C10 A9
Ö
VREF
12 0 B10 F11 2 -
13 1 D11 B11 NA IO_LVDS_DLL
14 1 D12 C12 2 -
15 1 A13 B12 2 -
16 1 B13 E12
Ö
VREF
17 1 D13 C13
Ö
-
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
58 1-800-255-7778 Preliminary Product Specification
18 1 C14 B14 2 -
19 1 A15 F12 2 -
20 1 C15 B15
Ö
-
21 1 E14 A16
Ö
VREF
22 1 C16 D14 2 -
23 1 A17 D15 2 -
24 1 A18 B17
Ö
VREF
25 1 C17 D16
Ö
-
26 1 A19 B18
Ö
VREF
27 1 C18 D17
Ö
-
28 1 C19 A20
Ö
CS
29 2 C21 D20
Ö
DIN, D0
30 2 C22 D21
Ö
-
31 2 D22 E21
Ö
VREF
32 2 E22 F18
Ö
-
33 2 F21 F19
Ö
VREF
34 2 F22 G19 2 -
35 2 G20 G18 1 -
36 2 H18 H22 2 D1, VREF
37 2 H20 H19
Ö
D2
38 2 H21 J19
Ö
-
39 2 J18 J20
Ö
-
40 2 K18 J21 2 -
41 2 K22 K21 1 VREF
42 2 K19 L22 2 -
43 2 L21 L18
Ö
-
44 2 L17 L20
Ö
-
45 3 M18 M20
Ö
-
46 3 M19 M17 2 -
47 3 N22 N21 2 VREF
48 3 N20 N18
Ö
-
49 3 N19 P21
Ö
-
50 3 P20 P19
Ö
-
51 3 P18 R21
Ö
D5
52 3 T22 R19 2 VREF
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
53 3 U22 R18 2 -
54 3 T21 V22
Ö
-
55 3 T20 U21
Ö
VREF
56 3 W22 T18
Ö
-
57 3 U19 U20
Ö
VREF
58 3 W21 AA22
Ö
-
59 3 Y21 V19
Ö
INIT
60 4 W18 AA20
Ö
-
61 4 Y18 V17 NA -
62 4 AB20 W17
Ö
VREF
63 4 AA18 V16 NA -
64 4 AB19 AB18
Ö
VREF
65 4 W16 AA17 1 -
66 4 Y16 V15 1 -
67 4 AB16 Y15
Ö
VREF
68 4 AA15 AB15
Ö
-
69 4 W15 Y14 1 -
70 4 V14 AA14 1 -
71 4 AB14 V13 NA -
72 4 AA13 AB13
Ö
VREF
73 4 W13 AA12 2 -
74 4 Y12 V12 2 -
75 5 U12 AA11 NA IO_LVDS_DLL
76 5 AB11 W11 1 -
77 5 V11 Y10
Ö
VREF
78 5 AB10 W10
Ö
-
79 5 V10 Y9 2 -
80 5 AB9 W9 2 -
81 5 V9 AA8
Ö
-
82 5 Y8 W8
Ö
VREF
83 5 W7 AA7 2 -
84 5 AB6 AA6 2 -
85 5 AB5 AA5
Ö
VREF
86 5 Y7 W6
Ö
-
87 5 AA4 Y6
Ö
VREF
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 59
FG676 Fine-Pitch Ball Grid Array Package
XCV400E and XCV600E devices in the FG676 fine-pitch
Ball Grid Array package have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF
, it can be used as general I/O. Immedi-
ately following Table 20, see Table 21 for Differential Pair
information.
88 5 V7 AB3
Ö
-
89 6 Y2 W3
Ö
-
90 6 V3 V4
Ö
-
91 6 U4 Y1
Ö
VREF
92 6 W1 V2
Ö
-
93 6 U2 T3
Ö
VREF
94 6 V1 T5 2 -
95 6 U1 R5 1 -
96 6 T1 R4 2 VREF
97 6 P3 R2
Ö
-
98 6 R1 P5
Ö
-
99 6 N5 P2
Ö
-
100 6 N4 P1 2 -
101 6 N2 N3 1 VREF
102 6 M4 N1 2 -
103 6 M6 M3
Ö
-
104 7 L4 L3
Ö
-
105 7 L1 L5
Ö
-
106 7 K2 L6 2 -
107 7 K3 K4 2 VREF
108 7 K5 K1
Ö
-
109 7 J2 J3
Ö
-
110 7 H1 J5
Ö
-
111 7 H3 H2
Ö
-
112 7 H4 G1 2 VREF
113 7 F2 F1 2 -
114 7 G3 H5
Ö
-
115 7 E2 E1
Ö
VREF
116 7 G5 F3
Ö
-
117 7 D2 E3
Ö
VREF
118 7 C1 F5
Ö
-
Notes:
1. AO in the XCV200E.
2. AO in the XCV300E.
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
0GCK3E13
0IOA6
0IOA9
1
0IOA10
1
0IOB3
0IOB4
1
0IOB12
1
0IOC6
0IOC8
0IOD5
0IOD13
1
0IOG13
0IO_L0N_YC4
0 IO_L0P_Y F7
0IO_L1N_YYG8
0 IO_L1P_YY C5
0 IO_VREF_L2N_YY D6
0 IO_L2P_YY E7
0 IO_L3N A4
0IO_L3PF8
0 IO_L4N B5
0IO_L4PD7
0 IO_VREF_L5N_YY E8
0 IO_L5P_YY G9
0IO_L6N_YYA5
0 IO_L6P_YY F9
0IO_L7N_YD8
0 IO_L7P_Y C7
0 IO_VREF_L8N_Y B72
0 IO_L8P_Y E9
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
60 1-800-255-7778 Preliminary Product Specification
0 IO_L9N A7
0IO_L9PD9
0 IO_L10N B8
0 IO_VREF_L10P G10
0 IO_L11N_YY C9
0 IO_L11P_YY F10
0 IO_L12N_Y A8
0 IO_L12P_Y E10
0 IO_L13N_YY G11
0 IO_L13P_YY D10
0 IO_L14N_YY B10
0 IO_L14P_YY F11
0 IO_L15N C10
0 IO_L15P E11
0 IO_L16N_YY G12
0 IO_L16P_YY D11
0 IO_VREF_L17N_YY C11
0 IO_L17P_YY F12
0 IO_L18N_YY A11
0 IO_L18P_YY E12
0 IO_L19N_Y D12
0 IO_L19P_Y C12
0 IO_VREF_L20N_Y A12
0 IO_L20P_Y H13
0 IO_LVDS_DLL_L21N B13
1GCK2C13
1IOA13
1
1IOA16
1
1IOA19
1IOA20
1IOA22
1IOA24
1
1IOB15
1
1IOB17
1
1IOB23
1 IO_LVDS_DLL_L21P F14
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
1 IO_L22N E14
1 IO_L22P F13
1 IO_L23N_Y D14
1 IO_VREF_L23P_Y A14
1 IO_L24N_Y C14
1 IO_L24P_Y H14
1 IO_L25N_YY G14
1 IO_L25P_YY C15
1 IO_L26N_YY E15
1 IO_VREF_L26P_YY D15
1 IO_L27N_YY C16
1 IO_L27P_YY F15
1 IO_L28N G15
1 IO_L28P D16
1 IO_L29N_YY E16
1 IO_L29P_YY A17
1 IO_L30N_YY C17
1 IO_L30P_YY E17
1 IO_L31N_Y F16
1 IO_L31P_Y D17
1 IO_L32N_YY F17
1 IO_L32P_YY C18
1 IO_L33N_YY A18
1 IO_VREF_L33P_YY G16
1 IO_L34N_YY C19
1 IO_L34P_YY G17
1 IO_L35N_Y D18
1 IO_VREF_L35P_Y B192
1 IO_L36N_Y D19
1 IO_L36P_Y E18
1 IO_L37N_YY F18
1 IO_L37P_YY B20
1 IO_L38N_YY G19
1 IO_VREF_L38P_YY C20
1 IO_L39N_YY G18
1 IO_L39P_YY E19
1 IO_L40N_YY A21
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 61
1 IO_L40P_YY D20
1 IO_L41N_YY F19
1 IO_VREF_L41P_YY C21
1 IO_L42N_YY B22
1 IO_L42P_YY E20
1 IO_L43N_Y A23
1 IO_L43P_Y D21
1 IO_WRITE_L44N_YY C22
1 IO_CS_L44P_YY E21
2IOD25
1
2IOD26
2IOE26
2IOF26
2IOH26
1
2IOK26
1
2IOM25
1
2ION26
1
2IO_D1K24
2 IO_DOUT_BUSY_L45P_YY E23
2 IO_DIN_D0_L45N_YY F22
2 IO_L46P_YY E24
2 IO_L46N_YY F20
2 IO_L47P_Y G21
2 IO_L47N_Y G22
2 IO_VREF_L48P_Y F24
2 IO_L48N_Y H20
2 IO_L49P_Y E25
2 IO_L49N_Y H21
2 IO_L50P_YY F23
2 IO_L50N_YY G23
2 IO_VREF_L51P_YY H23
2 IO_L51N_YY J20
2 IO_L52P_YY G24
2 IO_L52N_YY H22
2 IO_L53P_Y J21
2 IO_L53N_Y G25
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
2 IO_VREF_L54P_Y G262
2 IO_L54N_Y J22
2 IO_L55P_YY H24
2 IO_L55N_YY J23
2 IO_L56P_YY J24
2 IO_VREF_L56N_YY K20
2 IO_D2_L57P_YY K22
2 IO_L57N_YY K21
2 IO_L58P_YY H25
2 IO_L58N_YY K23
2 IO_L59P_Y L20
2 IO_L59N_Y J26
2 IO_L60P_Y K25
2 IO_L60N_Y L22
2 IO_L61P_Y L21
2 IO_L61N_Y L23
2 IO_L62P_Y M20
2 IO_L62N_Y L24
2 IO_VREF_L63P_YY M23
2 IO_D3_L63N_YY M22
2 IO_L64P_YY L26
2 IO_L64N_YY M21
2 IO_L65P_Y N19
2 IO_L65N_Y M24
2 IO_VREF_L66P_Y M26
2 IO_L66N_Y N20
2 IO_L67P_YY N24
2 IO_L67N_YY N21
2 IO_L68P_YY N23
2 IO_L68N_YY N22
3IOP24
3IOP26
1
3IOR26
1
3IOT26
1
3IOU26
1
3IOW25
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
62 1-800-255-7778 Preliminary Product Specification
3IOY26
3IOAB25
3IOAC25
1
3IOAC26
3 IO_L69P_YY P21
3 IO_L69N_YY P23
3 IO_L70P_Y P22
3 IO_VREF_L70N_Y R25
3 IO_L71P_Y P19
3 IO_L71N_Y P20
3 IO_L72P_YY R21
3 IO_L72N_YY R22
3 IO_D4_L73P_YY R24
3 IO_VREF_L73N_YY R23
3 IO_L74P_Y T24
3 IO_L74N_Y R20
3 IO_L75P_Y T22
3 IO_L75N_Y U24
3 IO_L76P_Y T23
3 IO_L76N_Y U25
3 IO_L77P_Y T21
3 IO_L77N_Y U20
3 IO_L78P_YY U22
3 IO_L78N_YY V26
3 IO_L79P_YY T20
3 IO_D5_L79N_YY U23
3 IO_D6_L80P_YY V24
3 IO_VREF_L80N_YY U21
3 IO_L81P_YY V23
3 IO_L81N_YY W24
3 IO_L82P_Y V22
3 IO_VREF_L82N_Y W262
3 IO_L83P_Y Y25
3 IO_L83N_Y V21
3 IO_L84P_YY V20
3 IO_L84N_YY AA26
3 IO_L85P_YY Y24
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
3 IO_VREF_L85N_YY W23
3 IO_L86P_Y AA24
3 IO_L86N_Y Y23
3 IO_L87P_Y AB26
3 IO_L87N_Y W21
3 IO_L88P_Y Y22
3 IO_VREF_L88N_Y W22
3 IO_L89P_Y AA23
3 IO_L89N_Y AB24
3 IO_L90P_YY W20
3 IO_L90N_YY AC24
3 IO_D7_L91P_YY AB23
3 IO_INIT_L91N_YY Y21
4GCK0AA14
4IOAC18
4IOAE15
1
4IOAE20
4IOAE23
4IOAF14
1
4IOAF16
1
4IOAF18
1
4IOAF21
4IOAF23
1
4 IO_L92P_YY AC22
4 IO_L92N_YY AD26
4 IO_L93P_Y AD23
4 IO_L93N_Y AA20
4 IO_L94P_YY Y19
4 IO_L94N_YY AC21
4 IO_VREF_L95P_YY AD22
4 IO_L95N_YY AB20
4 IO_L96P AE22
4 IO_L96N Y18
4 IO_L97P AF22
4 IO_L97N AA19
4 IO_VREF_L98P_YY AD21
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 63
4 IO_L98N_YY AB19
4 IO_L99P_YY AC20
4 IO_L99N_YY AA18
4 IO_L100P_Y AC19
4 IO_L100N_Y AD20
4 IO_VREF_L101P_Y AF202
4 IO_L101N_Y AB18
4 IO_L102P AD19
4 IO_L102N Y17
4 IO_L103P AE19
4 IO_VREF_L103N AD18
4 IO_L104P_YY AF19
4 IO_L104N_YY AA17
4 IO_L105P_Y AC17
4 IO_L105N_Y AB17
4 IO_L106P_YY Y16
4 IO_L106N_YY AE17
4 IO_L107P_YY AF17
4 IO_L107N_YY AA16
4 IO_L108P AD17
4 IO_L108N AB16
4 IO_L109P_YY AC16
4 IO_L109N_YY AD16
4 IO_VREF_L110P_YY AC15
4 IO_L110N_YY Y15
4 IO_L111P_YY AD15
4 IO_L111N_YY AA15
4 IO_L112P_Y W14
4 IO_L112N_Y AB15
4 IO_VREF_L113P_Y AF15
4 IO_L113N_Y Y14
4 IO_L114P AD14
4 IO_L114N AB14
4 IO_LVDS_DLL_L115P AC14
5GCK1AB13
5IOY13
1
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
5IOAD7
5IOAD13
5IOAE4
5IOAE7
5IOAE12
1
5IOAF3
1
5IOAF5
5IOAF10
1
5IOAF11
1
5 IO_LVDS_DLL_L115N AF13
5 IO_L116P_Y AA13
5 IO_VREF_L116N_Y AF12
5 IO_L117P_Y AC13
5 IO_L117N_Y W13
5 IO_L118P_YY AA12
5 IO_L118N_YY AD12
5 IO_L119P_YY AC12
5 IO_VREF_L119N_YY AB12
5 IO_L120P_YY AD11
5 IO_L120N_YY Y12
5 IO_L121P AB11
5 IO_L121N AD10
5 IO_L122P_YY AC11
5 IO_L122N_YY AE10
5 IO_L123P_YY AC10
5 IO_L123N_YY AA11
5 IO_L124P_Y Y11
5 IO_L124N_Y AD9
5 IO_L125P_YY AB10
5 IO_L125N_YY AF9
5 IO_L126P_YY AD8
5 IO_VREF_L126N_YY AA10
5 IO_L127P_YY AE8
5 IO_L127N_YY Y10
5 IO_L128P_Y AC9
5 IO_VREF_L128N_Y AF82
5 IO_L129P_Y AF7
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
64 1-800-255-7778 Preliminary Product Specification
5 IO_L129N_Y AB9
5 IO_L130P_YY AA9
5 IO_L130N_YY AF6
5 IO_L131P_YY AC8
5 IO_VREF_L131N_YY AC7
5 IO_L132P_YY AD6
5 IO_L132N_YY Y9
5 IO_L133P_YY AE5
5 IO_L133N_YY AA8
5 IO_L134P_YY AC6
5 IO_VREF_L134N_YY AB8
5 IO_L135P_YY AD5
5 IO_L135N_YY AA7
5 IO_L136P_Y AF4
5 IO_L136N_Y AC5
6IOP3
6 IO AA3
6IOAC1
1
6IOP1
1
6IOR2
1
6IOT1
1
6IOV1
1
6IOW3
6IOY2
6IOY6
6 IO_L137N_YY AA5
6 IO_L137P_YY AC3
6 IO_L138N_YY AC2
6 IO_L138P_YY AB4
6 IO_L139N_Y W6
6 IO_L139P_Y AA4
6 IO_VREF_L140N_Y AB3
6 IO_L140P_Y Y5
6 IO_L141N_Y AB2
6 IO_L141P_Y V7
6 IO_L142N_YY AB1
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
6 IO_L142P_YY Y4
6 IO_VREF_L143N_YY V5
6 IO_L143P_YY W5
6 IO_L144N_YY AA1
6 IO_L144P_YY V6
6 IO_L145N_Y W4
6 IO_L145P_Y Y3
6 IO_VREF_L146N_Y Y12
6 IO_L146P_Y U7
6 IO_L147N_YY W1
6 IO_L147P_YY V4
6 IO_L148N_YY W2
6 IO_VREF_L148P_YY U6
6 IO_L149N_YY V3
6 IO_L149P_YY T5
6 IO_L150N_YY U5
6 IO_L150P_YY U4
6 IO_L151N_Y T7
6 IO_L151P_Y U3
6 IO_L152N_Y U2
6 IO_L152P_Y T6
6 IO_L153N_Y U1
6 IO_L153P_Y T4
6 IO_L154N_Y R7
6 IO_L154P_Y T3
6 IO_VREF_L155N_YY R4
6 IO_L155P_YY R6
6 IO_L156N_YY R3
6 IO_L156P_YY R5
6 IO_L157N_Y P8
6 IO_L157P_Y P7
6 IO_VREF_L158N_Y R1
6 IO_L158P_Y P6
6 IO_L159N_YY P5
6 IO_L159P_YY P4
7IOD1
1
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 65
7IOD2
7IOD3
7IOE1
7IOG1
7IOH2
7IOJ1
1
7IOL1
1
7IOM1
1
7ION1
1
7 IO_L160N_YY N5
7 IO_L160P_YY N8
7 IO_L161N_YY N6
7 IO_L161P_YY N3
7 IO_L162N_Y N4
7 IO_VREF_L162P_Y M2
7 IO_L163N_Y N7
7 IO_L163P_Y M7
7 IO_L164N_YY M6
7 IO_L164P_YY M3
7 IO_L165N_YY M4
7 IO_VREF_L165P_YY M5
7 IO_L166N_Y L3
7 IO_L166P_Y L7
7 IO_L167N_Y L6
7 IO_L167P_Y K2
7 IO_L168N_Y L4
7 IO_L168P_Y K1
7 IO_L169N_Y K3
7 IO_L169P_Y L5
7 IO_L170N_YY K5
7 IO_L170P_YY J3
7 IO_L171N_YY K4
7 IO_L171P_YY J4
7 IO_L172N_YY H3
7 IO_VREF_L172P_YY K6
7 IO_L173N_YY K7
7 IO_L173P_YY G3
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
7 IO_L174N_Y J5
7 IO_VREF_L174P_Y H12
7 IO_L175N_Y G2
7 IO_L175P_Y J6
7 IO_L176N_YY J7
7 IO_L176P_YY F1
7 IO_L177N_YY H4
7 IO_VREF_L177P_YY G4
7 IO_L178N_Y F3
7 IO_L178P_Y H5
7 IO_L179N_Y E2
7 IO_L179P_Y H6
7 IO_L180N_Y G5
7 IO_VREF_L180P_Y F4
7 IO_L181N_Y H7
7 IO_L181P_Y G6
7 IO_L182N_YY E3
7 IO_L182P_YY E4
2CCLKD24
3DONEAB21
NA DXN AB7
NA DXP Y8
NA M0 AD4
NA M1 W7
NA M2 AB6
NA PROGRAM AA22
NA TCK E6
NA TDI D22
2TDOC23
NA TMS F5
NA NC T25
NA NC T2
NA NC P2
NA NC N25
NA NC L25
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
66 1-800-255-7778 Preliminary Product Specification
NA NC L2
NA NC F6
NA NC F25
NA NC F21
NA NC F2
NA NC C26
NA NC C25
NA NC C2
NA NC C1
NA NC B6
NA NC B26
NA NC B24
NA NC B21
NA NC B16
NA NC B11
NA NC B1
NA NC AF25
NA NC AF24
NA NC AF2
NA NC AE6
NA NC AE3
NA NC AE26
NA NC AE24
NA NC AE21
NA NC AE16
NA NC AE14
NA NC AE11
NA NC AE1
NA NC AD25
NA NC AD2
NA NC AD1
NA NC AA6
NA NC AA25
NA NC AA21
NA NC AA2
NA NC A3
NA NC A25
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
NA NC A2
NA NC A15
NA VCCINT G7
NA VCCINT G20
NA VCCINT H8
NA VCCINT H19
NA VCCINT J9
NA VCCINT J10
NA VCCINT J11
NA VCCINT J16
NA VCCINT J17
NA VCCINT J18
NA VCCINT K9
NA VCCINT K18
NA VCCINT L9
NA VCCINT L18
NA VCCINT T9
NA VCCINT T18
NA VCCINT U9
NA VCCINT U18
NA VCCINT V9
NA VCCINT V10
NA VCCINT V11
NA VCCINT V16
NA VCCINT V17
NA VCCINT V18
NA VCCINT Y7
NA VCCINT Y20
NA VCCINT W8
NA VCCINT W19
0 VCCO J13
0 VCCO J12
0 VCCO H9
0 VCCO H12
0 VCCO H11
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 67
0 VCCO H10
1 VCCO J15
1 VCCO J14
1 VCCO H18
1 VCCO H17
1 VCCO H16
1 VCCO H15
2 VCCO N18
2 VCCO M19
2 VCCO M18
2 VCCO L19
2 VCCO K19
2 VCCO J19
3 VCCO V19
3 VCCO U19
3 VCCO T19
3 VCCO R19
3 VCCO R18
3 VCCO P18
4 VCCO W18
4 VCCO W17
4 VCCO W16
4 VCCO W15
4 VCCO V15
4 VCCO V14
5 VCCO W9
5 VCCO W12
5 VCCO W11
5 VCCO W10
5 VCCO V13
5 VCCO V12
6 VCCO V8
6 VCCO U8
6 VCCO T8
6 VCCO R9
6 VCCO R8
6 VCCO P9
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
7 VCCO N9
7 VCCO M9
7 VCCO M8
7 VCCO L8
7 VCCO K8
7 VCCO J8
NA GND V25
NA GND V2
NA GND U17
NA GND U16
NA GND U15
NA GND U14
NA GND U13
NA GND U12
NA GND U11
NA GND U10
NA GND T17
NA GND T16
NA GND T15
NA GND T14
NA GND T13
NA GND T12
NA GND T11
NA GND T10
NA GND R17
NA GND R16
NA GND R15
NA GND R14
NA GND R13
NA GND R12
NA GND R11
NA GND R10
NA GND P25
NA GND P17
NA GND P16
NA GND P15
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
68 1-800-255-7778 Preliminary Product Specification
NA GND P14
NA GND P13
NA GND P12
NA GND P11
NA GND P10
NA GND N2
NA GND N17
NA GND N16
NA GND N15
NA GND N14
NA GND N13
NA GND N12
NA GND N11
NA GND N10
NA GND M17
NA GND M16
NA GND M15
NA GND M14
NA GND M13
NA GND M12
NA GND M11
NA GND M10
NA GND L17
NA GND L16
NA GND L15
NA GND L14
NA GND L13
NA GND L12
NA GND L11
NA GND L10
NA GND K17
NA GND K16
NA GND K15
NA GND K14
NA GND K13
NA GND K12
NA GND K11
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
NA GND K10
NA GND J25
NA GND J2
NA GND E5
NA GND E22
NA GND D4
NA GND D23
NA GND C3
NA GND C24
NA GND B9
NA GND B25
NA GND B2
NA GND B18
NA GND B14
NA GND AF26
NA GND AF1
NA GND AE9
NA GND AE25
NA GND AE2
NA GND AE18
NA GND AE13
NA GND AD3
NA GND AD24
NA GND AC4
NA GND AC23
NA GND AB5
NA GND AB22
NA GND A26
NA GND A1
Notes:
1. NC in the XCV400E.
2. VREF or I/O option only in the XCV600E; otherwise, I/O
option only.
Table 20: FG676 — XCV400E, XCV600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 69
FG676 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
Pair
Ban
k
P
Pin
N
Pin AO
Other
Functions
Global Differential Clock
3 0 E13 B13 NA IO_DLL_L21N
2 1 C13 F14 NA IO_DLL_L21P
1 5 AB13 AF13 NA IO_DLL_L115N
0 4 AA14 AC14 NA IO_DLL_L115P
IOLVDS
Total Pairs: 183, Asynchronous Output Pairs: 97
00F7C41 -
10C5G8
Ö
-
20E7D6
Ö
VREF
30F8A4NA -
40D7B5NA -
50G9E8
Ö
VREF
60F9A5
Ö
-
7 0 C7 D8 1 -
80E9B71 VREF
90D9A7NA -
10 0 G10 B8 NA VREF
11 0 F10 C9
Ö
-
12 0 E10 A8 1 -
13 0 D10 G11
Ö
-
14 0 F11 B10
Ö
-
15 0 E11 C10 NA -
16 0 D11 G12
Ö
-
17 0 F12 C11
Ö
VREF
18 0 E12 A11
Ö
-
19 0 C12 D12 1 -
20 0 H13 A12 1 VREF
21 1 F14 B13 NA IO_LVDS_DLL
221F13E14NA -
23 1 A14 D14 1 VREF
24 1 H14 C14 1 -
25 1 C15 G14
Ö
-
26 1 D15 E15
Ö
VREF
271F15C16
Ö
-
28 1 D16 G15 - -
29 1 A17 E16
Ö
-
30 1 E17 C17
Ö
-
31 1 D17 F16 1 -
32 1 C18 F17
Ö
-
33 1 G16 A18
Ö
VREF
34 1 G17 C19
Ö
-
35 1 B19 D18 1 VREF
36 1 E18 D19 1 -
37 1 B20 F18
Ö
-
38 1 C20 G19
Ö
VREF
39 1 E19 G18
Ö
-
40 1 D20 A21
Ö
-
41 1 C21 F19
Ö
VREF
42 1 E20 B22
Ö
-
43 1 D21 A23 2 -
44 1 E21 C22
Ö
CS
45 2 E23 F22
Ö
DIN, D0
46 2 E24 F20
Ö
-
47 2 G21 G22 2 -
48 2 F24 H20 1 VREF
49 2 E25 H21 1 -
502F23G23
Ö
-
51 2 H23 J20
Ö
VREF
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
Pair
Ban
k
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
70 1-800-255-7778 Preliminary Product Specification
52 2 G24 H22
Ö
-
53 2 J21 G25 2 -
542G26J221 VREF
55 2 H24 J23
Ö
-
56 2 J24 K20
Ö
VREF
57 2 K22 K21
Ö
D2
58 2 H25 K23
Ö
-
59 2 L20 J26 2 -
60 2 K25 L22 1 -
61 2 L21 L23 1 -
62 2 M20 L24 1 -
63 2 M23 M22
Ö
D3
64 2 L26 M21
Ö
-
65 2 N19 M24 2 -
66 2 M26 N20 1 VREF
67 2 N24 N21
Ö
-
68 2 N23 N22
Ö
-
69 3 P21 P23
Ö
-
70 3 P22 R25 1 VREF
71 3 P19 P20 2 -
72 3 R21 R22
Ö
-
73 3 R24 R23
Ö
VREF
74 3 T24 R20 1 -
75 3 T22 U24 1 -
76 3 T23 U25 1 -
77 3 T21 U20 2 -
78 3 U22 V26
Ö
-
79 3 T20 U23
Ö
D5
80 3 V24 U21
Ö
VREF
81 3 V23 W24
Ö
-
82 3 V22 W26 1 VREF
83 3 Y25 V21 2 -
84 3 V20 AA26
Ö
-
85 3 Y24 W23
Ö
VREF
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
Pair
Ban
k
P
Pin
N
Pin AO
Other
Functions
86 3 AA24 Y23 1 -
87 3 AB26 W21 2 -
88 3 Y22 W22 1 VREF
89 3 AA23 AB24 2 -
90 3 W20 AC24
Ö
-
91 3 AB23 Y21
Ö
INIT
92 4 AC22 AD26
Ö
-
93 4 AD23 AA20 1 -
94 4 Y19 AC21
Ö
-
95 4 AD22 AB20
Ö
VREF
96 4 AE22 Y18 NA -
97 4 AF22 AA19 NA -
98 4 AD21 AB19
Ö
VREF
99 4 AC20 AA18
Ö
-
100 4 AC19 AD20 1 -
101 4 AF20 AB18 1 VREF
102 4 AD19 Y17 NA -
103 4 AE19 AD18 NA VREF
104 4 AF19 AA17
Ö
-
105 4 AC17 AB17 1 -
106 4 Y16 AE17
Ö
-
107 4 AF17 AA16
Ö
-
108 4 AD17 AB16 NA -
109 4 AC16 AD16
Ö
-
110 4 AC15 Y15
Ö
VREF
111 4 AD15 AA15
Ö
-
112 4 W14 AB15 1 -
113 4 AF15 Y14 1 VREF
114 4 AD14 AB14 NA -
115 5 AC14 AF13 NA IO_LVDS_DLL
116 5 AA13 AF12 1 VREF
117 5 AC13 W13 1 -
118 5 AA12 AD12
Ö
-
119 5 AC12 AB12
Ö
VREF
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
Pair
Ban
k
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 71
120 5 AD11 Y12
Ö
-
121 5 AB11 AD10 NA -
122 5 AC11 AE10
Ö
-
123 5 AC10 AA11
Ö
-
124 5 Y11 AD9 1 -
125 5 AB10 AF9
Ö
-
126 5 AD8 AA10
Ö
VREF
127 5 AE8 Y10
Ö
-
128 5 AC9 AF8 1 VREF
129 5 AF7 AB9 1 -
130 5 AA9 AF6
Ö
-
131 5 AC8 AC7
Ö
VREF
132 5 AD6 Y9
Ö
-
133 5 AE5 AA8
Ö
-
134 5 AC6 AB8
Ö
VREF
135 5 AD5 AA7
Ö
-
136 5 AF4 AC5 2 -
137 6 AC3 AA5
Ö
-
138 6 AB4 AC2
Ö
-
139 6 AA4 W6 2 -
140 6 Y5 AB3 1 VREF
141 6 V7 AB2 1 -
142 6 Y4 AB1
Ö
-
143 6 W5 V5
Ö
VREF
144 6 V6 AA1
Ö
-
145 6 Y3 W4 2 -
146 6 U7 Y1 1 VREF
147 6 V4 W1
Ö
-
148 6 U6 W2
Ö
VREF
149 6 T5 V3
Ö
-
150 6 U4 U5
Ö
-
151 6 U3 T7 2 -
152 6 T6 U2 1 -
153 6 T4 U1 1 -
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
Pair
Ban
k
P
Pin
N
Pin AO
Other
Functions
154 6 T3 R7 1 -
155 6 R6 R4
Ö
VREF
156 6 R5 R3
Ö
-
157 6 P7 P8 2 -
158 6 P6 R1 1 VREF
159 6 P4 P5
Ö
-
160 7 N8 N5
Ö
-
161 7 N3 N6
Ö
-
162 7 M2 N4 1 VREF
163 7 M7 N7 2 -
164 7 M3 M6
Ö
-
165 7 M5 M4
Ö
VREF
166 7 L7 L3 1 -
167 7 K2 L6 1 -
168 7 K1 L4 1 -
169 7 L5 K3 2 -
170 7 J3 K5
Ö
-
171 7 J4 K4
Ö
-
172 7 K6 H3
Ö
VREF
173 7 G3 K7
Ö
-
174 7 H1 J5 1 VREF
175 7 J6 G2 2 -
176 7 F1 J7
Ö
-
177 7 G4 H4
Ö
VREF
178 7 H5 F3 1 -
179 7 H6 E2 2 -
180 7 F4 G5 1 VREF
181 7 G6 H7 2 -
182 7 E4 E3
Ö
-
Notes:
1. AO in the XCV600E.
2. AO in the XCV400E.
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
Pair
Ban
k
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
72 1-800-255-7778 Preliminary Product Specification
FG680 Fine-Pitch Ball Grid Array Package
XCV600E, XCV1000E, XCV1600E, and XCV2000E
devices in the FG680 fine-pitch Ball Grid Array package
have footprint compatibility. Pins labeled I0_VREF can be
used as either in all parts unless device-dependent as indi-
cated in the footnotes. If the pin is not used as VREF
, it can
be used as general I/O. Immediately following Table 22, see
Table 23 for Differential Pair information.
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
0GCK3A20
0IOD35
0IOB36
0IO_L0N_YC35
0 IO_L0P_Y A36
0 IO_VREF_L1N_Y D341
0 IO_L1P_Y B35
0 IO_L2N_YY C34
0 IO_L2P_YY A35
0 IO_VREF_L3N_YY D33
0 IO_L3P_YY B34
0IO_L4NC33
0 IO_L4P A34
0IO_L5N_YD32
0 IO_L5P_Y B33
0 IO_L6N_YY C32
0 IO_L6P_YY D31
0 IO_VREF_L7N_YY A33
0 IO_L7P_YY C31
0IO_L8N_YB32
0 IO_L8P_Y B31
0 IO_VREF_L9N_Y A323
0 IO_L9P_Y D30
0 IO_L10N_YY A31
0 IO_L10P_YY C30
0 IO_VREF_L11N_YY B30
0 IO_L11P_YY D29
0 IO_L12N_Y A30
0 IO_L12P_Y C29
0 IO_L13N_Y A29
0 IO_L13P_Y B29
0 IO_VREF_L14N_YY B28
0 IO_L14P_YY A28
0 IO_L15N_YY C28
0 IO_L15P_YY B27
0 IO_L16N_Y D27
0 IO_L16P_Y A27
0 IO_L17N_Y C27
0 IO_L17P_Y B26
0 IO_L18N_YY D26
0 IO_L18P_YY C26
0 IO_VREF_L19N_YY A261
0 IO_L19P_YY D25
0 IO_L20N_Y B25
0 IO_L20P_Y C25
0 IO_L21N_Y A25
0 IO_L21P_Y D24
0 IO_L22N_YY A24
0 IO_L22P_YY B23
0 IO_VREF_L23N_YY C24
0 IO_L23P_YY A23
0 IO_L24N_Y B24
0 IO_L24P_Y B22
0 IO_L25N_Y E23
0 IO_L25P_Y A22
0 IO_L26N_YY D23
0 IO_L26P_YY B21
0 IO_VREF_L27N_YY C23
0 IO_L27P_YY A21
0 IO_L28N_Y E22
0 IO_L28P_Y B20
0 IO_LVDS_DLL_L29N C22
0IO_VREFD22
2
1GCK2D21
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 73
1IOC5
1 IO_LVDS_DLL_L29P A19
1 IO_L30N_Y C21
1 IO_VREF_L30P_Y B192
1 IO_L31N_Y C19
1 IO_L31P_Y A18
1 IO_L32N_YY D19
1 IO_VREF_L32P_YY B18
1 IO_L33N_YY C18
1 IO_L33P_YY A17
1 IO_L34N_Y D18
1 IO_L34P_Y B17
1 IO_L35N_Y E18
1 IO_L35P_Y A16
1 IO_L36N_YY C17
1 IO_VREF_L36P_YY D17
1 IO_L37N_YY B16
1 IO_L37P_YY E17
1 IO_L38N_Y A15
1 IO_L38P_Y C16
1 IO_L39N_Y B15
1 IO_L39P_Y D16
1 IO_L40N_YY A14
1 IO_VREF_L40P_YY B141
1 IO_L41N_YY C15
1 IO_L41P_YY A13
1 IO_L42N_Y D15
1 IO_L42P_Y B13
1 IO_L43N_Y C14
1 IO_L43P_Y A12
1 IO_L44N_YY D14
1 IO_L44P_YY C13
1 IO_L45N_YY B12
1 IO_VREF_L45P_YY D13
1 IO_L46N_Y A11
1 IO_L46P_Y C12
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
1 IO_L47N_Y B11
1 IO_L47P_Y C11
1 IO_L48N_YY A10
1 IO_VREF_L48P_YY D11
1 IO_L49N_YY B10
1 IO_L49P_YY C10
1 IO_L50N_Y A9
1 IO_VREF_L50P_Y D103
1 IO_L51N_Y B9
1 IO_L51P_Y C9
1 IO_L52N_YY A8
1 IO_VREF_L52P_YY B8
1 IO_L53N_YY D9
1 IO_L53P_YY A7
1 IO_L54N_Y C8
1 IO_L54P_Y B7
1 IO_L55N_Y D8
1 IO_L55P_Y A6
1 IO_L56N_YY C7
1 IO_VREF_L56P_YY B6
1 IO_L57N_YY D7
1 IO_L57P_YY A5
1 IO_L58N_Y C6
1 IO_VREF_L58P_Y B51
1 IO_L59N_Y D6
1 IO_L59P_Y A4
1 IO_WRITE_L60N_YY B4
1 IO_CS_L60P_YY D5
2IOD1
2IOF4
2 IO_DOUT_BUSY_L61P_YY E3
2 IO_DIN_D0_L61N_YY C2
2 IO_L62P_Y D3
2 IO_L62N_Y F3
2 IO_VREF_L63P D21
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
74 1-800-255-7778 Preliminary Product Specification
2 IO_L63N G4
2 IO_L64P G3
2 IO_L64N E2
2 IO_VREF_L65P_Y H4
2 IO_L65N_Y E1
2 IO_L66P_YY H3
2 IO_L66N_YY F2
2 IO_L67P J4
2 IO_L67N F1
2 IO_L68P_Y J3
2 IO_L68N_Y G2
2 IO_VREF_L69P_YY G1
2 IO_L69N_YY K4
2 IO_L70P_YY H2
2 IO_L70N_YY K3
2 IO_VREF_L71P H13
2 IO_L71N L4
2 IO_L72P J2
2 IO_L72N L3
2 IO_VREF_L73P_YY J1
2 IO_L73N_YY M3
2 IO_L74P_YY K2
2 IO_L74N_YY N4
2 IO_L75P K1
2 IO_L75N N3
2 IO_VREF_L76P_YY L2
2 IO_D1_L76N_YY P4
2 IO_D2_L77P_YY P3
2 IO_L77N_YY L1
2 IO_L78P_Y R4
2 IO_L78N_Y M2
2 IO_L79P R3
2 IO_L79N M1
2 IO_L80P T4
2 IO_L80N N2
2 IO_VREF_L81P_Y N11
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
2 IO_L81N_Y T3
2 IO_L82P_YY P2
2 IO_L82N_YY U5
2 IO_L83P P1
2 IO_L83N U4
2 IO_L84P_Y R2
2 IO_L84N_Y U3
2 IO_VREF_L85P_YY V5
2 IO_D3_L85N_YY R1
2 IO_L86P_YY V4
2 IO_L86N_YY T2
2 IO_L87P V3
2 IO_L87N T1
2 IO_L88P W4
2 IO_L88N U2
2 IO_VREF_L89P_YY W3
2 IO_L89N_YY U1
2 IO_L90P_YY AA3
2 IO_L90N_YY V2
2 IO_VREF_L91P AA42
2 IO_L91N V1
2 IO_L92P_YY AB2
2 IO_L92N_YY W2
3IOAP3
3IOAT3
3IOAB3
3 IO_L93P AB4
3 IO_VREF_L93N W12
3 IO_L94P_YY AB5
3 IO_L94N_YY Y2
3 IO_L95P_YY AC2
3 IO_VREF_L95N_YY Y1
3 IO_L96P AC3
3 IO_L96N AA1
3 IO_L97P AC4
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 75
3 IO_L97N AA2
3 IO_L98P_YY AC5
3 IO_L98N_YY AB1
3 IO_D4_L99P_YY AD3
3 IO_VREF_L99N_YY AC1
3 IO_L100P_Y AD1
3 IO_L100N_Y AD4
3 IO_L101P AD2
3 IO_L101N AE3
3 IO_L102P_YY AE1
3 IO_L102N_YY AE4
3 IO_L103P_Y AE2
3 IO_VREF_L103N_Y AF31
3 IO_L104P AF4
3 IO_L104N AF1
3 IO_L105P AG3
3 IO_L105N AF2
3 IO_L106P_Y AG4
3 IO_L106N_Y AG1
3 IO_L107P_YY AH3
3 IO_D5_L107N_YY AG2
3 IO_D6_L108P_YY AH1
3 IO_VREF_L108N_YY AJ2
3 IO_L109P AH2
3 IO_L109N AJ3
3 IO_L110P_YY AJ1
3 IO_L110N_YY AJ4
3 IO_L111P_YY AK1
3 IO_VREF_L111N_YY AK3
3 IO_L112P AK2
3 IO_L112N AK4
3 IO_L113P AL1
3 IO_VREF_L113N AL23
3 IO_L114P_YY AM1
3 IO_L114N_YY AL3
3 IO_L115P_YY AM2
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
3 IO_VREF_L115N_YY AL4
3 IO_L116P_Y AM3
3 IO_L116N_Y AN1
3 IO_L117P AM4
3 IO_L117N AP1
3 IO_L118P_YY AN2
3 IO_L118N_YY AP2
3 IO_L119P_Y AN3
3 IO_VREF_L119N_Y AR1
3 IO_L120P AN4
3 IO_L120N AT1
3 IO_L121P AR2
3 IO_VREF_L121N AP41
3 IO_L122P_Y AT2
3 IO_L122N_Y AR3
3 IO_D7_L123P_YY AR4
3 IO_INIT_L123N_YY AU2
4GCK0AW19
4IOAV3
4 IO_L124P_YY AU4
4 IO_L124N_YY AV5
4 IO_L125P_Y AT6
4 IO_L125N_Y AV4
4 IO_VREF_L126P_Y AU61
4 IO_L126N_Y AW4
4 IO_L127P_YY AT7
4 IO_L127N_YY AW5
4 IO_VREF_L128P_YY AU7
4 IO_L128N_YY AV6
4 IO_L129P_Y AT8
4 IO_L129N_Y AW6
4 IO_L130P_Y AU8
4 IO_L130N_Y AV7
4 IO_L131P_YY AT9
4 IO_L131N_YY AW7
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
76 1-800-255-7778 Preliminary Product Specification
4 IO_VREF_L132P_YY AV8
4 IO_L132N_YY AU9
4 IO_L133P_Y AW8
4 IO_L133N_Y AT10
4 IO_VREF_L134P_Y AV93
4 IO_L134N_Y AU10
4 IO_L135P_YY AW9
4 IO_L135N_YY AT11
4 IO_VREF_L136P_YY AV10
4 IO_L136N_YY AU11
4 IO_L137P_Y AW10
4 IO_L137N_Y AU12
4 IO_L138P_Y AV11
4 IO_L138N_Y AT13
4 IO_VREF_L139P_YY AW11
4 IO_L139N_YY AU13
4 IO_L140P_YY AT14
4 IO_L140N_YY AV12
4 IO_L141P_Y AU14
4 IO_L141N_Y AW12
4 IO_L142P_Y AT15
4 IO_L142N_Y AV13
4 IO_L143P_YY AU15
4 IO_L143N_YY AW13
4 IO_VREF_L144P_YY AV141
4 IO_L144N_YY AT16
4 IO_L145P_Y AW14
4 IO_L145N_Y AU16
4 IO_L146P_Y AV15
4 IO_L146N_Y AR17
4 IO_L147P_YY AW15
4 IO_L147N_YY AT17
4 IO_VREF_L148P_YY AU17
4 IO_L148N_YY AV16
4 IO_L149P_Y AR18
4 IO_L149N_Y AW16
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
4 IO_L150P_Y AT18
4 IO_L150N_Y AV17
4 IO_L151P_YY AU18
4 IO_L151N_YY AW17
4 IO_VREF_L152P_YY AT19
4 IO_L152N_YY AV18
4 IO_L153P_Y AU19
4 IO_L153N_Y AW18
4 IO_VREF_L154P AU212
4 IO_L154N AV19
4 IO_LVDS_DLL_L155P AT21
5 GCK1 AU22
5IOAT34
5IOAW20
5 IO_LVDS_DLL_L155N AT22
5 IO_VREF_L156P_Y AV202
5 IO_L156N_Y AR22
5 IO_L157P_YY AV23
5 IO_VREF_L157N_YY AW21
5 IO_L158P_YY AU23
5 IO_L158N_YY AV21
5 IO_L159P_Y AT23
5 IO_L159N_Y AW22
5 IO_L160P_Y AR23
5 IO_L160N_Y AV22
5 IO_L161P_YY AV24
5 IO_VREF_L161N_YY AW23
5 IO_L162P_YY AW24
5 IO_L162N_YY AU24
5 IO_L163P_Y AW25
5 IO_L163N_Y AT24
5 IO_L164P_Y AV25
5 IO_L164N_Y AU25
5 IO_L165P_YY AW26
5 IO_VREF_L165N_YY AT251
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 77
5 IO_L166P_YY AV26
5 IO_L166N_YY AW27
5 IO_L167P_Y AU26
5 IO_L167N_Y AV27
5 IO_L168P_Y AT26
5 IO_L168N_Y AW28
5 IO_L169P_YY AU27
5 IO_L169N_YY AV28
5 IO_L170P_YY AW29
5 IO_VREF_L170N_YY AT27
5 IO_L171P_Y AW30
5 IO_L171N_Y AU28
5 IO_L172P_Y AV30
5 IO_L172N_Y AV29
5 IO_L173P_YY AW31
5 IO_VREF_L173N_YY AU29
5 IO_L174P_YY AV31
5 IO_L174N_YY AT29
5 IO_L175P_Y AW32
5 IO_VREF_L175N_Y AU303
5 IO_L176P_Y AW33
5 IO_L176N_Y AT30
5 IO_L177P_YY AV33
5 IO_VREF_L177N_YY AU31
5 IO_L178P_YY AT31
5 IO_L178N_YY AW34
5 IO_L179P_Y AV32
5 IO_L179N_Y AV34
5 IO_L180P_Y AU32
5 IO_L180N_Y AW35
5 IO_L181P_YY AT32
5 IO_VREF_L181N_YY AV35
5 IO_L182P_YY AU33
5 IO_L182N_YY AW36
5 IO_L183P_Y AT33
5 IO_VREF_L183N_Y AV361
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
5 IO_L184P_Y AU34
5 IO_L184N_Y AU36
6IOW39
6IOAR37
6IOAR39
6 IO_L185N_YY AR36
6 IO_L185P_YY AT38
6 IO_L186N_Y AR38
6 IO_L186P_Y AP36
6 IO_VREF_L187N AT391
6 IO_L187P AP37
6 IO_L188N AP38
6 IO_L188P AP39
6 IO_VREF_L189N_Y AN36
6 IO_L189P_Y AN38
6 IO_L190N_YY AN37
6 IO_L190P_YY AN39
6 IO_L191N AM36
6 IO_L191P AM38
6 IO_L192N_Y AM37
6 IO_L192P_Y AL36
6 IO_VREF_L193N_YY AM39
6 IO_L193P_YY AL37
6 IO_L194N_YY AL38
6 IO_L194P_YY AK36
6 IO_VREF_L195N AL393
6 IO_L195P AK37
6 IO_L196N AK38
6 IO_L196P AJ36
6 IO_VREF_L197N_YY AK39
6 IO_L197P_YY AJ37
6 IO_L198N_YY AJ38
6 IO_L198P_YY AH37
6 IO_L199N AJ39
6 IO_L199P AH38
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
78 1-800-255-7778 Preliminary Product Specification
6 IO_VREF_L200N_YY AH39
6 IO_L200P_YY AG38
6 IO_L201N_YY AG36
6 IO_L201P_YY AG39
6 IO_L202N_Y AG37
6 IO_L202P_Y AF39
6 IO_L203N AF36
6 IO_L203P AE38
6 IO_L204N AF37
6 IO_L204P AF38
6 IO_VREF_L205N_Y AE391
6 IO_L205P_Y AE36
6 IO_L206N_YY AD38
6 IO_L206P_YY AE37
6 IO_L207N AD39
6 IO_L207P AD36
6 IO_L208N_Y AC38
6 IO_L208P_Y AC39
6 IO_VREF_L209N_YY AD37
6 IO_L209P_YY AB38
6 IO_L210N_YY AC35
6 IO_L210P_YY AB39
6 IO_L211N AC36
6 IO_L211P AA38
6 IO_L212N AC37
6 IO_L212P AA39
6 IO_VREF_L213N_YY AB35
6 IO_L213P_YY Y38
6 IO_L214N_YY AB36
6 IO_L214P_YY Y39
6 IO_VREF_L215N AB372
6 IO_L215P AA36
7IOC38
7IOB37
7IOF37
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
7 IO_L216N_YY AA37
7 IO_L216P_YY W38
7 IO_L217N W37
7 IO_VREF_L217P V392
7 IO_L218N_YY W36
7 IO_L218P_YY U39
7 IO_L219N_YY V38
7 IO_VREF_L219P_YY U38
7 IO_L220N V37
7 IO_L220P T39
7 IO_L221N V36
7 IO_L221P T38
7 IO_L222N_YY V35
7 IO_L222P_YY R39
7 IO_L223N_YY U37
7 IO_VREF_L223P_YY U36
7 IO_L224N_Y R38
7 IO_L224P_Y U35
7 IO_L225N P39
7 IO_L225P T37
7 IO_L226N_YY P38
7 IO_L226P_YY T36
7 IO_L227N_Y N39
7 IO_VREF_L227P_Y N381
7 IO_L228N R37
7 IO_L228P M39
7 IO_L229N R36
7 IO_L229P M38
7 IO_L230N_Y P37
7 IO_L230P_Y L39
7 IO_L231N_YY P36
7 IO_L231P_YY N37
7 IO_L232N_YY L38
7 IO_VREF_L232P_YY N36
7 IO_L233N K39
7 IO_L233P M37
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 79
7 IO_L234N_YY K38
7 IO_L234P_YY L37
7 IO_L235N_YY J39
7 IO_VREF_L235P_YY L36
7 IO_L236N J38
7 IO_L236P K37
7 IO_L237N H39
7 IO_VREF_L237P K363
7 IO_L238N_YY H38
7 IO_L238P_YY J37
7 IO_L239N_YY G39
7 IO_VREF_L239P_YY G38
7 IO_L240N_Y J36
7 IO_L240P_Y F39
7 IO_L241N H37
7 IO_L241P F38
7 IO_L242N_YY H36
7 IO_L242P_YY E39
7 IO_L243N_Y G37
7 IO_VREF_L243P_Y E38
7 IO_L244N G36
7 IO_L244P D39
7 IO_L245N D38
7 IO_VREF_L245P F361
7 IO_L246N_Y D37
7 IO_L246P_Y E37
2CCLKE4
3DONEAU5
NA DXN AV37
NA DXP AU35
NA M0 AT37
NA M1 AU38
NA M2 AT35
NA PROGRAM AT5
NA TCK C36
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
NA TDI B3
2 TDO C4
NA TMS E36
NA VCCINT E8
NA VCCINT E9
NA VCCINT E15
NA VCCINT E16
NA VCCINT E24
NA VCCINT E25
NA VCCINT E31
NA VCCINT E32
NA VCCINT H5
NA VCCINT H35
NA VCCINT J5
NA VCCINT J35
NA VCCINT R5
NA VCCINT R35
NA VCCINT T5
NA VCCINT T35
NA VCCINT AD5
NA VCCINT AD35
NA VCCINT AE5
NA VCCINT AE35
NA VCCINT AL5
NA VCCINT AL35
NA VCCINT AM5
NA VCCINT AM35
NA VCCINT AR8
NA VCCINT AR9
NA VCCINT AR15
NA VCCINT AR16
NA VCCINT AR24
NA VCCINT AR25
NA VCCINT AR31
NA VCCINT AR32
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
80 1-800-255-7778 Preliminary Product Specification
0 VCCO E34
0 VCCO E33
0 VCCO E30
0 VCCO E29
0 VCCO E27
0 VCCO E26
1 VCCO E10
1 VCCO E11
1 VCCO E13
1 VCCO E14
1 VCCO E6
1 VCCO E7
2 VCCO P5
2 VCCO N5
2 VCCO L5
2 VCCO K5
2 VCCO G5
2 VCCO F5
3 VCCO AP5
3 VCCO AN5
3 VCCO AK5
3 VCCO AJ5
3 VCCO AG5
3 VCCO AF5
4 VCCO AR10
4 VCCO AR11
4 VCCO AR13
4 VCCO AR14
4 VCCO AR6
4 VCCO AR7
5 VCCO AR34
5 VCCO AR33
5 VCCO AR30
5 VCCO AR29
5 VCCO AR27
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
5 VCCO AR26
6 VCCO AP35
6 VCCO AN35
6 VCCO AK35
6 VCCO AJ35
6 VCCO AG35
6 VCCO AF35
7 VCCO P35
7 VCCO N35
7 VCCO L35
7 VCCO K35
7 VCCO G35
7 VCCO F35
NA GND Y5
NA GND Y4
NA GND Y37
NA GND Y36
NA GND Y35
NA GND Y3
NA GND W5
NA GND W35
NA GND M5
NA GND M4
NA GND M36
NA GND M35
NA GND E5
NA GND E35
NA GND E28
NA GND E21
NA GND E20
NA GND E19
NA GND E12
NA GND D4
NA GND D36
NA GND D28
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 81
NA GND D20
NA GND D12
NA GND C39
NA GND C37
NA GND C3
NA GND C20
NA GND C1
NA GND B39
NA GND B38
NA GND B2
NA GND B1
NA GND AW39
NA GND AW38
NA GND AW37
NA GND AW3
NA GND AW2
NA GND AW1
NA GND AV39
NA GND AV38
NA GND AV2
NA GND AV1
NA GND AU39
NA GND AU37
NA GND AU3
NA GND AU20
NA GND AU1
NA GND AT4
NA GND AT36
NA GND AT28
NA GND AT20
NA GND AT12
NA GND AR5
NA GND AR35
NA GND AR28
NA GND AR21
NA GND AR20
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
NA GND AR19
NA GND AR12
NA GND AH5
NA GND AH4
NA GND AH36
NA GND AH35
NA GND AA5
NA GND AA35
NA GND A39
NA GND A38
NA GND A37
NA GND A3
NA GND A2
NA GND A1
Notes:
1. VREF or I/O option only in the XCV1000E, 1600E, 2000E;
otherwise, I/O option only.
2. VREF or I/O option only in the XCV1600E, 2000E; otherwise,
I/O option only.
3. VREF or I/O option only in the XCV2000E; otherwise, I/O
option only.
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
82 1-800-255-7778 Preliminary Product Specification
FG680 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
GCLK LVDS
3 0 A20 C22 NA IO_DLL_L29N
2 1 D21 A19 NA IO_DLL_L29P
1 5 AU22 AT22 NA IO_DLL_L155N
0 4 AW19 AT21 NA IO_DLL_L155P
IO LVDS
Total Pairs: 247, Asynchronous Output Pairs: 111
00A36C355 -
10B35D345 VREF
20A35C34
Ö
-
30B34D33
Ö
VREF
40A34C333 -
50B33D323 -
60D31C32
Ö
-
70C31A33
Ö
VREF
80B31B325 -
90D30A325 VREF
10 0 C30 A31
Ö
-
11 0 D29 B30
Ö
VREF
12 0 C29 A30 2 -
13 0 B29 A29 2 -
14 0 A28 B28
Ö
VREF
15 0 B27 C28
Ö
-
16 0 A27 D27 5 -
17 0 B26 C27 5 -
18 0 C26 D26
Ö
-
19 0 D25 A26
Ö
VREF
20 0 C25 B25 3 -
21 0 D24 A25 3 -
22 0 B23 A24
Ö
-
23 0 A23 C24
Ö
VREF
24 0 B22 B24 5 -
25 0 A22 E23 5 -
26 0 B21 D23
Ö
-
27 0 A21 C23
Ö
VREF
28 0 B20 E22 2 -
29 1 A19 C22 NA IO_LVDS_DLL
30 1 B19 C21 2 VREF
31 1 A18 C19 2 -
32 1 B18 D19
Ö
VREF
33 1 A17 C18
Ö
-
34 1 B17 D18 5 -
35 1 A16 E18 5 -
36 1 D17 C17
Ö
VREF
37 1 E17 B16
Ö
-
38 1 C16 A15 3 -
39 1 D16 B15 3 -
40 1 B14 A14
Ö
VREF
41 1 A13 C15
Ö
-
42 1 B13 D15 5 -
43 1 A12 C14 5 -
44 1 C13 D14
Ö
-
45 1 D13 B12
Ö
VREF
46 1 C12 A11 2 -
47 1 C11 B11 2 -
48 1 D11 A10
Ö
VREF
49 1 C10 B10
Ö
-
50 1 D10 A9 5 VREF
51 1 C9 B9 5 -
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 83
52 1 B8 A8
Ö
VREF
53 1 A7 D9
Ö
-
54 1 B7 C8 3 -
55 1 A6 D8 3 -
56 1 B6 C7
Ö
VREF
57 1 A5 D7
Ö
-
58 1 B5 C6 5 VREF
59 1 A4 D6 5 -
60 1 D5 B4
Ö
CS
61 2 E3 C2
Ö
DIN, D0
62 2 D3 F3 6 -
63 2 D2 G4 4 VREF
64 2 G3 E2 4 -
65 2 H4 E1 6 VREF
66 2 H3 F2
Ö
-
67 2 J4 F1 4 -
68 2 J3 G2 6 -
69 2 G1 K4
Ö
VREF
70 2 H2 K3
Ö
-
71 2 H1 L4 7 VREF
72 2 J2 L3 4 -
73 2 J1 M3
Ö
VREF
74 2 K2 N4
Ö
-
75 2 K1 N3 4 -
76 2 L2 P4
Ö
D1
77 2 P3 L1
Ö
D2
78 2 R4 M2 6 -
79 2 R3 M1 4 -
80 2 T4 N2 4 -
81 2 N1 T3 6 VREF
82 2 P2 U5
Ö
-
83 2 P1 U4 4 -
84 2 R2 U3 6 -
85 2 V5 R1
Ö
D3
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
86 2 V4 T2
Ö
-
87 2 V3 T1 7 -
88 2 W4 U2 4 -
89 2 W3 U1
Ö
VREF
90 2 AA3 V2
Ö
-
91 2 AA4 V1 4 VREF
92 2 AB2 W2
Ö
-
93 3 AB4 W1 4 VREF
94 3 AB5 Y2
Ö
-
953AC2Y1
Ö
VREF
963AC3AA14 -
973AC4AA27 -
983AC5AB1
Ö
-
99 3 AD3 AC1
Ö
VREF
100 3 AD1 AD4 6 -
101 3 AD2 AE3 4 -
102 3 AE1 AE4
Ö
-
103 3 AE2 AF3 6 VREF
104 3 AF4 AF1 4 -
105 3 AG3 AF2 4 -
106 3 AG4 AG1 6 -
107 3 AH3 AG2
Ö
D5
108 3 AH1 AJ2
Ö
VREF
109 3 AH2 AJ3 4 -
110 3 AJ1 AJ4
Ö
-
111 3 AK1 AK3
Ö
VREF
112 3 AK2 AK4 4 -
113 3 AL1 AL2 7 VREF
114 3 AM1 AL3
Ö
-
115 3 AM2 AL4
Ö
VREF
116 3 AM3 AN1 6 -
117 3 AM4 AP1 4 -
118 3 AN2 AP2
Ö
-
119 3 AN3 AR1 6 VREF
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
84 1-800-255-7778 Preliminary Product Specification
120 3 AN4 AT1 4 -
121 3 AR2 AP4 4 VREF
122 3 AT2 AR3 6 -
123 3 AR4 AU2
Ö
INIT
124 4 AU4 AV5
Ö
-
125 4 AT6 AV4 5 -
126 4 AU6 AW4 5 VREF
127 4 AT7 AW5
Ö
-
128 4 AU7 AV6
Ö
VREF
129 4 AT8 AW6 3 -
130 4 AU8 AV7 3 -
131 4 AT9 AW7
Ö
-
132 4 AV8 AU9
Ö
VREF
133 4 AW8 AT10 5 -
134 4 AV9 AU10 5 VREF
135 4 AW9 AT11
Ö
-
136 4 AV10 AU11
Ö
VREF
137 4 AW10 AU12 2 -
138 4 AV11 AT13 2 -
139 4 AW11 AU13
Ö
VREF
140 4 AT14 AV12
Ö
-
141 4 AU14 AW12 5 -
142 4 AT15 AV13 5 -
143 4 AU15 AW13
Ö
-
144 4 AV14 AT16
Ö
VREF
145 4 AW14 AU16 3 -
146 4 AV15 AR17 3 -
147 4 AW15 AT17
Ö
-
148 4 AU17 AV16
Ö
VREF
149 4 AR18 AW16 5 -
150 4 AT18 AV17 5 -
151 4 AU18 AW17
Ö
-
152 4 AT19 AV18
Ö
VREF
153 4 AU19 AW18 2 -
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
154 4 AU21 AV19 2 VREF
155 5 AT21 AT22 NA IO_LVDS_DLL
156 5 AV20 AR22 8 VREF
157 5 AV23 AW21
Ö
VREF
158 5 AU23 AV21
Ö
-
159 5 AT23 AW22 5 -
160 5 AR23 AV22 5 -
161 5 AV24 AW23
Ö
VREF
162 5 AW24 AU24
Ö
-
163 5 AW25 AT24 3 -
164 5 AV25 AU25 3 -
165 5 AW26 AT25
Ö
VREF
166 5 AV26 AW27
Ö
-
167 5 AU26 AV27 5 -
168 5 AT26 AW28 5 -
169 5 AU27 AV28
Ö
-
170 5 AW29 AT27
Ö
VREF
171 5 AW30 AU28 2 -
172 5 AV30 AV29 2 -
173 5 AW31 AU29
Ö
VREF
174 5 AV31 AT29
Ö
-
175 5 AW32 AU30 5 VREF
176 5 AW33 AT30 5 -
177 5 AV33 AU31
Ö
VREF
178 5 AT31 AW34
Ö
-
179 5 AV32 AV34 3 -
180 5 AU32 AW35 3 -
181 5 AT32 AV35
Ö
VREF
182 5 AU33 AW36
Ö
-
183 5 AT33 AV36 5 VREF
184 5 AU34 AU36 5 -
185 6 AT38 AR36
Ö
-
186 6 AP36 AR38 6 -
187 6 AP37 AT39 4 VREF
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 85
188 6 AP39 AP38 4 -
189 6 AN38 AN36 6 VREF
190 6 AN39 AN37
Ö
-
191 6 AM38 AM36 4 -
192 6 AL36 AM37 6 -
193 6 AL37 AM39
Ö
VREF
194 6 AK36 AL38
Ö
-
195 6 AK37 AL39 7 VREF
196 6 AJ36 AK38 4 -
197 6 AJ37 AK39
Ö
VREF
198 6 AH37 AJ38
Ö
-
199 6 AH38 AJ39 4 -
200 6 AG38 AH39
Ö
VREF
201 6 AG39 AG36
Ö
-
202 6 AF39 AG37 6 -
203 6 AE38 AF36 4 -
204 6 AF38 AF37 4 -
205 6 AE36 AE39 6 VREF
206 6 AE37 AD38
Ö
-
207 6 AD36 AD39 4 -
208 6 AC39 AC38 6 -
209 6 AB38 AD37
Ö
VREF
210 6 AB39 AC35
Ö
-
211 6 AA38 AC36 7 -
212 6 AA39 AC37 4 -
213 6 Y38 AB35
Ö
VREF
214 6 Y39 AB36
Ö
-
215 6 AA36 AB37 4 VREF
216 7 W38 AA37
Ö
-
217 7 V39 W37 4 VREF
218 7 U39 W36
Ö
-
219 7 U38 V38
Ö
VREF
220 7 T39 V37 4 -
221 7 T38 V36 7 -
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
222 7 R39 V35
Ö
-
223 7 U36 U37
Ö
VREF
224 7 U35 R38 6 -
225 7 T37 P39 4 -
226 7 T36 P38
Ö
-
227 7 N38 N39 6 VREF
228 7 M39 R37 4 -
229 7 M38 R36 4 -
230 7 L39 P37 6 -
231 7 N37 P36
Ö
-
232 7 N36 L38
Ö
VREF
233 7 M37 K39 4 -
234 7 L37 K38
Ö
-
235 7 L36 J39
Ö
VREF
236 7 K37 J38 4 -
237 7 K36 H39
Ö
VREF
238 7 J37 H38
Ö
-
239 7 G38 G39
Ö
VREF
240 7 F39 J36 6 -
241 7 F38 H37 4 -
242 7 E39 H36
Ö
-
243 7 E38 G37 6 VREF
244 7 D39 G36 4 -
245 7 F36 D38 4 VREF
246 7 E37 D37 6 -
Notes:
1. AO in the XCV1000E, 1600E, 2000E.
2. AO in the XCV600E, 1000E, 1600E.
3. AO in the XCV600E, 1000E.
4. AO in the XCV1000E, 1600E.
5. AO in the XCV1000E, 2000E.
6. AO in the XCV600E, 1000E, 2000E.
7. AO in the XCV1000E.
8. AO in the XCV2000E.
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
86 1-800-255-7778 Preliminary Product Specification
FG860 Fine-Pitch Ball Grid Array Package
XCV1000E, XCV1600E, and XCV2000E devices in the
FG680 fine-pitch Ball Grid Array package have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as VREF
, it can be used as gen-
eral I/O. Immediately following Table 24, see Ta ble 2 5 for
Differential Pair information.
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
0GCK3C22
0IOA26
0IOB31
0IOB34
0IOC24
0IOC29
0IOC34
0IOD24
0IOD36
0IOD40
0IOE26
0IOE28
0IOE35
0 IO_L0N_Y A38
0 IO_L0P_Y D38
0 IO_L1N_Y B37
0 IO_L1P_Y E37
0 IO_VREF_L2N_Y A37
0 IO_L2P_Y C39
0 IO_L3N_Y B36
0 IO_L3P_Y C38
0 IO_L4N_YY A36
0 IO_L4P_YY B35
0 IO_VREF_L5N_YY A35
0 IO_L5P_YY D37
0IO_L6N_YC37
0 IO_L6P_Y A34
0 IO_L7N_Y E36
0 IO_L7P_Y B33
0 IO_L8N_YY A33
0 IO_L8P_YY C32
0 IO_VREF_L9N_YY C36
0 IO_L9P_YY B32
0 IO_L10N_Y A32
0 IO_L10P_Y D35
0 IO_VREF_L11N_Y C312
0 IO_L11P_Y C35
0 IO_L12N_YY E34
0 IO_L12P_YY A31
0 IO_VREF_L13N_YY D34
0 IO_L13P_YY C30
0 IO_L14N_Y B30
0 IO_L14P_Y E33
0 IO_L15N_Y A30
0 IO_L15P_Y D33
0 IO_VREF_L16N_YY C33
0 IO_L16P_YY B29
0 IO_L17N_YY E32
0 IO_L17P_YY A29
0 IO_L18N_Y D32
0 IO_L18P_Y C28
0 IO_L19N_Y E31
0 IO_L19P_Y B28
0 IO_L20N_Y D31
0 IO_L20P_Y A28
0 IO_L21N_Y D30
0 IO_L21P_Y C27
0 IO_L22N_YY E29
0 IO_L22P_YY B27
0 IO_VREF_L23N_YY D29
0 IO_L23P_YY A27
0 IO_L24N_Y C26
0 IO_L24P_Y D28
0 IO_L25N_Y B26
0 IO_L25P_Y F27
0 IO_L26N_YY E27
0 IO_L26P_YY C25
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 87
0 IO_VREF_L27N_YY D27
0 IO_L27P_YY B25
0 IO_L28N_Y A25
0 IO_L28P_Y D26
0 IO_L29N_Y A24
0 IO_L29P_Y E25
0 IO_L30N_YY D25
0 IO_L30P_YY B24
0 IO_VREF_L31N_YY E24
0 IO_L31P_YY A23
0 IO_L32N_Y C23
0 IO_L32P_Y E23
0 IO_VREF_L33N_Y B231
0 IO_L33P_Y D23
0 IO_LVDS_DLL_L34N A22
1GCK2B22
1IOA14
1IOA20
1IOB11
1IOB13
1IOC8
1IOC18
1IOC21
1IOD7
1IOD10
1IOD15
1IOD17
1IOE20
1 IO_LVDS_DLL_L34P D22
1 IO_L35N_Y D21
1 IO_VREF_L35P_Y B211
1 IO_L36N_Y D20
1 IO_L36P_Y A21
1 IO_L37N_YY C20
1 IO_VREF_L37P_YY D19
1 IO_L38N_YY B20
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
1 IO_L38P_YY E19
1 IO_L39N_Y D18
1 IO_L39P_Y A19
1 IO_L40N_Y E18
1 IO_L40P_Y C19
1 IO_L41N_YY B19
1 IO_VREF_L41P_YY E17
1 IO_L42N_YY A18
1 IO_L42P_YY D16
1 IO_L43N_Y E16
1 IO_L43P_Y B18
1 IO_L44N_Y F16
1 IO_L44P_Y A17
1 IO_L45N_YY C17
1 IO_VREF_L45P_YY E15
1 IO_L46N_YY B17
1 IO_L46P_YY D14
1 IO_L47N_Y A16
1 IO_L47P_Y E14
1 IO_L48N_Y C16
1 IO_L48P_Y D13
1 IO_L49N_Y B16
1 IO_L49P_Y D12
1 IO_L50N_Y A15
1 IO_L50P_Y E12
1 IO_L51N_YY C15
1 IO_L51P_YY C11
1 IO_L52N_YY B15
1 IO_VREF_L52P_YY D11
1 IO_L53N_Y E11
1 IO_L53P_Y C14
1 IO_L54N_Y C10
1 IO_L54P_Y B14
1 IO_L55N_YY A13
1 IO_VREF_L55P_YY E10
1 IO_L56N_YY C13
1 IO_L56P_YY C9
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
88 1-800-255-7778 Preliminary Product Specification
1 IO_L57N_Y D9
1 IO_VREF_L57P_Y A122
1 IO_L58N_Y E9
1 IO_L58P_Y C12
1 IO_L59N_YY B12
1 IO_VREF_L59P_YY D8
1 IO_L60N_YY A11
1 IO_L60P_YY E8
1 IO_L61N_Y C7
1 IO_L61P_Y A10
1 IO_L62N_Y C6
1 IO_L62P_Y B10
1 IO_L63N_YY A9
1 IO_VREF_L63P_YY B9
1 IO_L64N_YY A8
1 IO_L64P_YY E7
1 IO_L65N_Y B8
1 IO_L65P_Y C5
1 IO_L66N_Y A7
1 IO_VREF_L66P_Y A6
1 IO_L67N_Y B7
1 IO_L67P_Y D6
1 IO_L68N_Y A5
1 IO_L68P_Y C4
1 IO_WRITE_L69N_YY B6
1 IO_CS_L69P_YY E6
2IOH2
2IOH3
2IOJ1
2IOK5
2IOM2
2ION1
2IOR5
2IOU1
2IOU4
2IOW3
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
2IOY3
2IOAA3
2 IO_DOUT_BUSY_L70P_YY F5
2 IO_DIN_D0_L70N_YY D2
2 IO_L71P_Y E4
2 IO_L71N_Y E2
2 IO_L72P_Y D3
2 IO_L72N_Y F2
2 IO_VREF_L73P_Y E1
2 IO_L73N_Y F4
2 IO_L74P G2
2 IO_L74N E3
2 IO_L75P_Y F1
2 IO_L75N_Y G5
2 IO_VREF_L76P_Y G1
2 IO_L76N_Y F3
2 IO_L77P_YY G4
2 IO_L77N_YY H1
2 IO_L78P_Y J2
2 IO_L78N_Y G3
2 IO_L79P_Y H5
2 IO_L79N_Y K2
2 IO_VREF_L80P_YY H4
2 IO_L80N_YY K1
2 IO_L81P_YY L2
2 IO_L81N_YY L3
2 IO_VREF_L82P_Y L12
2 IO_L82N_Y J5
2 IO_L83P_Y J4
2 IO_L83N_Y M3
2 IO_VREF_L84P_YY J3
2 IO_L84N_YY M1
2 IO_L85P_YY N2
2 IO_L85N_YY K4
2 IO_L86P_Y N3
2 IO_L86N_Y K3
2 IO_VREF_L87P_YY L5
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 89
2 IO_D1_L87N_YY P2
2 IO_D2_L88P_YY P3
2 IO_L88N_YY L4
2 IO_L89P_Y P1
2 IO_L89N_Y R2
2 IO_L90P_Y M5
2 IO_L90N_Y R3
2 IO_L91P_Y M4
2 IO_L91N_Y R1
2 IO_L92P N4
2 IO_L92N T2
2 IO_L93P_Y P5
2 IO_L93N_Y T3
2 IO_VREF_L94P_Y P4
2 IO_L94N_Y T1
2 IO_L95P_YY U2
2 IO_L95N_YY R4
2 IO_L96P_Y U3
2 IO_L96N_Y T5
2 IO_L97P_Y T4
2 IO_L97N_Y V2
2 IO_VREF_L98P_YY U5
2 IO_D3_L98N_YY V3
2 IO_L99P_YY V1
2 IO_L99N_YY V5
2 IO_L100P_Y W2
2 IO_L100N_Y V4
2 IO_L101P_Y W5
2 IO_L101N_Y W1
2 IO_VREF_L102P_YY Y2
2 IO_L102N_YY W4
2 IO_L103P_YY Y1
2 IO_L103N_YY Y5
2 IO_VREF_L104P_Y AA11
2 IO_L104N_Y Y4
2 IO_L105P_YY AA4
2 IO_L105N_YY AA2
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
3IOAB4
3IOAC2
3IOAD1
3IOAE3
3IOAF4
3IOAH5
3IOAJ2
3IOAL1
3IOAM3
3IOAP3
3IOAR5
3IOAU4
3IOAB2
3 IO_L106P_Y AB3
3 IO_VREF_L106N_Y AC41
3 IO_L107P_YY AB1
3 IO_L107N_YY AC5
3 IO_L108P_YY AD4
3 IO_VREF_L108N_YY AC3
3 IO_L109P_Y AC1
3 IO_L109N_Y AD5
3 IO_L110P_Y AE4
3 IO_L110N_Y AD3
3 IO_L111P_YY AE5
3 IO_L111N_YY AD2
3 IO_D4_L112P_YY AE1
3 IO_VREF_L112N_YY AF5
3 IO_L113P_Y AE2
3 IO_L113N_Y AG4
3 IO_L114P_Y AG5
3 IO_L114N_Y AF1
3 IO_L115P_YY AH4
3 IO_L115N_YY AF2
3 IO_L116P_Y AF3
3 IO_VREF_L116N_Y AJ4
3 IO_L117P_Y AG1
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
90 1-800-255-7778 Preliminary Product Specification
3 IO_L117N_Y AJ5
3 IO_L118P AG2
3 IO_L118N AK4
3 IO_L119P_Y AG3
3 IO_L119N_Y AL4
3 IO_L120P_Y AH1
3 IO_L120N_Y AL5
3 IO_L121P_Y AH2
3 IO_L121N_Y AM4
3 IO_L122P_YY AH3
3 IO_D5_L122N_YY AM5
3 IO_D6_L123P_YY AJ1
3 IO_VREF_L123N_YY AN3
3 IO_L124P_Y AN4
3 IO_L124N_Y AJ3
3 IO_L125P_YY AN5
3 IO_L125N_YY AK1
3 IO_L126P_YY AK2
3 IO_VREF_L126N_YY AP4
3 IO_L127P_Y AK3
3 IO_L127N_Y AP5
3 IO_L128P_Y AR3
3 IO_VREF_L128N_Y AL22
3 IO_L129P_YY AR4
3 IO_L129N_YY AL3
3 IO_L130P_YY AM1
3 IO_VREF_L130N_YY AT3
3 IO_L131P_Y AM2
3 IO_L131N_Y AT4
3 IO_L132P_Y AT5
3 IO_L132N_Y AN1
3 IO_L133P_YY AU3
3 IO_L133N_YY AN2
3 IO_L134P_Y AP1
3 IO_VREF_L134N_Y AP2
3 IO_L135P_Y AR1
3 IO_L135N_Y AV3
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
3 IO_L136P AR2
3 IO_L136N AT1
3 IO_L137P_Y AV4
3 IO_VREF_L137N_Y AT2
3 IO_L138P_Y AU1
3 IO_L138N_Y AU5
3 IO_L139P_Y AU2
3 IO_L139N_Y AW3
3 IO_D7_L140P_YY AV1
3 IO_INIT_L140N_YY AW5
4GCK0BA22
4IOAV17
4IOAY11
4IOAY12
4IOAY13
4IOAY14
4IOBA8
4IOBA17
4IOBA19
4IOBA20
4IOBA21
4IOBB9
4IOBB18
4 IO_L141P_YY AV6
4 IO_L141N_YY BA4
4 IO_L142P_Y AY4
4 IO_L142N_Y BA5
4 IO_L143P_Y AW6
4 IO_L143N_Y BB5
4 IO_VREF_L144P_Y BA6
4 IO_L144N_Y AY5
4 IO_L145P_Y BB6
4 IO_L145N_Y AY6
4 IO_L146P_YY BA7
4 IO_L146N_YY AV7
4 IO_VREF_L147P_YY BB7
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 91
4 IO_L147N_YY AW7
4 IO_L148P_Y AY7
4 IO_L148N_Y BB8
4 IO_L149P_Y BA9
4 IO_L149N_Y AV8
4 IO_L150P_YY AW8
4 IO_L150N_YY BA10
4 IO_VREF_L151P_YY BB10
4 IO_L151N_YY AY8
4 IO_L152P_Y AV9
4 IO_L152N_Y BA11
4 IO_VREF_L153P_Y BB112
4 IO_L153N_Y AW9
4 IO_L154P_YY AY9
4 IO_L154N_YY BA12
4 IO_VREF_L155P_YY BB12
4 IO_L155N_YY AV10
4 IO_L156P_Y BA13
4 IO_L156N_Y AW10
4 IO_L157P_Y BB13
4 IO_L157N_Y AY10
4 IO_VREF_L158P_YY AV11
4 IO_L158N_YY BA14
4 IO_L159P_YY AW11
4 IO_L159N_YY BB14
4 IO_L160P_Y AV12
4 IO_L160N_Y BA15
4 IO_L161P_Y AW12
4 IO_L161N_Y AY15
4 IO_L162P_Y AW13
4 IO_L162N_Y BB15
4 IO_L163P_Y AV14
4 IO_L163N_Y BA16
4 IO_L164P_YY AW14
4 IO_L164N_YY AY16
4 IO_VREF_L165P_YY BB16
4 IO_L165N_YY AV15
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
4 IO_L166P_Y AY17
4 IO_L166N_Y AW15
4 IO_L167P_Y BB17
4 IO_L167N_Y AU16
4 IO_L168P_YY AV16
4 IO_L168N_YY AY18
4 IO_VREF_L169P_YY AW16
4 IO_L169N_YY BA18
4 IO_L170P_Y BB19
4 IO_L170N_Y AW17
4 IO_L171P_Y AY19
4 IO_L171N_Y AV18
4 IO_L172P_YY AW18
4 IO_L172N_YY BB20
4 IO_VREF_L173P_YY AY20
4 IO_L173N_YY AV19
4 IO_L174P_Y BB21
4 IO_L174N_Y AW19
4 IO_VREF_L175P_Y AY211
4 IO_L175N_Y AV20
4 IO_LVDS_DLL_L176P AW20
5GCK1AY22
5IOAV24
5IOAV34
5IOAW27
5IOAW36
5IOAY23
5IOAY31
5IOAY33
5IOBA26
5IOBA29
5IOBA33
5IOBB25
5 IO_LVDS_DLL_L176N AW21
5 IO_L177P_Y BB22
5 IO_VREF_L177N_Y AW221
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
92 1-800-255-7778 Preliminary Product Specification
5 IO_L178P_Y BB23
5 IO_L178N_Y AW23
5 IO_L179P_YY AV23
5 IO_VREF_L179N_YY BA23
5 IO_L180P_YY AW24
5 IO_L180N_YY BB24
5 IO_L181P_Y AY24
5 IO_L181N_Y AW25
5 IO_L182P_Y BA24
5 IO_L182N_Y AV25
5 IO_L183P_YY AW26
5 IO_VREF_L183N_YY AY25
5 IO_L184P_YY AV26
5 IO_L184N_YY BA25
5 IO_L185P_Y BB26
5 IO_L185N_Y AV27
5 IO_L186P_Y AY26
5 IO_L186N_Y AU27
5 IO_L187P_YY AW28
5 IO_VREF_L187N_YY BB27
5 IO_L188P_YY AY27
5 IO_L188N_YY AV28
5 IO_L189P_Y BA27
5 IO_L189N_Y AW29
5 IO_L190P_Y BB28
5 IO_L190N_Y AV29
5 IO_L191P_Y AY28
5 IO_L191N_Y AW30
5 IO_L192P_Y BA28
5 IO_L192N_Y AW31
5 IO_L193P_YY BB29
5 IO_L193N_YY AV31
5 IO_L194P_YY AY29
5 IO_VREF_L194N_YY AY32
5 IO_L195P_Y AW32
5 IO_L195N_Y BB30
5 IO_L196P_Y AV32
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
5 IO_L196N_Y AY30
5 IO_L197P_YY BA30
5 IO_VREF_L197N_YY AW33
5 IO_L198P_YY BB31
5 IO_L198N_YY AV33
5 IO_L199P_Y AY34
5 IO_VREF_L199N_Y BA312
5 IO_L200P_Y AW34
5 IO_L200N_Y BB32
5 IO_L201P_YY BA32
5 IO_VREF_L201N_YY AY35
5 IO_L202P_YY BB33
5 IO_L202N_YY AW35
5 IO_L203P_Y AV35
5 IO_L203N_Y BB34
5 IO_L204P_Y AY36
5 IO_L204N_Y BA34
5 IO_L205P_YY BB35
5 IO_VREF_L205N_YY AV36
5 IO_L206P_YY BA35
5 IO_L206N_YY AY37
5 IO_L207P_Y BB36
5 IO_L207N_Y BA36
5 IO_L208P_Y AW37
5 IO_VREF_L208N_Y BB37
5 IO_L209P_Y BA37
5 IO_L209N_Y AY38
5 IO_L210P_Y BB38
5 IO_L210N_Y AY39
6IOAA40
6IOAB41
6IOAC42
6IOAD39
6IOAE40
6IOAF38
6IOAF40
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 93
6IOAJ40
6IOAL41
6IOAN38
6IOAN42
6IOAP41
6IOAR39
6 IO_L211N_YY AV41
6 IO_L211P_YY AV42
6 IO_L212N_Y AW40
6 IO_L212P_Y AU41
6 IO_L213N_Y AV39
6 IO_L213P_Y AU42
6 IO_VREF_L214N_Y AT41
6 IO_L214P_Y AU38
6 IO_L215N AT42
6 IO_L215P AV40
6 IO_L216N_Y AR41
6 IO_L216P_Y AU39
6 IO_VREF_L217N_Y AR42
6 IO_L217P_Y AU40
6 IO_L218N_YY AT38
6 IO_L218P_YY AP42
6 IO_L219N_Y AN41
6 IO_L219P_Y AT39
6 IO_L220N_Y AT40
6 IO_L220P_Y AM40
6 IO_VREF_L221N_YY AR38
6 IO_L221P_YY AM41
6 IO_L222N_YY AM42
6 IO_L222P_YY AR40
6 IO_VREF_L223N_Y AL402
6 IO_L223P_Y AP38
6 IO_L224N_Y AP39
6 IO_L224P_Y AL42
6 IO_VREF_L225N_YY AP40
6 IO_L225P_YY AK40
6 IO_L226N_YY AK41
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
6 IO_L226P_YY AN39
6 IO_L227N_Y AK42
6 IO_L227P_Y AN40
6 IO_VREF_L228N_YY AM38
6 IO_L228P_YY AJ41
6 IO_L229N_YY AJ42
6 IO_L229P_YY AM39
6 IO_L230N_Y AH40
6 IO_L230P_Y AH41
6 IO_L231N_Y AL38
6 IO_L231P_Y AH42
6 IO_L232N_Y AL39
6 IO_L232P_Y AG41
6 IO_L233N AK39
6 IO_L233P AG40
6 IO_L234N_Y AJ38
6 IO_L234P_Y AG42
6 IO_VREF_L235N_Y AF42
6 IO_L235P_Y AJ39
6 IO_L236N_YY AF41
6 IO_L236P_YY AH38
6 IO_L237N_Y AE42
6 IO_L237P_Y AH39
6 IO_L238N_Y AG38
6 IO_L238P_Y AE41
6 IO_VREF_L239N_YY AG39
6 IO_L239P_YY AD42
6 IO_L240N_YY AD40
6 IO_L240P_YY AF39
6 IO_L241N_Y AD41
6 IO_L241P_Y AE38
6 IO_L242N_Y AE39
6 IO_L242P_Y AC40
6 IO_VREF_L243N_YY AD38
6 IO_L243P_YY AC41
6 IO_L244N_YY AB42
6 IO_L244P_YY AC38
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
94 1-800-255-7778 Preliminary Product Specification
6 IO_VREF_L245N_Y AB401
6 IO_L245P_Y AC39
7IOF38
7IOH40
7IOH41
7IOJ42
7IOK39
7IOL42
7ION40
7IOT40
7IOU40
7IOV38
7IOW42
7IOY42
7IOAA42
7 IO_L246N_YY AA41
7 IO_L246P_YY AB39
7 IO_L247N_Y Y41
7 IO_VREF_L247P_Y AA391
7 IO_L248N_YY Y40
7 IO_L248P_YY Y39
7 IO_L249N_YY Y38
7 IO_VREF_L249P_YY W41
7 IO_L250N_Y W40
7 IO_L250P_Y W39
7 IO_L251N_Y W38
7 IO_L251P_Y V41
7 IO_L252N_YY V39
7 IO_L252P_YY V40
7 IO_L253N_YY V42
7 IO_VREF_L253P_YY U39
7 IO_L254N_Y U41
7 IO_L254P_Y U38
7 IO_L255N_Y U42
7 IO_L255P_Y T39
7 IO_L256N_YY T41
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
7 IO_L256P_YY T38
7 IO_L257N_Y R39
7 IO_VREF_L257P_Y T42
7 IO_L258N_Y R42
7 IO_L258P_Y R38
7 IO_L259N R40
7 IO_L259P P39
7 IO_L260N_Y R41
7 IO_L260P_Y P38
7 IO_L261N_Y P42
7 IO_L261P_Y N39
7 IO_L262N_Y P40
7 IO_L262P_Y M39
7 IO_L263N_YY P41
7 IO_L263P_YY M38
7 IO_L264N_YY N42
7 IO_VREF_L264P_YY L39
7 IO_L265N_Y L38
7 IO_L265P_Y N41
7 IO_L266N_YY K40
7 IO_L266P_YY M42
7 IO_L267N_YY M40
7 IO_VREF_L267P_YY K38
7 IO_L268N_Y M41
7 IO_L268P_Y J40
7 IO_L269N_Y J39
7 IO_VREF_L269P_Y L40
7 IO_L270N_YY J38
7 IO_L270P_YY L41
7 IO_L271N_YY K42
7 IO_VREF_L271P_YY H39
7 IO_L272N_Y K41
7 IO_L272P_Y H38
7 IO_L273N_Y J41
7 IO_L273P_Y G40
7 IO_L274N_YY H42
7 IO_L274P_YY G39
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 95
7 IO_L275N_Y G38
7 IO_VREF_L275P_Y G42
7 IO_L276N_Y G41
7 IO_L276P_Y F40
7 IO_L277N F42
7 IO_L277P F41
7 IO_L278N_Y F39
7 IO_VREF_L278P_Y E42
7 IO_L279N_Y E40
7 IO_L279P_Y E41
7 IO_L280N_Y E39
7 IO_L280P_Y D41
2CCLKB4
3DONEAW2
NA DXN BA38
NA DXP AW38
NA M0 AW41
NA M1 AV37
NA M2 BA39
NA PROGRAM AV2
NA TCK B38
NA TDI B5
2TDOD5
NA TMS B39
NA VCCINT F9
NA VCCINT F10
NA VCCINT F17
NA VCCINT F18
NA VCCINT F25
NA VCCINT F26
NA VCCINT F33
NA VCCINT F34
NA VCCINT J6
NA VCCINT J37
NA VCCINT K6
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
NA VCCINT K37
NA VCCINT T6
NA VCCINT T37
NA VCCINT U6
NA VCCINT U37
NA VCCINT V6
NA VCCINT V37
NA VCCINT AE6
NA VCCINT AE37
NA VCCINT AF6
NA VCCINT AF37
NA VCCINT AG6
NA VCCINT AG37
NA VCCINT AN6
NA VCCINT AN37
NA VCCINT AP6
NA VCCINT AP37
NA VCCINT AU9
NA VCCINT AU10
NA VCCINT AU17
NA VCCINT AU18
NA VCCINT AU25
NA VCCINT AU26
NA VCCINT AU33
NA VCCINT AU34
NA VCCO_0 F23
NA VCCO_0 F24
NA VCCO_0 F28
NA VCCO_0 F29
NA VCCO_0 F31
NA VCCO_0 F32
NA VCCO_0 F35
NA VCCO_0 F36
NA VCCO_1 F11
NA VCCO_1 F12
NA VCCO_1 F14
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
96 1-800-255-7778 Preliminary Product Specification
NA VCCO_1 F15
NA VCCO_1 F19
NA VCCO_1 F20
NA VCCO_1 F7
NA VCCO_1 F8
NA VCCO_2 G6
NA VCCO_2 H6
NA VCCO_2 L6
NA VCCO_2 M6
NA VCCO_2 P6
NA VCCO_2 R6
NA VCCO_2 W6
NA VCCO_2 Y6
NA VCCO_3 AC6
NA VCCO_3 AD6
NA VCCO_3 AH6
NA VCCO_3 AJ6
NA VCCO_3 AL6
NA VCCO_3 AM6
NA VCCO_3 AR6
NA VCCO_3 AT6
NA VCCO_4 AU11
NA VCCO_4 AU12
NA VCCO_4 AU14
NA VCCO_4 AU15
NA VCCO_4 AU19
NA VCCO_4 AU20
NA VCCO_4 AU7
NA VCCO_4 AU8
NA VCCO_5 AU23
NA VCCO_5 AU24
NA VCCO_5 AU28
NA VCCO_5 AU29
NA VCCO_5 AU31
NA VCCO_5 AU32
NA VCCO_5 AU35
NA VCCO_5 AU36
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
NA VCCO_6 AC37
NA VCCO_6 AD37
NA VCCO_6 AH37
NA VCCO_6 AJ37
NA VCCO_6 AL37
NA VCCO_6 AM37
NA VCCO_6 AR37
NA VCCO_6 AT37
NA VCCO_7 G37
NA VCCO_7 H37
NA VCCO_7 L37
NA VCCO_7 M37
NA VCCO_7 P37
NA VCCO_7 R37
NA VCCO_7 W37
NA VCCO_7 Y37
NA GND N6
NA GND N5
NA GND N38
NA GND N37
NA GND F6
NA GND F37
NA GND F30
NA GND F22
NA GND F21
NA GND F13
NA GND E5
NA GND E38
NA GND E30
NA GND E22
NA GND E21
NA GND E13
NA GND D42
NA GND D4
NA GND D39
NA GND D1
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 97
NA GND C42
NA GND C41
NA GND C40
NA GND C3
NA GND C2
NA GND C1
NA GND BB41
NA GND BB40
NA GND BB4
NA GND BB39
NA GND BB3
NA GND BB2
NA GND BA42
NA GND BA41
NA GND BA40
NA GND BA3
NA GND BA2
NA GND BA1
NA GND B42
NA GND B41
NA GND B40
NA GND B3
NA GND B2
NA GND B1
NA GND AY42
NA GND AY41
NA GND AY40
NA GND AY3
NA GND AY2
NA GND AY1
NA GND AW42
NA GND AW4
NA GND AW39
NA GND AW1
NA GND AV5
NA GND AV38
NA GND AV30
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
NA GND AV22
NA GND AV21
NA GND AV13
NA GND AU6
NA GND AU37
NA GND AU30
NA GND AU22
NA GND AU21
NA GND AU13
NA GND AK6
NA GND AK5
NA GND AK38
NA GND AK37
NA GND AB6
NA GND AB5
NA GND AB38
NA GND AB37
NA GND AA6
NA GND AA5
NA GND AA38
NA GND AA37
NA GND A41
NA GND A40
NA GND A4
NA GND A39
NA GND A3
NA GND A2
Notes:
1. VREF or I/O option only in the XCV1600E, 2000E; otherwise,
I/O option only.
2. VREF or I/O option only in the XCV2000E; otherwise, I/O
option only.
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
98 1-800-255-7778 Preliminary Product Specification
FG860 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Global Differential Clock
3 0 C22 A22 NA IO_DLL_L34N
2 1 B22 D22 NA IO_DLL_L34P
1 5 AY22 AW21 NA IO_DLL_L176N
0 4 BA22 AW20 NA IO_DLL_L176P
IO LVDS
Total Pairs: 281, Asynchronous Output Pairs: 111
00D38A382 -
10E37B371 -
2 0 C39 A37 1 VREF
30C38B361 -
40B35A36
Ö
-
50D37A35
Ö
VREF
60A34C375 -
70B33E365 -
80C32A33
Ö
-
90B32C36
Ö
VREF
10 0 D35 A32 1 -
11 0 C35 C31 1 VREF
12 0 A31 E34
Ö
-
13 0 C30 D34
Ö
VREF
14 0 E33 B30 2 -
15 0 D33 A30 2 -
16 0 B29 C33
Ö
VREF
17 0 A29 E32
Ö
-
18 0 C28 D32 2 -
19 0 B28 E31 1 -
20 0 A28 D31 1 -
21 0 C27 D30 5 -
22 0 B27 E29
Ö
-
23 0 A27 D29
Ö
VREF
24 0 D28 C26 5 -
25 0 F27 B26 5 -
26 0 C25 E27
Ö
-
27 0 B25 D27
Ö
VREF
28 0 D26 A25 1 -
29 0 E25 A24 1 -
30 0 B24 D25
Ö
-
31 0 A23 E24
Ö
VREF
32 0 E23 C23 2 -
33 0 D23 B23 2 VREF
34 1 D22 A22 NA IO_LVDS_DLL
35 1 B21 D21 2 VREF
36 1 A21 D20 2 -
37 1 D19 C20
Ö
VREF
38 1 E19 B20
Ö
-
39 1 A19 D18 1 -
40 1 C19 E18 1 -
41 1 E17 B19
Ö
VREF
42 1 D16 A18
Ö
-
43 1 B18 E16 5 -
44 1 A17 F16 5 -
45 1 E15 C17
Ö
VREF
46 1 D14 B17
Ö
-
47 1 E14 A16 5 -
48 1 D13 C16 1 -
49 1 D12 B16 1 -
50 1 E12 A15 2 -
51 1 C11 C15
Ö
-
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 99
52 1 D11 B15
Ö
VREF
53 1 C14 E11 2 -
54 1 B14 C10 2 -
55 1 E10 A13
Ö
VREF
56 1 C9 C13
Ö
-
57 1 A12 D9 1 VREF
58 1 C12 E9 1 -
59 1 D8 B12
Ö
VREF
60 1 E8 A11
Ö
-
61 1 A10 C7 5 -
62 1 B10 C6 5 -
63 1 B9 A9
Ö
VREF
64 1 E7 A8
Ö
-
65 1 C5 B8 5 -
66 1 A6 A7 1 VREF
67 1 D6 B7 1 -
68 1 C4 A5 2 -
69 1 E6 B6
Ö
CS
70 2 F5 D2
Ö
DIN, D0
71 2 E4 E2 3 -
72 2 D3 F2 1 -
73 2 E1 F4 2 VREF
74 2 G2 E3 4 -
75 2 F1 G5 2 -
76 2 G1 F3 1 VREF
77 2 G4 H1
Ö
-
78 2 J2 G3 2 -
79 2 H5 K2 1 -
80 2 H4 K1
Ö
VREF
81 2 L2 L3
Ö
-
82 2 L1 J5 5 VREF
83 2 J4 M3 2 -
84 2 J3 M1
Ö
VREF
85 2 N2 K4
Ö
-
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
86 2 N3 K3 2 -
87 2 L5 P2
Ö
D1
88 2 P3 L4
Ö
D2
89 2 P1 R2 3 -
90 2 M5 R3 1 -
91 2 M4 R1 2 -
92 2 N4 T2 4 -
93 2 P5 T3 2 -
94 2 P4 T1 1 VREF
95 2 U2 R4
Ö
-
96 2 U3 T5 2 -
97 2 T4 V2 1 -
98 2 U5 V3
Ö
D3
99 2 V1 V5
Ö
-
100 2 W2 V4 5 -
101 2 W5 W1 2 -
102 2 Y2 W4
Ö
VREF
103 2 Y1 Y5
Ö
-
104 2 AA1 Y4 2 VREF
105 2 AA4 AA2
Ö
-
106 3 AB3 AC4 2 VREF
107 3 AB1 AC5
Ö
-
108 3 AD4 AC3
Ö
VREF
109 3 AC1 AD5 2 -
110 3 AE4 AD3 5 -
111 3 AE5 AD2
Ö
-
112 3 AE1 AF5
Ö
VREF
113 3 AE2 AG4 1 -
114 3 AG5 AF1 2 -
115 3 AH4 AF2
Ö
-
116 3 AF3 AJ4 1 VREF
117 3 AG1 AJ5 2 -
118 3 AG2 AK4 4 -
119 3 AG3 AL4 2 -
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
100 1-800-255-7778 Preliminary Product Specification
120 3 AH1 AL5 1 -
121 3 AH2 AM4 3 -
122 3 AH3 AM5
Ö
D5
123 3 AJ1 AN3
Ö
VREF
124 3 AN4 AJ3 2 -
125 3 AN5 AK1
Ö
-
126 3 AK2 AP4
Ö
VREF
127 3 AK3 AP5 2 -
128 3 AR3 AL2 5 VREF
129 3 AR4 AL3
Ö
-
130 3 AM1 AT3
Ö
VREF
131 3 AM2 AT4 1 -
132 3 AT5 AN1 2 -
133 3 AU3 AN2
Ö
-
134 3 AP1 AP2 1 VREF
135 3 AR1 AV3 2 -
136 3 AR2 AT1 4 -
137 3 AV4 AT2 2 VREF
138 3 AU1 AU5 1 -
139 3 AU2 AW3 3 -
140 3 AV1 AW5
Ö
INIT
141 4 AV6 BA4
Ö
-
142 4 AY4 BA5 2 -
143 4 AW6 BB5 1 -
144 4 BA6 AY5 1 VREF
145 4 BB6 AY6 5 -
146 4 BA7 AV7
Ö
-
147 4 BB7 AW7
Ö
VREF
148 4 AY7 BB8 5 -
149 4 BA9 AV8 5 -
150 4 AW8 BA10
Ö
-
151 4 BB10 AY8
Ö
VREF
152 4 AV9 BA11 1 -
153 4 BB11 AW9 1 VREF
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
154 4 AY9 BA12
Ö
-
155 4 BB12 AV10
Ö
VREF
156 4 BA13 AW10 2 -
157 4 BB13 AY10 2 -
158 4 AV11 BA14
Ö
VREF
159 4 AW11 BB14
Ö
-
160 4 AV12 BA15 2 -
161 4 AW12 AY15 1 -
162 4 AW13 BB15 1 -
163 4 AV14 BA16 5 -
164 4 AW14 AY16
Ö
-
165 4 BB16 AV15
Ö
VREF
166 4 AY17 AW15 5 -
167 4 BB17 AU16 5 -
168 4 AV16 AY18
Ö
-
169 4 AW16 BA18
Ö
VREF
170 4 BB19 AW17 1 -
171 4 AY19 AV18 1 -
172 4 AW18 BB20
Ö
-
173 4 AY20 AV19
Ö
VREF
174 4 BB21 AW19 2 -
175 4 AY21 AV20 2 VREF
176 5 AW20 AW21 NA IO_LVDS_DLL
177 5 BB22 AW22 2 VREF
178 5 BB23 AW23 2 -
179 5 AV23 BA23
Ö
VREF
180 5 AW24 BB24
Ö
-
181 5 AY24 AW25 1 -
182 5 BA24 AV25 1 -
183 5 AW26 AY25
Ö
VREF
184 5 AV26 BA25
Ö
-
185 5 BB26 AV27 5 -
186 5 AY26 AU27 5 -
187 5 AW28 BB27
Ö
VREF
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 101
188 5 AY27 AV28
Ö
-
189 5 BA27 AW29 5 -
190 5 BB28 AV29 1 -
191 5 AY28 AW30 1 -
192 5 BA28 AW31 2 -
193 5 BB29 AV31
Ö
-
194 5 AY29 AY32
Ö
VREF
195 5 AW32 BB30 2 -
196 5 AV32 AY30 2 -
197 5 BA30 AW33
Ö
VREF
198 5 BB31 AV33
Ö
-
199 5 AY34 BA31 1 VREF
200 5 AW34 BB32 1 -
201 5 BA32 AY35
Ö
VREF
202 5 BB33 AW35
Ö
-
203 5 AV35 BB34 5 -
204 5 AY36 BA34 5 -
205 5 BB35 AV36
Ö
VREF
206 5 BA35 AY37
Ö
-
207 5 BB36 BA36 5 -
208 5 AW37 BB37 1 VREF
209 5 BA37 AY38 1 -
210 5 BB38 AY39 2 -
211 6 AV42 AV41
Ö
-
212 6 AU41 AW40 3 -
213 6 AU42 AV39 1 -
214 6 AU38 AT41 2 VREF
215 6 AV40 AT42 4 -
216 6 AU39 AR41 2 -
217 6 AU40 AR42 1 VREF
218 6 AP42 AT38
Ö
-
219 6 AT39 AN41 2 -
220 6 AM40 AT40 1 -
221 6 AM41 AR38
Ö
VREF
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
222 6 AR40 AM42
Ö
-
223 6 AP38 AL40 5 VREF
224 6 AL42 AP39 2 -
225 6 AK40 AP40
Ö
VREF
226 6 AN39 AK41
Ö
-
227 6 AN40 AK42 2 -
228 6 AJ41 AM38
Ö
VREF
229 6 AM39 AJ42
Ö
-
230 6 AH41 AH40 3 -
231 6 AH42 AL38 1 -
232 6 AG41 AL39 2 -
233 6 AG40 AK39 4 -
234 6 AG42 AJ38 2 -
235 6 AJ39 AF42 1 VREF
236 6 AH38 AF41
Ö
-
237 6 AH39 AE42 2 -
238 6 AE41 AG38 1 -
239 6 AD42 AG39
Ö
VREF
240 6 AF39 AD40
Ö
-
241 6 AE38 AD41 5 -
2426AC40AE392 -
243 6 AC41 AD38
Ö
VREF
2446AC38AB42
Ö
-
245 6 AC39 AB40 2 VREF
246 7 AB39 AA41
Ö
-
247 7 AA39 Y41 2 VREF
248 7 Y39 Y40
Ö
-
249 7 W41 Y38
Ö
VREF
250 7 W39 W40 2 -
251 7 V41 W38 5 -
252 7 V40 V39
Ö
-
253 7 U39 V42
Ö
VREF
254 7 U38 U41 1 -
255 7 T39 U42 2 -
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
102 1-800-255-7778 Preliminary Product Specification
FG900 Fine-Pitch Ball Grid Array Package
XCV600E, XCV1000E, and XCV1600E devices in the
FG900 fine-pitch Ball Grid Array package have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as VREF
, it can be used as gen-
eral I/O. Immediately following Ta bl e 2 6, see Table 27 for
Differential Pair information.
256 7 T38 T41
Ö
-
257 7 T42 R39 1 VREF
258 7 R38 R42 2 -
259 7 P39 R40 4 -
260 7 P38 R41 2 -
261 7 N39 P42 1 -
262 7 M39 P40 3 -
263 7 M38 P41
Ö
-
264 7 L39 N42
Ö
VREF
265 7 N41 L38 2 -
266 7 M42 K40
Ö
-
267 7 K38 M40
Ö
VREF
268 7 J40 M41 2 -
269 7 L40 J39 5 VREF
270 7 L41 J38
Ö
-
271 7 H39 K42
Ö
VREF
272 7 H38 K41 1 -
273 7 G40 J41 2 -
274 7 G39 H42
Ö
-
275 7 G42 G38 1 VREF
276 7 F40 G41 2 -
277 7 F41 F42 4 -
278 7 E42 F39 2 VREF
279 7 E41 E40 1 -
280 7 D41 E39 3 -
Notes:
1. AO in the XCV1000E, 2000E.
2. AO in the XCV1000E, 1600E.
3. AO in the XCV2000E.
4. AO in the XCV1600E.
5. AO in the XCV1000E.
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
0GCK3C15
0IOA7
4
0IOA13
4
0IOC5
4
0IOC6
4
0IOC14
4
0IOD8
5
0IOD10
0IOD13
4
0IO E6
0IOE9
5
0IOE14
5
0IOF9
4
0IOF14
5
0IOG15
0IOK11
5
0IOK12
0IOL13
4
0 IO_L0N_YY C44
0IO_L0P_YYF7
3
0 IO_L1N_Y D5
0IO_L1P_Y G8
0 IO_VREF_L2N_Y A31
0IO_L2P_Y H9
0 IO_L3N_Y B44
0 IO_L3P_Y J104
0 IO_L4N_YY A4
0IO_L4P_YY D6
0 IO_VREF_L5N_YY E7
0 IO_L5P_YY B5
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 103
0 IO_L6N_Y A5
0 IO_L6P_Y F8
0 IO_L7N_Y D7
0 IO_L7P_Y N11
0 IO_L8N_YY G9
0 IO_L8P_YY E8
0 IO_VREF_L9N_YY A6
0 IO_L9P_YY J11
0 IO_L10N_Y C7
0 IO_L10P_Y B7
0 IO_L11N_Y C8
0 IO_L11P_Y H10
0 IO_L12N_YY G10
0 IO_L12P_YY F10
0 IO_VREF_L13N_YY A8
0 IO_L13P_YY H11
0 IO_L14N D94
0 IO_L14P C93
0 IO_L15N_YY B9
0 IO_L15P_YY J12
0 IO_L16N E104
0 IO_VREF_L16P A9
0 IO_L17N G11
0 IO_L17P B10
0 IO_L18N_YY H124
0 IO_L18P_YY C104
0 IO_L19N_Y H13
0 IO_L19P_Y F11
0 IO_L20N_Y E11
0 IO_L20P_Y D11
0 IO_L21N_Y B114
0 IO_L21P_Y G124
0 IO_L22N_YY F12
0 IO_L22P_YY C11
0 IO_VREF_L23N_YY A101
0 IO_L23P_YY D12
0 IO_L24N_Y E12
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
0 IO_L24P_Y A11
0 IO_L25N_Y G13
0 IO_L25P_Y B12
0 IO_L26N_YY A12
0 IO_L26P_YY K13
0 IO_VREF_L27N_YY F13
0 IO_L27P_YY B13
0 IO_L28N_Y G14
0 IO_L28P_Y E13
0 IO_L29N_Y D14
0 IO_L29P_Y B14
0 IO_L30N_YY A14
0 IO_L30P_YY J14
0 IO_VREF_L31N_YY K14
0 IO_L31P_YY J15
0 IO_L32N B154
0 IO_L32P H153
0 IO_VREF_L33N_YY F152,3
0 IO_L33P_YY D154
0 IO_LVDS_DLL_L34N A15
1GCK2E15
1IOA25
4
1IOB17
4
1IOB18
4
1IOC23
4
1IOD16
4
1IOD17
5
1IOD23
4
1IOE19
4
1IOE24
5
1IOF22
4
1IOG17
5
1IOG20
4
1IOJ16
4
1IOJ17
4
1IOJ19
5
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
104 1-800-255-7778 Preliminary Product Specification
1IOJ20
5
1IOL18
4
1 IO_LVDS_DLL_L34P E16
1 IO_L35N_YY B16
1 IO_VREF_L35P_YY F162
1 IO_L36N_YY A16
1 IO_L36P_YY H16
1 IO_L37N_YY C16
1 IO_VREF_L37P_YY K15
1 IO_L38N_YY K16
1 IO_L38P_YY G16
1 IO_L39N_Y A17
1 IO_L39P_Y E17
1 IO_L40N_Y F17
1 IO_L40P_Y C17
1 IO_L41N_YY E18
1 IO_VREF_L41P_YY A18
1 IO_L42N_YY D18
1 IO_L42P_YY A19
1 IO_L43N_Y B19
1 IO_L43P_Y G18
1 IO_L44N_Y D19
1 IO_L44P_Y H18
1 IO_L45N_YY F18
1 IO_VREF_L45P_YY F191
1 IO_L46N_YY B20
1 IO_L46P_YY K17
1 IO_L47N_Y D204
1 IO_L47P_Y A204
1 IO_L48N_Y G19
1 IO_L48P_Y C20
1 IO_L49N_Y K18
1 IO_L49P_Y E20
1 IO_L50N_YY B214
1 IO_L50P_YY D214
1 IO_L51N_YY F20
1 IO_L51P_YY A21
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
1 IO_L52N_YY C21
1 IO_VREF_L52P_YY A22
1 IO_L53N_YY H19
1 IO_L53P_YY B22
1 IO_L54N_YY E21
1 IO_L54P_YY D22
1 IO_L55N_YY F21
1 IO_VREF_L55P_YY C22
1 IO_L56N_YY H20
1 IO_L56P_YY E22
1 IO_L57N_Y G21
1 IO_L57P_Y A23
1 IO_L58N_Y A24
1 IO_L58P_Y K19
1 IO_L59N_YY C24
1 IO_VREF_L59P_YY B24
1 IO_L60N_YY H21
1 IO_L60P_YY G22
1 IO_L61N_Y E23
1 IO_L61P_Y C25
1 IO_L62N_Y D24
1 IO_L62P_Y A26
1 IO_L63N_YY B26
1 IO_VREF_L63P_YY K20
1 IO_L64N_YY D25
1 IO_L64P_YY J21
1 IO_L65N_Y C264
1 IO_L65P_Y F234
1 IO_L66N_Y B27
1 IO_VREF_L66P_Y G231
1 IO_L67N_Y A27
1 IO_L67P_Y F24
1 IO_L68N_YY B283
1 IO_L68P_YY A284
1 IO_WRITE_L69N_YY K21
1 IO_CS_L69P_YY C27
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 105
2IOD29
5
2IOG26
4
2IOH24
4
2IOH25
4
2IOH28
5
2IOJ25
4
2IOJ27
5
2IOK30
4
2IOM24
4
2IOM25
4
2ION20
2ION23
4
2IOP26
5
2IOP27
5
2IOP30
4
2IOR30
2 IO_DOUT_BUSY_L70P_YY J22
2 IO_DIN_D0_L70N_YY E27
2 IO_L71P C294
2 IO_L71N D283
2 IO_L72P_Y G25
2 IO_L72N_Y E25
2 IO_VREF_L73P_YY E281
2 IO_L73N_YY C30
2 IO_L74P_Y K224
2 IO_L74N_Y F273
2 IO_L75P_YY D30
2 IO_L75N_YY J23
2 IO_VREF_L76P_Y L21
2 IO_L76N_Y F28
2 IO_L77P_YY G28
2 IO_L77N_YY E30
2 IO_L78P_YY G27
2 IO_L78N_YY E29
2 IO_L79P K23
2 IO_L79N H26
2 IO_VREF_L80P_YY F30
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
2 IO_L80N_YY L22
2 IO_L81P_YY H27
2 IO_L81N_YY G29
2 IO_L82P G30
2 IO_L82N M21
2 IO_L83P_YY J24
2 IO_L83N_YY J26
2 IO_VREF_L84P_YY H30
2 IO_L84N_YY L23
2 IO_L85P_YY K264
2 IO_L85N_YY J283
2 IO_L86P_YY J29
2 IO_L86N_YY K24
2 IO_L87P_YY K274
2 IO_VREF_L87N_YY J30
2 IO_D1_L88P M22
2 IO_D2_L88N K29
2 IO_L89P_YY K283
2 IO_L89N_YY L254
2 IO_L90P N21
2 IO_L90N K25
2 IO_L91P_YY L24
2 IO_L91N_YY L27
2 IO_L92P_Y L294
2 IO_L92N_Y M234
2 IO_L93P_YY L26
2 IO_L93N_YY L28
2 IO_VREF_L94P L301
2 IO_L94N M27
2 IO_L95P_YY M26
2 IO_L95N_YY M29
2 IO_L96P_YY N29
2 IO_L96N_YY M30
2 IO_L97P N25
2 IO_L97N N27
2 IO_VREF_L98P_YY N30
2 IO_D3_L98N_YY P21
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
106 1-800-255-7778 Preliminary Product Specification
2 IO_L99P_YY N26
2 IO_L99N_YY P28
2 IO_L100P P29
2 IO_L100N N24
2 IO_L101P_YY P22
2 IO_L101N_YY R26
2 IO_VREF_L102P_YY P25
2 IO_L102N_YY R29
2 IO_L103P_YY R214
2 IO_L103N_YY R283
2 IO_VREF_L104P_YY R252
2 IO_L104N_YY T30
2 IO_L105P_YY P244
2 IO_L105N_YY R273
2 IO_L106P R24
3IOT22
4
3IOT24
4
3IOT26
4
3IOT29
4
3IOU26
5
3IOV23
4
3IOV25
4
3IOV30
5
3IOY21
4
3IOAA26
4
3IOAA23
4
3IOAB27
4
3IOAB29
4
3IOAC28
5
3IOAD26
4
3IOAD29
5
3IOAE27
5
3 IO_L106N U29
3 IO_L107P_YY R22
3 IO_VREF_L107N_YY T272
3 IO_L108P_YY R23
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
3 IO_L108N_YY T28
3 IO_L109P_YY T21
3 IO_VREF_L109N_YY T25
3 IO_L110P_YY U28
3 IO_L110N_YY U30
3 IO_L111P T23
3 IO_L111N U27
3 IO_L112P_YY U25
3 IO_L112N_YY V27
3 IO_D4_L113P_YY U24
3 IO_VREF_L113N_YY V29
3 IO_L114P W30
3 IO_L114N U22
3 IO_L115P_YY U21
3 IO_L115N_YY W29
3 IO_L116P_YY V26
3 IO_L116N_YY W27
3 IO_L117P W26
3 IO_VREF_L117N Y291
3 IO_L118P_YY W25
3 IO_L118N_YY Y30
3 IO_L119P_Y V244
3 IO_L119N_Y Y284
3 IO_L120P_YY AA30
3 IO_L120N_YY W24
3 IO_L121P AA29
3 IO_L121N V20
3 IO_L122P Y274
3 IO_L122N W234
3 IO_L123P_YY Y26
3 IO_D5_L123N_YY AB30
3 IO_D6_L124P_YY V21
3 IO_VREF_L124N_YY AA28
3 IO_L125P_YY Y25
3 IO_L125N_YY AA27
3 IO_L126P_YY W22
3 IO_L126N_YY Y23
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 107
3 IO_L127P_YY Y24
3 IO_VREF_L127N_YY AB28
3 IO_L128P_YY AC30
3 IO_L128N_YY AA25
3 IO_L129P W21
3 IO_L129N AA24
3 IO_L130P_YY AB26
3 IO_L130N_YY AD30
3 IO_L131P_YY Y22
3 IO_VREF_L131N_YY AC27
3 IO_L132P AD28
3 IO_L132N AB25
3 IO_L133P_YY AC26
3 IO_L133N_YY AE30
3 IO_L134P_YY AD27
3 IO_L134N_YY AF30
3 IO_L135P AF29
3 IO_VREF_L135N AB24
3 IO_L136P_YY AB23
3 IO_L136N_YY AE28
3 IO_L137P_Y AG303
3 IO_L137N_Y AC254
3 IO_L138P_YY AE26
3 IO_VREF_L138N_YY AG291
3 IO_L139P AH30
3 IO_L139N AC24
3 IO_L140P AF283
3 IO_L140N AD254
3 IO_D7_L141P_YY AH29
3 IO_INIT_L141N_YY AA22
4GCK0AJ16
4IOAB19
4
4IOAC16
4
4IOAC19
4IOAD18
4
4IOAD21
4
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
4IOAE15
4
4IOAE18
4
4IOAE21
4IOAE24
5
4IOAF17
5
4IOAF18
5
4IOAJ18
4
4IOAK18
4IOAK25
5
4IOAK27
4
4IOAH23
4
4IOAH24
5
4 IO_L142P_YY AF27
4 IO_L142N_YY AK28
4 IO_L143P_YY AG264
4 IO_L143N_YY AH273
4 IO_L144P AD23
4 IO_L144N AJ27
4 IO_VREF_L145P AB211
4 IO_L145N AF25
4 IO_L146P AC224
4 IO_L146N AH264
4 IO_L147P_YY AA21
4 IO_L147N_YY AG25
4 IO_VREF_L148P_YY AJ26
4 IO_L148N_YY AD22
4 IO_L149P AA20
4 IO_L149N AH25
4 IO_L150P AC21
4 IO_L150N AF24
4 IO_L151P_YY AG24
4 IO_L151N_YY AK26
4 IO_VREF_L152P_YY AJ24
4 IO_L152N_YY AF23
4 IO_L153P AE23
4 IO_L153N AB20
4 IO_L154P AC20
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
108 1-800-255-7778 Preliminary Product Specification
4 IO_L154N AG23
4 IO_L155P_YY AF22
4 IO_L155N_YY AE22
4 IO_VREF_L156P_YY AJ22
4 IO_L156N_YY AG22
4 IO_L157P AK244
4 IO_L157N AD203
4 IO_L158P_YY AA19
4 IO_L158N_YY AF21
4 IO_L159P AH224
4 IO_VREF_L159N AA18
4 IO_L160P AG21
4 IO_L160N AK23
4 IO_L161P_YY AH214
4 IO_L161N_YY AD194
4 IO_L162P AE20
4 IO_L162N AJ21
4 IO_L163P AG20
4 IO_L163N AF20
4 IO_L164P AC184
4 IO_L164N AF194
4 IO_L165P_YY AJ20
4 IO_L165N_YY AE19
4 IO_VREF_L166P_YY AK221
4 IO_L166N_YY AH20
4 IO_L167P AG19
4 IO_L167N AB17
4 IO_L168P AJ19
4 IO_L168N AD17
4 IO_L169P_YY AA16
4 IO_L169N_YY AA17
4 IO_VREF_L170P_YY AK21
4 IO_L170N_YY AB16
4 IO_L171P AG18
4 IO_L171N AK20
4 IO_L172P AK19
4 IO_L172N AD16
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
4 IO_L173P_YY AE16
4 IO_L173N_YY AE17
4 IO_VREF_L174P_YY AG17
4 IO_L174N_YY AJ17
4 IO_L175P AD154
4 IO_L175N AH173
4 IO_VREF_L176P_YY AG162
4 IO_L176N_YY AK17
4 IO_LVDS_DLL_L177P AF16
5GCK1AK16
5IOAA11
4
5IOAA14
4
5IOAD14
4
5IOAE7
5
5IOAE8
5
5IOAE10
4
5IOAF6
4
5IOAF10
4
5IOAG9
4
5IOAG12
4
5IOAG14
5
5IOAH8
4
5IOAK6
5
5IOAK14
5
5IOAJ13
4
5IOAJ15
4
5 IO_LVDS_DLL_L177N AH16
5 IO_L178P_YY AC154
5 IO_VREF_L178N_YY AG152,3
5 IO_L179P_YY AB15
5 IO_L179N_YY AF15
5 IO_L180P_YY AA15
5 IO_VREF_L180N_YY AF14
5 IO_L181P_YY AH15
5 IO_L181N_YY AK15
5 IO_L182P AB14
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 109
5 IO_L182N AF13
5 IO_L183P AH14
5 IO_L183N AJ14
5 IO_L184P_YY AE14
5 IO_VREF_L184N_YY AG13
5 IO_L185P_YY AK13
5 IO_L185N_YY AD13
5 IO_L186P AE13
5 IO_L186N AF12
5 IO_L187P AC13
5 IO_L187N AA13
5 IO_L188P_YY AA12
5 IO_VREF_L188N_YY AJ121
5 IO_L189P_YY AB12
5 IO_L189N_YY AE11
5 IO_L190P AK124
5 IO_L190N Y134
5 IO_L191P AG11
5 IO_L191N AF11
5 IO_L192P AH11
5 IO_L192N AJ11
5 IO_L193P_YY AE124
5 IO_L193N_YY AG104
5 IO_L194P_YY AD12
5 IO_L194N_YY AK11
5 IO_L195P_YY AJ10
5 IO_VREF_L195N_YY AC12
5 IO_L196P_YY AK10
5 IO_L196N_YY AD11
5 IO_L197P_YY AJ9
5 IO_L197N_YY AE9
5 IO_L198P_YY AH10
5 IO_VREF_L198N_YY AF9
5 IO_L199P_YY AH9
5 IO_L199N_YY AK9
5 IO_L200P AF8
5 IO_L200N AB11
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
5 IO_L201P AC11
5 IO_L201N AG8
5 IO_L202P_YY AK8
5 IO_VREF_L202N_YY AF7
5 IO_L203P_YY AG7
5 IO_L203N_YY AK7
5 IO_L204P AJ7
5 IO_L204N AD10
5 IO_L205P AH6
5 IO_L205N AC10
5 IO_L206P_YY AD9
5 IO_VREF_L206N_YY AG6
5 IO_L207P_YY AB10
5 IO_L207N_YY AJ5
5 IO_L208P AD84
5 IO_L208N AK54
5 IO_L209P AC9
5 IO_VREF_L209N AJ41
5 IO_L210P AG5
5 IO_L210N AK4
5 IO_L211P_YY AH53
5 IO_L211N_YY AG34
6IOT2
4
6IOT10
4
6IO U1
6IOU4
5
6IOU6
4
6IOU7
4
6IOV1
4
6IOV5
5
6IO V8
6IOY10
4
6IOAA4
4
6IOAB5
5
6IOAB7
4
6IOAC3
5
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
110 1-800-255-7778 Preliminary Product Specification
6IOAC5
4
6IOAD1
4
6IOAE5
5
6 IO_L212N_YY AF3
6 IO_L212P_YY AC6
6 IO_L213N AH24
6 IO_L213P AG23
6 IO_L214N AB9
6 IO_L214P AE4
6 IO_VREF_L215N_YY AE31
6 IO_L215P_YY AH1
6 IO_L216N_Y AB84
6 IO_L216P_Y AD63
6 IO_L217N_YY AG1
6 IO_L217P_YY AA10
6 IO_VREF_L218N AA9
6 IO_L218P AD4
6 IO_L219N_YY AD5
6 IO_L219P_YY AD2
6 IO_L220N_YY AD3
6 IO_L220P_YY AF2
6 IO_L221N AA8
6 IO_L221P AA7
6 IO_VREF_L222N_YY AF1
6 IO_L222P_YY Y9
6 IO_L223N_YY AB6
6 IO_L223P_YY AC4
6 IO_L224N AE1
6 IO_L224P W8
6 IO_L225N_YY Y8
6 IO_L225P_YY AB4
6 IO_VREF_L226N_YY AB3
6 IO_L226P_YY W9
6 IO_L227N_YY AA54
6 IO_L227P_YY W103
6 IO_L228N_YY AB1
6 IO_L228P_YY V10
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
6 IO_L229N_YY Y74
6 IO_VREF_L229P_YY AC1
6 IO_L230N V11
6 IO_L230P AA3
6 IO_L231N_YY AA23
6 IO_L231P_YY U104
6 IO_L232N W7
6 IO_L232P AA6
6 IO_L233N_YY Y6
6 IO_L233P_YY Y4
6 IO_L234N_Y AA14
6 IO_L234P_Y V74
6 IO_L235N_YY Y3
6 IO_L235P_YY Y2
6 IO_VREF_L236N Y51
6 IO_L236P W5
6 IO_L237N_YY W4
6 IO_L237P_YY W6
6 IO_L238N_YY V6
6 IO_L238P_YY W2
6 IO_L239N U9
6 IO_L239P V4
6 IO_VREF_L240N_YY AB2
6 IO_L240P_YY T8
6 IO_L241N_YY U5
6 IO_L241P_YY W1
6 IO_L242N Y1
6 IO_L242P T9
6 IO_L243N_YY T7
6 IO_L243P_YY U3
6 IO_VREF_L244N_YY T5
6 IO_L244P_YY V2
6 IO_L245N_YY R94
6 IO_L245P_YY T63
6 IO_VREF_L246N_YY T42
6 IO_L246P_YY U2
6 IO_L247N T1
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 111
7IO E3
7IOF1
4
7IOG1
5
7IOG4
5
7IOH3
5
7IOJ1
4
7IOJ3
4
7IOJ4
4
7IOJ6
4
7IOL10
4
7ION2
4
7ION8
4
7ION10
4
7IOP3
5
7IOP9
4
7IOR1
5
7IOT3
4
7 IO_L247P R10
7 IO_L248N_YY R53
7 IO_L248P_YY R64
7 IO_L249N_YY R8
7 IO_VREF_L249P_YY R42
7 IO_L250N_YY R7
7 IO_L250P_YY R3
7 IO_L251N_YY P10
7 IO_VREF_L251P_YY P6
7 IO_L252N_YY P5
7 IO_L252P_YY P2
7 IO_L253N P7
7 IO_L253P P4
7 IO_L254N_YY N4
7 IO_L254P_YY R2
7 IO_L255N_YY N7
7 IO_VREF_L255P_YY P1
7 IO_L256N M6
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
7 IO_L256P N6
7 IO_L257N_YY N5
7 IO_L257P_YY N1
7 IO_L258N_YY M4
7 IO_L258P_YY M5
7 IO_L259N M2
7 IO_VREF_L259P M11
7 IO_L260N_YY L4
7 IO_L260P_YY L2
7 IO_L261N_Y M74
7 IO_L261P_Y L54
7 IO_L262N_YY L1
7 IO_L262P_YY M8
7 IO_L263N K2
7 IO_L263P M9
7 IO_L264N L34
7 IO_L264P M104
7 IO_L265N_YY K5
7 IO_L265P_YY K1
7 IO_L266N_YY L6
7 IO_VREF_L266P_YY K3
7 IO_L267N_YY L7
7 IO_L267P_YY K4
7 IO_L268N_YY L8
7 IO_L268P_YY J5
7 IO_L269N_YY K6
7 IO_VREF_L269P_YY H4
7 IO_L270N_YY H1
7 IO_L270P_YY K7
7 IO_L271N J7
7 IO_L271P J2
7 IO_L272N_YY H5
7 IO_L272P_YY G2
7 IO_L273N_YY L9
7 IO_VREF_L273P_YY G5
7 IO_L274N F3
7 IO_L274P K8
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
112 1-800-255-7778 Preliminary Product Specification
7 IO_L275N_YY G3
7 IO_L275P_YY E1
7 IO_L276N_YY H6
7 IO_L276P_YY E2
7 IO_L277N E4
7 IO_VREF_L277P K9
7 IO_L278N_YY J8
7 IO_L278P_YY F4
7 IO_L279N_Y D13
7 IO_L279P_Y H74
7 IO_L280N_YY G6
7 IO_VREF_L280P_YY C21
7 IO_L281N D2
7 IO_L281P F5
7 IO_L282N_YY D34
7 IO_L282P_YY K103
2 CCLK F26
3DONEAJ28
NA DXN AJ3
NA DXP AH4
NA M0 AF4
NA M1 AC7
NA M2 AK3
NA PROGRAM AG28
NA TCK B3
NA TDI H22
2 TDO D26
NA TMS C1
NA VCCINT L11
NA VCCINT L12
NA VCCINT L19
NA VCCINT L20
NA VCCINT M11
NA VCCINT M12
NA VCCINT M19
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
NA VCCINT M20
NA VCCINT N13
NA VCCINT N14
NA VCCINT N15
NA VCCINT N16
NA VCCINT N17
NA VCCINT N18
NA VCCINT P13
NA VCCINT P18
NA VCCINT R13
NA VCCINT R18
NA VCCINT T13
NA VCCINT T18
NA VCCINT U13
NA VCCINT U18
NA VCCINT V13
NA VCCINT V14
NA VCCINT V15
NA VCCINT V16
NA VCCINT V17
NA VCCINT V18
NA VCCINT W11
NA VCCINT W12
NA VCCINT W19
NA VCCINT W20
NA VCCINT Y11
NA VCCINT Y12
NA VCCINT Y19
NA VCCINT Y20
NA VCCO_0 B6
NA VCCO_0 M15
NA VCCO_0 M14
NA VCCO_0 L15
NA VCCO_0 L14
NA VCCO_0 H14
NA VCCO_0 M13
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 113
NA VCCO_0 C12
NA VCCO_1 B25
NA VCCO_1 C19
NA VCCO_1 M18
NA VCCO_1 M17
NA VCCO_1 L17
NA VCCO_1 H17
NA VCCO_1 L16
NA VCCO_1 M16
NA VCCO_2 F29
NA VCCO_2 M28
NA VCCO_2 P23
NA VCCO_2 R20
NA VCCO_2 P20
NA VCCO_2 R19
NA VCCO_2 N19
NA VCCO_2 P19
NA VCCO_3 AE29
NA VCCO_3 W28
NA VCCO_3 U23
NA VCCO_3 U20
NA VCCO_3 T20
NA VCCO_3 V19
NA VCCO_3 T19
NA VCCO_3 U19
NA VCCO_4 AJ25
NA VCCO_4 AH19
NA VCCO_4 W18
NA VCCO_4 AC17
NA VCCO_4 Y17
NA VCCO_4 W17
NA VCCO_4 W16
NA VCCO_4 Y16
NA VCCO_5 AJ6
NA VCCO_5 Y15
NA VCCO_5 W15
NA VCCO_5 AC14
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
NA VCCO_5 Y14
NA VCCO_5 W14
NA VCCO_5 W13
NA VCCO_5 AH12
NA VCCO_6 AE2
NA VCCO_6 V12
NA VCCO_6 U12
NA VCCO_6 T12
NA VCCO_6 U11
NA VCCO_6 T11
NA VCCO_6 U8
NA VCCO_6 W3
NA VCCO_7 F2
NA VCCO_7 R12
NA VCCO_7 P12
NA VCCO_7 N12
NA VCCO_7 R11
NA VCCO_7 P11
NA VCCO_7 P8
NA VCCO_7 M3
NA GND Y18
NA GND AH7
NA GND AK30
NA GND AJ30
NA GND B30
NA GND A30
NA GND AK29
NA GND AJ29
NA GND AC29
NA GND H29
NA GND B29
NA GND A29
NA GND AH28
NA GND V28
NA GND N28
NA GND C28
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
114 1-800-255-7778 Preliminary Product Specification
NA GND AG27
NA GND D27
NA GND AF26
NA GND E26
NA GND F25
NA GND AE25
NA GND G24
NA GND AJ23
NA GND AD24
NA GND H23
NA GND B23
NA GND AC23
NA GND AB22
NA GND V22
NA GND N22
NA GND AH18
NA GND AB18
NA GND J18
NA GND C18
NA GND U17
NA GND T17
NA GND R17
NA GND P17
NA GND U16
NA GND T16
NA GND R16
NA GND P16
NA GND U15
NA GND T15
NA GND R15
NA GND P15
NA GND U14
NA GND T14
NA GND R14
NA GND P14
NA GND AH13
NA GND AB13
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
NA GND J13
NA GND C13
NA GND V9
NA GND N9
NA GND J9
NA GND AJ8
NA GND AC8
NA GND H8
NA GND AD7
NA GND B8
NA GND AE6
NA GND G7
NA GND F6
NA GND AF5
NA GND E5
NA GND AG4
NA GND D4
NA GND V3
NA GND N3
NA GND C3
NA GND AK2
NA GND AH3
NA GND AC2
NA GND H2
NA GND B2
NA GND A2
NA GND AK1
NA GND AJ2
NA GND AJ1
NA GND A1
NA GND B1
Notes:
1. VREF or I/O option only in the XCV1000E and XCV1600E;
otherwise, I/O option only.
2. VREF or I/O option only in the XCV1600E; otherwise, I/O
option only.
3. I/O option only in the XCV600E.
4. No Connect in the XCV600E.
5. No Connect in the XCV600E, 1000E.
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 115
FG900 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
Ö
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
GCLK LVDS
3 0 C15 A15 NA IO_DLL_ 34N
2 1 E15 E16 NA IO_DLL_ 34P
1 5 AK16 AH16 NA IO_DLL_ 177N
0 4 AJ16 AF16 NA IO_DLL_ 177P
IO LVDS
Total Pairs: 283, Asynchronous Output Pairs: 168
00F7C44 -
10G8D52 -
20H9A32 VREF
30J10B42 -
40D6A4
Ö
-
50B5E7
Ö
VREF
60F8A51 -
70N11D71 -
80E8G9
Ö
-
90J11A6
Ö
VREF
10 0 B7 C7 2 -
11 0 H10 C8 2 -
12 0 F10 G10
Ö
-
13 0 H11 A8
Ö
VREF
14 0 C9 D9 NA -
15 0 J12 B9 4 -
16 0 A9 E10 NA VREF
17 0 B10 G11 NA -
18 0 C10 H12 4 -
19 0 F11 H13 2 -
20 0 D11 E11 2 -
21 0 G12 B11 2 -
22 0 C11 F12
Ö
-
23 0 D12 A10
Ö
VREF
24 0 A11 E12 1 -
25 0 B12 G13 1 -
26 0 K13 A12
Ö
-
27 0 B13 F13
Ö
VREF
28 0 E13 G14 2 -
29 0 B14 D14 2 -
30 0 J14 A14
Ö
-
31 0 J15 K14
Ö
VREF
32 0 H15 B15 NA -
33 0 D15 F15
Ö
VREF
34 1 E16 A15 NA IO_ LVDS_DLL
35 1 F16 B16 4 VREF
36 1 H16 A16 4 -
37 1 K15 C16
Ö
VREF
38 1 G16 K16
Ö
-
39 1 E17 A17 2 -
40 1 C17 F17 2 -
41 1 A18 E18
Ö
VREF
42 1 A19 D18
Ö
-
43 1 G18 B19 1 -
44 1 H18 D19 1 -
45 1 F19 F18
Ö
VREF
46 1 K17 B20
Ö
-
47 1 A20 D20 2 -
48 1 C20 G19 2 -
49 1 E20 K18 2 -
50 1 D21 B21 4 -
51 1 A21 F20
Ö
-
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
116 1-800-255-7778 Preliminary Product Specification
52 1 A22 C21
Ö
VREF
53 1 B22 H19 4 -
54 1 D22 E21 4 -
55 1 C22 F21
Ö
VREF
56 1 E22 H20
Ö
-
57 1 A23 G21 2 -
58 1 K19 A24 2 -
59 1 B24 C24
Ö
VREF
60 1 G22 H21
Ö
-
61 1 C25 E23 1 -
62 1 A26 D24 1 -
63 1 K20 B26
Ö
VREF
64 1 J21 D25
Ö
-
65 1 F23 C26 2 -
66 1 G23 B27 2 VREF
67 1 F24 A27 2 -
68 1 A28 B28 4 -
69 1 C27 K21
Ö
CS
70 2 J22 E27
Ö
DIN, D0
71 2 C29 D28 NA -
72 2 G25 E25 1 -
73 2 E28 C30 4 VREF
74 2 K22 F27 3 -
75 2 D30 J23 4 -
76 2 L21 F28 1 VREF
77 2 G28 E30
Ö
-
78 2 G27 E29 4 -
79 2 K23 H26 1 -
80 2 F30 L22
Ö
VREF
81 2 H27 G29
Ö
-
82 2 G30 M21 2 -
83 2 J24 J26 4 -
84 2 H30 L23 4 VREF
85 2 K26 J28 4 -
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
86 2 J29 K24 4 -
87 2 K27 J30 4 VREF
88 2 M22 K29 NA D2
89 2 K28 L25 4 -
90 2 N21 K25 1 -
91 2 L24 L27 4 -
92 2 L29 M23 3 -
93 2 L26 L28 4 -
94 2 L30 M27 1 VREF
95 2 M26 M29
Ö
-
96 2 N29 M30 4 -
97 2 N25 N27 1 -
98 2 N30 P21
Ö
D3
99 2 N26 P28
Ö
-
100 2 P29 N24 2 -
101 2 P22 R26
Ö
-
102 2 P25 R29 4 VREF
103 2 R21 R28 4 -
104 2 R25 T30 4 VREF
105 2 P24 R27 4 -
106 3 R24 U29 NA
107 3 R22 T27 4 VREF
108 3 R23 T28 4 -
109 3 T21 T25 4 VREF
110 3 U28 U30 4 -
111 3 T23 U27 2 -
112 3 U25 V27
Ö
-
113 3 U24 V29
Ö
VREF
114 3 W30 U22 1 -
115 3 U21 W29 4 -
116 3 V26 W27
Ö
-
117 3 W26 Y29 1 VREF
118 3 W25 Y30 4 -
119 3 V24 Y28 3 -
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 117
120 3 AA30 W24 4 -
121 3 AA29 V20 1 -
122 3 Y27 W23 NA -
123 3 Y26 AB30
Ö
D5
124 3 V21 AA28
Ö
VREF
125 3 Y25 AA27 4 -
126 3 W22 Y23 4 -
127 3 Y24 AB28 4 VREF
128 3 AC30 AA25
Ö
-
129 3 W21 AA24 2 -
130 3 AB26 AD30
Ö
-
131 3 Y22 AC27
Ö
VREF
132 3 AD28 AB25 2 -
133 3 AC26 AE30 4 -
134 3 AD27 AF30
Ö
-
135 3 AF29 AB24 1 VREF
136 3 AB23 AE28 4 -
137 3 AG30 AC25 3 -
138 3 AE26 AG29 4 VREF
139 3 AH30 AC24 1 -
140 3 AF28 AD25 NA -
141 3 AH29 AA22
Ö
INIT
142 4 AF27 AK28
Ö
-
143 4 AG26 AH27 4 -
144 4 AD23 AJ27 2 -
145 4 AB21 AF25 2 VREF
146 4 AC22 AH26 2 -
147 4 AA21 AG25
Ö
-
148 4 AJ26 AD22
Ö
VREF
149 4 AA20 AH25 1 -
150 4 AC21 AF24 1 -
151 4 AG24 AK26
Ö
-
152 4 AJ24 AF23
Ö
VREF
153 4 AE23 AB20 2 -
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
154 4 AC20 AG23 2 -
155 4 AF22 AE22
Ö
-
156 4 AJ22 AG22
Ö
VREF
157 4 AK24 AD20 NA -
158 4 AA19 AF21 4 -
159 4 AH22 AA18 NA VREF
160 4 AG21 AK23 NA -
161 4 AH21 AD19 4 -
162 4 AE20 AJ21 2 -
163 4 AG20 AF20 2 -
164 4 AC18 AF19 2 -
165 4 AJ20 AE19
Ö
-
166 4 AK22 AH20
Ö
VREF
167 4 AG19 AB17 1 -
168 4 AJ19 AD17 1 -
169 4 AA16 AA17
Ö
-
170 4 AK21 AB16
Ö
VREF
171 4 AG18 AK20 2 -
172 4 AK19 AD16 2 -
173 4 AE16 AE17
Ö
-
174 4 AG17 AJ17
Ö
VREF
175 4 AD15 AH17 NA -
176 4 AG16 AK17 4 VREF
177 5 AF16 AH16 NA IO_ LVDS_DLL
178 5 AC15 AG15 4 VREF
179 5 AB15 AF15
Ö
-
180 5 AA15 AF14
Ö
VREF
181 5 AH15 AK15
Ö
-
182 5 AB14 AF13 2 -
183 5 AH14 AJ14 2 -
184 5 AE14 AG13
Ö
VREF
185 5 AK13 AD13
Ö
-
186 5 AE13 AF12 1 -
187 5 AC13 AA13 1 -
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
118 1-800-255-7778 Preliminary Product Specification
188 5 AA12 AJ12
Ö
VREF
189 5 AB12 AE11
Ö
-
190 5 AK12 Y13 2 -
191 5 AG11 AF11 2 -
192 5 AH11 AJ11 2 -
193 5 AE12 AG10 4 -
194 5 AD12 AK11
Ö
-
195 5 AJ10 AC12
Ö
VREF
196 5 AK10 AD11 4 -
197 5 AJ9 AE9 4 -
198 5 AH10 AF9
Ö
VREF
199 5 AH9 AK9
Ö
-
200 5 AF8 AB11 2 -
201 5 AC11 AG8 2 -
202 5 AK8 AF7
Ö
VREF
203 5 AG7 AK7
Ö
-
204 5 AJ7 AD10 1 -
205 5 AH6 AC10 1 -
206 5 AD9 AG6
Ö
VREF
207 5 AB10 AJ5
Ö
-
208 5 AD8 AK5 2 -
209 5 AC9 AJ4 2 VREF
210 5 AG5 AK4 2 -
211 5 AH5 AG3 4 -
212 6 AC6 AF3
Ö
-
213 6 AG2 AH2 NA -
214 6 AE4 AB9 1 -
215 6 AH1 AE3 4 VREF
216 6 AD6 AB8 3 -
217 6 AA10 AG1 4 -
218 6 AD4 AA9 1 VREF
219 6 AD2 AD5
Ö
-
220 6 AF2 AD3 4 -
221 6 AA7 AA8 1 -
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
222 6 Y9 AF1
Ö
VREF
223 6 AC4 AB6
Ö
-
224 6 W8 AE1 2 -
225 6 AB4 Y8 4 -
226 6 W9 AB3 4 VREF
227 6 W10 AA5 4 -
228 6 V10 AB1 4 -
229 6 AC1 Y7 4 VREF
230 6 AA3 V11 NA -
231 6 U10 AA2 4 -
232 6 AA6 W7 1 -
233 6 Y4 Y6 4 -
234 6 V7 AA1 3 -
235 6 Y2 Y3 4 -
236 6 W5 Y5 1 VREF
237 6 W6 W4
Ö
-
238 6 W2 V6 4 -
239 6 V4 U9 1 -
240 6 T8 AB2
Ö
VREF
241 6 W1 U5
Ö
-
242 6 T9 Y1 2 -
243 6 U3 T7 4 -
244 6 V2 T5 4 VREF
245 6 T6 R9 4 -
246 6 U2 T4 4 VREF
247 7 R10 T1 NA
248 7 R6 R5 4 -
249 7 R4 R8 4 VREF
250 7 R3 R7 4 -
251 7 P6 P10 4 VREF
252 7 P2 P5 4 -
253 7 P4 P7 2 -
254 7 R2 N4
Ö
-
255 7 P1 N7
Ö
VREF
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 119
FG1156 Fine-Pitch Ball Grid Array Package
XCV1000E, XCV1600E, XCV2000E, XCV2600E, and
XCV3200E devices in the FG1156 fine-pitch Ball Grid Array
package have footprint compatibility. Pins labeled IO_VREF
can be used as either VREF or general I/O, unless indicated
in the footnotes. If the pin is not used as VREF
, it can be used
as general I/O. Immediately following Table 28, see
Table 29 for Differential Pair information.
256 7 N6 M6 1 -
257 7 N1 N5 4 -
258 7 M5 M4
Ö
-
259 7 M1 M2 1 VREF
260 7 L2 L4 4 -
261 7 L5 M7 3 -
262 7 M8 L1 4 -
263 7 M9 K2 1 -
264 7 M10 L3 NA -
265 7 K1 K5
Ö
-
266 7 K3 L6
Ö
VREF
267 7 K4 L7 4 -
268 7 J5 L8 4 -
269 7 H4 K6 4 VREF
270 7 K7 H1 4 -
271 7 J2 J7 2 -
272 7 G2 H5
Ö
-
273 7 G5 L9
Ö
VREF
274 7 K8 F3 1 -
275 7 E1 G3 4 -
276 7 E2 H6
Ö
-
277 7 K9 E4 1 VREF
278 7 F4 J8 4 -
279 7 H7 D1 3 -
280 7 C2 G6 4 VREF
281 7 F5 D2 1 -
282 7 K10 D3 4 -
Notes:
1. AO in the XCV600E, 1000E.
2. AO in the XCV1000E.
3. AO in the XCV1600E.
4. AO in the XCV1000E, XCV1600E.
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
0GCK3E17
0IO B4
0IO B9
0IOB10
0IOD9
3
0IOD16
0IOE7
3
0IOE11
3
0IOE13
3
0IOE16
3
0IOF17
3
0IOJ12
3
0IOJ13
3
0IOJ14
3
0IOK11
3
0 IO_L0N_Y F7
0IO_L0P_Y H9
0 IO_L1N_Y C5
0IO_L1P_YJ10
0 IO_VREF_L2N_Y E6
0IO_L2P_Y D6
0 IO_L3N_Y A4
0IO_L3P_Y G8
0 IO_L4N_YY C6
0IO_L4P_YYJ11
0 IO_VREF_L5N_YY G9
0IO_L5P_YY F8
0 IO_L6N_YY A54
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
120 1-800-255-7778 Preliminary Product Specification
0IO_L6P_YYH10
5
0 IO_L7N_Y D7
0 IO_L7P_Y B5
0 IO_L8N_Y K12
0 IO_L8P_Y E8
0 IO_L9N B64
0 IO_L9P F95
0 IO_L10N_YY G10
0 IO_L10P_YY C7
0 IO_VREF_L11N_YY D8
0 IO_L11P_YY B7
0 IO_L12N H114
0 IO_L12P C85
0 IO_L13N_Y E9
0 IO_L13P_Y B8
0 IO_VREF_L14N_Y K132
0 IO_L14P_Y G11
0 IO_L15N A84
0 IO_L15P F105
0 IO_L16N_YY C9
0 IO_L16P_YY H12
0 IO_VREF_L17N_YY D10
0 IO_L17P_YY A9
0 IO_L18N_Y F11
0 IO_L18P_Y A10
0 IO_L19N_Y K14
0 IO_L19P_Y C10
0 IO_VREF_L20N_YY H13
0 IO_L20P_YY G12
0 IO_L21N_YY A11
0 IO_L21P_YY B11
0 IO_L22N_Y E12
0 IO_L22P_Y D11
0 IO_L23N_Y G13
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
0 IO_L23P_Y C12
0 IO_L24N_Y K15
0 IO_L24P_Y A12
0 IO_L25N_Y B12
0 IO_L25P_Y H14
0 IO_L26N_YY D12
0 IO_L26P_YY F13
0 IO_VREF_L27N_YY A13
0 IO_L27P_YY B13
0 IO_L28N_YY J154
0 IO_L28P_YY G145
0 IO_L29N_Y C13
0 IO_L29P_Y F14
0 IO_L30N_Y H15
0 IO_L30P_Y D13
0 IO_L31N A144
0 IO_L31P K165
0 IO_L32N_YY E14
0 IO_L32P_YY B14
0 IO_VREF_L33N_YY G15
0 IO_L33P_YY D14
0 IO_L34N J164
0 IO_L34P D155
0 IO_L35N_Y F15
0 IO_L35P_Y B15
0 IO_L36N_Y A15
0 IO_L36P_Y E15
0 IO_L37N G164
0 IO_L37P A165
0 IO_L38N_YY F16
0 IO_L38P_YY J17
0 IO_VREF_L39N_YY C16
0 IO_L39P_YY B16
0 IO_L40N_Y H17
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 121
0 IO_L40P_Y A17
0 IO_VREF_L41N_Y G171
0 IO_L41P_Y B17
0 IO_LVDS_DLL_L42N C17
1GCK2D17
1IOA18
1IOB18
3
1IOB24
1IOB25
1IOE22
3
1IOE23
3
1IOD18
3
1IOD19
1IOD25
3
1IOD26
3
1IOD28
3
1IOD29
3
1IOG23
3
1IOJ23
3
1 IO_LVDS_DLL_L42P J18
1 IO_L43N_Y G18
1 IO_VREF_L43P_Y C181
1 IO_L44N_Y H18
1 IO_L44P_Y F18
1 IO_L45N_YY B19
1 IO_VREF_L45P_YY A19
1 IO_L46N_YY K19
1 IO_L46P_YY C19
1 IO_L47N F195
1 IO_L47P E194
1 IO_L48N_Y G19
1 IO_L48P_Y J19
1 IO_L49N_Y A20
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
1 IO_L49P_Y G20
1 IO_L50N B205
1 IO_L50P F204
1 IO_L51N_YY D20
1 IO_VREF_L51P_YY E20
1 IO_L52N_YY H20
1 IO_L52P_YY A21
1 IO_L53N E215
1 IO_L53P J204
1 IO_L54N_Y D21
1 IO_L54P_Y K20
1 IO_L55N_Y B21
1 IO_L55P_Y H21
1 IO_L56N_YY G215
1 IO_L56P_YY F214
1 IO_L57N_YY A22
1 IO_VREF_L57P_YY B22
1 IO_L58N_YY J21
1 IO_L58P_YY C22
1 IO_L59N_Y D22
1 IO_L59P_Y G22
1 IO_L60N_Y K21
1 IO_L60P_Y A23
1 IO_L61N_Y F22
1 IO_L61P_Y B23
1 IO_L62N_Y C23
1 IO_L62P_Y H22
1 IO_L63N_YY D23
1 IO_L63P_YY K22
1 IO_L64N_YY A24
1 IO_VREF_L64P_YY J22
1 IO_L65N_Y H23
1 IO_L65P_Y D24
1 IO_L66N_Y A25
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
122 1-800-255-7778 Preliminary Product Specification
1 IO_L66P_Y E24
1 IO_L67N_YY A26
1 IO_VREF_L67P_YY C25
1 IO_L68N_YY F24
1 IO_L68P_YY B26
1 IO_L69N K235
1 IO_L69P F254
1 IO_L70N_Y C26
1 IO_VREF_L70P_Y H242
1 IO_L71N_Y G24
1 IO_L71P_Y A27
1 IO_L72N B275
1 IO_L72P G254
1 IO_L73N_YY E26
1 IO_VREF_L73P_YY C27
1 IO_L74N_YY J24
1 IO_L74P_YY B28
1 IO_L75N K245
1 IO_L75P H254
1 IO_L76N_Y D27
1 IO_L76P_Y F26
1 IO_L77N_Y G26
1 IO_L77P_Y C28
1 IO_L78N_YY E275
1 IO_L78P_YY J254
1 IO_L79N_YY A30
1 IO_VREF_L79P_YY H26
1 IO_L80N_YY G27
1 IO_L80P_YY B29
1 IO_L81N_Y F27
1 IO_L81P_Y C29
1 IO_L82N_Y E28
1 IO_VREF_L82P_Y F28
1 IO_L83N_Y L25
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
1 IO_L83P_Y B30
1 IO_L84N B31
1 IO_L84P E29
1 IO_WRITE_L85N_YY A31
1 IO_CS_L85P_YY D30
2IOF31
3
2IOJ32
2IOK27
3
2IOK31
3
2 IO L283
2 IO L303
2IOM32
3
2ION26
2ION28
3
2IOP25
3
2IOU26
3
2IOU30
2IOU32
3
2IOU34
2IO_D2M30
2 IO_DOUT_BUSY_L86P_YY D32
2 IO_DIN_D0_L86N_YY J27
2 IO_L87P_Y E31
2 IO_L87N_Y F30
2 IO_L88P_Y G29
2 IO_L88N_Y F32
2 IO_VREF_L89P_Y E32
2 IO_L89N_Y G30
2 IO_L90P M25
2 IO_L90N G31
2 IO_L91P_Y L26
2 IO_L91N_Y D33
2 IO_VREF_L92P_Y D34
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 123
2 IO_L92N_Y H29
2 IO_L93P_YY J284
2 IO_L93N_YY E335
2 IO_L94P_YY H28
2 IO_L94N_YY H30
2 IO_L95P_Y H32
2 IO_L95N_Y K28
2 IO_L96P_Y L274
2 IO_L96N_Y F335
2 IO_L97P_Y M26
2 IO_L97N_Y E34
2 IO_VREF_L98P_YY H31
2 IO_L98N_YY G32
2 IO_L99P_YY N254
2 IO_L99N_YY J315
2 IO_L100P_YY J30
2 IO_L100N_YY G33
2 IO_VREF_L101P_Y H342
2 IO_L101N_Y J29
2 IO_L102P M274
2 IO_L102N H335
2 IO_L103P_Y K29
2 IO_L103N_Y J34
2 IO_VREF_L104P_YY L29
2 IO_L104N_YY J33
2 IO_L105P_YY M28
2 IO_L105N_YY K34
2 IO_L106P_Y N27
2 IO_L106N_Y L34
2 IO_VREF_L107P_YY K33
2 IO_D1_L107N_YY P26
2 IO_L108P_Y R25
2 IO_L108N_Y M34
2 IO_L109P_Y L31
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
2 IO_L109N_Y L33
2 IO_L110P_Y P27
2 IO_L110N_Y M33
2 IO_L111P M31
2 IO_L111N R26
2 IO_L112P_Y N30
2 IO_L112N_Y P28
2 IO_VREF_L113P_Y N29
2 IO_L113N_Y N33
2 IO_L114P_YY T254
2 IO_L114N_YY N345
2 IO_L115P_YY P34
2 IO_L115N_YY R27
2 IO_L116P_Y P29
2 IO_L116N_Y P31
2 IO_L117P_Y P334
2 IO_L117N_Y T265
2 IO_L118P_Y R34
2 IO_L118N_Y R28
2 IO_VREF_L119P_YY N31
2 IO_D3_L119N_YY N32
2 IO_L120P_YY P304
2 IO_L120N_YY R335
2 IO_L121P_YY R29
2 IO_L121N_YY T34
2 IO_L122P_Y R30
2 IO_L122N_Y T30
2 IO_L123P T284
2 IO_L123N R315
2 IO_L124P_Y T29
2 IO_L124N_Y U27
2 IO_VREF_L125P_YY T31
2 IO_L125N_YY T33
2 IO_L126P_YY U28
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
124 1-800-255-7778 Preliminary Product Specification
2 IO_L126N_YY T32
2 IO_VREF_L127P_Y U291
2 IO_L127N_Y U33
2 IO_L128P_YY V33
2 IO_L128N_YY U31
3IOV27
3
3IOV31
3IOV32
3
3IOW33
3IOAB25
3
3IOAB26
3
3IOAB31
3
3IOAC31
3
3IOAF34
3IOAG31
3
3IOAG33
3
3IOAG34
3IOAH29
3
3IOAJ30
3
3 IO_L129P_Y V26
3 IO_VREF_L129N_Y V301
3 IO_L130P_YY W34
3 IO_L130N_YY V28
3 IO_L131P_YY W32
3 IO_VREF_L131N_YY W30
3 IO_L132P_Y V29
3 IO_L132N_Y Y34
3 IO_L133P W295
3 IO_L133N Y334
3 IO_L134P_Y W26
3 IO_L134N_Y W28
3 IO_L135P_YY Y31
3 IO_L135N_YY Y30
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
3 IO_L136P_YY AA345
3 IO_L136N_YY W314
3 IO_D4_L137P_YY AA33
3 IO_VREF_L137N_YY Y29
3 IO_L138P_Y W25
3 IO_L138N_Y AB34
3 IO_L139P_Y Y285
3 IO_L139N_Y AB334
3 IO_L140P_Y AA30
3 IO_L140N_Y Y26
3 IO_L141P_YY Y27
3 IO_L141N_YY AA31
3 IO_L142P_YY AA275
3 IO_L142N_YY AA294
3 IO_L143P_Y AB32
3 IO_VREF_L143N_Y AB29
3 IO_L144P_Y AA28
3 IO_L144N_Y AC34
3 IO_L145P Y25
3 IO_L145N AD34
3 IO_L146P_Y AB30
3 IO_L146N_Y AC33
3 IO_L147P_Y AA26
3 IO_L147N_Y AC32
3 IO_L148P_Y AD33
3 IO_L148N_Y AB28
3 IO_L149P_YY AE34
3 IO_D5_L149N_YY AB27
3 IO_D6_L150P_YY AE33
3 IO_VREF_L150N_YY AC30
3 IO_L151P_Y AA25
3 IO_L151N_Y AE32
3 IO_L152P_YY AE31
3 IO_L152N_YY AD29
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 125
3 IO_L153P_YY AD31
3 IO_VREF_L153N_YY AF33
3 IO_L154P_Y AC28
3 IO_L154N_Y AF31
3 IO_L155P_Y AC275
3 IO_L155N_Y AF324
3 IO_L156P_Y AE29
3 IO_VREF_L156N_Y AD282
3 IO_L157P_YY AD30
3 IO_L157N_YY AG32
3 IO_L158P_YY AC265
3 IO_L158N_YY AH334
3 IO_L159P_YY AD26
3 IO_VREF_L159N_YY AF30
3 IO_L160P_Y AC25
3 IO_L160N_Y AH32
3 IO_L161P_Y AE285
3 IO_L161N_Y AL344
3 IO_L162P_Y AG30
3 IO_L162N_Y AD27
3 IO_L163P_YY AF29
3 IO_L163N_YY AK34
3 IO_L164P_YY AD255
3 IO_L164N_YY AE274
3 IO_L165P_Y AJ33
3 IO_VREF_L165N_Y AH31
3 IO_L166P_Y AE26
3 IO_L166N_Y AL33
3 IO_L167P AF28
3 IO_L167N AL32
3 IO_L168P_Y AJ31
3 IO_VREF_L168N_Y AF27
3 IO_L169P_Y AG29
3 IO_L169N_Y AJ32
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
3 IO_L170P_Y AK33
3 IO_L170N_Y AH30
3 IO_D7_L171P_YY AK32
3 IO_INIT_L171N_YY AK31
3IOV34
4 GCK0 AH18
4IOAE21
3
4IOAG18
4IOAG23
4IOAH24
3
4IOAH25
3
4IOAJ28
3
4IOAK18
3
4IOAK19
3
4IOAL25
4IOAL27
3
4IOAL30
3
4IOAN18
4IOAN22
3
4IOAN24
3
4 IO_L172P_YY AP31
4 IO_L172N_YY AK29
4 IO_L173P_Y AP30
4 IO_L173N_Y AN31
4 IO_L174P_Y AH27
4 IO_L174N_Y AN30
4 IO_VREF_L175P_Y AM30
4 IO_L175N_Y AK28
4 IO_L176P_Y AG26
4 IO_L176N_Y AN29
4 IO_L177P_YY AF25
4 IO_L177N_YY AM29
4 IO_VREF_L178P_YY AL29
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
126 1-800-255-7778 Preliminary Product Specification
4 IO_L178N_YY AL28
4 IO_L179P_YY AE244
4 IO_L179N_YY AN285
4 IO_L180P_Y AJ27
4 IO_L180N_Y AH26
4 IO_L181P_Y AG25
4 IO_L181N_Y AK27
4 IO_L182P AM284
4 IO_L182N AF245
4 IO_L183P_YY AJ26
4 IO_L183N_YY AP27
4 IO_VREF_L184P_YY AK26
4 IO_L184N_YY AN27
4 IO_L185P AE234
4 IO_L185N AM275
4 IO_L186P_Y AL26
4 IO_L186N_Y AP26
4 IO_VREF_L187P_Y AN262
4 IO_L187N_Y AJ25
4 IO_L188P AG244
4 IO_L188N AP255
4 IO_L189P_YY AF23
4 IO_L189N_YY AM26
4 IO_VREF_L190P_YY AJ24
4 IO_L190N_YY AN25
4 IO_L191P_Y AE22
4 IO_L191N_Y AM25
4 IO_L192P_Y AK24
4 IO_L192N_Y AH23
4 IO_VREF_L193P_YY AF22
4 IO_L193N_YY AP24
4 IO_L194P_YY AL24
4 IO_L194N_YY AK23
4 IO_L195P_Y AG22
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
4 IO_L195N_Y AN23
4 IO_L196P_Y AP23
4 IO_L196N_Y AM23
4 IO_L197P_Y AH22
4 IO_L197N_Y AP22
4 IO_L198P_Y AL23
4 IO_L198N_Y AF21
4 IO_L199P_YY AL22
4 IO_L199N_YY AJ22
4 IO_VREF_L200P_YY AK22
4 IO_L200N_YY AM22
4 IO_L201P_YY AG214
4 IO_L201N_YY AJ215
4 IO_L202P_Y AP21
4 IO_L202N_Y AE20
4 IO_L203P_Y AH21
4 IO_L203N_Y AL21
4 IO_L204P AN214
4 IO_L204N AF205
4 IO_L205P_YY AK21
4 IO_L205N_YY AP20
4 IO_VREF_L206P_YY AE19
4 IO_L206N_YY AN20
4 IO_L207P_Y AG204
4 IO_L207N_Y AL205
4 IO_L208P_Y AH20
4 IO_L208N_Y AK20
4 IO_L209P_Y AN19
4 IO_L209N_Y AJ20
4 IO_L210P AF194
4 IO_L210N AP195
4 IO_L211P_YY AM19
4 IO_L211N_YY AH19
4 IO_VREF_L212P_YY AJ19
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 127
4 IO_L212N_YY AP18
4 IO_L213P_Y AF18
4 IO_L213N_Y AP17
4 IO_VREF_L214P_Y AJ181
4 IO_L214N_Y AL18
4 IO_LVDS_DLL_L215P AM18
5 GCK1 AL19
5IOAF17
3
5IOAG12
3
5IOAH12
5IOAJ10
3
5IOAJ11
3
5IOAK7
3
5IOAK13
3
5IOAL13
3
5IOAM4
3
5IOAN9
5IOAN10
3
5IOAN16
5IOAN17
3
5 IO_LVDS_DLL_L215N AL17
5 IO_L216P_Y AH17
5 IO_VREF_L216N_Y AM171
5 IO_L217P_Y AJ17
5 IO_L217N_Y AG17
5 IO_L218P_YY AP16
5 IO_VREF_L218N_YY AL16
5 IO_L219P_YY AJ16
5 IO_L219N_YY AM16
5 IO_L220P AK165
5 IO_L220N AP154
5 IO_L221P_Y AL15
5 IO_L221N_Y AH16
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
5 IO_L222P_Y AN15
5 IO_L222N_Y AF16
5 IO_L223P_Y AP145
5 IO_L223N_Y AE164
5 IO_L224P_YY AK15
5 IO_VREF_L224N_YY AJ15
5 IO_L225P_YY AH15
5 IO_L225N_YY AN14
5 IO_L226P AK145
5 IO_L226N AG154
5 IO_L227P_Y AM13
5 IO_L227N_Y AF15
5 IO_L228P_Y AG14
5 IO_L228N_Y AP13
5 IO_L229P_YY AE145
5 IO_L229N_YY AE154
5 IO_L230P_YY AN13
5 IO_VREF_L230N_YY AG13
5 IO_L231P_YY AH14
5 IO_L231N_YY AP12
5 IO_L232P_Y AJ14
5 IO_L232N_Y AL14
5 IO_L233P_Y AF13
5 IO_L233N_Y AN12
5 IO_L234P_Y AF14
5 IO_L234N_Y AP11
5 IO_L235P_Y AN11
5 IO_L235N_Y AH13
5 IO_L236P_YY AM12
5 IO_L236N_YY AL12
5 IO_L237P_YY AJ13
5 IO_VREF_L237N_YY AP10
5 IO_L238P_Y AK12
5 IO_L238N_Y AM10
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
128 1-800-255-7778 Preliminary Product Specification
5 IO_L239P_Y AP9
5 IO_L239N_Y AK11
5 IO_L240P_YY AL11
5 IO_VREF_L240N_YY AL10
5 IO_L241P_YY AE13
5 IO_L241N_YY AM9
5 IO_L242P AF125
5 IO_L242N AP84
5 IO_L243P_Y AL9
5 IO_VREF_L243N_Y AH112
5 IO_L244P_Y AF11
5 IO_L244N_Y AN8
5 IO_L245P_Y AM85
5 IO_L245N_Y AG114
5 IO_L246P_YY AL8
5 IO_VREF_L246N_YY AK9
5 IO_L247P_YY AH10
5 IO_L247N_YY AN7
5 IO_L248P AE125
5 IO_L248N AJ94
5 IO_L249P_Y AM7
5 IO_L249N_Y AL7
5 IO_L250P_Y AG10
5 IO_L250N_Y AN6
5 IO_L251P_YY AK85
5 IO_L251N_YY AH94
5 IO_L252P_YY AP5
5 IO_VREF_L252N_YY AJ8
5 IO_L253P_YY AE11
5 IO_L253N_YY AN5
5 IO_L254P_Y AF10
5 IO_L254N_Y AM6
5 IO_L255P_Y AL6
5 IO_VREF_L255N_Y AG9
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
5 IO_L256P_Y AH8
5 IO_L256N_Y AP4
5 IO_L257P_Y AN4
5 IO_L257N_Y AJ7
5 IO_L258P_YY AM5
5 IO_L258N_YY AK6
6IO T1
6IO V2
6IO V3
6IOV5
3
6IOV8
3
6IOAA10
3
6IOAB5
3
6IOAB7
3
6IOAB9
3
6IOAD7
3
6IOAD8
3
6IOAE2
6IOAE4
6IOAJ4
3
6IOAH5
3
6 IO_L259N_YY AH6
6 IO_L259P_YY AF8
6 IO_L260N_Y AE9
6 IO_L260P_Y AK3
6 IO_L261N_Y AD10
6 IO_L261P_Y AL2
6 IO_VREF_L262N_Y AL1
6 IO_L262P_Y AH4
6 IO_L263N AG6
6 IO_L263P AK1
6 IO_L264N_Y AF7
6 IO_L264P_Y AK2
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 129
6 IO_VREF_L265N_Y AJ3
6 IO_L265P_Y AG5
6 IO_L266N_YY AD94
6 IO_L266P_YY AJ25
6 IO_L267N_YY AC10
6 IO_L267P_YY AH2
6 IO_L268N_Y AH3
6 IO_L268P_Y AF5
6 IO_L269N_Y AE84
6 IO_L269P_Y AG35
6 IO_L270N_Y AE7
6 IO_L270P_Y AG2
6 IO_VREF_L271N_YY AF6
6 IO_L271P_YY AG1
6 IO_L272N_YY AC94
6 IO_L272P_YY AG45
6 IO_L273N_YY AE6
6 IO_L273P_YY AF3
6 IO_VREF_L274N_Y AF12
6 IO_L274P_Y AF4
6 IO_L275N AB104
6 IO_L275P AF25
6 IO_L276N_Y AC8
6 IO_L276P_Y AE1
6 IO_VREF_L277N_YY AD5
6 IO_L277P_YY AE3
6 IO_L278N_YY AC7
6 IO_L278P_YY AD1
6 IO_L279N_Y AD6
6 IO_L279P_Y AD2
6 IO_VREF_L280N_YY AB8
6 IO_L280P_YY AC1
6 IO_L281N_YY AC5
6 IO_L281P_YY AC2
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
6 IO_L282N_Y AA9
6 IO_L282P_Y AC3
6 IO_L283N_Y AC4
6 IO_L283P_Y AD4
6 IO_L284N_Y AA8
6 IO_L284P_Y AB6
6 IO_L285N AB1
6 IO_L285P Y10
6 IO_L286N_Y AB2
6 IO_L286P_Y AA7
6 IO_VREF_L287N_Y AA4
6 IO_L287P_Y AA1
6 IO_L288N_YY Y94
6 IO_L288P_YY AB45
6 IO_L289N_YY AA2
6 IO_L289P_YY Y8
6 IO_L290N_Y AA6
6 IO_L290P_Y AA5
6 IO_L291N_Y AB34
6 IO_L291P_Y Y75
6 IO_L292N_Y Y1
6 IO_L292P_Y W10
6 IO_VREF_L293N_YY Y5
6 IO_L293P_YY Y2
6 IO_L294N_YY W94
6 IO_L294P_YY W25
6 IO_L295N_YY W7
6 IO_L295P_YY Y4
6 IO_L296N_Y W1
6 IO_L296P_Y Y6
6 IO_L297N_Y W64
6 IO_L297P_Y W35
6 IO_L298N_Y V9
6 IO_L298P_Y W4
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
130 1-800-255-7778 Preliminary Product Specification
6 IO_VREF_L299N_YY W5
6 IO_L299P_YY V1
6 IO_L300N_YY V7
6 IO_L300P_YY U2
6 IO_VREF_L301N_Y V61
6 IO_L301P_Y U1
7IO F5
7IOG6
3
7IO H1
7IOH7
3
7IOK2
3
7IOK4
3
7IOL6
3
7IOM5
3
7IOM10
3
7ION5
3
7ION10
7IOR7
4
7IO T2
7IOT7
3
7IO U8
7IOV4
3
7 IO_L302N_YY U9
7 IO_L302P_YY U4
7 IO_L303N_Y U7
7 IO_VREF_L303P_Y U51
7 IO_L304N_YY U3
7 IO_L304P_YY U6
7 IO_L305N_YY T3
7 IO_VREF_L305P_YY T6
7 IO_L306N_Y T9
7 IO_L306P_Y T4
7 IO_L307N_Y T55
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
7 IO_L307P_Y R14
7 IO_L308N_Y R6
7 IO_L308P_Y T10
7 IO_L309N_YY R2
7 IO_L309P_YY R5
7 IO_L310N_YY P1
7 IO_VREF_L310P_YY P5
7 IO_L311N_Y R8
7 IO_L311P_Y P2
7 IO_L312N_Y R95
7 IO_L312P_Y N14
7 IO_L313N_Y P4
7 IO_L313P_Y R10
7 IO_L314N_YY P8
7 IO_L314P_YY N2
7 IO_L315N_YY P65
7 IO_L315P_YY P74
7 IO_L316N_Y M1
7 IO_VREF_L316P_Y N4
7 IO_L317N_Y N6
7 IO_L317P_Y N3
7 IO_L318N P9
7 IO_L318P M2
7 IO_L319N_Y N7
7 IO_L319P_Y M3
7 IO_L320N_Y P10
7 IO_L320P_Y M4
7 IO_L321N_Y L1
7 IO_L321P_Y N8
7 IO_L322N_YY L2
7 IO_L322P_YY N9
7 IO_L323N_YY M7
7 IO_VREF_L323P_YY K1
7 IO_L324N_Y M8
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 131
7 IO_L324P_Y L4
7 IO_L325N_YY J1
7 IO_L325P_YY L5
7 IO_L326N_YY J2
7 IO_VREF_L326P_YY K3
7 IO_L327N_Y L7
7 IO_L327P_Y J3
7 IO_L328N_Y M95
7 IO_L328P_Y H24
7 IO_L329N_Y J4
7 IO_VREF_L329P_Y K62
7 IO_L330N_YY L8
7 IO_L330P_YY G2
7 IO_L331N_YY H35
7 IO_L331P_YY K74
7 IO_L332N_YY G3
7 IO_VREF_L332P_YY J5
7 IO_L333N_Y L9
7 IO_L333P_Y H5
7 IO_L334N_Y J65
7 IO_L334P_Y H44
7 IO_L335N_Y G4
7 IO_L335P_Y K8
7 IO_L336N_YY J7
7 IO_L336P_YY F2
7 IO_L337N_YY F35
7 IO_L337P_YY L104
7 IO_L338N_Y E1
7 IO_VREF_L338P_Y_Y H6
7 IO_L339N_Y G5
7 IO_L339P_Y E2
7 IO_L340N K9
7 IO_L340P D1
7 IO_L341N_Y E3
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
7 IO_VREF_L341P_Y J8
7 IO_L342N_Y E4
7 IO_L342P_Y D2
7 IO_L343N_Y F4
7 IO_L343P_Y D3
2 CCLK C31
3DONEAM31
NA DXN AJ5
NA DXP AL5
NA M0 AK4
NA M1 AG7
NA M2 AL3
NA PROGRAM AG28
NA TCK D5
NA TDI C30
2TDOK26
NA TMS C4
NA VCCINT K10
NA VCCINT K17
NA VCCINT K18
NA VCCINT K25
NA VCCINT L11
NA VCCINT L24
NA VCCINT M12
NA VCCINT M23
NA VCCINT N13
NA VCCINT N14
NA VCCINT N15
NA VCCINT N16
NA VCCINT N19
NA VCCINT N20
NA VCCINT N21
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
132 1-800-255-7778 Preliminary Product Specification
NA VCCINT N22
NA VCCINT P13
NA VCCINT P22
NA VCCINT R13
NA VCCINT R22
NA VCCINT T13
NA VCCINT T22
NA VCCINT U10
NA VCCINT U25
NA VCCINT V10
NA VCCINT V25
NA VCCINT W13
NA VCCINT W22
NA VCCINT Y13
NA VCCINT Y22
NA VCCINT AA13
NA VCCINT AA22
NA VCCINT AB13
NA VCCINT AB14
NA VCCINT AB15
NA VCCINT AB16
NA VCCINT AB19
NA VCCINT AB20
NA VCCINT AB21
NA VCCINT AB22
NA VCCINT AC12
NA VCCINT AC23
NA VCCINT AD24
NA VCCINT AD11
NA VCCINT AE10
NA VCCINT AE17
NA VCCINT AE18
NA VCCINT AE25
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
NA VCCO_0 M17
NA VCCO_0 L17
NA VCCO_0 L16
NA VCCO_0 E10
NA VCCO_0 C14
NA VCCO_0 A6
NA VCCO_0 M13
NA VCCO_0 M14
NA VCCO_0 M15
NA VCCO_0 M16
NA VCCO_0 L12
NA VCCO_0 L13
NA VCCO_0 L14
NA VCCO_0 L15
NA VCCO_1 M18
NA VCCO_1 L18
NA VCCO_1 L23
NA VCCO_1 E25
NA VCCO_1 C21
NA VCCO_1 A29
NA VCCO_1 M19
NA VCCO_1 M20
NA VCCO_1 M21
NA VCCO_1 M22
NA VCCO_1 L19
NA VCCO_1 L20
NA VCCO_1 L21
NA VCCO_1 L22
NA VCCO_2 U24
NA VCCO_2 U23
NA VCCO_2 N24
NA VCCO_2 M24
NA VCCO_2 K30
NA VCCO_2 F34
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 133
NA VCCO_2 T23
NA VCCO_2 T24
NA VCCO_2 R23
NA VCCO_2 R24
NA VCCO_2 P23
NA VCCO_2 P24
NA VCCO_2 P32
NA VCCO_2 N23
NA VCCO_3 V23
NA VCCO_3 V24
NA VCCO_3 Y23
NA VCCO_3 Y24
NA VCCO_3 W23
NA VCCO_3 W24
NA VCCO_3 AJ34
NA VCCO_3 AE30
NA VCCO_3 AC24
NA VCCO_3 AB23
NA VCCO_3 AB24
NA VCCO_3 AA23
NA VCCO_3 AA24
NA VCCO_3 AA32
NA VCCO_4 AD18
NA VCCO_4 AC18
NA VCCO_4 AC19
NA VCCO_4 AC20
NA VCCO_4 AC21
NA VCCO_4 AC22
NA VCCO_4 AP29
NA VCCO_4 AM21
NA VCCO_4 AK25
NA VCCO_4 AD19
NA VCCO_4 AD20
NA VCCO_4 AD21
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
NA VCCO_4 AD22
NA VCCO_4 AD23
NA VCCO_5 AC17
NA VCCO_5 AD17
NA VCCO_5 AC13
NA VCCO_5 AC14
NA VCCO_5 AC15
NA VCCO_5 AC16
NA VCCO_5 AP6
NA VCCO_5 AM14
NA VCCO_5 AK10
NA VCCO_5 AD12
NA VCCO_5 AD13
NA VCCO_5 AD14
NA VCCO_5 AD15
NA VCCO_5 AD16
NA VCCO_6 V11
NA VCCO_6 V12
NA VCCO_6 Y11
NA VCCO_6 Y12
NA VCCO_6 W11
NA VCCO_6 W12
NA VCCO_6 AJ1
NA VCCO_6 AE5
NA VCCO_6 AC11
NA VCCO_6 AB11
NA VCCO_6 AB12
NA VCCO_6 AA3
NA VCCO_6 AA11
NA VCCO_6 AA12
NA VCCO_7 U11
NA VCCO_7 U12
NA VCCO_7 N12
NA VCCO_7 M11
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
134 1-800-255-7778 Preliminary Product Specification
NA VCCO_7 K5
NA VCCO_7 F1
NA VCCO_7 T11
NA VCCO_7 T12
NA VCCO_7 R11
NA VCCO_7 R12
NA VCCO_7 P3
NA VCCO_7 P11
NA VCCO_7 P12
NA VCCO_7 N11
NA GND K32
NA GND R4
NA GND AN1
NA GND AM11
NA GND AK5
NA GND AH28
NA GND AD32
NA GND AA20
NA GND Y20
NA GND W19
NA GND V19
NA GND U20
NA GND T20
NA GND R19
NA GND P19
NA GND H8
NA GND F12
NA GND C2
NA GND B1
NA GND A7
NA GND AP1
NA GND AN2
NA GND AM15
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
NA GND AK17
NA GND AH34
NA GND AC6
NA GND AA21
NA GND Y21
NA GND W20
NA GND V20
NA GND U21
NA GND T21
NA GND R20
NA GND P20
NA GND H16
NA GND F23
NA GND C3
NA GND B2
NA GND A28
NA GND AP34
NA GND AM3
NA GND AL31
NA GND AH7
NA GND AD3
NA GND AA19
NA GND Y19
NA GND W18
NA GND V18
NA GND U19
NA GND T19
NA GND R18
NA GND P18
NA GND J26
NA GND F6
NA GND C1
NA GND C34
NA GND A3
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 135
NA GND AP2
NA GND AN3
NA GND AM20
NA GND AK30
NA GND AG8
NA GND AC29
NA GND Y3
NA GND Y32
NA GND W21
NA GND V21
NA GND T8
NA GND T27
NA GND R21
NA GND P21
NA GND H19
NA GND F29
NA GND C11
NA GND B3
NA GND A32
NA GND AP3
NA GND AN32
NA GND AM24
NA GND AJ6
NA GND AG16
NA GND AA14
NA GND Y14
NA GND W8
NA GND W27
NA GND U14
NA GND T14
NA GND R3
NA GND R32
NA GND M6
NA GND H27
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
NA GND E5
NA GND C15
NA GND B32
NA GND A33
NA GND AP7
NA GND AN33
NA GND AM32
NA GND AJ12
NA GND AG19
NA GND AA15
NA GND Y15
NA GND W14
NA GND V14
NA GND U15
NA GND T15
NA GND R14
NA GND P14
NA GND M29
NA GND G1
NA GND E18
NA GND C20
NA GND B33
NA GND A34
NA GND AP28
NA GND AN34
NA GND AM33
NA GND AJ23
NA GND AG27
NA GND AA16
NA GND Y16
NA GND W15
NA GND V15
NA GND U16
NA GND T16
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
136 1-800-255-7778 Preliminary Product Specification
NA GND R15
NA GND P15
NA GND L3
NA GND G7
NA GND E30
NA GND C24
NA GND B34
NA GND AP32
NA GND AM1
NA GND AM34
NA GND AJ29
NA GND AF9
NA GND AA17
NA GND Y17
NA GND W16
NA GND V16
NA GND U17
NA GND T17
NA GND R16
NA GND P16
NA GND L32
NA GND G28
NA GND D4
NA GND C32
NA GND A1
NA GND AP33
NA GND AM2
NA GND AL4
NA GND AH1
NA GND AF26
NA GND AA18
NA GND Y18
NA GND W17
NA GND V17
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
NA GND U18
NA GND T18
NA GND R17
NA GND P17
NA GND J9
NA GND G34
NA GND D31
NA GND C33
NA GND A2
NA GND AB17
NA GND AB18
NA GND N17
NA GND N18
NA GND U13
NA GND V13
NA GND U22
NA GND V22
Notes:
1. VREF or I/O option only in the XCV1600E, XCV2000E,
XCV2600E, and XCV3200E; otherwise, I/O option only.
2. VREF or I/O option only in the XCV2000E, XCV2600E, and
XCV3200E; otherwise, I/O option only.
3. No Connect in the XCV1000E, XCV1600E.
4. No Connect in the XCV1000E.
5. I/O in the XCV1000E.
Ta b l e 2 8 : FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank Pin Description Pin #
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 137
FG1156 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. The
AO column in Table 29 indicates which devices in this pack-
age can use the pin pair as an asynchronous output. The
“Other Functions” column indicates alternative function(s)
that are not available when the pair is used as a differential
pair or differential clock.
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
GCLK LVDS
3 0 E17 C17 NA IO_DLL_L 42N
2 1 D17 J18 NA IO_DLL_L 42P
1 5 AL19 AL17 NA IO_DLL_L 215N
0 4 AH18 AM18 NA IO_DLL_L 215P
IO LVDS
Total Pairs: 344, Asynchronous Output Pairs: 134
00H9F7
3200 1600
1000 -
10J10C5
3200 2000
1000 -
20D6E6
3200 2000
1000 VREF
30G8A4
3200 2600
1000 -
40J11C6
3200 2600
2000 1600
1000
-
50F8G9
3200 2600
2000 1600
1000
VREF
6 0 H10 A5 2000 1600 -
7 0 B5 D7 3200 1000 -
8 0 E8 K12 3200 1000 -
9 0 F9 B6 3200 2600 -
10 0 C7 G10
3200 2600
2000 1600
1000
-
11 0 B7 D8
3200 2600
2000 1600
1000
VREF
12 0 C8 H11 3200 1600 -
13 0 B8 E9 3200 2000
1000 -
14 0 G11 K13 3200 2000
1000 VREF
15 0 F10 A8 3200 2600 -
160H12C9
3200 2600
2000 1600
1000
-
17 0 A9 D10
3200 2600
2000 1600
1000
VREF
18 0 A10 F11 2600 1600
1000 -
190C10K14
2600 1600
1000 -
20 0 G12 H13
3200 2600
2000 1600
1000
VREF
21 0 B11 A11
3200 2600
2000 1600
1000
-
220D11E12
3200 1600
1000 -
230C12G13
3200 2000
1000 -
24 0 A12 K15 3200 2000
1000 -
250H14B12
3200 2600
1000 -
26 0 F13 D12
3200 2600
2000 1600
1000
-
27 0 B13 A13
3200 2600
2000 1600
1000
VREF
28 0 G14 J15 2000 1600 -
29 0 F14 C13 3200 2600
1000 -
300D13H15
3200 2600
1000 -
31 0 K16 A14 3200 -
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
138 1-800-255-7778 Preliminary Product Specification
32 0 B14 E14
3200 2600
2000 1600
1000
-
330D14G15
3200 2600
2000 1600
1000
VREF
34 0 D15 J16 3200 1600 -
35 0 B15 F15 3200 2000
1000 -
36 0 E15 A15 3200 2000
1000 -
37 0 A16 G16 3200 2600 -
38 0 J17 F16
3200 2600
2000 1600
1000
-
39 0 B16 C16
3200 2600
2000 1600
1000
VREF
40 0 A17 H17 2600 1600
1000 -
41 0 B17 G17 2600 1600
1000 VREF
42 1 J18 C17 None IO_LVDS_DLL
431C18G18
2600 1600
1000 VREF
44 1 F18 H18 2600 1600
1000 -
45 1 A19 B19
3200 2600
2000 1600
1000
VREF
461C19K19
3200 2600
2000 1600
1000
-
47 1 E19 F19 3200 2600 -
48 1 J19 G19 3200 2000
1000 -
49 1 G20 A20 3200 2000
1000 -
50 1 F20 B20 3200 1600 -
51 1 E20 D20
3200 2600
2000 1600
1000
VREF
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
52 1 A21 H20
3200 2600
2000 1600
1000
-
53 1 J20 E21 3200 -
54 1 K20 D21 3200 2600
1000 -
551H21B21
3200 2600
1000 -
56 1 F21 G21 2000 1600 -
57 1 B22 A22
3200 2600
2000 1600
1000
VREF
581C22J21
3200 2600
2000 1600
1000
-
59 1 G22 D22 3200 2600
1000 -
60 1 A23 K21 3200 2000
1000 -
61 1 B23 F22 3200 2000
1000 -
621H22C23
3200 1600
1000 -
63 1 K22 D23
3200 2600
2000 1600
1000
-
64 1 J22 A24
3200 2600
2000 1600
1000
VREF
651D24H23
2600 1600
1000 -
66 1 E24 A25 2600 1600
1000 -
671C25A26
3200 2600
2000 1600
1000
VREF
68 1 B26 F24
3200 2600
2000 1600
1000
-
69 1 F25 K23 3200 2600 -
701H24C26
3200 2000
1000 VREF
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 139
71 1 A27 G24 3200 2000
1000 -
72 1 G25 B27 3200 1600 -
731C27E26
3200 2600
2000 1600
1000
VREF
74 1 B28 J24
3200 2600
2000 1600
1000
-
75 1 H25 K24 3200 2600 -
76 1 F26 D27 3200 1000 -
77 1 C28 G26 3200 1000 -
78 1 J25 E27 2000 1600 -
791H26A30
3200 2600
2000 1600
1000
VREF
80 1 B29 G27
3200 2600
2000 1600
1000
-
811C29F27
3200 2600
1000 -
82 1 F28 E28 3200 2000
1000 VREF
83 1 B30 L25 3200 2000
1000 -
84 1 E29 B31 3200 1600
1000 -
851D30A31
3200 2600
2000 1600
1000
CS
862D32J27
3200 2600
2000 1600
1000
DIN, D0
87 2 E31 F30 3200 2600
2000 -
88 2 G29 F32 2600 2000
1000 -
89 2 E32 G30 3200 2600
1600 1000 VREF
90 2 M25 G31 2600 1600 -
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
91 2 L26 D33 3200 2600
1600 1000 -
922D34H29
2600 2000
1000 VREF
93 2 J28 E33 3200 2600
2000 1600 -
942H28H30
3200 2600
2000 1600
1000
-
952H32K28
3200 2600
1600 1000 -
96 2 L27 F33 3200 2600
2000 -
97 2 M26 E34 2600 2000
1000 -
982H31G32
3200 2600
2000 1600
1000
VREF
99 2 N25 J31 2000 1600 -
100 2 J30 G33
3200 2600
2000 1600
1000
-
101 2 H34 J29 2600 1000 VREF
102 2 M27 H33 3200 2600
1600 -
103 2 K29 J34 3200 2600
1600 1000 -
104 2 L29 J33
3200 2600
2000 1600
1000
VREF
105 2 M28 K34
3200 2600
2000 1600
1000
-
106 2 N27 L34 3200 1600
1000 -
107 2 K33 P26 2000 1600
1000 D1
108 2 R25 M34 3200 2600
2000 -
109 2 L31 L33 2000 1000 -
110 2 P27 M33 3200 2600
1600 1000 -
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
140 1-800-255-7778 Preliminary Product Specification
111 2 M31 R26 2600 1600 -
112 2 N30 P28 3200 1600
1000 -
113 2 N29 N33 2600 2000
1000 VREF
114 2 T25 N34 3200 2600
2000 1600 -
115 2 P34 R27
3200 2600
2000 1600
1000
-
116 2 P29 P31 3200 2600
1600 1000 -
117 2 P33 T26 3200 2600
2000 -
118 2 R34 R28 2600 2000
1000 -
119 2 N31 N32 2000 1600
1000 D3
120 2 P30 R33 2000 1600 -
121 2 R29 T34
3200 2600
2000 1600
1000
-
122 2 R30 T30 1000 -
123 2 T28 R31 3200 1600 -
124 2 T29 U27 3200 2600
1600 1000 -
125 2 T31 T33 2000 1600
1000 VREF
126 2 U28 T32 2000 1600
1000 -
127 2 U29 U33 3200 2600
1600 1000 VREF
128 2 V33 U31
3200 2600
2000 1600
1000
-
129 3 V26 V30 3200 2600
1600 1000 VREF
130 3 W34 V28 2000 1600
1000 -
131 3 W32 W30 2000 1600
1000 VREF
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
132 3 V29 Y34 3200 2600
1600 1000 -
133 3 W29 Y33 3200 1600 -
134 3 W26 W28 1000 -
135 3 Y31 Y30
3200 2600
2000 1600
1000
-
136 3 AA34 W31 2000 1600 -
137 3 AA33 Y29 2000 1600
1000 VREF
138 3 W25 AB34 2600 2000
1000 -
139 3 Y28 AB33 3200 2600
2000 -
140 3 AA30 Y26 3200 2600
1600 1000 -
141 3 Y27 AA31
3200 2600
2000 1600
1000
-
142 3 AA27 AA29 3200 2600
2000 1600 -
143 3 AB32 AB29 2600 2000
1000 VREF
144 3 AA28 AC34 3200 1600
1000 -
145 3 Y25 AD34 2600 1600 -
146 3 AB30 AC33 3200 2600
1600 1000 -
147 3 AA26 AC32 2000 1000 -
148 3 AD33 AB28 3200 2600
2000 -
149 3 AE34 AB27
3200 2600
2000 1600
1000
D5
150 3 AE33 AC30 2000 1600
1000 VREF
151 3 AA25 AE32 3200 1600
1000 -
152 3 AE31 AD29
3200 2600
2000 1600
1000
-
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 141
153 3 AD31 AF33
3200 2600
2000 1600
1000
VREF
154 3 AC28 AF31 3200 2600
1600 1000 -
155 3 AC27 AF32 3200 2600
1600 -
156 3 AE29 AD28 2600 1000 VREF
157 3 AD30 AG32
3200 2600
2000 1600
1000
-
158 3 AC26 AH33 2000 1600 -
159 3 AD26 AF30
3200 2600
2000 1600
1000
VREF
160 3 AC25 AH32 2600 2000
1000 -
161 3 AE28 AL34 3200 2600
2000 -
162 3 AG30 AD27 3200 2600
1600 1000 -
163 3 AF29 AK34
3200 2600
2000 1600
1000
-
164 3 AD25 AE27 3200 2600
2000 1600 -
165 3 AJ33 AH31 2600 2000
1000 VREF
166 3 AE26 AL33 3200 2600
1600 1000 -
167 3 AF28 AL32 2600 1600 -
168 3 AJ31 AF27 3200 2600
1600 1000 VREF
169 3 AG29 AJ32 2600 2000
1000 -
170 3 AK33 AH30 3200 2600
2000 -
171 3 AK32 AK31
3200 2600
2000 1600
1000
INIT
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
172 4 AP31 AK29
3200 2600
2000 1600
1000
-
173 4 AP30 AN31 3200 1600
1000 -
174 4 AH27 AN30 3200 2000
1000 -
175 4 AM30 AK28 3200 2000
1000 VREF
176 4 AG26 AN29 3200 2600
1000 -
177 4 AF25 AM29
3200 2600
2000 1600
1000
-
178 4 AL29 AL28
3200 2600
2000 1600
1000
VREF
179 4 AE24 AN28 2000 1600 -
180 4 AJ27 AH26 3200 1000 -
181 4 AG25 AK27 3200 1000 -
182 4 AM28 AF24 3200 2600 -
183 4 AJ26 AP27
3200 2600
2000 1600
1000
-
184 4 AK26 AN27
3200 2600
2000 1600
1000
VREF
185 4 AE23 AM27 3200 1600 -
186 4 AL26 AP26 3200 2000
1000 -
187 4 AN26 AJ25 3200 2000
1000 VREF
188 4 AG24 AP25 3200 2600 -
189 4 AF23 AM26
3200 2600
2000 1600
1000
-
190 4 AJ24 AN25
3200 2600
2000 1600
1000
VREF
191 4 AE22 AM25 2600 1600
1000 -
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
142 1-800-255-7778 Preliminary Product Specification
192 4 AK24 AH23 2600 1600
1000 -
193 4 AF22 AP24
3200 2600
2000 1600
1000
VREF
194 4 AL24 AK23
3200 2600
2000 1600
1000
-
195 4 AG22 AN23 3200 1600
1000 -
196 4 AP23 AM23 3200 2000
1000 -
197 4 AH22 AP22 3200 2000
1000 -
198 4 AL23 AF21 3200 2600
1000 -
199 4 AL22 AJ22
3200 2600
2000 1600
1000
-
200 4 AK22 AM22
3200 2600
2000 1600
1000
VREF
201 4 AG21 AJ21 2000 1600 -
202 4 AP21 AE20 3200 2600
1000 -
203 4 AH21 AL21 3200 2600
1000 -
204 4 AN21 AF20 3200 -
205 4 AK21 AP20
3200 2600
2000 1600
1000
-
206 4 AE19 AN20
3200 2600
2000 1600
1000
VREF
207 4 AG20 AL20 3200 1600 -
208 4 AH20 AK20 3200 2000
1000 -
209 4 AN19 AJ20 3200 2000
1000 -
210 4 AF19 AP19 3200 2600 -
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
211 4 AM19 AH19
3200 2600
2000 1600
1000
-
212 4 AJ19 AP18
3200 2600
2000 1600
1000
VREF
213 4 AF18 AP17 2600 1600
1000 -
214 4 AJ18 AL18 2600 1600
1000 VREF
215 5 AM18 AL17 None IO_LVDS_DLL
216 5 AH17 AM17 2600 1600
1000 VREF
217 5 AJ17 AG17 2600 1600
1000 -
218 5 AP16 AL16
3200 2600
2000 1600
1000
VREF
219 5 AJ16 AM16
3200 2600
2000 1600
1000
-
220 5 AK16 AP15 3200 2600 -
221 5 AL15 AH16 3200 2000
1000 -
222 5 AN15 AF16 3200 2000
1000 -
223 5 AP14 AE16 3200 1600 -
224 5 AK15 AJ15
3200 2600
2000 1600
1000
VREF
225 5 AH15 AN14
3200 2600
2000 1600
1000
-
226 5 AK14 AG15 3200 -
227 5 AM13 AF15 3200 2600
1000 -
228 5 AG14 AP13 3200 2600
1000 -
229 5 AE14 AE15 2000 1600 -
230 5 AN13 AG13
3200 2600
2000 1600
1000
VREF
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 143
231 5 AH14 AP12
3200 2600
2000 1600
1000
-
232 5 AJ14 AL14 3200 2600
1000 -
233 5 AF13 AN12 3200 2000
1000 -
234 5 AF14 AP11 3200 2000
1000 -
235 5 AN11 AH13 3200 1600
1000 -
236 5 AM12 AL12
3200 2600
2000 1600
1000
-
237 5 AJ13 AP10
3200 2600
2000 1600
1000
VREF
238 5 AK12 AM10 2600 1600
1000 -
239 5 AP9 AK11 2600 1600
1000 -
240 5 AL11 AL10
3200 2600
2000 1600
1000
VREF
241 5 AE13 AM9
3200 2600
2000 1600
1000
-
242 5 AF12 AP8 3200 2600 -
243 5 AL9 AH11 3200 2000
1000 VREF
244 5 AF11 AN8 3200 2000
1000 -
245 5 AM8 AG11 3200 1600 -
246 5 AL8 AK9
3200 2600
2000 1600
1000
VREF
247 5 AH10 AN7
3200 2600
2000 1600
1000
-
248 5 AE12 AJ9 3200 2600 -
249 5 AM7 AL7 3200 1000 -
250 5 AG10 AN6 3200 1000 -
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
251 5 AK8 AH9 2000 1600 -
252 5 AP5 AJ8
3200 2600
2000 1600
1000
VREF
253 5 AE11 AN5
3200 2600
2000 1600
1000
-
254 5 AF10 AM6 3200 2600
1000 -
255 5 AL6 AG9 3200 2000
1000 VREF
256 5 AH8 AP4 3200 2000
1000 -
257 5 AN4 AJ7 3200 1600
1000 -
258 5 AM5 AK6
3200 2600
2000 1600
1000
-
259 6 AF8 AH6
3200 2600
2000 1600
1000
-
260 6 AK3 AE9 3200 2600
2000 -
261 6 AL2 AD10 2600 2000
1000 -
262 6 AH4 AL1 3200 2600
1600 1000 VREF
263 6 AK1 AG6 2600 1600 -
264 6 AK2 AF7 3200 2600
1600 1000 -
265 6 AG5 AJ3 2600 2000
1000 VREF
266 6 AJ2 AD9 3200 2600
2000 1600 -
267 6 AH2 AC10
3200 2600
2000 1600
1000
-
268 6 AF5 AH3 3200 2600
1600 1000 -
269 6 AG3 AE8 3200 2600
2000 -
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
144 1-800-255-7778 Preliminary Product Specification
270 6 AG2 AE7 2600 2000
1000 -
271 6 AG1 AF6
3200 2600
2000 1600
1000
VREF
272 6 AG4 AC9 2000 1600 -
273 6 AF3 AE6
3200 2600
2000 1600
1000
-
274 6 AF4 AF1 2600 1000 VREF
275 6 AF2 AB10 3200 2600
1600 -
276 6 AE1 AC8 3200 2600
1600 1000 -
277 6 AE3 AD5
3200 2600
2000 1600
1000
VREF
278 6 AD1 AC7
3200 2600
2000 1600
1000
-
279 6 AD2 AD6 3200 1600
1000 -
280 6 AC1 AB8 2000 1600
1000 VREF
281 6 AC2 AC5
3200 2600
2000 1600
1000
-
282 6 AC3 AA9 3200 2600
2000 -
283 6 AD4 AC4 2000 1000 -
284 6 AB6 AA8 3200 2600
1600 1000 -
285 6 Y10 AB1 2600 1600 -
286 6 AA7 AB2 3200 1600
1000 -
287 6 AA1 AA4 2600 2000
1000 VREF
288 6 AB4 Y9 3200 2600
2000 1600 -
289 6 Y8 AA2
3200 2600
2000 1600
1000
-
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
290 6 AA5 AA6 3200 2600
1600 1000 -
291 6 Y7 AB3 3200 2600
2000 -
292 6 W10 Y1 2600 2000
1000 -
293 6 Y2 Y5 2000 1600
1000 VREF
294 6 W2 W9 2000 1600 -
295 6 Y4 W7
3200 2600
2000 1600
1000
-
296 6 Y6 W1 1000 -
297 6 W3 W6 3200 1600 -
298 6 W4 V9 3200 2600
1600 1000 -
299 6 V1 W5 2000 1600
1000 VREF
300 6 U2 V7 2000 1600
1000 -
301 6 U1 V6 3200 2600
1600 1000 VREF
302 7 U4 U9
3200 2600
2000 1600
1000
-
303 7 U5 U7 3200 2600
1600 1000 VREF
304 7 U6 U3 2000 1600
1000 -
305 7 T6 T3 2000 1600
1000 VREF
306 7 T4 T9 3200 2600
1600 1000 -
307 7 R1 T5 3200 1600 -
308 7 T10 R6 1000 -
309 7 R5 R2
3200 2600
2000 1600
1000
-
310 7 P5 P1 2000 1600
1000 VREF
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 145
311 7 P2 R8 2600 2000
1000 -
312 7 N1 R9 3200 2600
2000 -
313 7 R10 P4 3200 2600
1600 1000 -
314 7 N2 P8
3200 2600
2000 1600
1000
-
315 7 P7 P6 3200 2600
2000 1600 -
316 7 N4 M1 2600 2000
1000 VREF
317 7 N3 N6 3200 1600
1000 -
318 7 M2 P9 2600 1600 -
319 7 M3 N7 3200 2600
1600 1000 -
320 7 M4 P10 2000 1000 -
321 7 N8 L1 3200 2600
2000 -
322 7 N9 L2
3200 2600
2000 1600
1000
-
323 7 K1 M7 2000 1600
1000 VREF
324 7 L4 M8 3200 1600
1000 -
325 7 L5 J1
3200 2600
2000 1600
1000
-
326 7 K3 J2
3200 2600
2000 1600
1000
VREF
327 7 J3 L7 3200 2600
1600 1000 -
328 7 H2 M9 3200 2600
1600 -
329 7 K6 J4 2600 1000 VREF
330 7 G2 L8
3200 2600
2000 1600
1000
-
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
331 7 K7 H3 2000 1600 -
332 7 J5 G3
3200 2600
2000 1600
1000
VREF
333 7 H5 L9 2600 2000
1000 -
334 7 H4 J6 3200 2600
2000 -
335 7 K8 G4 3200 2600
1600 1000 -
336 7 F2 J7
3200 2600
2000 1600
1000
-
337 7 L10 F3 3200 2600
2000 1600 -
338 7 H6 E1 2600 2000
1000 VREF
339 7 E2 G5 3200 2600
1600 1000 -
340 7 D1 K9 2600 1600 -
341 7 J8 E3 3200 2600
1600 1000 VREF
342 7 D2 E4 2600 2000
1000 -
343 7 D3 F4 3200 2600
2000 -
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Pair Bank
P
Pin
N
Pin AO
Other
Functions
Virtex™-E 1.8 V Field Programmable Gate Arrays R
Module 4 of 4 www.xilinx.com DS022-4 (v2.3) November 15, 2001
146 1-800-255-7778 Preliminary Product Specification
Revision History
The following table shows the revision history for this document.
Date Version Revision
12/7/99 1.0 Initial Xilinx release.
1/10/00 1.1 Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00 1.2 Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, TBYP values, buffered Hex Line info, p. 8, I/O Timing
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00 1.3 Updated pinout tables, VCC page 20, and corrected Figure 20.
5/23/00 1.4 Correction to table on p. 22.
7/10/00 1.5 •Numerous minor edits.
•Data sheet upgraded to Preliminary.
•Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
8/1/00 1.6 •Reformatted entire document to follow new style guidelines.
•Changed speed grade values in tables on pages 35-37.
9/20/00 1.7 •Min values added to Virtex-E Electrical Characteristics tables.
•XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
•Corrected user I/O count for XCV100E device in Table 1 (Module 1).
•Changed several pins to “No Connect in the XCV100E“ and removed duplicate VCCINT
pins in Table ~ (Module 4).
•Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
•Changed pin J30 to “VREF or I/O option only in the XCV600E” in Table 74 (Module 4).
•Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
11/20/00 1.8 •Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
•Updated minimums in Table 13 and added notes to Table 14.
•Added to note 2 to Absolute Maximum Ratings.
•Changed speed grade -8 numbers for TSHCKO32, TREG, TBCCS, and TICKOF
.
•Changed all minimum hold times to –0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.
•Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters.
•Changed GCLK0 to BA22 for FG860 package in Table 46.
2/12/01 1.9 •Revised footnote for Table 14.
•Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
•Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
•Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.
•Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
Virtex™-E 1.8 V Field Programmable Gate Arrays
R
DS022-4 (v2.3) November 15, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 147
Virtex-E Data Sheet
The Virtex-E Data Sheet contains the following modules:
•DS022-1, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1)
•DS022-2, Virtex-E 1.8V FPGAs:
Functional Description (Module 2)
•DS022-3, Virtex-E 1.8V FPGAs:
DC and Switching Characteristics (Module 3)
•DS022-4, Virtex-E 1.8V FPGAs:
Pinout Tables (Module 4)
4/2/01 2.0 •Updated numerous values in Virtex-E Switching Characteristics tables.
•Changed pinout table footnotes from "VREF option only" to "VREF or I/O option only" to
improve clarity.
•Converted file to modularized format. See the Virtex-E Data Sheet section.
7/26/01 2.1 •Changed pinout table footnotes from "VREF or I/O option only" to "VREF or I/O option only;
otherwise I/O only" to improve clarity.
•Changed designation for pin pair 300 in Table 29 from AO to footnote 9.
10/25/01 2.2 •Changed Tabl e 2 9 to clarify which devices in the FG1156 package can use each pin
pair as an asynchronous output.
•Updated references to the XCV3200E device in the FG1156 package.
11/15/01 2.3 •Fixed cosmetic error.
Date Version Revision
