Automotive Power
Data Sheet
Rev. 1.3, 2018-03-05
TLE42744
Low Dropout Linear Voltage Regulator
TLE42744DV50
TLE42744GV50
TLE42744EV50
TLE42744GV33
TLE42744DV33
TLE42744GSV33
TLE42744
Type Package Marking
TLE42744DV50 PG-TO252-3 42744V5
TLE42744GV50 PG-TO263-3 42744V5
TLE42744EV50 PG-SSOP-14 exposed pad 42744V5
TLE42744DV33 PG-TO252-3 4274433
TLE42744GV33 PG-TO263-3 42744V33
TLE42744GSV33 PG-SOT223-4 427443
Data Sheet 2 Rev. 1.3, 2018-03-05
PG-TO252-3
PG-TO263-3
PG-SSOP-14 exposed pad
PG-SOT223-4
Low Dropout Linear Voltage Regulator
1Overview
Features
• Very Low Current Consumption
• Output Voltages 5 V and 3.3 V ±2%
• Output Current up to 400 mA
• Very Low Dropout Voltage
• Output Current Limitation
• Reverse Polarity Protection
• Overtemperature Shutdown
• Wide Temperature Range
From -40 °C up to 150 °C
• Green Product (RoHS compliant)
• AEC Qualified
Description
The TLE42744 is a monolithic integrated low dropout voltage regulator for load currents up to 400 mA. An input
voltage up to 40 V is regulated to VQ,nom = 5 V / 3.3 V with a precision of ±2%. The device is designed for the harsh
environment of automotive applications. Therefore it is protected against overload, short circuit and
overtemperature conditions by the implemented output current limitation and the overtemperature shutdown
circuit. The TLE42744 can be also used in all other applications requiring a stabilized 5 V / 3.3 V voltage.
Due to its very low quiescent current the TLE42744 is dedicated for use in applications permanently connected to
VBAT.
TLE42744
Block Diagram
Data Sheet 3 Rev. 1.3, 2018-03-05
2 Block Diagram
Figure 1 Block Diagram
Ι
AEB01959
GND
Q
Bandgap
Reference
Control
Amplifier
Sensor
Temperature
Buffer
Saturation
Control and
Protection
Circuit
Data Sheet 4 Rev. 1.3, 2018-03-05
TLE42744
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment PG-TO252-3, PG-TO263-3 and PG-SOT223-4
Figure 2 Pin Configuration (top view)
3.2 Pin Definitions and Functions PG-TO252-3, PG-TO263-3 and PG-SOT223-4
Pin No. Symbol Function
1IInput
block to ground directly at the IC with a ceramic capacitor
2GNDGround
internally connected to heat slug
3QOutput
block to ground with a capacitor close to the IC terminals, respecting the values given
for its capacitance and ESR in “Functional Range” on Page 6
4 / Heat Slug – Heat Slug
internally connected to GND;
connect to GND and heatsink area
AEP02561
13
ΙQ
GND
GND
Ι
Q
AEP02281
PinConfig_PG-SOT223-
4.vsd
123
4
IGND
GND
Q
TLE42744
Pin Configuration
Data Sheet 5 Rev. 1.3, 2018-03-05
3.3 Pin Assignment PG-SSOP-14 exposed pad
Figure 3 Pin Configuration (top view)
3.4 Pin Definitions and Functions PG-SSOP-14 exposed pad
Pin No. Symbol Function
1, 2, 3, 5, 6, 7 n.c. Not connected
can be open or connected to GND
4GNDGround
8, 10, 11, 12,
14
n.c. Not connected
can be open or connected to GND
9QOutput
block to ground with a capacitor close to the IC terminals, respecting the values given
for its capacitance and ESR in “Functional Range” on Page 6
13 I Input
block to ground directly at the IC with a ceramic capacitor
Pad – Exposed Pad
connect to GND and heatsink area
n.c.
n.c.
Q
n.c.
n.c.
n.c.
I
n.c.
n.c.
n.c.
n.c.
GND
n.c.
n.c.
1
2
3
4
5
6
7
14
9
10
11
12
13
8
TLE7274-2_PINCONFIG_SSOP-
14.SVG
Data Sheet 6 Rev. 1.3, 2018-03-05
TLE42744
General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
4.2 Functional Range
Table 1 Absolute Maximum Ratings1)
Tj=-40 °C to 150 °C; all voltages with respect to ground, (unless otherwise specified)
1) not subject to production test, specified by design
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Input I
Voltage VI-42 – 45 V – P_4.1.1
Output Q
Voltage VQ-1 – 40 V – P_4.1.2
Temperature
Junction temperature Tj-40 – 150 °C – P_4.1.3
Storage temperature Tstg -50 – 150 °C – P_4.1.4
ESD Susceptibility
ESD Absorption VESD,HBM -4 – 4 kV Human Body Model
(HBM)2)
2) ESD susceptibility Human Body Model “HBM” according to AEC-Q100-002 - JESD22-A114
P_4.1.5
ESD Absorption VESD,CDM -1000 – 1000 V Charge Device Model
(CDM)3) at all pins
3) ESD susceptibility Charged Device Model “CDM” according to ESDA STM5.3.1
P_4.1.6
Table 2 Functional Range
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Input voltage VI5.5 – 40 V TLE42744DV50,
TLE42744GV50,
TLE42744EV50
P_4.2.1
Input voltage VI4.7 – 40 V TLE42744GV33,
TLE42744DV33,
TLE42744GSV33
P_4.2.2
TLE42744
General Product Characteristics
Data Sheet 7 Rev. 1.3, 2018-03-05
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Output Capacitor’s
Requirements for Stability
CQ22 – µF 1) P_4.2.3
Output Capacitor’s
Requirements for Stability
ESR(CQ)–32) P_4.2.4
Junction temperature Tj-40 150 °C – P_4.2.5
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
2) relevant ESR value at f=10kHz
Table 3 Thermal Resistance
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
TLE42744DV50, TLE42744DV33 (PG-TO252-3)
Junction to Case1) RthJC – 3.6 – K/W measured to heat slug P_4.3.1
Junction to Ambient1) RthJA – 27 – K/W FR4 2s2p board2) P_4.3.2
Junction to Ambient1) RthJA – 115 – K/W FR4 1s0p board,
footprint only3)
P_4.3.3
Junction to Ambient1) RthJA – 52 – K/W FR4 1s0p board,
300 mm² heatsink
area3)
P_4.3.4
Junction to Ambient1) RthJA – 40 – K/W FR4 1s0p board,
600 mm² heatsink
area3)
P_4.3.5
TLE42744GV50, TLE42744GV33 (PG-TO263-3)
Junction to Case1) RthJC – 3.6 – K/W measured to heat slug P_4.3.6
Junction to Ambient1) RthJA – 22 – K/W FR4 2s2p board2) P_4.3.7
Junction to Ambient1) RthJA – 74 – K/W FR4 1s0p board,
footprint only3)
P_4.3.8
Junction to Ambient1) RthJA – 42 – K/W FR4 1s0p board,
300 mm² heatsink
area3)
P_4.3.9
Junction to Ambient1) RthJA – 34 – K/W FR4 1s0p board,
600 mm² heatsink
area3)
P_4.3.10
Table 2 Functional Range (cont’d)
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Data Sheet 8 Rev. 1.3, 2018-03-05
TLE42744
General Product Characteristics
TLE42744EV50 (PG-SSOP-14 exposed pad)
Junction to Case1) RthJC – 7 – K/W measured to exposed
pad
P_4.3.11
Junction to Ambient1) RthJA – 43 – K/W FR4 2s2p board2) P_4.3.12
Junction to Ambient1) RthJA – 120 – K/W FR4 1s0p board,
footprint only3)
P_4.3.13
Junction to Ambient1) RthJA – 59 – K/W FR4 1s0p board,
300 mm² heatsink
area3)
P_4.3.14
Junction to Ambient1) RthJA – 49 – K/W FR4 1s0p board,
600 mm² heatsink
area3)
P_4.3.15
TLE42744GSV33 (PG-SOT223-4)
Junction to Case1) RthJC – 17 – K/W measured to heat slug P_4.3.16
Junction to Ambient1) RthJA – 54 – K/W FR4 2s2p board2) P_4.3.17
Junction to Ambient1) RthJA – 139 – K/W FR4 1s0p board,
footprint only3)
P_4.3.18
Junction to Ambient1) RthJA – 73 – K/W FR4 1s0p board,
300 mm² heatsink
area3)
P_4.3.19
Junction to Ambient1) RthJA – 64 – K/W FR4 1s0p board,
600 mm² heatsink
area3)
P_4.3.20
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Table 3 Thermal Resistance (cont’d)
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
TLE42744
Electrical Characteristics
Data Sheet 9 Rev. 1.3, 2018-03-05
5 Electrical Characteristics
5.1 Electrical Characteristics Voltage Regulator
Table 4 Electrical Characteristics
VI =13.5 V; Tj=-40 °C to 150 °C; all voltages with respect to ground (unless otherwise specified)
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Output Q
Output Voltage VQ4.9 5.0 5.1 V TLE42744DV50,
TLE42744GV50,
TLE42744EV50
5mA<IQ<400mA
6V<VI<28V
P_5.1.1
Output Voltage VQ4.9 5.0 5.1 V TLE42744DV50,
TLE42744GV50,
TLE42744EV50
5mA<IQ<200 mA
6V<VI<40V
P_5.1.2
Output Voltage VQ3.23 3.3 3.37 V TLE42744GV33,
TLE42744DV33,
TLE42744GSV33;
5mA<IQ<400mA
4.7 V < VI<28V
P_5.1.3
Output Voltage VQ3.23 3.3 3.37 V TLE42744GV33,
TLE42744DV33,
TLE42744GSV33;
5mA<IQ<200 mA
4.7 V < VI<40V
P_5.1.4
Dropout Voltage Vdr – 250 500 mV TLE42744DV50,
TLE42744GV50,
TLE42744EV50
IQ= 250 mA
Vdr =VI–VQ1)
P_5.1.5
Load Regulation VQ, lo – 20 50 mV TLE42744DV50,
TLE42744GV50,
TLE42744EV50;
IQ= 5 mA to 400 mA
VI=6V
P_5.1.6
Load Regulation VQ, lo – 40 70 mV TLE42744GV33,
TLE42744DV33,
TLE42744GSV33;
IQ= 5 mA to 300 mA
P_5.1.7
Line Regulation VQ, li – 1025mVVl= 12 V to 32 V
IQ=5mA
P_5.1.8
Data Sheet 10 Rev. 1.3, 2018-03-05
TLE42744
Electrical Characteristics
Output Current Limitation IQ400 600 1100 mA 1) P_5.1.9
Power Supply Ripple Rejection2) PSRR –60–dBfr=100Hz; Vr= 0.5 Vpp P_5.1.10
Temperature Output Voltage
Drift
– 0.5 – mV/K – P_5.1.11
Overtemperature Shutdown
Threshold
Tj,sd 151– 200°C Tj increasing2) P_5.1.12
Overtemperature Shutdown
Threshold Hysteresis
Tj,sdh –25–°CTj decreasing2) P_5.1.13
Current Consumption
Quiescent Current
Iq=II–IQ
Iq–100220µAIQ= 1 mA P_5.1.14
Current Consumption
Iq=II–IQ
Iq–815mAIQ= 250 mA P_5.1.15
Current Consumption
Iq=II–IQ
Iq– 15 25 mA TLE42744DV50,
TLE42744GV50,
TLE42744EV50;
IQ= 400 mA
P_5.1.16
Current Consumption
Iq=II–IQ
Iq– 20 30 mA TLE42744GV33,
TLE42744DV33,
TLE42744GSV33;
IQ= 400 mA
P_5.1.17
1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V.
2) not subject to production test, specified by design
Table 4 Electrical Characteristics (cont’d)
VI =13.5 V; Tj=-40 °C to 150 °C; all voltages with respect to ground (unless otherwise specified)
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
dVQ
dT
-----------
TLE42744
Electrical Characteristics
Data Sheet 11 Rev. 1.3, 2018-03-05
5.2 Typical Performance Characteristics Voltage Regulator
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Low Output Current IQ
Output Voltage Variation VQ versus
Junction Temperature TJ
Dropout Voltage Vdr versus
Output Current IQ (5 V versions only)
01_IQ_IQ.VSD
0
2
4
6
8
10
12
14
16
0 100 200 300 400
IQ [mA]
Iq
[mA]
V
I
= 13.5 V
T
j
= 25 °C
02_IQ_IQLOW.VSD
0
0,2
0,4
0,6
0,8
1
1,2
1,4
0 20406080100
IQ
[mA]
Iq
[mA]
V
I
= 13.5 V
T
j
= 25 °C
03_VQ_TJ.VSD
-0,5
-0,4
-0,3
-0,2
-0,1
0
0,1
0,2
0,3
0,4
0,5
-40 0 40 80 120
T
j
[°C]
Δ
V
Q
[%]
I
Q
= 5 mA
V
I
= 13.5 V
150
04_VDR_IQ.VSD
0
50
100
150
200
250
300
350
400
450
500
0 100 200 300 400
I
Q
[mA]
V
DR
[mV]
Tj
= 150 °C
Tj
= 25 °C
Tj
= -40 °C
Data Sheet 12 Rev. 1.3, 2018-03-05
TLE42744
Electrical Characteristics
Dropout Voltage Vdr versus
Junction Temperature (5 V versions only)
Maximum Output Current IQ versus
Input Voltage VI
Region Of Stability: Output Capacitor’s ESR
ESR(CQ) versus Output Current IQ
05_VDR_TJ.VSD
0
50
100
150
200
250
300
350
400
450
500
-40 0 40 80 120 160
T
j
[°C]
V
DR
[mV]
I
Q
= 400 mA
I
Q
= 100 mA
I
Q
= 10 mA
06 _ IQMAX_VI.VSD
0
100
200
300
400
500
600
700
800
900
010203040
V
I
[V]
I
Q,max
[mA]
V
Q
= V
Q,nom
- 100 mV
T
j
= -40 °C
T
j
= 25 °C
T
j
= 150 °C
07_ESR_IQ.VSD
0,01
0,1
1
10
0 100 200 300 400
IQ
[mA]
ESR(CQ)
[Ω]
CQ = 22 µF
VI = 13.5 V
Stable
Region
Unstable
Region
TLE42744
Application Information
Data Sheet 13 Rev. 1.3, 2018-03-05
6 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
6.1 Application Diagram
Figure 4 Application Diagram
6.2 Selection of External Components
6.2.1 Input Pin
The typical input circuitry for a linear voltage regulator is shown in the application diagram above.
A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high frequency
disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to the input pin
of the linear voltage regulator on the PCB.
An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to smooth
out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear
voltage regulator on the PCB.
An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum rating
of the linear voltage regulator and protect the device against any damage due to over-voltage.
The external components at the input are not mandatory for the operation of the voltage regulator, but they are
recommended in case of possible external disturbances.
6.2.2 Output Pin
An output capacitor is mandatory for the stability of linear voltage regulators.
The requirement to the output capacitor is given in “Functional Range” on Page 6. The graph “Region Of
Stability: Output Capacitor’s ESR ESR(CQ) versus Output Current IQ” on Page 12 shows the stable
operation range of the device.
Supply
100nF10µF
C
I1
C
I2
Regulated
Output Voltage
I
Q
C
Q
<45V
D
I
Load
(e.g.
Micro
Controller)
GND
I
I
Bandgap
Reference
GND
Q
I
Current
Limitation
Temperature
Shutdown
22µF
(ESR<3î Ť)
Data Sheet 14 Rev. 1.3, 2018-03-05
TLE42744
Application Information
TLE42744 is designed to be stable with extremely low ESR capacitors. According to the automotive environment,
ceramic capacitors with X5R or X7R dielectrics are recommended.
The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the
same side of the PCB as the regulator itself.
In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in accordance
and verified in the real application that the output stability requirements are fulfilled.
6.3 Thermal Considerations
Knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation
can be calculated:
(1)
with
•PD: continuous power dissipation
•VI: input voltage
•VQ: output voltage
•IQ: output current
•Iq: quiescent current
The maximum acceptable thermal resistance RthJA can then be calculated:
(2)
with
•Tj,max: maximum allowed junction temperature
•Ta: ambient temperature
Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with
reference to the specification in “Thermal Resistance” on Page 7.
Example
Application conditions:
VI= 13.5 V
VQ= 5 V
IQ= 250 mA
Ta= 85 °C
Calculation of RthJA,max:
PD=(VI – VQ) • IQ + VI • Iq
= (13.5 V – 5 V) • 250 mA + 13.5 V • 15 mA
= 2.125 W + 0.2025 W
= 2.3275 W
PDVIVQ
–()IQVIIq
Ă—+Ă—=
RthJA max,
Tjmax,Ta
–
PD
----------------------------=
TLE42744
Application Information
Data Sheet 15 Rev. 1.3, 2018-03-05
RthJA,max =(Tj,max – Ta) / PD
= (150 °C – 85 °C) / 2.3275 W
=27.93K/W
As a result, the PCB design must ensure a thermal resistance RthJA lower than 27.93 K/W. By considering
TLE42744GV50 (PG-TO263-3 package) and according to “Thermal Resistance” on Page 7, only the FR4 2s2p
board is applicable.
6.4 Reverse Polarity Protection
TLE42744 is self protected against reverse polarity faults and allows negative supply voltage. External reverse
polarity diode is not needed. However, the absolute maximum ratings of the device as specified in “Absolute
Maximum Ratings” on Page 6 must be kept.
The reverse voltage causes several small currents to flow into the IC hence increasing its junction temperature.
As the thermal shut down circuitry does not work in the reverse polarity condition, designers have to consider this
in their thermal design.
Data Sheet 16 Rev. 1.3, 2018-03-05
TLE42744
Package Outlines
7 Package Outlines
Figure 5 PG-TO252-3
5.4 ±0.1
-0.05
6.5 +0.15
A
±0.5
9.98
6.22 -0.2
1±0.1
±0.15
0.8
0.15 MAX.
±0.1
per side 0.75
2.28
4.57
+0.08
GPT09277
-0.04
0.5
2.3 -0.10
+0.05
B
0.51 MIN.
+0.08
-0.04
0.5
0...0.15
B
A0.25 M
0.1
All metal surfaces tin plated,
except area of cut.
3x
(5)
(4.24)
-0.01
+0.20
0.9
B
TLE42744
Package Outlines
Data Sheet 17 Rev. 1.3, 2018-03-05
Figure 6 PG-TO263-3
BA0.25
M
0.1
Typical
±0.2
GPT09362
10
8.5
1)
7.55
1)
(15)
±0.2
9.25
±0.3
1
0...0.15
5.08
2.54
0.75
±0.1
1.05
±0.1
1.27
4.4
B
0.5
±0.1
±0.3
2.7
4.7
±0.5
0.05
1)
0.1
All metal surfaces: tin plated, except area of cut.
2.4
Metal surface min. x=7.25, y=6.9
A
0...0.3
B
8Ëš MAX.
Data Sheet 18 Rev. 1.3, 2018-03-05
TLE42744
Package Outlines
Figure 7 PG-SSOP-14 exposed pad
17
14 8
14
17
8
14x
0.25
±0.05
±0.05
2)
M
0.15 DC A-B
0.65 C
STAND OFF
0.05
(1.45)
1.7 MAX.
0.08C
A
B
4.9
±0.11)
A-BH0.1 2x
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
Bottom View
±0.2
3
±0.2
2.65
±0.2
D
H
614x
0.64±0.25
3.9
±0.11)
0.35 x 45°
0.1 HD2x
0.2 C
+0.06
0.19
8
°
MAX.
Index
Marking
Exposed
Diepad
SEATING
PLANE
6 x 0.65 = 3.9
TLE42744
Package Outlines
Data Sheet 19 Rev. 1.3, 2018-03-05
Figure 8 PG-SOT223-4
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
SOT223-PO V04
123
3
4
±0.1
±0.04
0.5 MIN.
0.28
0.1 MAX.
6.5
±0.2
A
4.6
2.3
0.7
±0.1
0.25
M
A
1.6
±0.1
7
±0.3
B0.25
M
±0.2
3.5
B
0...10Ëš
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
Data Sheet 20 Rev. 1.3, 2018-03-05
TLE42744
Revision History
8 Revision History
Revision Date Changes
1.3 2018-03-05 Marking update in Chapter Overview (TLE42744GSV33 and TLE42744DV33)
Updated Template on the last page.
1.2 2014-07-03 Application Information added.
PG-TO252-3 and PG-SSOP-14 EP package outlines updated.
1.1 2010-01-13 Updated Version Data Sheet:
version TLE42744EV50 in PG-SSOP-14 exposed pad and all related description
added;
3.3V versions TLE42744GV33 in PG-TO263-3, TLE42744DV33 in PG-TO252-3
and TLE42744GSV33 in PG-SOT223-4 and all related description added
1.0 2009-01-14 Initial Version final Data Sheet
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2018-03-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics ("Beschaffenheitsgarantie").
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to
such application.
For further information on technology, delivery terms
and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or any
consequences of the use thereof can reasonably be
expected to result in personal injury.
