3-204
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
HFA1130/883
Output Clamping,
850MHz Current Feedback Amplifier
Description
The HFA1130/883 is a high speed, wideband current feed-
back amplifier featuring programmable output clamps. Built
with Intersil’ proprietary complementary bipolar UHF-1 pro-
cess, it is the fastest monolithic amplifier available from any
semiconductor manufacturer.
This amplifier is the ideal choice for high frequency applica-
tions requiring output limiting, especially those needing ultra
fast overdrive recovery times. The output clamp function
allows the designer to set the maximum positive and nega-
tive output levels, thereby protecting later stages from dam-
age or input saturation. The sub-nanosecond overdrive
recovery time quickly returns the amplifier to linear operation
following an overdrive condition.
The HFA1130/883’s wide bandwidth, fast settling character-
istic, and low output impedance, coupled with the output
clamping ability, make this amplifier ideal for driving fast A/D
converters.
Component and composite video systems will also benefit
from this amplifier ’s performance, as indicated by the excel-
lent gain flatness, and 0.03%/0.05 Degree Differential Gain/
Phase specifications (RL = 75Ω).
Ordering Information
PART NUMBER TEMPERATURE
RANGE PACKAGE
HFA1130MJ/883 -55oC to +125oC 8 Lead CerDIP
HFA1130ML/883 -55oC to +125oC 20 Lead Ceramic LCC
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• User Programmable Output Voltage Clamps
• Low Distortion (HD3, 30MHz) . . . . . . . . . . -84dBc (Typ)
• Wide -3dB Bandwidth . . . . . . . . . . . . . . . 850MHz (Typ)
• Very High Slew Rate . . . . . . . . . . . . . . . 2300V/µs (Typ)
• Fast Settling (0.1%) . . . . . . . . . . . . . . . . . . . . 11ns (Typ)
• Excellent Gain Flatness (to 50MHz) . . . . . 0.05dB (Typ)
• High Output Current . . . . . . . . . . . . . . . . . . 65mA (Typ)
• Fast Overdrive Recovery. . . . . . . . . . . . . . . . <1ns (Typ)
Applications
• Residue Amplifier
• Video Switching and Routing
• Pulse and Video Amplifiers
• Wideband Amplifiers
• RF/IF Signal Processing
• Flash A/D Driver
• Medical Imaging Systems
July 1994
Pinouts
HFA1130/883
(CERDIP)
TOP VIEW
HFA1130/883
(CLCC)
TOP VIEW
NC
-IN
+IN
V-
1
2
3
4
8
7
6
5
VH
V+
OUT
VL
+
- NC
-IN
NC
+IN
NC
NC
NC
NC
NC
NC
NC
V-
VL
NC
NC
VH
V+
NC
OUT
NC
4
5
6
7
8
10 11 12 139
3212019
16
17
18
15
14
+
-
Spec Number 511082-883
File Number 3625.1
3-205
Specifications HFA1130/883
Absolute Maximum Ratings Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to V-
Voltage at VH or VL Terminal . . . . . . . . . . . . . .(V+) + 2V to (V-) - 2V
Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . .±55mA
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .< 2000V
Storage Temperature Range . . . . . . . . . . . . . .-65oC ≤ TA≤ +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
Thermal Resistance θJA θJC
CerDIP Package . . . . . . . . . . . . . . . . . . . 115oC/W 30oC/W
Ceramic LCC Package . . . . . . . . . . . . . . 75oC/W 23oC/W
Maximum Package Power Dissipation at +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.87W
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.33W
Package Power Dissipation Derating Factor above +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.7mW/oC
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . .13.3mW/oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5V
Operating Temperature Range. . . . . . . . . . . . .-55oC≤ TA≤ +125oCRL ≥ 50Ω
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: VSUPPLY = ±5V, AV = +1, RF = 510Ω, RSOURCE = 0Ω, RL = 100Ω, VOUT = 0V, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Input Offset Voltage VIO VCM = 0V 1 +25oC-66mV
2, 3 +125oC, -55oC -10 10 mV
Common Mode
Rejection Ratio CMRR ∆VCM = ±2V
V+ = 3V, V- = -7V
V+ = 7V, V- = -3V
1 +25oC40-dB
2, 3 +125oC, -55oC38 - dB
Power Supply
Rejection Ratio PSRRP ∆VSUP = ±1.25V
V+ = 6.25V, V- = -5V
V+ = 3.75V, V- = -5V
1 +25oC45-dB
2, 3 +125oC, -55oC42 - dB
PSRRN ∆VSUP = ±1.25V
V+ = 5V, V- = -6.25V
V+ = 5V, V- = -3.75V
1 +25oC45-dB
2, 3 +125oC, -55oC42 - dB
Non-Inverting Input
(+IN) Current IBSP VCM = 0V 1 +25oC -40 40 µA
2, 3 +125oC, -55oC -65 65 µA
+IN Current Common
Mode Sensitivity CMSIBP ∆VCM = ±2V
V+ = 3V, V- = -7V
V+ = 7V, V- = -3V
1 +25oC-40µA/V
2, 3 +125oC, -55oC-50µA/V
+IN Resistance +RIN Note 1 1 +25oC25-kΩ
2, 3 +125oC, -55oC20 - kΩ
Inverting Input (-IN)
Current IBSN VCM = 0V 1 +25oC -50 50 µA
2, 3 +125oC, -55oC -75 75 µA
-IN Current Common
Mode Sensitivity CMSIBN ∆VCM = ±2V
V+ = 3V, V- = -7V
V+ = 7V, V- = -3V
1 +25oC-7µA/V
2, 3 +125oC, -55oC-10µA/V
-IN Current Power
Supply Sensitivity PPSSIBN ∆VSUP = ±1.25V
V+ = 6.25V, V- = -5V
V+ = 3.75V, V- = -5V
1 +25oC-15µA/V
2, 3 +125oC, -55oC-27µA/V
NPSSIBN ∆VSUP = ±1.25V
V+ = 5V, V- = -6.25V
V+ = 5V, V- = -3.75V
1 +25oC-15µA/V
2, 3 +125oC, -55oC-27µA/V
Output Voltage Swing VOP100 AV = -1
RL =100ΩVIN = 3.5V 1 +25oC3-V
VIN = -3V 2, 3 +125oC, -55oC 2.5 - V
VON100 AV = -1
RL =100ΩVIN =+3.5V 1 +25oC - -3 V
VIN = +3V 2, 3 +125oC, -55oC - -2.5 V
Spec Number 511082-883
3-206
Specifications HFA1130/883
Output Voltage Swing VOP50 AV = -1
RL = 50ΩVIN = -3V 1, 2 +25oC, +125oC 2.5 - V
VIN = -2V 3 -55oC 1.5 - V
VON50 AV = -1
RL = 50ΩVIN = +3V 1, 2 +25oC, +125oC - -2.5 V
VIN = +2V 3 -55oC - -1.5 V
Output Current +IOUT Note 2 1, 2 +25oC, +125oC50 - mA
3 -55oC30-mA
-IOUT Note 2 1, 2 +25oC, +125oC - -50 mA
3 -55oC - -30 mA
Quiescent Power
Supply Current ICC RL = 100Ω1 +25oC1426mA
2, 3 +125oC, -55oC - 33 mA
IEE RL = 100Ω1 +25oC -26 -14 mA
2, 3 +125oC, -55oC -33 - mA
Clamp Accuracy VHCLMP AV = -1, VIN = -2V
VH = 1V 1 +25oC -125 125 mV
2, 3 +125oC, -55oC -200 200 mV
VLCLMP AV = -1, VIN = +2V
VL = -1V 1 +25oC -125 125 mV
2, 3 +125oC, -55oC -200 200 mV
Clamp Input Current VHBIAS VH = 1V 1 +25oC - 200 µA
2, 3 +125oC, -55oC - 300 µA
VLBIAS VL = -1V 1 +25oC -200 - µA
2, 3 +125oC, -55oC -300 - µA
NOTES:
1. Guaranteed from +IN Common Mode Rejection Test, by: +RIN = 1/CMSIBP.
2. Guaranteed from VOUT Test with RL = 50Ω, by: IOUT = VOUT/50Ω.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: VSUPPLY = ±5V, AV = +2, RF = 360Ω, RL = 100Ω, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
-3dB Bandwidth BW(-1) AV = -1, RF = 430Ω
VOUT = 200mVP-P
1 +25oC 300 - MHz
BW(+1) AV = +1, RF = 510Ω
VOUT = 200mVP-P
1 +25oC 550 - MHz
BW(+2) AV = +2, VOUT = 200mVP-P 1 +25oC 350 - MHz
Gain Flatness GF30 AV = +2, RF = 510Ω, f ≤ 30MHz
VOUT = 200mVP-P
1 +25oC-±0.04 dB
GF50 AV = +2, RF = 510Ω, f ≤ 50MHz
VOUT = 200mVP-P
1 +25oC-±0.10 dB
GF100 AV = +2, RF = 510Ω, f ≤ 100MHz,
VOUT = 200mVP-P
1 +25oC-±0.30 dB
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: VSUPPLY = ±5V, AV = +1, RF = 510Ω, RSOURCE = 0Ω, RL = 100Ω, VOUT = 0V, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Spec Number 511082-883
3-207
Specifications HFA1130/883
Slew Rate +SR(+1) AV = +1, RF = 510Ω
VOUT = 5VP-P
1, 2 +25oC 1200 - V/µs
-SR(+1) AV = +1, RF = 510Ω
VOUT = 5VP-P
1, 2 +25oC 1100 - V/µs
+SR(+2) AV = +2, VOUT = 5VP-P 1, 2 +25oC 1650 - V/µs
-SR(+2) AV = +2, VOUT = 5VP-P 1, 2 +25oC 1500 - V/µs
Rise and Fall Time TRAV = +2, VOUT = 0.5VP-P 1, 2 +25oC-1ns
TFAV = +2, VOUT = 0.5VP-P 1, 2 +25oC-1ns
Overshoot +OS AV = +2, VOUT = 0.5VP-P 1, 3 +25oC - 25 %
-OS AV = +2, VOUT = 0.5VP-P 1, 3 +25oC - 20 %
Settling Time TS(0.1) AV = +2, RF = 510Ω
VOUT = 2V to 0V, to 0.1% 1 +25oC - 20 ns
TS(0.05) AV = +2, RF = 510Ω
VOUT = 2V to 0V, to 0.05% 1 +25oC - 33 ns
2nd Harmonic
Distortion HD2(30) AV = +2, f = 30MHz
VOUT = 2VP-P
1 +25oC - -48 dBc
HD2(50) AV = +2, f = 50MHz
VOUT = 2VP-P
1 +25oC - -45 dBc
HD2(100) AV = +2, f = 100MHz
VOUT = 2VP-P
1 +25oC - -35 dBc
3rd Harmonic
Distortion HD3(30) AV = +2, f = 30MHz
VOUT = 2VP-P
1 +25oC - -65 dBc
HD3(50) AV = +2, f = 50MHz
VOUT = 2VP-P
1 +25oC - -60 dBc
HD3(100) AV = +2, f = 100MHz
VOUT = 2VP-P
1 +25oC - -40 dBc
NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These param-
eters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization
based upon data from multiple production runs which reflect lot-to-lot and within lot variation.
2. Measured between 10% and 90% points.
3. For 200ps input transition times. Overshoot decreases as input transition times increase, especially for AV = +1. Please refer to
Performance Curves.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1)
Interim Electrical Parameters (Pre Burn-In) 1
Final Electrical Test Parameters 1 (Note 1), 2, 3
Group A Test Requirements 1, 2, 3
Groups C and D Endpoints 1
NOTE:
1. PDA applies to Subgroup 1 only.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: VSUPPLY = ±5V, AV = +2, RF = 360Ω, RL = 100Ω, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Spec Number 511082-883
3-208
HFA1130/883
Die Characteristics
DIE DIMENSIONS:
63 x 44 x 19 mils ± 1 mils
1600 x 1130 x 483µm± 25.4µm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW Type: Metal 2: AICu(2%)
Thickness: Metal 1: 8kű0.4kÅThickness: Metal 2: 16kű0.8kÅ
GLASSIVATION:
Type: Nitride
Thickness: 4kű 0.5kÅ
WORST CASE CURRENT DENSITY:
2.0 x 105 A/cm2at 47.5mA
TRANSISTOR COUNT: 52
SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1130/883
+IN
V-
VL
BAL
OUT
-IN
BAL
VH
V+
Spec Number 511082-883
3-209
HFA1130/883
Test Circuit
(Applies to Table 1)
Test Waveforms
SIMPLIFIED TEST CIRCUIT FOR LARGE AND SMALL SIGNAL PULSE RESPONSE (Applies to Table 3)
AV = +1 TEST CIRCUIT AV = +2 TEST CIRCUIT
LARGE SIGNAL WAVEFORM SMALL SIGNAL WAVEFORM
V+
ICC 10 0.1
50
K3
7
5
DUT
-
+
2
3
4
8
510
VIN
-
+
HA-5177
200pF
100K (0.01%)
VZ
VXx100 -
+470pF
VIO = VX
100
+IBIAS = VZ
100K
10 0.1
V-
IEE
VH
-IBIAS = VX
50K K5
100 100
VOUT
All Resistors = ±1% (Ω)
All Capacitors = ±10% (µF)
Unless Otherwise Noted
6
+
+
0.1
100
0.1
0.1
NC
VL0.1
50
0.1
K4
0.1
K1 NC
510
0.1
1K
510
510
0.1
K2
NC
2
1
K2 = POSITION 1:
K2 = POSITION 2:
0.1
Chip Components Recommended
Terminal Numbers Refer to CDIP Package
NOTE:
-
+
VIN RS
50Ω
V+
RF
510ΩV-
NOTE: VS = ±5V, AV = +1
RS = 50Ω
RL = 100Ω For Small and Large Signals
VOUT
50Ω
50Ω2-
+
VIN RS
50ΩRF
V+
V-
360Ω
RG
360Ω
NOTE: VS = ±5V, AV = +2
RS = 50Ω
VOUT
50Ω
50Ω2
RL=100Ω For Small and Large Signals
+2.5V
-SR
+2.5V
+SR
VOUT
-2.5V -2.5V
90%
10%
90%
10%
90%
10%
90%
10%
+250mV
TF , -OS
+250mV
TR , +OS
VOUT
-250mV -250mV
Spec Number 511082-883
3-210
HFA1130/883
Burn-In Circuits
HFA1130MJ/883 CERAMIC DIP
NOTES:
R1 = R2 = 1kΩ,±5% (Per Socket)
R3 = 10kΩ,±5% (Per Socket)
C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum
D1 = D2 = 1N4002 or Equivalent (Per Board)
D3 = D4 = 1N4002 or Equivalent (Per Socket)
V+ = +5.5V ± 0.5V
V- = -5.5V ± 0.5V
HFA1130ML/883 CERAMIC LCC
NOTES:
R1 = R2 = 1kΩ,±5% (Per Socket)
R3 = 10kΩ,±5% (Per Socket)
C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum
D1 = D2 = 1N4002 or Equivalent (Per Board)
D3 = D4 = 1N4002 or Equivalent (Per Socket)
V+ = +5.5V ± 0.5V
V- = -5.5V ± 0.5V
1
2
3
4
8
7
6
5
V+
C1 D1
D2 C2
V-
-
+
D4
D3
R3
R2
R1
V+
C1 D1
D2
V- D4
D3
R3
R2
R1
4
5
6
7
8
9101112
13
3212019
15
14
18
17
16
+
-
C2
Spec Number 511082-883
3-211
HFA1130/883
Packaging
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b1.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling Dimension: Inch
11. Lead Finish: Type A.
12. Materials: Compliant to MIL-I-38535.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
eA
ccc C A - B
MD
SSaaa C A - B
MD
SS
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD DUAL-IN-LINE FRIT-SEAL CERAMIC PACKAGE
SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.405 - 10.29 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
S2 0.005 - 0.13 - -
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2
N8 88
Spec Number 511082-883
3-212
HFA1130/883
Packaging
(Continued)
D
j x 45o
D3
B
h x 45o
AA1
E
LL3
e
B3
B1
L1
D2
D1
e1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.381mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals
shall be ellectrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Maximum limits allows for 0.007 inch solder thickness on pads.
8. Lead Finish: Type A.
9. Materials: Compliant to MIL-I-38535.
J20.A MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER
SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX
A 0.060 0.100 1.52 2.54 6, 7
A1 0.050 0.088 1.27 2.23 7
B----4
B1 0.022 0.028 0.56 0.71 2, 4
B2 0.072 REF 1.83 REF -
B3 0.006 0.022 0.15 0.56 -
D 0.342 0.358 8.69 9.09 -
D1 0.200 BSC 5.08 BSC -
D2 0.100 BSC 2.54 BSC -
D3 - 0.358 - 9.09 2
E 0.342 0.358 8.69 9.09 -
E1 0.200 BSC 5.08 BSC -
E2 0.100 BSC 2.54 BSC -
E3 - 0.358 - 9.09 2
e 0.050 BSC 1.27 BSC -
e1 0.015 - 0.38 - 2
h 0.040 REF 1.02 REF 5
j 0.020 REF 0.51 REF 5
L 0.045 0.055 1.14 1.40 -
L1 0.045 0.055 1.14 1.40 -
L2 0.075 0.095 1.90 2.41 -
L3 0.003 0.015 0.08 0.38 -
ND 5 5 3
NE 5 5 3
N20 203
Spec Number 511082-883
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
3-213
DESIGN INFORMATION
August 1999
Semiconductor
Typical Performance Curves
VSUPPLY = ±5V, RF = 510Ω, TA = +25oC, RL = 100Ω, Unless Otherwise Specified.
SMALL SIGNAL PULSE RESPONSE LARGE SIGNAL PULSE RESPONSE
UNCLAMPED PERFORMANCE CLAMPED PERFORMANCE
120
5ns/DIV
90
60
30
0
-30
-60
-90
-120
OUTPUT VOLTAGE (mV)
AV = +2
5ns/DIV
OUTPUT VOLTAGE (V)
1.2
0.9
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
AV = +2
IN
0V TO 0.5V
OUT
0V TO 1V
10ns/DIV
AV = +2, VH = 2V, VL = -2V
IN
0V TO 1V
OUT
0V TO 1V
10ns/DIV
AV = +2, VH = 1V, VL = -1V, 2X OVERDRIVE
HFA1130
Output Clamping, Ultra High Speed
Current Feedback Amplifier
Spec Number 511082-883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
3-214
HFA1130
NON-INVERTING FREQUENCY RESPONSE INVERTING FREQUENCY RESPONSE
FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
Typical Performance Curves
VSUPPLY = ±5V, RF = 510Ω, TA = +25oC, RL = 100Ω, Unless Otherwise Specified.
(Continued)
FREQUENCY (MHz)
0
-3
-6
-9
-12
GAIN (dB) NORMALIZED
0.3 1 10 100 1K
0
-90
-180
-270
-360
PHASE (DEGREES)
PHASE
GAIN
AV = +1
AV = +6
AV = +2
VOUT = 200mVP-P
AV = +11
AV = +1
AV = +6
AV = +2
AV = +11
FREQUENCY (MHz)
PHASE
0
-3
-6
-9
-12
GAIN (dB) NORMALIZED
0.3 1 10 100 1K
180
90
0
-90
-180
PHASE (DEGREES)
AV = -5
AV = -1
AV = -10
AV = -20
AV = -20
AV = -10
AV = -5
AV = -1
VOUT = 200mVP-P
GAIN
FREQUENCY (MHz)
+6
+3
0
-3
-6
GAIN (dB)
0.3 1 10 100 1K
0
-90
-180
-270
-360
PHASE (DEGREES)
PHASE
GAIN
RL = 1kΩ
RL = 100Ω
RL = 50Ω
RL = 100Ω
RL = 50Ω
RL = 100Ω
RL = 1kΩ
AV = +1, VOUT = 200mVP-P RL = 1kΩ
FREQUENCY (MHz)
PHASE
+3
0
-3
-6
GAIN (dB) NORMALIZED
0.3 1 10 100 1K
0
-90
-180
-270
-360
PHASE (DEGREES)
RL = 100Ω
RL = 1kΩ
RL = 50Ω
RL = 100ΩRL = 1kΩ
RL = 50Ω
RL = 100Ω
RL = 1kΩ
AV = +2, VOUT = 200mVP-P
GAIN
FREQUENCY (MHz)
+20
+10
0
-10
-20
GAIN (dB)
0.3 1 10 100 1K
-30
0.500VP-P
0.920VP-P
1.63VP-P
0.160VP-P
AV = +1
FREQUENCY (MHz)
+20
+10
0
-10
-20
GAIN (dB) NORMALIZED
0.3 1 10 100 1K
-30
1.00VP-P
1.84VP-P
3.26VP-P
0.32VP-P
AV = +2
Spec Number 511082-883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
3-215
HFA1130
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES -3dB BANDWIDTH vs TEMPERATURE
GAIN FLATNESS DEVIATION FROM LINEAR PHASE
SETTLING RESPONSE 3rd ORDER INTERMODULATION INTERCEPT
Typical Performance Curves
VSUPPLY = ±5V, RF = 510Ω, TA = +25oC, RL = 100Ω, Unless Otherwise Specified.
(Continued)
FREQUENCY (MHz)
+20
+10
0
-10
-20
GAIN (dB) NORMALIZED
0.3 1 10 100 1K
-30
0.96VP-P
3.89VP-P
TO
AV = +6
TEMPERATURE (oC)
950
900
850
800
750
BANDWIDTH (MHz)
-50 -25 0 +75 +125
700
+25 +50 +100
AV = +1
FREQUENCY (MHz)
0
-0.05
-0.10
GAIN (dB)
1 10 100
-0.15
-0.20
AV = +2 +2.0
+1.5
+1.0
+0.5
0
-0.5
-1.0
-1.5
-2.0
0 15 30 45 60 75 90 105 120 135 150
FREQUENCY (MHz)
DEVIATION (DEGREES)
AV = +2
TIME (ns)
0.6
0.4
0.2
0
SETTLING ERROR (%)
-4 1 6 21 31
-0.2
11 16 26 36 41 46
-0.4
-0.6
AV = +2, VOUT = 2V
FREQUENCY (MHz)
40
35
30
25
20
INTERCEPT POINT (dBm)
0 100 200
15
300 400
10
5
0
2-TONE
Spec Number 511082-883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
3-216
HFA1130
2nd HARMONIC DISTORTION vs POUT 3rd HARMONIC DISTORTION vs POUT
OVERSHOOT vs INPUT RISE TIME OVERSHOOT vs INPUT RISE TIME
OVERSHOOT vs FEEDBACK RESISTOR SUPPLY CURRENT vs TEMPERATURE
Typical Performance Curves
VSUPPLY = ±5V, RF = 510Ω, TA = +25oC, RL = 100Ω, Unless Otherwise Specified.
(Continued)
OUTPUT POWER (dBm)
-30
-35
-40
-45
-50
DISTORTION (dBc)
-5 3
-55
-60
-65
-70 -3 -1 1 5 7 9 11 13 15
100MHz
50MHz
30MHz
OUTPUT POWER (dBm)
-30
-40
-50
-60
-70
DISTORTION (dBc)
-5 3
-80
-90
-100
-110 -3 -1 1 5 7 9 11 13 15
100MHz
50MHz
30MHz
INPUT RISE TIME (ps)
38
36
34
32
30
OVERSHOOT (%)
100 500
28
26
24
22
200 300 400 600 700 800 900 1000
VOUT = 1VP-P
VOUT = 2VP-P
VOUT = 0.5VP-P
20
18
16
14
12
10
8
6
AV = +1
INPUT RISE TIME (ps)
35
30
25
20
15
OVERSHOOT (%)
100 500
10
5
0200 300 400 600 700 800 900 1000
RF = 360Ω
VOUT = 2VP-P
RF =510Ω
VOUT = 1VP-P
RF = 360Ω
VOUT = 1VP-P
RF = 360Ω
VOUT = 0.5VP-P
RF = 510Ω
VOUT = 2VP-P
AV = +2
VOUT = 0.5VP-P
RF = 510Ω
FEEDBACK RESISTOR (Ω)
36
34
32
30
OVERSHOOT (%)
360 520
28
26
24
22
400 440 480 560 600 640 680
20
18
16
14
12
10
8
6
4
AV = +2, tR = 200ps, VOUT = 2VP-P
TEMPERATURE (oC)
25
24
23
22
21
SUPPLY CURRENT (mA)
-60 +20
20
19
18 -40 -20 0 +40 +60 +80 +100 +120
Spec Number 511082-883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
3-217
HFA1130
SUPPLY CURRENT vs SUPPLY VOLTAGE VIO AND BIAS CURRENTS vs TEMPERATURE
OUTPUT VOLTAGE vs TEMPERATURE INPUT NOISE vs FREQUENCY
NON-LINEARITY NEAR CLAMP VOLTAGE
Typical Performance Curves
VSUPPLY = ±5V, RF = 510Ω, TA = +25oC, RL = 100Ω, Unless Otherwise Specified.
(Continued)
TOTAL SUPPLY VOLTAGE (V+ - V-, V)
22
17
15
13
11
SUPPLY CURRENT (mA)
59
9
7
5678 10
21
20
19
6
8
10
12
14
16
18
TEMPERATURE (oC)
45
42
39
36
33
BIAS CURRENTS (µA)
-60
30
27
24
-40 -20 0
21
18
15
12
9
6
3
0
2.8
2.7
2.6
2.5
2.4
INPUT OFFSET VOLTAGE (mV)
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
+IBIAS
VIO
-IBIAS
+20 +40 +60 +80 +100+120
TEMPERATURE (oC)
3.7
3.6
3.5
3.4
OUTPUT VOLTAGE (V)
-60
3.3
3.2
3.1
3.0
-40 -20 0
2.9
2.8
2.7
2.6
2.5
| - VOUT |
+VOUT
AV = -1, RL = 50Ω
+20 +40 +60 +80 +100+120
300
275
250
225
200
175
150
125
100
75
50
25
0
30
25
20
15
10
5
0
100 1K 10K 100K
FREQUENCY (Hz)
NOISE VOLTAGE (nV/√Hz)
NOISE CURRENT (pA/√Hz)
ENI
INI-
INI+
20
15
10
5
0
-5
-10
-15
-20
VOUT - (AV * VIN) (mV)
-3 -2 -1 0 1 2 3
AV * VIN (V)
VL = -3V VL = -1V
VL = -2V
VH = 1V VH = 2V
AV = -1, RL = 100Ω
VH = 3V
Spec Number 511082-883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
3-218
HFA1130
Application Information
Optimum Feedback Resistor
The enclosed plots of inverting and non-inverting frequency
response illustrate the performance of the HFA1130 in
various gains. Although the bandwidth dependency on
closed loop gain isn’t as severe as that of a voltage feedback
amplifier, there can be an appreciable decrease in
bandwidth at higher gains. This decrease may be minimized
by taking advantage of the current feedback amplifier’s
unique relationship between bandwidth and RF. All current
feedback amplifiers require a feedback resistor, even for
unity gain applications, and RF, in conjunction with the
internal compensation capacitor, sets the dominant pole of
the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to RF. The HFA1130 design is
optimized for a 510Ω RF at a gain of +1. Decreasing RF in a
unity gain application decreases stability, resulting in
excessive peaking and overshoot. At higher gains the
amplifier is more stable, so RF can be decreased in a trade-
off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth.
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resis-
tors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. To this end, it is
GAIN
(ACL)R
F (Ω)BANDWIDTH
(MHz)
-1 430 580
+1 510 850
+2 360 670
+5 150 520
+10 180 240
+19 270 125
recommended that the ground plane be removed under
traces connected to -IN, and connections to -IN should be
kept as short as possible.
An example of a good high frequency layout is the Evalua-
tion Board shown in Figure 2.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this resis-
tor. The points on the curve indicate the RS and CL combina-
tions for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.
RS and CL form a low pass network at the output, thus limit-
ing system bandwidth well below the amplifier bandwidth of
850MHz. By decreasing RS as CL increases (as illustrated in
the curves), the maximum bandwidth is obtained without
sacrificing stability. Even so, bandwidth does decrease as
you move to the right along the curve. For example, at
AV=+1, RS = 50Ω, CL=30pF, the overall bandwidth is lim-
ited to 300MHz, and bandwidth drops to 100MHz at A V = +1,
RS = 5Ω, CL=340pF.
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1130 may be evaluated using
the HFA11XX Evaluation Board.
The layout and schematic of the board are shown in Figure
2. To order evaluation boards, please contact your local
sales office.
RS (Ω)
LOAD CAPACITANCE (pF)
50
45
40
35
30
25
20
15
10
5
00 40 80 120 160 200 240 280 320 360 400
AV = +1
AV = +2
Spec Number 511082-883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
3-219
HFA1130
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
Clamp Operation
General
The HFA1130 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the VH and VL terminals (DIP pins 8
and 5) of the amplifier. VH sets the upper output limit, while
VL sets the lower clamp level. If the amplifier tries to drive the
output above VH, or below VL, the clamp circuitry limits the
output voltage at VH or VL (± the clamp accuracy), respec-
tively. The low input bias currents of the clamp pins allow
them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
VH
+IN
VLV+
GND
1
V-
OUT
TOP LAYOUT
BOTTOM LAYOUT
1
2
3
4
8
7
6
5
+5V
10µF
0.1µF
VH
50Ω
GND GND
R1
-5V
0.1µF
10µF
50Ω
IN OUT
VL
500 500
FIGURE 3. HFA1130 SIMPLIFIED VH CLAMP CIRCUITRY
Clamp Circuitry
Figure 3 shows a simplified schematic of the HFA1130 input
stage, and the high clamp (VH) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QX1 - QX2)
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
(V-IN - VOUT)/RF + V-IN / RG
where RG is the gain setting resistor from -IN to GND. This
current is mirrored onto the high impedance node (Z) by
QX3 - QX4, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
by QP4 and QN4. Note that when the output reaches it’s qui-
escent value, the current flowing through -IN is reduced to
only that small current (-IBIAS) required to keep the output at
the final voltage.
Tracing the path from VH to Z illustrates the effect of the
clamp voltage on the high impedance node. VH decreases
by 2VBE (QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node
reaches a voltage equal to QP5’s base voltage + 2VBE (QP5
and QN5). Thus, QP5 clamps node Z whenever Z reaches
VH. R1 provides a pull-up network to ensure functionality
with the clamp inputs floating. A similar description applies to
the symmetrical low clamp circuitry controlled by VL.
+1
+IN V-
V+
QP1
QN1
V-
QN3
QP3 QP4
QN2
QP2
QN4 QP5
QN5
Z
V+
-IN VOUT
ICLAMP
RF
(EXTERNAL)
QP6
QN6 VH
R1 50K
(30K
FOR VL)
Spec Number 511082-883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
3-220
HFA1130
When the output is clamped, the negative input continues to
source a slewing current (ICLAMP) in an attempt to force the out-
put to the quiescent voltage defined by the input. QP5 must
sink this current while clamping, because the -IN current is
always mirrored onto the high impedance node. The clamping
current is calculated as:
ICLAMP = (V-IN - VOUT CLAMPED) / RF + V-IN / RG.
As an example, a unity gain circuit with VIN = 2V, VH = 1V, and
RF = 510Ωwould have ICLAMP = (2V - 1V) / 510Ω + 2V / ∞=
1.96mA. Note that Icc will increase by ICLAMP when the output
is clamp limited.
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
voltage applied to VH or VL Offset errors, mostly due to VBE
mismatches, necessitate a clamp accuracy parameter which
is found in the device specifications. Clamp accuracy is a
function of the clamping conditions. Referring again to Figure
3, it can be seen that one component of clamp accuracy is the
VBE mismatch between the QX6 transistors, and the QX5
transistors. If the transistors always ran at the same current
level there would be no VBE mismatch, and no contribution to
the inaccuracy. The QX6 transistors are biased at a constant
current, but as described earlier, the current through QX5 is
equivalent to ICLAMP. VBE increases as ICLAMP increases,
causing the clamped output voltage to increase as well.
ICLAMP is a function of the overdrive level (AVCL x VIN - VOUT
CLAMPED) and RF, so clamp accuracy degrades as the over-
drive increases, and as RF decreases. As an example, the
specified accuracy of ±60mV for a 2X overdrive with
RF=510Ω degrades to ±220mV for RF= 240Ω at the same
overdrive, or to ±250mV for a 3X overdrive with RF = 510Ω.
Consideration must also be given to the fact that the clamp
voltages have an effect on amplifier linearity. The “Nonlinearity
Near Clamp Voltage” curve in the data sheet illustrates the
impact of several clamp levels on linearity.
Clamp Range
Unlike some competitor devices, both VH and VL have usable
ranges that cross 0V. While VH must be more positive than VL,
both may be positive or negative, within the range restrictions
indicated in the specifications. For example, the HFA1130
could be limited to ECL output levels by setting VH = -0.8V
and VL = -1.8V. VH and VL may be connected to the same
voltage (GND for instance) but the result won’t be in a DC out-
put voltage from an AC input signal. A 150mV - 200mV AC
signal will still be present at the output.
Recovery from Overdrive
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
below the overdrive level (VCLAMP / AVCL) the amplifier will
return to linear operation. A time delay, known as the Over-
drive Recovery Time, is required for this resumption of linear
operation. The plots of “Unclamped Performance” and
“Clamped Performance” highlight the HFA1130’s subnano-
second recovery time. The difference between the
unclamped and clamped propagation delays is the overdrive
recovery time. The appropriate propagation delays are 4.0ns
for the unclamped pulse, and 4.8ns for the clamped (2X
overdrive) pulse yielding an overdrive recovery time of
800ps. The measurement uses the 90% point of the output
transition to ensure that linear operation has resumed. Note:
The propagation delay illustrated is dominated by the fixtur-
ing. The delta shown is accurate, but the true HF A1130 prop-
agation delay is 500ps.
Spec Number 511082-883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
3-221
HFA1130
TYPICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: VSUPPLY = ±5V, RF = 360Ω, AV = +2V/V, RL = 100Ω, Unless Otherwise Specified
PARAMETERS CONDITIONS TEMPERATURE TYPICAL UNITS
Input Offset Voltage * VCM = 0V +25oC2 mV
Average Offset Voltage Drift Versus Temperature Full 10 µV/oC
VIO CMRR ∆VCM = ±2V +25oC46 dB
VIO PSRR ∆VS = ±1.25V +25oC50 dB
+Input Current * VCM = 0V +25oC25 µA
Average +Input Current Drift Versus Temperature Full 40 nA/oC
-Input Current * VCM = 0V +25oC12 µA
Average -Input Current Drift Versus Temperature Full 40 nA/oC
+Input Resistance ∆VCM = ±2V +25oC50 kΩ
-Input Resistance +25oC16 Ω
Input Capacitance +25oC 2.2 pF
Input Noise Voltage * f = 100kHz +25oC 4 nV/√Hz
+Input Noise Current * f = 100kHz +25oC 18 pA/√Hz
-Input Noise Current * f = 100kHz +25oC 21 pA/√Hz
Input Common Mode Range Full ±3.0 V
Open Loop
Transimpedance AV= -1 +25oC 500 kΩ
Output Voltage AV = -1, RL = 100Ω+25oC±3.3 V
AV = -1, RL = 100ΩFull ±3.0 V
Output Current * AV = -1, RL = 50Ω+25oC to +125oC±65 mA
AV = -1, RL = 50Ω-55oC to 0oC±50 mA
DC Closed Loop Output
Resistance +25oC 0.1 Ω
Quiescent Supply Current * RL = Open Full 24 mA
-3dB Bandwidth * AV = -1, RF = 430Ω, VOUT = 200mVP-P +25oC 580 MHz
AV = +1, RF = 510Ω, VOUT = 200mVP-P +25oC 850 MHz
AV = +2, RF = 360Ω, VOUT = 200mVP-P +25oC 670 MHz
Slew Rate AV = +1, RF = 510Ω, VOUT = 5VP-P +25oC 1500 V/µs
AV = +2, VOUT = 5VP-P +25oC 2300 V/µs
Full Power Bandwidth VOUT = 5VP-P +25oC 220 MHz
Gain Flatness * To 30MHz, RF = 510Ω+25oC±0.014 dB
To 50MHz, RF = 510Ω+25oC±0.05 dB
To 100MHz, RF = 510Ω+25oC±0.14 dB
Linear Phase Deviation * To 100MHz, RF = 510Ω+25oC±0.6 Degrees
2nd Harmonic Distortion * 30MHz, VOUT = 2VP-P +25oC -55 dBc
50MHz, VOUT =2V
P-P +25oC -49 dBc
100MHz, VOUT = 2VP-P +25oC -44 dBc
3rd Harmonic Distortion * 30MHz, VOUT = 2VP-P +25oC -84 dBc
50MHz, VOUT = 2VP-P +25oC -70 dBc
100MHz, VOUT = 2VP-P +25oC -57 dBc
Spec Number 511082-883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
3-222
HFA1130
3rd Order Intercept * 100MHz, RF = 510Ω+25oC 30 dBm
1dB Compression 100MHz, RF = 510Ω+25oC 20 dBm
Reverse Isolation (S12) 40MHz, RF = 510Ω+25oC -70 dB
100MHz, RF = 510Ω+25oC -60 dB
600MHz, RF = 510Ω+25oC -32 dB
Rise & Fall Time VOUT = 0.5VP-P +25oC 500 ps
VOUT = 2VP-P +25oC 800 ps
Overshoot * VOUT = 0.5VP-P, Input tR/tF = 550ps +25oC11 %
Settling Time * To 0.1%, VOUT = 2V to 0V, RF = 510Ω+25oC11 ns
To 0.05%, VOUT = 2V to 0V, RF = 510Ω+25oC19 ns
To 0.02%, VOUT = 2V to 0V, RF = 510Ω+25oC34 ns
Differential Gain AV = +2, RL = 75Ω, NTSC +25oC 0.03 %
Differential Phase AV = +2, RL = 75Ω, NTSC +25oC 0.05 Degrees
Overdrive Recovery Time
(2X Overdrive) RF = 510Ω, VIN = ±1V, VH = +1V, VL = -1V +25oC 750 ps
Clamp Accuracy AV = -1, RF = 510Ω, VIN = ±2V, VH = +1V,
VL = -1V +25oC±60 mV
Clamped Overshoot RF= 510Ω, VIN =±1V, VH= +1V, VL= -1V,
Input tR/t
F= 2ns +25oC4 %
Negative Clamp Range (VL)R
F= 510Ω+25oC -5.0 to +2.0 V
Positive Clamp Range (VH)R
F= 510Ω+25oC -2.0 to +5.0 V
Clamp Input Bias Current VH= +1V, VL= -1V +25oC50 µA
Clamp Input Bandwidth VIN =±100mV, VH or VL= 100mVP-P +25oC 500 MHz
*See Typical Performance Curves For More Information
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: VSUPPLY = ±5V, RF = 360Ω, AV = +2V/V, RL = 100Ω, Unless Otherwise Specified
PARAMETERS CONDITIONS TEMPERATURE TYPICAL UNITS
Spec Number 511082-883
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
