HEF4066BT,652 - NEXPERIA

Important notice

Dear Customer,

On 7 February 2017 the former NXP Standard Product business became a new company with the

tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS

semiconductors with its focus on the automotive, industrial, computing, consumer and wearable

application markets

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use

the references to Nexperia, as shown below.

Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,

use http://www.nexperia.com

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salesaddresses@nexperia.com (email)

Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on

the version, as shown below:

reserved

Should be replaced with:

If you have any questions related to the data sheet, please contact our nearest sales office via e-mail

or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and

understanding,

Kind regards,

Team Nexperia

1. General description

The HEF4066B provides four single-pole, single-throw analog switch functions. Each

switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).

When nE is LOW, the analog switch is turned off.

The HEF4066B is pin compatible with the HEF4016B but exhibits a much lower ON

resistance. In addition the ON resistance is relatively constant over the full inpu t signal

range.

2. Features and benefits

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Inputs and outputs are protected against electrostatic effects

Specified from 40 C to +85 C and 40 C to +125 C

Complies with JEDEC standard JESD 13-B

3. Applications

Analog multiplexing and demultiplexing

Digital multiplexing and demultiplexing

Signal gating

4. Ordering information

HEF4066B

Quad single-pole single-throw analog switch

Rev. 9 — 19 April 2016 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

HEF4066BT 40 C to +125 C SO14 plastic small outline package; 14 leads;

body width 3.9 mm SOT108-1

Product data sheet Rev. 9 — 19 April 2016 2 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

5. Functional diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 1. Functional di ag ram Fig 2. Logic diagram (one swi tch)

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Table 2. Pin description

Symbol Pin Description

1Y, 2Y, 3Y, 4Y 1, 4, 8, 11 independent input or output

1Z, 2Z, 3Z, 4Z 2, 3, 9, 10 independent input or output

1E, 2E, 3E, 4E 13, 5, 6, 12 enable input (active HIGH)

VSS 7 ground (0 V)

VDD 14 supply voltage

Product data sheet Rev. 9 — 19 April 2016 3 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level.

8. Limiting values

[1] To avoid drawing VDD current out of terminal nZ, when switch current flows into terminals nY, the voltage drop across the bidirectional

switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VDD current will flow out of terminals nY, in this case there

is no limit for the voltage drop across the switch, but the voltages at nY and nZ may not exceed VDD or VSS.

[2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.

9. Recommended operating conditions

Table 3. Function table[1]

Input nE Switch

HON

LOFF

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +18 V

IIK input clamping current VI<0.5 V or VI>V

DD + 0.5 V - 10 mA

VIinput voltage 0.5 VDD + 0.5 V

II/O input/output current [1] -10 mA

Tstg storage temperature 65 +150 C

Tamb ambient temperature 40 +125 C

Ptot total power dissipation Tamb = 40 C to +125 C

SO14 [2] -500mW

P power dissipation per switch - 100 mW

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air 40 - +125 C

t/V input transition rise and fall

rate VDD = 5 V - - 3.75 s/V

VDD = 10 V - - 0.5 s/V

VDD = 15 V - - 0.08 s/V

Product data sheet Rev. 9 — 19 April 2016 4 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

10. Static characteristics

10.1 Test circuit

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 CUnit

Min Max Min Max Min Max Min Max

VIH HIGH-level

input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - 11.0 - V

VIL LOW-level

input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 - 4.0 V

IIinput leakage

current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A

IS(OFF) OFF-state

leakage

current

per channel;

see Figure 4 15 V - - - 200 - - - - nA

IDD supply current all valid input

combinations 5 V - 1.0 - 1.0 - 7.5 - 7.5 A

10 V - 2.0 - 2.0 - 15.0 - 15.0 A

15 V - 4.0 - 4.0 - 30.0 - 30.0 A

CIinput

capacitance nE input - - - - 7.5 - - - - pF

Fig 4. Test circuit for measuring OFF-state leakage current

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Product data sheet Rev. 9 — 19 April 2016 5 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

10.2 ON resistance

10.2.1 ON resistance waveform and test circuit

Table 7. ON resistance

Tamb = 25



C; ISW =200



A; VSS = 0 V.

Symbol Parameter Conditions VDD Typ Max Unit

RON(peak) ON resistance (peak) VI = 0 V to VDD; see Figure 5 and

Figure 6 5 V 350 2500 

10 V 80 245 

15 V 60 175 

RON(rail) ON resistance (rail) VI = 0 V; see Figure 5 and Figure 6 5 V 115 340 

10 V 50 160 

15 V 40 115 

VI = VDD; see Figure 5 and Figure 6 5 V 120 365 

10 V 65 200 

15 V 50 155 

RON ON resistance mismatch

between channel s VI = 0 V to VDD; see Figure 5 5V 25 - 

10 V 10 - 

15 V 5 - 

RON =V

SW /I

SW.I

SW = 200 A.

(1) VDD = 5 V

(2) VDD = 10 V

(3) VDD = 15 V

Fig 5. Test circuit for measuring RON Fig 6. Typical RON as a function of input voltage

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Product data sheet Rev. 9 — 19 April 2016 6 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

11. Dynamic characteristics

Table 8. Dynamic characteristics

Tamb = 25



C; VSS = 0 V; for test circuit see Figure 9.

Symbol Parameter Conditions VDD Typ Max Unit

tPHL HIGH to LOW propagation delay nY, nZ to nZ, nY; see Figure 7 5 V 10 20 ns

10 V 5 10 ns

15 V 5 10 ns

nY, nZ to nZ, nY; see Figure 7 5 V 10 20 ns

10 V 5 10 ns

15 V 5 10 ns

tPHZ HIGH to OFF-state

propagation delay nE to nY, nZ; see Figure 8 5 V 80 160 ns

10 V 65 130 ns

15 V 60 120 ns

tPZH OFF-state to HIGH

propagation delay nE to nY, nZ; see Figure 8 5 V 40 80 ns

10 V 20 40 ns

15 V 15 30 ns

tPLZ LOW to OFF-state

propagation delay nE to nY, nZ; see Figure 8 5 V 80 160 ns

10 V 70 140 ns

15 V 70 140 ns

tPZL OFF-state to LOW

propagation delay nE to nY, nZ; see Figure 8 5 V 45 90 ns

10 V 20 40 ns

15 V 15 30 ns

Table 9. Dynamic power dissipation PD

PD can be calculated from the formulas shown; VSS = 0 V; tr = tf



20 ns; Tamb = 25



Symbol Parameter VDD Typical formula for PD (W) where:

PDdynamic power

dissipation 5V P

D = 2500  fi + (fo  CL)  VDD2fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VDD = supply voltage in V;

(CL  fo) = sum of the outputs.

10 V PD = 11500  fi + (fo  CL)  VDD2

15 V PD = 29000  fi + (fo  CL)  VDD2

Product data sheet Rev. 9 — 19 April 2016 7 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

11.1 W aveforms and test circuit

Measurement points are given in Table 10.

Fig 7. nY or nZ to nZ or nY propagation delays

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Measurement points are given in Table 10.

Fig 8. Enable and disable times

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Table 10. Measurement points

Supply voltage Input Output

VDD VMVM

5 V to 15 V 0.5VDD 0.5VDD

Product data sheet Rev. 9 — 19 April 2016 8 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

11.2 Additional dynamic parameters

Test data is given in Table 11.

Definitions:

DUT = Device Under Test.

RT= Termination resistance should be equal to output impedance Zo of the pulse generator.

CL= Load capacitance including test jig and probe.

RL= Load resistance.

Fig 9. Test circuit for measuring switching times

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Table 11. Test data

Supply voltage Input Load S1 position

VDD VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ

5 V to 15 V 0 V or VDD 20 ns 50 pF 10 kVSS VSS VDD

Table 12. Additional dynamic characte ristics

VSS = 0 V; Tamb = 25



Symbol Parameter Conditions VDD Typ Max Unit

THD total harmonic distortion see Figure 10; RL=10k; CL=15pF;

channel ON; VI=0.5V

DD (p-p);

fi=1kHz

5V [1] 0.25 - %

10 V [1] 0.04 - %

15 V [1] 0.04 - %

Vct crosstalk voltage nE input to switch; see Figure 11;

RL= 10 k; CL=15pF;

nE = VDD (square-wave)

10 V 50 - mV

Product data sheet Rev. 9 — 19 April 2016 9 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

[1] fi is biased at 0.5VDD.

11.2.1 Test circuits

Xtalk crosstalk between switches; see Figure 12;

fi= 1 MHz; RL=1 k;

VI=0.5V

DD (p-p)

10 V [1] 50 - dB

iso isolation (OFF-state) see Figure 13; fi= 1 MHz; RL = 1 k;

CL = 5 pF; VI=0.5V

DD (p-p) 10 V [1] 50 - dB

f(3dB) 3 dB frequency response see Figure 14; RL = 1 k; CL = 5 pF;

VI=0.5V

DD (p-p) 10 V [1] 90 - MHz

Table 12. Additional dynamic characte ristics …continued

VSS = 0 V; Tamb = 25



Symbol Parameter Conditions VDD Typ Max Unit

Fig 10. Test circuit for measuring total harmonic distortion

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a. Test circuit

b. Input and output pulse definitions

Fig 11. Test circuit for measuring crosstalk voltage between digital input and switch

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Product data sheet Rev. 9 — 19 April 2016 10 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).

Fig 12. Test circuit for measuring crosstalk between switches

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fi frequency until dB meter reads 3dB.

Fig 13. Test circuit for measuring isolation (OFF-state) Fig 14. Test circuit for measuring frequency response

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Product data sheet Rev. 9 — 19 April 2016 11 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

12. Package outline

Fig 15. Package outline SOT108-1 (SO14)

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Product data sheet Rev. 9 — 19 April 2016 12 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

13. Abbreviations

14. Revision history

Table 13. Abbreviations

Acronym Description

DUT Device Under Test

Table 14. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4066B v.10 20160419 Product data sheet - HEF4066B v.9

Modifications: •Table 4: Condition for total power dissipation changed (errata)

•Table 4: Maximum ambient temperature changed (errata)

HEF4066B v.9 20151216 Product data sheet - HEF4066B v.8

Modifications: •Type number HEF4066BP (SOT27-1) removed.

HEF4066B v.8 20140911 Product data sheet - HEF4066B v.7

Modifications: •Figure 11: Test circuit modified

HEF4066B v.7 20111116 Product data sheet - HEF4066B v.6

Modifications: •Legal pages updated.

•Changes in “General description”, “Features and benefits” and “Applications”.

HEF4066B v.6 20100325 Product data sheet - HEF4066B v.5

HEF4066B v.5 20100225 Product data sheet - HEF4066B v.4

HEF4066B v.4 20091013 Product data sheet - HEF4066B_CNV v.3

HEF4066B_CNV v.3 19950101 Product specification - HEF4066B_CNV v.2

HEF4066B_CNV v.2 19950101 Product specification - -

Product data sheet Rev. 9 — 19 April 2016 13 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict wit h the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect , incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, lif e-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applicati ons or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for t he customer’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product develop ment.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 9 — 19 April 2016 14 of 15

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neither qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in au tomotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specificatio ns, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed produ ct claims result ing from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specificat ions.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to : salesaddresses@nxp.com

NXP Semiconductors HEF4066B

Quad single-pole single-throw analog switch

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 April 2016

Document identifier: HEF4066B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

9 Recommended operating conditions. . . . . . . . 3

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

10.1 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

10.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 5

10.2.1 ON resistance waveform and test circuit . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

11.1 Waveforms and test circuit . . . . . . . . . . . . . . . . 7

11.2 Additional dynamic parameters . . . . . . . . . . . . 8

11.2.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

16 Contact information. . . . . . . . . . . . . . . . . . . . . 14

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15