© Semiconductor Components Industries, LLC, 2012
June, 2012 − Rev. 6
1Publication Order Number:
NTHD4502N/D
NTHD4502N
Power MOSFET
30 V, 3.9 A, Dual N−Channel ChipFETt
Features
•Planar Technology Device Offers Low RDS(on) and Fast Switching Speed
•Leadless ChipFET Package has 40% Smaller Footprint than TSOP−6.
Ideal Device for Applications Where Board Space is at a Premium.
•ChipFET Package Exhibits Excellent Thermal Capabilities. Ideal for
Applications Where Heat Transfer is Required.
•These Devices are Pb−Free and are RoHS Compliant
Applications
•DC−DC Buck or Boost Converters
•Low Side Switching
•Optimized for Battery and Low Side Switching Applications in
Computing and Portable Equipment
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 30 V
Gate−to−Source Voltage VGS ±20 V
Continuous Drain
Current (Note 1) Steady
State
TA = 25°CID2.9 A
TA = 85°C 2.1
t ≤ 5 s TA = 25°C 3.9
Power Dissipation
(Note 1)
Steady
State TA = 25°C
PD1.13 W
t ≤ 5 s 2.1
Continuous Drain
Current (Note 2) Steady
State
TA = 25°CID2.2 A
TA = 85°C 1.6
Power Dissipation
(Note 2)
TA = 25°C PD0.64 W
Pulsed Drain Current tp = 10 msIDM 12 A
ESD Capability
(Note 3)
C = 100 pF,
RS = 1500 W
ESD−
HBM
125 V
Operating Junction and Storage Temperature TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode) IS2.5 A
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size
(Cu area = 0.214 in sq).
3. ESD Rating Information: HBM Class 0.
Device Package Shipping†
ORDERING INFORMATION
ChipFET
CASE 1206A
STYLE 2
http://onsemi.com
30 V
110 mW @ 4.5 V
80 mW @ 10 V
RDS(on) TYP
3.9 A
ID MAXV(BR)DSS
MARKING
DIAGRAM
1
2
3
4
S1
G1
S2
G2
D1
D1
D2
D2
PIN
CONNECTIONS
NTHD4502NT1G ChipFET
(Pb−Free)
3000/Tape & Reel
8
7
6
5
5
6
7
81
2
3
4
D1 (7, 8)
G1
(2)
S1 (1)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
C5 M
G
C5 = Specific Device Code
M = Month Code
G= Pb−Free Package
N−Channel MOSFET
1
8
D2 (5, 6)
G2
(4)
S2 (3)
NTHD4502N
http://onsemi.com
2
THERMAL RESISTANCE RATINGS
Parameter Symbol Max Unit
Junction−to−Ambient – Steady State (Note 4) RqJA 110 °C/W
Junction−to−Ambient – t ≤5 s (Note 4) RqJA 60
Junction−to−Ambient – Steady State (Note 5) RqJA 195
Junction−to−Foot – Steady State (Note 5) RqJF 40
4. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
5. Surface Mounted on FR4 Board using the minimum recommended pad size (Cu area = 0.214 in sq).
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter Symbol Test Conditions Min Typ Max Units
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA30 36 V
Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = 24 V 1.0 mA
VGS = 0 V, VDS = 24 V, TJ = 125°C 10
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = "20 V "100 nA
ON CHARACTERISTICS (Note 6)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 mA1.0 1.65 3.0 V
Drain−to−Source On−Resistance RDS(on) VGS = 10 V, ID = 2.9 A 78 85 mW
VGS = 4.5 V, ID = 2.2 A 105 140
Forward Transconductance gFS VDS = 15 V, ID = 2.9 A 3.8 S
CHARGES AND CAPACITANCES
Input Capacitance CISS
VGS = 0 V, f = 1.0 MHz,
VDS = 15 V
140 pF
Output Capacitance COSS 53
Reverse Transfer Capacitance CRSS 16
Input Capacitance CISS
VGS = 0 V, f = 1.0 MHz,
VDS = 24 V
135 250 pF
Output Capacitance COSS 42 75
Reverse Transfer Capacitance CRSS 13 25
Total Gate Charge QG(TOT)
VGS = 10 V, VDS = 15 V,
ID = 2.9 A
3.6 7.0 nC
Threshold Gate Charge QG(TH) 0.3
Gate−to−Source Charge QGS 0.6
Gate−to−Drain Charge QGD 0.7
Total Gate Charge QG(TOT)
VGS = 4.5 V, VDS = 24 V,
ID = 2.9 A
1.9 nC
Threshold Gate Charge QG(TH) 0.3
Gate−to−Source Charge QGS 0.6
Gate−to−Drain Charge QGD 0.9
6. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
NTHD4502N
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (continued) (TJ = 25°C unless otherwise noted)
Parameter Symbol Test Conditions Min Typ Max Units
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V, IS = 2.5 A 0.85 1.2 V
Reverse Recovery Time tRR VGS = 0 V, IS = 2.9 A,
dIS/dt = 100 A/ms
8.6 ns
Reverse Recovery Charge QRR 4.0 nC
Reverse Recovery Time tRR VGS = 0 V, IS = 1.0 A,
dIS/dt = 100 A/ms
8.4 ns
Reverse Recovery Charge QRR 4.0 nC
SWITCHING CHARACTERISTICS (Note 7)
Turn−On Delay Time td(ON)
VGS = 10 V, VDD = 24 V,
ID = 1 A, RG = 6 W
6.5 12 ns
Rise Time tr5.4 10
Turn−Off Delay Time td(OFF) 14.9 25
Fall Time tf1.8 5.0
Turn−On Delay Time td(ON)
VGS = 4.5 V, VDD = 24 V,
ID = 2.9 A, RG = 2.5 W
7.8 ns
Rise Time tr12.6
Turn−Off Delay Time td(OFF) 9.6
Fall Time tf2.8
7. Switching characteristics are independent of operating junction temperatures.
NTHD4502N
http://onsemi.com
4
TYPICAL PERFORMANCE CURVES
4 V
100°C
0
10
5
6
632
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
4
2
0
1
Figure 1. On−Region Characteristics
1
6
45
5
4
2
3
0
6
Figure 2. Transfer Characteristics
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
57
0.2
0.1
0
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
26
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
ID, DRAIN CURRENT (AMPS)
−50 0−25 25
1.4
1.2
1.0
0.8
0.6
50 125100
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
0.3
46
TJ = −55°C
ID = 2.9 A
TJ = 25°C
0.12
0.07
75 150
TJ = 25°C
ID = 2.9 A
VGS = 10 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
4
25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
1.8
VGS = 4.5 V
310
5
0.1
3025
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
15
VGS = 0 V
IDSS, LEAKAGE (nA)
TJ = 100°C
3.4 V
2.6 V
2.8 V
VGS = 10 V
10
1000
VDS ≥ 10 V
35
0.09
10
VGS = 10, 6, 5, 4.5 & 4.2 V resp.
2
2
0.25
89
0.10
0.08
0.11
4
1.6
100
1
20
TJ = 150°C
8
3 V
3.2 V
3.6 V
3.8 V
3
1
0.15
0.05
NTHD4502N
http://onsemi.com
5
TYPICAL PERFORMANCE CURVES
VDS = 0 V VGS = 0 V
510 10
300
200
100
0
30
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
C, CAPACITANCE (pF)
021
8
2
0
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
QG, TOTAL GATE CHARGE (nC)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
COSS
CISS
CRSS
ID = 2.9 A
TJ = 25°C
QG
4
6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
24
8
0
QGD
101
10
0.1
100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
t, TIME (ns)
VDD = 24 V
ID = 1.0 A
VGS = 10 V
100
50
12
4
td(off)
td(on)
tf
tr
VGS VDS
15 4
0.9
3
0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
IS, SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
0.7
0.4
0.3
1
2
20
10.5 0.8
QGS
16
12
10
3
1
0.6
20 25
VDS
VGS
NTHD4502N
http://onsemi.com
6
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE K
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
E
A
b
e
e1
D
1234
8765
c
L
1234
8765
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
0.05 (0.002)
DIM
A
MIN NOM MAX MIN
MILLIMETERS
1.00 1.05 1.10 0.039
INCHES
b0.25 0.30 0.35 0.010
c0.10 0.15 0.20 0.004
D2.95 3.05 3.10 0.116
E1.55 1.65 1.70 0.061
e0.65 BSC
e1 0.55 BSC
L0.28 0.35 0.42 0.011
0.041 0.043
0.012 0.014
0.006 0.008
0.120 0.122
0.065 0.067
0.025 BSC
0.022 BSC
0.014 0.017
NOM MAX
1.80 1.90 2.00 0.071 0.075 0.079
HE
5°NOM
q5°NOM
HE
q
SOLDERING FOOTPRINT
0.457
0.018
2.032
0.08
0.65
0.025
PITCH
0.66
0.026 ǒmm
inchesǓ
2.362
0.093
1
8X
8X
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NTHD4502N/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loca
l
Sales Representative
