USER'S GUIDE CODEC-5.1 Daughtercard February 2003 Engineering Draft (R) DB15-000281-00 Engineering Draft This document is an engineering draft. Because of an overriding need to get this information to the customer quickly, this document may not have been reviewed for technical content, clarity, organization, or accuracy. This document may not have been edited for spelling, grammar, and punctuation. This document may not be in LSI Logic standard document, page, paragraph, or table formats, and may not have cross references to or from other documents. This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. Document number DB15-000281-00, February 2003 This document describes the version of LSI Logic Corporation's Codec 5.1 Daughter Card and will remain the official reference source for this product until rescinded by an update. To receive other ZSP-related product literature, visit us at http://www.zsp.com. LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties. Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT LSI Logic, the LSI Logic logo design and ZSP are trademarks or registered trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies. ii Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Engineering Draft Preface This book is the primary reference for the CODEC-5.1 daughtercard. It contains detailed descriptions of the Card's features, design and how to use it with the EB402 and EB403 evaluation boards. Audience This document assumes that you have some familiarity with micro and/or digital signal processors and digital and analog audio electronics. The people who benefit from this book are: * Engineers who are using the CODEC-5.1 card in conjunction with the EB402 and EB403 ZSPTM processor evaluation boards. Organization This document has the following chapters and appendixes: * Chapter 1, "Introduction" provides an overview of the CODEC-5.1 card and its features. * Chapter 2, "Installation," describes how to install the CODEC-5.1 card on an EB402 or EB403. * Chapter 3, "Operation," describes the interfaces between the CODEC-5.1 card and the EB402/EB403 boards, and describes the operation of the CODEC-5.1 circuitry. Related Publications The following documents are available from LSI Logic Corporation. * LSI402ZX User's Guide CODEC-5.1 User's Guide Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. iii Engineering Draft * LSI403LP User's Guide * LSI EB402 User's Guide * LSI EB403 User's Guide * EB402 Board Support Package Technical Manual * EB403 Board Support Package Technical Manual This document is intended to provide information to help the reader install and use the CODEC-5.1 board to AKM Corporation AK4586 DataSheet http://www.akm.com/datasheets/ek4586.pdf Conventions Used in This Manual The first time a word or phrase is defined in this manual, it is italicized. The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Signals that are active LOW end in an "n." Hexadecimal numbers are indicated by the prefix "0x" --for example, 0x32CF. Binary numbers are indicated by the prefix "0b" --for example, 0b0011.0010.1100.1111. iv Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Engineering Draft Contents Chapter 1 Introduction 1.1 1.2 Introduction Product Features 1-1 1-2 2.1 2.2 2.3 Hardware Equipment Required Hardware Setup for the CODEC-5.1 Daughtercard Installation 2-1 2-2 2-2 3.1 3.2 Interface to LSI402ZX/LSI403LP Circuit Description 3-1 3-2 Chapter 2 Installation Chapter 3 Operation Appendix A Schematics CODEC-5.1 User's Guide Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. v Engineering Draft vi Contents Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Engineering Draft Chapter 1 Introduction This section introduces the features of the CODEC-5.1 card and describes the purpose for which it has been designed. It contains the following sections: 1.1 * Section 1.1, "Introduction," page 1-1, * Section 1.2, "Product Features," page 1-2. Introduction This document is the primary reference and user's guide for the MultiChannel Audio Codec (CODEC-5.1) daughtercard. This daughtercard interfaces with the LSI Logic ZSP400-based standard product evaluation boards, EB402 and EB403. The daughtercard allows applications development for a 6-channel output codec for multi-channel audio applications. The codec used on board is an AKM AK4586, featuring 2x24-bit input channels, 6x24-bit output channels, with sampling rates up to 96KHz. The daughtercard provides 6 line-level outputs. These outputs are available on both RCA-style connectors and 3.5mm phonojacks for ease of connecting to an external amplifier or powered speakers. The daughtercard has 2 line-level analog inputs which support both RCA-style and a 35mm phonojack. In addition to these inputs, a separate 3.5mm phonojack input is connected to a circuit to support a Electret microphone input. A potentiometer is mounted on the board to adjust the gain of the microphone input circuit. The analog section of the daughtercard can be powered from an external source for improved noise performance. For ease of use, the power CODEC-5.1 User's Guide Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. 1-1 Engineering Draft supplies can also be derived from the EB402/EB403 thus eliminating the need for separate power supplies. The CODEC-5.1 daughtercard plugs into both of the SPORT connectors on the EB402 or EB403 evaluation board. All connections are made through the use of these 2 connectors. This manual describes all the steps necessary to interface the CODEC5.1 daughtercard to the LSI Logic ZSP processor evaluation boards (either EB402 or EB403). 1.2 Product Features The CODEC-5.1 daughtercard provides the following features: * AKM AK4586 codec chip * SPDIF input * SPDIF output * 6 line-level output channels at 24-bits each * 2 line-level input channels at 24-bits each * Mono Electret microphone input * Optional external power supplies for amplifiers * Optional internal power supplies * EB402/EB403 TDM serial port for data * EB402/EB403 GPIO lines for configuration and control * Interrupt lines to EB402/EB403 The codec analog outputs are limited to driving high-impedance loads. They should only be used to drive amplified speakers that accept linelevel inputs. Do not connect passive, low-impedance (8 ohm) speakers to these outputs. The analog inputs must also be line-level signals. The CODEC-5.1 is fully supported by the EB402 and EB403 Board Support Packages that are available as part of the LSI402ZX and LSI403LP Development Kits. Please refer to the EB402 Board Support Package User Guide or EB403 Board Support Package User Guide for further information. 1-2 Introduction Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Engineering Draft Chapter 2 Installation This chapter describes installation of the CODEC-5.1 card. It contains the following sections: 2.1 * Section 2.1, "Hardware Equipment Required," page 2-1 * Section 2.2, "Hardware Setup for the CODEC-5.1 Daughtercard," page 2-2 * Section 2.3, "Installation," page 2-2 Hardware Equipment Required The following is the minimum recommended list of hardware required to evaluate and/or use the CODEC-5.1 daughtercard: * LSI Logic EB402 or EB403 evaluation board. * Host computer with SDK tools and debugger interface * CODEC-5.1 Daughtercard * Audio output devices * - Line powered speakers, or - Amplifier with speakers, or - Analyzer Input Sources - DVD player or other SPDIF generating device - Stereo line-level inputs - Electret microphone CODEC-5.1 User's Guide Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. 2-1 Engineering Draft 2.2 Hardware Setup for the CODEC-5.1 Daughtercard The CODEC-5.1 daughtercard may be used with either the LSI Logic EB402 or the EB403 evaluation boards. The daughtercard is installed onto the SPORT0 and SPORT1 TDM interface connectors provided on the ZSP evaluation boards. Figure 2.1 shows an illustration of the CODEC-5.1 indicating locations of the various connectors and jumpers on the board. Figure 2.1 CODEC-5.1 Connectors SPDIF IN SPDIF OUT RCA Analog IN An IN MIC IN LFE/C RCA Out RS/LS L/R L/R LS/ RS C/ LFE J3 R38 J5 J24 +12 Ext -12 Ext BD-CODEC-5.1 J4 Ext Gnd 2.3 Installation The installation procedure is as follows: 1. Set jumpers J3, J4, and J5 for either internal or external power as shown in Table 2.1 2-2 Installation Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Engineering Draft Table 2.1 Power connections Jumper Power from EB40X External Power J5 Open Installed J3 2-3 1-2 J4 2-3 1-2 J6 Open Analog Ground J7 Open -12V DC (Acceptable range is -7Vdc to _15Vdc) J8 Open +12V DC (Acceptable range is +7Vdc to +15Vdc) 2. Install J24 for input selection as shown in Table 2.2 Table 2.2 Input Selection Jumper SPDIF Input Stereo Line Input Microphone Input J24 2-3 2-3 1-2 3. Plug the CODEC-5.1 daughtercard into the motherboard. The connectors are keyed and can only be installed in one orientation. 4. Connect an external power source to the CODEC-5.1 daughtercard if configured from step 1. The external supply should be turned off during connection and only turned on after the connections have been made. 5. Connect an input source to one of the following locations as shown in Table 2.3. Table 2.3 Input Source Connector selection Type Input Connection RCA Input Connection PhonoJack Jumpers Digital Audio J19 NA NA Analog In J20 - Bottom- Left J20 - Top - Right J25 - TIP - Left J25 - RING - Right J24 2-3 J21 - TIP J24 2-3 Microphone In NA Installation Rev. A 2-3 Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Engineering Draft 6. When using a microphone input, Potentiometer RX can be adjusted to increase or decrease the gain of the microphone amplifier. 7. Connect a destination to the output channels as shown in Table 2.4. Table 2.4 Output Channel Connectors Channel RCA PhonoJack Left J10-CH3-Bottom J18-Tip Right J10-CH3-Top J18-Ring Left Surround J10-CH2-Bottom J15-Tip Right Surround J10-CH2-Top J15-Ring Center J10-CH1-Bottom J12-Tip Base J10-CH1-Top J12-Ring 8. Note that all output channels are line-level outputs and require an amplifier or powered speakers. 9. Turn the EB402/EB403 evaluation board power on. 10. Turn on the external power supply if one is being used. A software driver for the CODEC-5.1 daughtercard is provided in the EB402 and EB403 Board Support Packages. These BSPs are included on the ZSP Development Kit (ZDK) CDROM supplied with the EB402 and EB403. For details of the CODEC-5.1 driver, please refer to the EB402 Board Support Package Technical Manual or EB403 Board Support Package Technical Manual. 2-4 Installation Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Engineering Draft Chapter 3 Operation This chapter describes the CODEC-5.1 interfaces to the EB402/EB403 cards and the operation of its circuitry. It contains the following sections: 3.1 * Section 3.1, "Interface to LSI402ZX/LSI403LP," page 3-1, * Section 3.2, "Circuit Description," page 3-2 Interface to LSI402ZX/LSI403LP The AK4586 has two interfaces: a control interface and a data interface. The control interface is used to set the operating mode of the Codec chip and to read status information back. The data interface is used to read data, either digital audio or digitized analog inputs, and to write the 6 output channels. Four GPIOs on the LSI402ZX/LSI403LP are used for the control interface. These signals comprise a clock, chip select, data in, and data out. All data is read and written from/to the control interface by manipulating individual bits in the PIO register. Serial port 0 is used for the data interface to the codec. The AK4586 codec can be configured for TDM mode. This puts all three output pairs on a single serial port output wire and the input data on a single input wire. Serial port 1 is used to provide a clock input to the AK4586 when in nondigital audio mode. By setting the clock rate of the serial port, the sample rate of the codec can be controlled. The sample rate of the codec is equal to the SP1 Clock Rate divided by 256. For example, to achieve a 44.1 kHz sample rate, the serial port clock rate should be 44.1K x 256 or 11.2896 MHz. Setting the EB402 clock rate at 170 MHz and using a CODEC-5.1 User's Guide Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. 3-1 Engineering Draft clock divider of 15 would yield a sample rate of 170 MHz/12/256 or 44.27 kHz, an error of 0.4%. 3.2 Circuit Description This section describes the schematic for the audio daughtercard. The schematics for the CODEC-5.1 card are shown at the end of this manual. Figure A.1 shows the hierarchical connections between the various blocks. Figure A.2 illustrates the connections to the EB402/3. Both SPORT0 and SPORT1 are used to provide access to the GPIO lines required. GPIO lines on the LSI402ZX/LSI403LP chip are used to control the 4-wire interface on the Codec. This four-wire interface is used to configure the codec and read back status information. SPORT0 contains the serial TDM interface between the AK4586 Codec and the ZSP processor. The TX clock from SPORT1 is routed to the clock input of the AK4586. When no external digital source is present, the AK4586 will automatically switch to the clock input signal to generate it's clock. This allows the codec rate to be set under program control. The codec produces 2 interrupts which are routed to the LSI402ZX/LSI403LP to pins INT2 and INT3. These interrupt lines are used to indicate operational status like the lock signal, non-PCM data stream, etc. Figure A.3 contains the connections to the AK4586 Codec. A separate +5V regulator is used to provide the +5V rail required for the AK4586. U11 generates a reset pulse at powerup for the AK4586. Figure A.4 shows the power supplies for the daughtercard. U2 is used to provide the +7V supply for the op-amps when using internal power. The analog power used by the amplifiers can either be produced on the CODEC-5.1 or through an external power supply. Jumpers J3, J4, and J5 are used to select either internally generated power or external power. J5, when installed, shuts down both U3 and U4. U3 generates a -9V rail from the +9V supplied from the EB402, and U4 generates -7V from the -9V supply. The use of external supplies helps to reduce noise in sensitive environments, while the internal supplies provide a level of convenience for development purposes. J9 provides the common connection between the analog and digital ground planes and must be always installed. The artwork includes a permanent connection across J9 3-2 Operation Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Engineering Draft on the top layer which can be cut for those applications requiring a separated ground system. Figure A.5 shows the Audio connections on and off the board. J10 contains the 6 output channels in an RCA block connector. J12, J15, and J18 provide the same output connections in 3.5mm line-output jacks. J12 provides Left and Right channels for either 6 channel output or for stereo output. J15 provides Left Surround and Right Surround for 6 channel outputs. J18 provides Center and Base for 6 channel outputs. J19 is an RCA connector for the SPDIF input source, typically a DVD player. J23 is a SPDIF output pass through connection. J20 provides an RCA-style input connection for left and right stereo channels, and J25 provides the input connection using a phonojack input. J21 is a microphone input for a mono electret microphone. Figure A.6 shows the amplifiers for each of the output DAC channels, the stereo line-inputs, and the microphone input. Figure A.7 shows one of the output DAC amplifiers. This amplifier will produce a +/- 3V signal suitable for driving line-level outputs. Figure A.13 shows a line-input amplifier. This amplifier takes a line-level input signal and produces a valid analog input signal for the codec. Figure A.14 shows the microphone amplifier circuit. This circuit provides power and amplification for an electret microphone. R38 is available on the board to adjust the gain of the amplifier. Circuit Description Rev. A 3-3 Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Engineering Draft 3-4 Operation Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Engineering Draft Appendix A Schematics CODEC-5.1 User's Guide Rev. A Copyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. A-1 A-2 A B C SP0_CLK SP0_XFS SP0_RFS EB_Connections 5 CLK PIO0 PIO1 PIO2 PIO3 INT2 INT3 SP0_DOUT SP0_DIN EB Interface Figure A.1 AKM_CLK SP_FS 4 TDM_DOUT TDM_DIN CODEC_CLKIN C_CSN C_CCLK C_DIN C_DOUT INT_2 INT_3 AK4586 Codec MCLK_OUT BICK LRCK SDTI1 SDTO CLK_IN CSN CCLK CDTO CDTI INT0 INT1 AK4586 3 CODEC_POWER POWER SPDIF_IN SPDIF_OUT RIN LIN DAC_OUTPUTS[5..0] RIN LIN DAC_O[5..0] Schematics Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Date: Size A Title Amplifiers RIN LIN 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 MIC_IN LINE_IN_RIGHT LINE_IN_LEFT A_DAC_O[5..0] AUDIO DAUGHTERCARD MIC_IN LINE_IN_RIGHT LINE_IN_LEFT AMP_OUT[5..0] DAC_OUT[5..0] Amplifiers Sheet 1 1 of AUDIO_IO_PAGE SPDIF_INPUT SPDIF_OUTPUT MIC_IN LINE_IN_RIGHT LINE_IN_LEFT 15 DAC_OUTPUTS[5..0] AUDIO_IO Rev A A B C January 2003 Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. A B C D SP0_CLK 1 2 4 6 8 10 12 14 16 18 20 5 DGND CLK SPORT_0 CON20 J1 7404 2 U1A 1 3 5 7 9 11 13 15 17 19 3.3V 4 R1 33.2 SP0_DIN SP0_RFS 3 0.1u C1 SP0_XFS INT3 PIO2 PIO3 Date: Size A Title 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 SPORT_1 CON20 J2 DGND R2 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 AUDIO DAUGHTERCARD Sheet 2 Serial Port 1 TX clock is used to drive the Codec Xtal input signal. Must set SP1 in continuous mode to proper clock rate (256 x 48k[fs value]) then write a word to the sp1 TX register to start the clock. +9V Daughtercard Interface Connections Codec MCLK output is used to drive the BICK which is the common clock between the codec and the serial port. The Codec will automatically switch from XTAL input to PLL input when a valid PLL clock is found, ie from a DVD player. SP0_DOUT INT2 PIO0 PIO1 +9V 14 7 Figure A.2 1 of 15 33.2 Rev A A B C D January 2003 A-3 A-4 Schematics Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. A B C D RST VDD 5 INT0 INT1 CDTO CDTI CCLK CSN LRCK BICK SDTO SDTI1 ADJ_5 MCP130-485 VSS U11 CLK_IN MCLK_OUT 3 Figure A.3 1 2 R3 R51 10.0K + +5V RSTN R50 32.4K +5V +5V 10u C19 14 15 16 17 18 19 8 9 10 11 12 13 1 2 7 44 42 40 38 25 20 5.1 4 ROUT1 LOUT1 ROUT2 LOUT2 ROUT3 LOUT3 RIN LIN TX RX1 RX2 RX3 RX4 VREFH AVDD AVSS VCOM TVDD DVDD DVSS PVDD R PVSS 0.1u C3 ADJ_5 AK4586 0.01u C21 INT0 INT1 CDTO CDTI CCLK CCSN LRCK BICK SDTO SDTI1 SDTI2 SDTI3 XTO EXTCLK MCKO PDN I2C TST SLAVE DZF1 DZF2 U1 10u C2 PVDD 1 2 4 3 31 30 29 28 27 26 33 32 6 43 41 39 37 23 22 21 24 5 3 4 34 35 36 LT1763CS8 OUT IN SENSE GND BYP GND GND SHDN U10 3 8 7 6 5 DAC_OUTPUTS5 DAC_OUTPUTS4 DAC_OUTPUTS3 DAC_OUTPUTS2 DAC_OUTPUTS1 DAC_OUTPUTS0 18.2K R5 AKM 4586 Codec 10u C4 +9V RIN LIN Date: Size A Title SPDIF_OUT SPDIF_IN 3.3V 2.2u C10 2 Sheet C11 0.1u C6 10u DVDD AGND R4 5.1 Monday, December 16, 2002 Document Number BD-CODEC-5.1 AUDIO DAUGHTERCARD DAC_OUTPUTS[5..0] C5 0.1u +5V 3 1 C8 10u +5V of C7 0.1u 15 Rev A C9 0.1u A B C D January 2003 Figure A.4 +9V +7V Power Supplies, Internal and External U2 R44 47.5K D C12 + +9V 1 2 4 3 ADJ_P C14 -9V 10u ADJ_P OUT IN SENSE GND BYP GND GND SHDN 8 V+ 1 7 BOOST OSC 2 4 CAP+ CAP- 6 SHDN 5 VOUT 0.01u C15 GND 100u NEG_AMP_PWR PLUS_AMP_PWR D4 D1 D2 D3 3 LT1054CS8 C R45 10.0K + C16 100u D 10u January 2003 Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. + C13 + LT1763CS8 U3 NC NC 8 7 6 5 C gnd is pin 3 B130L -9V R49 470 1/4W B130L R48 LED 470 1/4W P12V_EXT LED -7V N12V_EXT +7V Internal B ADJ_M 1 2 3 4 -7V Vin Vin Ilim2 Ilim4 Out SHDN Sense Gnd 8 7 6 5 Internal J3 Install for External J5 U4 CON3 J7 BANANA_BLK J4 External J8 CON3 BANANA_RED External B 2 1 LT1175CS8 CON2 NEG_AMP_PWR PLUS_AMP_PWR J6 R46 8.45K 1 3 2 1 3 2 1 + 10u 1 C17 BANANA_BLK C22 C26 Always Installed C18 + C20 C24 J9 CON2 + 10u 1 + 10u ADJ_M 0.1u 0.1u 10u 1 2 R47 10.0K A AGND A DGND Title AUDIO DAUGHTERCARD GND_POWER Size A GND Date: 5 4 3 Document Number BD-CODEC-5.1 Monday, December 16, 2002 2 Rev A Sheet of 4 1 15 A-5 A-6 Figure A.5 Connectors DAC_OUTPUTS[5..0] NOTE: DAC_OUTPUTS 5, 3, AND 1 ARE RIGHT; DAC_OUTPUTS 4, 2, AND 0 ARE LEFT J12 DAC_OUTPUTS4 5 4 3 2 1 DAC_OUTPUTS5 D STEREOJACK January 2003 Schematics J15 DAC_OUTPUTS2 J10 C DAC_OUTPUTS0 DAC_OUTPUTS1 DAC_OUTPUTS2 DAC_OUTPUTS3 DAC_OUTPUTS4 DAC_OUTPUTS5 = = = = = = CH3 CH3 CH2 CH2 CH1 CH1 BOT TOP BOT TOP BOT TOP = = = = = = J18 J18 J15 J15 J12 J12 TIP = LEFT RING = RIGHT TIP = LS RING = RS TIP = CENTER RING = BASE DAC_OUTPUTS4 DAC_OUTPUTS5 1 2 3 1 2 3 DAC_OUTPUTS2 DAC_OUTPUTS3 4 5 6 4 5 6 DAC_OUTPUTS0 DAC_OUTPUTS1 7 8 9 7 8 9 5 4 3 2 1 DAC_OUTPUTS3 C STEREOJACK J18 DAC_OUTPUTS0 RCJ-61 5 4 3 2 1 DAC_OUTPUTS1 AGND STEREOJACK J19 C28 B B 2 SPDIF_INPUT J20 RCJ-22 J21 1 0.1u R6 75.0 RCJ-01 1 2 3 LINE_IN_LEFT LINE_IN_RIGHT MIC_IN 5 4 3 2 1 DGND J25 J23 R7 T1 SPDIF_OUTPUT 1 4 3 6 STEREOJACK 5 4 3 2 1 TRANSFORMER 2 STEREOJACK A A 33.2 1 Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. DAC_OUTPUTS5 DAC_OUTPUTS4 DAC_OUTPUTS3 DAC_OUTPUTS2 DAC_OUTPUTS1 DAC_OUTPUTS0 D R8 100 Title RCJ-01 AUDIO DAUGHTERCARD Size A DGND Date: 5 4 3 Document Number BD-CODEC-5.1 Tuesday, December 17, 2002 Sheet 2 Rev A of 5 1 15 Figure A.6 Amplifiers for Input, Output, and Microphone DAC_OUT[5..0] AMP_OUT[5..0] AM P D D DAC_OUT0 AMP_OUT0 IN PLUS_AMP_PWR OUT DAC_OUT1 C30 C32 10u 0.1u 10u OUT PLUS_AMP_PWR AMP _2 AMP _3 OUT C41 C42 C44 AMP_OUT2 10u 0.1u 10u IN 0.1u OUT C53 NEG_AMP_PWR C54 C56 C57 + 10u out_amp DAC_OUT4 0.1u 10u 0.1u OUT PLUS_AMP_PWR AMP _5 NEG_AMP_PWR out_amp + C65 C66 C68 C69 + DAC_OUT5 10u AMP_OUT5 IN LIN 0.1u 10u 0.1u out_amp MIC_IN AMP_OUT B MIC_AMP IN_AMP 3 2 1 BYPASS FOR U8 OUT MIC IN 1-2 LINE IN 2-3 J24 BYPASS FOR U7 AMP_OUT4 IN B C AMP_OUT3 + AMP _4 BYPASS FOR U6 out_amp PLUS_AMP_PWR DAC_OUT3 C45 + IN NEG_AMP_PWR out_amp + C 0.1u AMP_OUT1 IN DAC_OUT2 BYPASS FOR U5 C33 + Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. out_amp January 2003 C29 + AMP _1 NEG_AMP_PWR LINE_IN MICIN MIC_AMP LINE_IN_LEFT input_amp MIC_AMP IN_AMP_1 CON3 A RIN A AMP_OUT LINE_IN LINE_IN_RIGHT Title AUDIO DAUGHTERCARD Size A input_amp Date: 5 4 3 Document Number BD-CODEC-5.1 Monday, December 16, 2002 2 Rev A Sheet of 6 1 15 A-7 5 IN C31 22u + 4 AGND R10 10.0K 4.75K R11 OPA2227 330p 3 R12 4.75K C34 U5A 1 NEG_AMP_PWR 2 - 3 + PLUS_AMP_PWR R9 Schematics Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Date: Size A Title 221 OUT 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 AUDIO DAUGHTERCARD Output Amplifier for each DAC channel 8 A-8 4 Figure A.7 Sheet 7 1 of 15 Rev A A B C D January 2003 5 IN C37 22u + 4 AGND R14 10.0K 4.75K R15 OPA2227 330p 3 R16 4.75K C40 U5B 7 NEG_AMP_PWR 6 - 5 + PLUS_AMP_PWR Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Date: Size A Title R13 221 OUT 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 PRO AUDIO DAUGHTERCARD Output Amplifier for each DAC channel 8 4 Figure A.8 Sheet 8 1 of 15 Rev A A B C D January 2003 A-9 5 IN C43 22u + 4 AGND R18 10.0K 4.75K R19 OPA2227 330p 3 R20 4.75K C46 U6A 1 NEG_AMP_PWR 2 - 3 + PLUS_AMP_PWR Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Schematics Date: Size A Title R17 221 OUT 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 PRO AUDIO DAUGHTERCARD Output Amplifier for each DAC channel 8 A-10 4 Figure A.9 Sheet 9 1 of 15 Rev A A B C D January 2003 5 IN C49 22u + 4 AGND R22 10.0K 4.75K R23 OPA2227 330p 3 R24 4.75K C52 U6B 7 NEG_AMP_PWR 6 - 5 + PLUS_AMP_PWR Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Date: Size A Title R21 221 OUT 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 PRO AUDIO DAUGHTERCARD Output Amplifier for each DAC channel 8 4 Figure A.10 Sheet 10 1 of 15 Rev A A B C D January 2003 A-11 5 IN C55 22u + 4 AGND R26 10.0K 4.75K R27 OPA2227 330p 3 R28 4.75K C58 U7A 1 NEG_AMP_PWR 2 - 3 + PLUS_AMP_PWR Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Schematics Date: Size A Title R25 221 OUT 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 PRO AUDIO DAUGHTERCARD Output Amplifier for each DAC channel 8 A-12 4 Figure A.11 Sheet 11 1 of 15 Rev A A B C D January 2003 5 IN C61 22u + 4 AGND R30 10.0K 4.75K R31 OPA2227 330p 3 R32 4.75K C64 U7B 7 NEG_AMP_PWR 6 - 5 + PLUS_AMP_PWR Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Date: Size A Title R29 221 OUT 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 PRO AUDIO DAUGHTERCARD Output Amplifier for each DAC channel 8 4 Figure A.12 Sheet 12 1 of 15 Rev A A B C D January 2003 A-13 4 3 AUDIO DAUGHTERCARD 33.2 R35 10u Sheet AMP_OU T 13 1 of 15 Rev A C Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Schematics Date: Size A 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 A Title R33 33.2 C67 A 5 OPA2227 NEG_AMP_PWR 2 - 1 U8A D B AGND R34 OPEN 3 + + B LINE_IN PLUS_AMP_PWR Line Input Amplifier 8 4 A-14 C D Figure A.13 January 2003 Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. A B C MICIN 5 0.1u C73 1.00K R39 4 R40 10.0K R37 10.0K U9A + 10u C70 3 C75 0.1u CLOCKWISE FOR LOUDER 100K_POT 10u C74 R38 LM358D 1 NEG_AMP_PWR 2 - 3 + 8 4 R36 10.0K PLUS_AMP_PWR C72 10u Date: Size A Title 0.1u C71 + Microphone Input Amplifier LM358D 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 AUDIO DAUGHTERCARD U9B 7 NEG_AMP_PWR 6 - 5 + PLUS_AMP_PWR MIC_AMP 8 4 D + Figure A.14 Sheet 14 1 of 15 Rev A A B C D January 2003 A-15 4 3 PRO AUDIO DAUGHTERCARD 33.2 R43 10u Sheet AMP_OU T 15 1 of 15 Rev A C Rev. ACopyright (c) 2002-2003 by LSI Logic Corporation. All rights reserved. Schematics Date: Size A 2 Monday, December 16, 2002 Document Number BD-CODEC-5.1 A Title R41 33.2 C78 A 5 OPA2227 NEG_AMP_PWR 6 - 7 U8B D B AGND R42 OPEN 5 + + B LINE_IN PLUS_AMP_PWR Line Input Amplifier 8 4 A-16 C D Figure A.15 January 2003