CODEC-5.1 Daughtercard - LSI Logic Corporation

DB15-000281-00

CODEC-5.1

Daughtercard

USER’S

GUIDE

February 2003

Engineering Draft

This document is an engineering draft. Because of an overriding need to get this

information to the customer quickly, this document may not have been reviewed

for technical content, clarity, organization, or accuracy. This document may not

have been edited for spelling, grammar, and punctuation. This document may not

be in LSI Logic standard document, page, paragraph, or table formats, and may

not have cross references to or from other documents.

This document contains proprietary information of LSI Logic Corporation. The

information contained herein is not to be used by or disclosed to third parties

without the express written permission of an ofﬁcer of LSI Logic Corporation.

Document number DB15-000281-00, February 2003

This document describes the version of LSI Logic Corporation’s Codec 5.1

Daughter Card and will remain the ofﬁcial reference source for this product until

rescinded by an update.

To receive other ZSP-related product literature, visit us at

http://www.zsp.com.

LSI Logic Corporation reserves the right to make changes to any products herein

at any time without notice. LSI Logic does not assume any responsibility or

liability arising out of the application or use of any product described herein,

except as expressly agreed to in writing by LSI Logic; nor does the purchase or

use of a product from LSI Logic convey a license under any patent rights,

copyrights, trademark rights, or any other of the intellectual property rights of LSI

Logic or third parties.

TRADEMARK ACKNOWLEDGMENT

LSI Logic, the LSI Logic logo design and ZSP are trademarks or registered

trademarks of LSI Logic Corporation. All other brand and product names may be

trademarks of their respective companies.

CODEC-5.1 User’s Guide iii

Engineering Draft

Preface

This book is the primary reference for the CODEC-5.1 daughtercard. It

contains detailed descriptions of the Card’s features, design and how to

use it with the EB402 and EB403 evaluation boards.

Audience

This document assumes that you have some familiarity with micro and/or

digital signal processors and digital and analog audio electronics. The

people who beneﬁt from this book are:

•Engineers who are using the CODEC-5.1 card in conjunction with

the EB402 and EB403 ZSP™ processor evaluation boards.

Organization

This document has the following chapters and appendixes:

•Chapter 1, “Introduction” provides an overview of the CODEC-5.1

card and its features.

•Chapter 2, “Installation,” describes how to install the CODEC-5.1

card on an EB402 or EB403.

•Chapter 3, “Operation,” describes the interfaces between the

CODEC-5.1 card and the EB402/EB403 boards, and describes the

operation of the CODEC-5.1 circuitry.

Related Publications

The following documents are available from LSI Logic Corporation.

•LSI402ZX User’s Guide

Engineering Draft

•LSI403LP User’s Guide

•LSI EB402 User’s Guide

•LSI EB403 User’s Guide

•EB402 Board Support Package Technical Manual

•EB403 Board Support Package Technical Manual

This document is intended to provide information to help the reader

install and use the CODEC-5.1 board to AKM Corporation AK4586

DataSheet http://www.akm.com/datasheets/ek4586.pdf

Conventions Used in This Manual

The ﬁrst time a word or phrase is deﬁned in this manual, it is italicized.

The word assert means to drive a signal true or active. The word

deassert means to drive a signal false or inactive. Signals that are active

LOW end in an “n.”

Hexadecimal numbers are indicated by the preﬁx “0x” —for example,

0x32CF. Binary numbers are indicated by the preﬁx “0b” —for example,

0b0011.0010.1100.1111.

CODEC-5.1 User’s Guide v
Rev. A Copyright © 2002-2003 by LSI Logic Corporation. All rights reserved.
Engineering Draft
Contents
Chapter 1
Introduction 1.1 Introduction 1-1
1.2 Product Features 1-2
Chapter 2
Installation 2.1 Hardware Equipment Required 2-1
2.2 Hardware Setup for the CODEC-5.1 Daughtercard 2-2
2.3 Installation 2-2
Chapter 3
Operation 3.1 Interface to LSI402ZX/LSI403LP 3-1
3.2 Circuit Description 3-2
Appendix A
Schematics

Engineering Draft

vi Contents

CODEC-5.1 User’s Guide 1-1

Engineering Draft

Chapter 1

Introduction

This section introduces the features of the CODEC-5.1 card and

describes the purpose for which it has been designed. It contains the

following sections:

•Section 1.1, “Introduction,” page 1-1,

•Section 1.2, “Product Features,” page 1-2.

1.1 Introduction

This document is the primary reference and user’s guide for the Multi-

Channel Audio Codec (CODEC-5.1) daughtercard. This daughtercard

interfaces with the LSI Logic ZSP400-based standard product evaluation

boards, EB402 and EB403.

The daughtercard allows applications development for a 6-channel

output codec for multi-channel audio applications. The codec used on

board is an AKM AK4586, featuring 2x24-bit input channels, 6x24-bit

output channels, with sampling rates up to 96KHz.

The daughtercard provides 6 line-level outputs. These outputs are

available on both RCA-style connectors and 3.5mm phonojacks for ease

of connecting to an external ampliﬁer or powered speakers.

The daughtercard has 2 line-level analog inputs which support both

RCA-style and a 35mm phonojack. In addition to these inputs, a separate

3.5mm phonojack input is connected to a circuit to support a Electret

microphone input. A potentiometer is mounted on the board to adjust the

gain of the microphone input circuit.

The analog section of the daughtercard can be powered from an external

source for improved noise performance. For ease of use, the power

Engineering Draft

1-2 Introduction

supplies can also be derived from the EB402/EB403 thus eliminating the

need for separate power supplies.

The CODEC-5.1 daughtercard plugs into both of the SPORT connectors

on the EB402 or EB403 evaluation board. All connections are made

through the use of these 2 connectors.

This manual describes all the steps necessary to interface the CODEC-

5.1 daughtercard to the LSI Logic ZSP processor evaluation boards

(either EB402 or EB403).

1.2 Product Features

The CODEC-5.1 daughtercard provides the following features:

•AKM AK4586 codec chip

•SPDIF input

•SPDIF output

•6 line-level output channels at 24-bits each

•2 line-level input channels at 24-bits each

•Mono Electret microphone input

•Optional external power supplies for ampliﬁers

•Optional internal power supplies

•EB402/EB403 TDM serial port for data

•EB402/EB403 GPIO lines for conﬁguration and control

•Interrupt lines to EB402/EB403

The codec analog outputs are limited to driving high-impedance loads.

They should only be used to drive ampliﬁed speakers that accept line-

level inputs. Do not connect passive, low-impedance (8 ohm) speakers

to these outputs. The analog inputs must also be line-level signals.

The CODEC-5.1 is fully supported by the EB402 and EB403 Board

Support Packages that are available as part of the LSI402ZX and

LSI403LP Development Kits. Please refer to the EB402 Board Support

Package User Guide or EB403 Board Support Package User Guide for

further information.

CODEC-5.1 User’s Guide 2-1

Engineering Draft

Chapter 2

Installation

This chapter describes installation of the CODEC-5.1 card. It contains

the following sections:

•Section 2.1, “Hardware Equipment Required,” page 2-1

•Section 2.2, “Hardware Setup for the CODEC-5.1 Daughtercard,”

page 2-2

•Section 2.3, “Installation,” page 2-2

2.1 Hardware Equipment Required

The following is the minimum recommended list of hardware required to

evaluate and/or use the CODEC-5.1 daughtercard:

•LSI Logic EB402 or EB403 evaluation board.

•Host computer with SDK tools and debugger interface

•CODEC-5.1 Daughtercard

•Audio output devices

– Line powered speakers, or

– Ampliﬁer with speakers, or

– Analyzer

•Input Sources

– DVD player or other SPDIF generating device

– Stereo line-level inputs

– Electret microphone

Engineering Draft

2-2 Installation

2.2 Hardware Setup for the CODEC-5.1 Daughtercard

The CODEC-5.1 daughtercard may be used with either the LSI Logic

EB402 or the EB403 evaluation boards. The daughtercard is installed

onto the SPORT0 and SPORT1 TDM interface connectors provided on

the ZSP evaluation boards. Figure 2.1 shows an illustration of the

CODEC-5.1 indicating locations of the various connectors and jumpers

on the board.

Figure 2.1 CODEC-5.1 Connectors

2.3 Installation

The installation procedure is as follows:

1. Set jumpers J3, J4, and J5 for either internal or external power as

shown in Table 2.1

BD-CODEC-5.1

SPDIF

IN SPDIF

OUT RCA Analog

IN MIC

IN L/R LS/

RS C/

LFE

RCA Out

LFE/C RS/LS L/R

R38

+12

Ext

-12

Ext

Gnd

J5 J24

Engineering Draft

Installation 2-3

2. Install J24 for input selection as shown in Table 2.2

3. Plug the CODEC-5.1 daughtercard into the motherboard. The

connectors are keyed and can only be installed in one orientation.

4. Connect an external power source to the CODEC-5.1 daughtercard

if conﬁgured from step 1. The external supply should be turned off

during connection and only turned on after the connections have

been made.

5. Connect an input source to one of the following locations as shown

in Table 2.3.

Table 2.1 Power connections

Jumper Power from

EB40X External Power

J5 Open Installed

J3 2-3 1-2

J4 2-3 1-2

J6 Open Analog Ground

J7 Open -12V DC (Acceptable range is -7Vdc to _15Vdc)

J8 Open +12V DC (Acceptable range is +7Vdc to +15Vdc)

Table 2.2 Input Selection

Jumper SPDIF Input Stereo Line Input Microphone Input

J24 2-3 2-3 1-2

Table 2.3 Input Source Connector selection

Type Input Connection -

RCA Input Connection -

PhonoJack Jumpers

Digital Audio J19 NA NA

Analog In J20 - Bottom- Left

J20 - Top - Right J25 - TIP - Left

J25 - RING - Right J24 2-3

Microphone In NA J21 - TIP J24 2-3

Engineering Draft

2-4 Installation

6. When using a microphone input, Potentiometer RX can be adjusted

to increase or decrease the gain of the microphone ampliﬁer.

7. Connect a destination to the output channels as shown in Table 2.4.

8. Note that all output channels are line-level outputs and require an

ampliﬁer or powered speakers.

9. Turn the EB402/EB403 evaluation board power on.

10. Turn on the external power supply if one is being used.

A software driver for the CODEC-5.1 daughtercard is provided in the

EB402 and EB403 Board Support Packages. These BSPs are included

on the ZSP Development Kit (ZDK) CDROM supplied with the EB402

and EB403. For details of the CODEC-5.1 driver, please refer to the

EB402 Board Support Package Technical Manual or EB403 Board

Support Package Technical Manual.

Table 2.4 Output Channel Connectors

Channel RCA PhonoJack

Left J10-CH3-Bottom J18-Tip

Right J10-CH3-Top J18-Ring

Left Surround J10-CH2-Bottom J15-Tip

Right Surround J10-CH2-Top J15-Ring

Center J10-CH1-Bottom J12-Tip

Base J10-CH1-Top J12-Ring

CODEC-5.1 User’s Guide 3-1

Engineering Draft

Chapter 3

Operation

This chapter describes the CODEC-5.1 interfaces to the EB402/EB403

cards and the operation of its circuitry. It contains the following sections:

•Section 3.1, “Interface to LSI402ZX/LSI403LP,” page 3-1,

•Section 3.2, “Circuit Description,” page 3-2

3.1 Interface to LSI402ZX/LSI403LP

The AK4586 has two interfaces: a control interface and a data interface.

The control interface is used to set the operating mode of the Codec chip

and to read status information back. The data interface is used to read

data, either digital audio or digitized analog inputs, and to write the 6

output channels.

Four GPIOs on the LSI402ZX/LSI403LP are used for the control

interface. These signals comprise a clock, chip select, data in, and data

out. All data is read and written from/to the control interface by

manipulating individual bits in the PIO register.

Serial port 0 is used for the data interface to the codec. The AK4586

codec can be conﬁgured for TDM mode. This puts all three output pairs

on a single serial port output wire and the input data on a single input

wire.

Serial port 1 is used to provide a clock input to the AK4586 when in non-

digital audio mode. By setting the clock rate of the serial port, the sample

rate of the codec can be controlled. The sample rate of the codec is

equal to the SP1 Clock Rate divided by 256. For example, to achieve a

44.1 kHz sample rate, the serial port clock rate should be 44.1K x 256

or 11.2896 MHz. Setting the EB402 clock rate at 170 MHz and using a

Engineering Draft

3-2 Operation

clock divider of 15 would yield a sample rate of 170 MHz/12/256 or 44.27

kHz, an error of 0.4%.

3.2 Circuit Description

This section describes the schematic for the audio daughtercard. The

schematics for the CODEC-5.1 card are shown at the end of this manual.

Figure A.1 shows the hierarchical connections between the various

blocks.

Figure A.2 illustrates the connections to the EB402/3. Both SPORT0 and

SPORT1 are used to provide access to the GPIO lines required. GPIO

lines on the LSI402ZX/LSI403LP chip are used to control the 4-wire

interface on the Codec. This four-wire interface is used to conﬁgure the

codec and read back status information. SPORT0 contains the serial

TDM interface between the AK4586 Codec and the ZSP processor. The

TX clock from SPORT1 is routed to the clock input of the AK4586. When

no external digital source is present, the AK4586 will automatically switch

to the clock input signal to generate it’s clock. This allows the codec rate

to be set under program control. The codec produces 2 interrupts which

are routed to the LSI402ZX/LSI403LP to pins INT2 and INT3. These

interrupt lines are used to indicate operational status like the lock signal,

non-PCM data stream, etc.

Figure A.3 contains the connections to the AK4586 Codec. A separate

+5V regulator is used to provide the +5V rail required for the AK4586.

U11 generates a reset pulse at powerup for the AK4586.

Figure A.4 shows the power supplies for the daughtercard. U2 is used to

provide the +7V supply for the op-amps when using internal power. The

analog power used by the ampliﬁers can either be produced on the

CODEC-5.1 or through an external power supply. Jumpers J3, J4, and

J5 are used to select either internally generated power or external power.

J5, when installed, shuts down both U3 and U4. U3 generates a -9V rail

from the +9V supplied from the EB402, and U4 generates -7V from the

-9V supply. The use of external supplies helps to reduce noise in

sensitive environments, while the internal supplies provide a level of

convenience for development purposes. J9 provides the common

connection between the analog and digital ground planes and must be

always installed. The artwork includes a permanent connection across J9

Engineering Draft

Circuit Description 3-3

on the top layer which can be cut for those applications requiring a

separated ground system.

Figure A.5 shows the Audio connections on and off the board. J10

contains the 6 output channels in an RCA block connector. J12, J15, and

J18 provide the same output connections in 3.5mm line-output jacks. J12

provides Left and Right channels for either 6 channel output or for stereo

output. J15 provides Left Surround and Right Surround for 6 channel

outputs. J18 provides Center and Base for 6 channel outputs. J19 is an

RCA connector for the SPDIF input source, typically a DVD player. J23

is a SPDIF output pass through connection. J20 provides an RCA-style

input connection for left and right stereo channels, and J25 provides the

input connection using a phonojack input. J21 is a microphone input for

a mono electret microphone.

Figure A.6 shows the ampliﬁers for each of the output DAC channels, the

stereo line-inputs, and the microphone input. Figure A.7 shows one of

the output DAC ampliﬁers. This ampliﬁer will produce a +/- 3V signal

suitable for driving line-level outputs.

Figure A.13 shows a line-input ampliﬁer. This ampliﬁer takes a line-level

input signal and produces a valid analog input signal for the codec.

Figure A.14 shows the microphone ampliﬁer circuit. This circuit provides

power and ampliﬁcation for an electret microphone. R38 is available on

the board to adjust the gain of the ampliﬁer.

Engineering Draft

3-4 Operation

CODEC-5.1 User’s Guide A-1

Engineering Draft

Appendix A

Schematics

January 2003

A-2 Schematics

Figure A.1

5 4 3 2 1

C C

B B

A A

BD-CODEC-5.1 A

AUDIO DAUGHTERCARD

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Title

Size Document Number Rev

Date: Sheet of

AK4586

AK4586 Codec

INT0

INT1

CSN

CCLK

CDTI

CDTO

CLK_IN

SDTI1

SDTO

LRCK

BICK

DAC_OUTPUTS[5..0]

SPDIF_OUT

SPDIF_IN

MCLK_OUT

LIN

RIN

EB Interface

EB_Connections

INT2

INT3

PIO0

PIO1

PIO2

PIO3

CLK

SP0_DOUT

SP0_DIN

SP0_XFS

SP0_RFS

SP0_CLK

POWER

CODEC_POWER

AUDIO_IO

AUDIO_IO_PAGE

DAC_OUTPUTS[5..0]

SPDIF_INPUT

SPDIF_OUTPUT

LINE_IN_LEFT

LINE_IN_RIGHT

MIC_IN

Amplifiers

DAC_OUT[5..0]

AMP_OUT[5..0]

RIN

LIN LINE_IN_LEFT

LINE_IN_RIGHT

MIC_IN

INT_2

INT_3

C_CSN

C_CCLK

C_DIN

C_DOUT

TDM_DOUT

TDM_DIN

SP_FS

DAC_O[5..0]

A_DAC_O[5..0]

LIN

RIN

LINE_IN_LEFT

LINE_IN_RIGHT

MIC_IN

CODEC_CLKIN

AKM_CLK

January 2003

A-3

Figure A.2

5 4 3 2 1

D D

C C

B B

A A

Serial Port 1 TX clock is used to drive the

Codec Xtal input signal. Must set SP1 in

continuous mode to proper clock rate (256 x

48k[fs value]) then write a word to the sp1

TX register to start the clock.

Daughtercard Interface Connections

Codec MCLK output is used to drive the BICK

which is the common clock between the codec

and the serial port. The Codec will

automatically switch from XTAL input to PLL

input when a valid PLL clock is found, ie

from a DVD player.

SPORT_0 SPORT_1

BD-CODEC-5.1 A

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Title

Size Document Number Rev

Date: Sheet of

DGND DGND

3.3V

+9V +9V

0.1u

R2 33.2

CON20

U1A

7404

1 2

147

R1 33.2

INT2 INT3

PIO0

PIO1 PIO2

PIO3

CLK

SP0_DOUT

SP0_DIN

SP0_XFS

SP0_RFS

SP0_CLK

January 2003

A-4 Schematics

Figure A.3

5 4 3 2 1

D D

C C

B B

A A

AKM 4586 Codec

BD-CODEC-5.1 A

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Title

Size Document Number Rev

Date: Sheet of

AGND

DAC_OUTPUTS2

DAC_OUTPUTS5

DAC_OUTPUTS4

PVDD

DAC_OUTPUTS3

DAC_OUTPUTS0

DVDD

DAC_OUTPUTS1

ADJ_5

RSTN

3.3V

+5V

+5V +9V

18.2K

R3 5.1

U10

LT1763CS8

OUT

SENSE

GND

BYP SHDN

GND

0.1u

10u

AK4586

XTO

EXTCLK

DVDD

DVSS

TVDD

TXMCKO

LRCK

BICK

SDTO

SDTI1

SDTI2

SDTI3

INT0

INT1

CDTO

CDTI

CCLK

CCSN

DZF2

AVSS

AVDD

VREFH

VCOM

DZF1

LOUT3

ROUT3

LOUT2

ROUT2

LOUT1

ROUT1

LIN

RIN

PVDD

PVSS

RX4

SLAVE

RX3

TST

RX2

I2C

RX1

PDN

10u

0.1u

C10

2.2u

C19

10u

0.1u

5.1

U11

MCP130-485

RST

VDD

VSS

10u

R51

10.0K

C21

0.01u

C11

0.1u

10u

0.1u

R50

32.4K

CSN

CCLK

CDTI

CDTO

CLK_IN

SDTI1

SDTO

LRCK

BICK

DAC_OUTPUTS[5..0]

SPDIF_OUT

SPDIF_IN

INT1

INT0

MCLK_OUT

RIN

LIN

January 2003

A-5

Figure A.4

5 4 3 2 1

D D

C C

B B

A A

gnd is pin 3

Always Installed

Install for

External

Internal Internal

Power Supplies, Internal and External

External External

GND_POWER GND

BD-CODEC-5.1 A

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Title

Size Document Number Rev

Date: Sheet of

ADJ_P

DGND

ADJ_P

ADJ_M

AGND

+9V -9V

-9V

-7V

+9V

PLUS_AMP_PWR

+7V

NEG_AMP_PWR

-7V +7V

NEG_AMP_PWR

N12V_EXT

PLUS_AMP_PWR

P12V_EXT

B130L

J7 BANANA_BLK

C18

0.1u

C16

100u

C26

0.1u

R49

470 1/4W

B130L

C17

10u

LT1763CS8

OUT

SENSE

GND

BYP SHDN

GND

R46

8.45K

C24

10u

CON2

J6 BANANA_BLK

C12

10u

CON2

R48

470 1/4W

LT1175CS8

4 5

Vin

Ilim2

Out

Sense Gnd

SHDN

Ilim4

Vin

CON3

C22

10u

J8 BANANA_RED

C20

10u

CON3

LT1054CS8

BOOST

GND

VOUT

SHDN

OSC

V+

CAP+

CAP-

R45

10.0K

C14

0.01u

LED

R47

10.0K

C13

10u

C15

100u

R44

47.5K

LED

January 2003

A-6 Schematics

Figure A.5

5 4 3 2 1

D D

C C

B B

A A

Connectors

NOTE: DAC_OUTPUTS 5, 3, AN D

1 ARE RIGHT; DAC_OUTPUTS 4,

2, AND 0 ARE LEFT

DAC_OUTPUTS0 = CH3 BOT = J18 TIP = LEFT

DAC_OUTPUTS1 = CH3 TOP = J18 RING = RIGHT

DAC_OUTPUTS2 = CH2 BOT = J15 TIP = LS

DAC_OUTPUTS3 = CH2 TOP = J15 RING = RS

DAC_OUTPUTS4 = CH1 BOT = J12 TIP = CENTER

DAC_OUTPUTS5 = CH1 TOP = J12 RING = BASE

BD-CODEC-5.1 A

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Title

Size Document Number Rev

Date: Sheet of

AGND

DGND

DAC_OUTPUTS0

DAC_OUTPUTS3

DAC_OUTPUTS5

DAC_OUTPUTS2

DAC_OUTPUTS4

DAC_OUTPUTS1

DAC_OUTPUTS4

DAC_OUTPUTS3

DAC_OUTPUTS2

DAC_OUTPUTS4

DAC_OUTPUTS5

DAC_OUTPUTS0

DAC_OUTPUTS2

DAC_OUTPUTS3

DAC_OUTPUTS0

DAC_OUTPUTS1

75.0

J23

RCJ-01

J10

RCJ-61

9J18

STEREOJACK

J19

RCJ-01

33.2

J21

STEREOJACK

TRANSFORMER

1 4

3 6

J12

STEREOJACK

100

J20 RCJ-22

J15

STEREOJACK

C28

0.1u

J25

STEREOJACK

DAC_OUTPUTS[5..0]

SPDIF_INPUT

SPDIF_OUTPUT

LINE_IN_LEFT

LINE_IN_RIGHT MIC_IN

January 2003

A-7

Figure A.6

5 4 3 2 1

D D

C C

B B

A A

MIC IN 1-2

LINE IN 2-3

Amplifiers for Input, Output, and Microphone

BYPASS

FOR U5

BYPASS

FOR U6

BYPASS

FOR U7

BYPASS

FOR U8

BD-CODEC-5.1 A

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Title

Size Document Number Rev

Date: Sheet of

AMP _1

out_amp

IN OUT

AMP _2

out_amp

IN OUT

AMP _3

out_amp

IN OUT

AM P

out_amp

IN OUT

AMP _4

out_amp

IN OUT

AMP _5

out_amp

IN OUT

IN_AMP_1

input_amp

LINE_INAMP_OUT

IN_AMP

input_amp

LINE_INAMP_OUT

MIC_AMP

MICIN MIC_AMP

DAC_OUT5

DAC_OUT4

DAC_OUT3

DAC_OUT2

DAC_OUT0

DAC_OUT1

AMP_OUT5

AMP_OUT4

AMP_OUT3

AMP_OUT2

AMP_OUT1

AMP_OUT0 PLUS_AMP_PWR NEG_AMP_PWR

NEG_AMP_PWRPLUS_AMP_PWR

C44

10u

C65

10u

C53

10u

C69

0.1u

C29

10u

C30

0.1u

C57

0.1u

C41

10u

C68

10u

C54

0.1u

C45

0.1u

C56

10u

J24

CON3

C33

0.1u

C42

0.1u

C66

0.1u

C32

10u

DAC_OUT[5..0] AMP_OUT[5..0]

LIN

RIN

LINE_IN_LEFT

LINE_IN_RIGHT

MIC_IN

January 2003

A-8 Schematics

Figure A.7

5 4 3 2 1

Output Amplifier for each DAC channel

BD-CODEC-5.1 A

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Title

Size Document Number Rev

Date: Sheet of

AGND

NEG_AMP_PWR

PLUS_AMP_PWR

U5A

OPA2227

C34 330p

R12 4.75K

R9 221

R11

4.75K

R10

10.0K

C31

22u

IN OUT

January 2003

A-9

Figure A.8

5 4 3 2 1

Output Amplifier for each DAC channel

BD-CODEC-5.1 A

PRO AUDIO DAUGHTERCARD

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Title

Size Document Number Rev

Date: Sheet of

AGND

NEG_AMP_PWR

PLUS_AMP_PWR

U5B

OPA2227

C40 330p

R16 4.75K

R13 221

R15

4.75K

R14

10.0K

C37

22u

IN OUT

January 2003

A-10 Schematics

Figure A.9

5 4 3 2 1

Output Amplifier for each DAC channel

BD-CODEC-5.1 A

PRO AUDIO DAUGHTERCARD

915Monday, December 16, 2002

Title

Size Document Number Rev

Date: Sheet of

AGND

NEG_AMP_PWR

PLUS_AMP_PWR

U6A

OPA2227

C46 330p

R20 4.75K

R17 221

R19

4.75K

R18

10.0K

C43

22u

IN OUT

January 2003

A-11

Figure A.10

5 4 3 2 1

Output Amplifier for each DAC channel

BD-CODEC-5.1 A

PRO AUDIO DAUGHTERCARD

10 15Monday, December 16, 2002

Title

Size Document Number Rev

Date: Sheet of

AGND

NEG_AMP_PWR

PLUS_AMP_PWR

U6B

OPA2227

C52 330p

R24 4.75K

R21 221

R23

4.75K

R22

10.0K

C49

22u

IN OUT

January 2003

A-12 Schematics

Figure A.11

5 4 3 2 1

Output Amplifier for each DAC channel

BD-CODEC-5.1 A

PRO AUDIO DAUGHTERCARD

11 15Monday, December 16, 2002

Title

Size Document Number Rev

Date: Sheet of

AGND

NEG_AMP_PWR

PLUS_AMP_PWR

U7A

OPA2227

C58 330p

R28 4.75K

R25 221

R27

4.75K

R26

10.0K

C55

22u

IN OUT

January 2003

A-13

Figure A.12

5 4 3 2 1

Output Amplifier for each DAC channel

BD-CODEC-5.1 A

PRO AUDIO DAUGHTERCARD

12 15Monday, December 16, 2002

Title

Size Document Number Rev

Date: Sheet of

AGND

NEG_AMP_PWR

PLUS_AMP_PWR

U7B

OPA2227

C64 330p

R32 4.75K

R29 221

R31

4.75K

R30

10.0K

C61

22u

IN OUT

January 2003

A-14 Schematics

Figure A.13

5 4 3 2 1

D D

C C

B B

A A

Line Input Amplifier

BD-CODEC-5.1 A

AUDIO DAUGHTERCARD

13 15Monday, December 16, 2002

Title

Size Document Number Rev

Date: Sheet of

AGND

PLUS_AMP_PWR

NEG_AMP_PWR

R35

33.2

U8A

OPA2227

R33 33.2

C67

10u

R34

OPEN

LINE_IN AMP_OU T

January 2003

A-15

Figure A.14

5 4 3 2 1

D D

C C

B B

A A

Microphone Input Amplifier

CLOCKWISE FOR LOUDER

BD-CODEC-5.1 A

AUDIO DAUGHTERCARD

14 15Monday, December 16, 2002

Title

Size Document Number Rev

Date: Sheet of

PLUS_AMP_PWR

NEG_AMP_PWR

PLUS_AMP_PWR

C75

0.1u

C73

0.1u

C74

10u

C71

0.1u

R38

100K_POT

U9A

LM358D

U9B

LM358D

R40

10.0K

R37

10.0K

R36

10.0K

C70

10u

C72

10u

R39

1.00K

MICIN MIC_AMP

January 2003

A-16 Schematics

Figure A.15

5 4 3 2 1

D D

C C

B B

A A

Line Input Amplifier

BD-CODEC-5.1 A

PRO AUDIO DAUGHTERCARD

15 15Monday, December 16, 2002

Title

Size Document Number Rev

Date: Sheet of

AGND

PLUS_AMP_PWR

NEG_AMP_PWR

R43

33.2

U8B

OPA2227

R41 33.2

C78

10u

R42

OPEN

LINE_IN AMP_OU T