PS3422-0600
2365 NE Ho p kin s Co urt
Pullman, WA 99163-5601
tel: 509.334.1000
fax: 509.334.9000
e-mail: sales@aha . com
www.aha.com
advancedhardwarearchitectures
Product Specification
AHA3422 StarLiteTM
16 MBytes/sec Lossless
Decompressor IC
Advanced Hardware Architectures, Inc.
PS3422-0600 i
Table of Contents
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 Data Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 Pad Word Handling in Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.4 DMA Request Signals and Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.4.1 FIFO Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.4.2 Request During an End-of-Record. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4.3 Request Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.6 Odd Byte Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6.1 Input, Pad Bytes and Error Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6.2 Output and Pad Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.7 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.7.1 Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.8 Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.9 Decompression Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.10 Prearming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.12 Duplex Printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2
3.13 Blank Bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.14 Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.15 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.1 System Configuration 0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.2 System Configuration 1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3 Input FIFO Thresholds, Address 0x02 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.4 Output FIFO Thresholds, Address 0x03 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.5 Decompression Ports Status, Address 0x05 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.6 Port Control, Address 0x06 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.7 Interrupt Status/Control 0, Address 0x07 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.8 Interrupt Mask 0, Address 0x09 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.9 Version, Address 0x0A - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 8
4.10 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write. . . . . . . . . . . . . . . . . . . .18
4.11 Decompression Control, Address 0x18 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.12 Decompression Reserved, Address 0x1A, 0x3A - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.13 Decompression Line Length, Address 0x1C, 0x1D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.14 Interrupt Status/Control 1, Address 0x27 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.15 Interrupt Mask 1, Address 0x29 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.16 Decompression Record Count, Address 0x2C, 0x2D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.17 Pattern, Address 0x35 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.18 Decompression Control Prearm, Address 0x38 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.19 Control, Address 0x3F - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1
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5.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.2 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.3 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.4 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
7.0 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7.1 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7.2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8.0 AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
10.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
10.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
10.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
11.0 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 6
Appendix A: Additional Timing Diagrams for DMA Mode Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Appendix B: Sequential Register Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Advanced Hardware Architectures, Inc.
PS3422-0600 iii
Figures
Figure 1: Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . .6
Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . .6
Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=100. . . . . . . .6
Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=100 . . . . . . .7
Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=100. . . . . . .7
Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DS C=100. . . . . . .7
Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 14: Timing Diagram, Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 15: Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 16: Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 17: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0. . . . . . . . . . . . . . . . . . . . . . .28
Figure 18: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1. . . . . . . . . . . . . . . . . . . . . . .29
Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0 . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1 . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 21: Output Enable Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 22: Video Output Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 23: Microprocessor Interface Timing (PROCMODE[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 24: Microprocessor Interface Timing (PROCMODE[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 25: Interrupt Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 26: Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 27: Power On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . .37
Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . .37
Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=000. . . . . . .37
Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=000 . . . . . .38
Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=000. . . . . .38
Figure A6: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=000. . . . . .38
Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . .39
Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . .39
Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=010. . . . . . .39
Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=010 . . . . . .40
Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=010. . . . . .40
Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=010. . . . . .40
Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . .41
Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . .41
Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011. . . . . . .41
Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=011 . . . . . .42
Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=011. . . . . .42
Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=011. . . . . .42
Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . .43
Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . .43
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Tables
Table 1: Data Bus and FIFO Sizes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 2: Connection to Host Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3: Microprocessor Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 4: Internal Strobe Conditions for DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 5: Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 6: Data Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 7: Request vs. EOR Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 8: Output Enable Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 9: Video Output Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 10: Microprocessor Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 11: Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 12: Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 13: Power On Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PS3422-0600 Page 1 of 44
Advanced Hardware Architectures, Inc.
1.0 INTRODUCTION
AHA3422 is a lossless decompression
coprocessor IC for hardcopy systems on many
standard platforms. The device is targeted for high
throughput and high resolution hardcopy systems.
Multiple record counters, higher clock
frequency, advanced banding and duplex printing
features enhance this product from the first
StarLite introduction, AHA3410. Identical
decompression algorithm and similar firmware
considerations ease migration to this second
generation device.
Blank band generation in real time and
prearming registers between records enable
advanced banding techniques. Bands may be in raw
uncompressed, compressed or blank format in the
frame buffer. The device processes all three formats
and outputs the raster data to the printer engine.
Appropri ate registers are prearmed when swit ching
from one type t o the next . Byte or dering all ows full
reversal of the image data for duplex printing
support. A system may use multiple record counters
and End-of-Transfer interrupts to easily handle
pages partitioned into smaller records or bands.
This docume nt contains f unctional descr iption,
system configurations, register descriptions,
electrical characteristics and ordering information.
It is inten ded for system designers c onsi derin g a
decompression coprocessor in their embedded
applications. Software simulation and an analysis of
the algorithm for p r inter and copier image s of
various complexity are also available for
evaluation. A comprehensive Designer’s Guide
complements this document to assist with the
system design. Section 11.0 contains a list of related
technical publications.
1.1 CONVENTIONS, NOTATIONS AND
DEFINITIONS
–Active low signals h ave an “N” appended to the
end of the signal name. For example, CSN and
RDYN.
–A “bar” over a signal name indicates an inverse of
the signal. For example, SD indicates an inverse
of SD. This terminology is used only in logic
equations.
–“Signal assertion” means the output signal is
logically true.
–Hex values are represented with a prefix of “0x”,
such as Register “0x00”. Binary values do not
contain a prefix, for example, DSC=000.
–A range of signal names or register bits is denoted
by a set of colons between the numbers. Most
signif icant bit i s a lway s shown fir st , followed by
least significant bit. For example, VOD[7:0]
indicates signal names VOD7 through VOD0.
–A logical “AND” function of two signals is
expressed w i th an “&” between variables.
–Mega Bytes per second is referred to as MBytes/
sec or MB/sec.
–In refe rencing microproc essors, an x, xx or xxx is
used as suffix to indicate more than one
process or. For example, Motor ola 68xxx
processor family includes various 68000
processors from Motorola.
–Reserved bits in reg isters are referred as “res”.
–REQN or ACKN refer to either DI, or DO
Request or Acknowledge signals, as applicable.
–NC in pinout description means “no connect”.
1.2 FEATURES
PERFORMANCE:
•16 MBytes/sec maximum sustained data
throughput
•132 MBytes/sec burst data rate over a 32-bit data bus
•33 MBytes/sec synchronous 8-bit video out port
•Maximum clock speeds up to 33 MHz
•Average 15 to 1 compression ratio for 1200 dpi
bitmap image data
•Advanced banding support : bl ank ba nds,
prearming
FLEXIBILITY:
•Big Endian or Little Endian; 32 or 16-bit bus
width and data byte reordering for duplex printing
support
•Prearmab le reg isters
•Scan line length up to 2K bytes
•Interfaces directly with various MIPS, Motorola
68xxx and Cold FIRE, Intel i960 embedded
processors
•Pass-through mode passes raw data through the
decompression engine
•Counter checks errors in decompression
SYSTEM INTERFACE:
•Single ch ip decompres sion solutio n – no exte rnal
SRAM required
•Two 16 × 32-bit FIFOs with programmable
threshold counters facilitate burst mode transfers
OTHERS:
•Low power modes
•Software emulation program available
•128 pin quad flat package
•Test pin tr istates output s
Page 2 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
Figure 1: Functional Block Diagram
1.3 FUNCTIONAL OVERVIEW
The coprocessor device has two external high
speed synchronous data ports capable of transferring
once every clock cycle. These are a 32-bit
bidirectional data port and a Video Output Data
(VOD) port. The 32-bit port is capable of
transferring up to 4 bytes per clock. The VOD is
capable of up to one byte per clock.
Decompression data is accepted through the 32-
bit data port, buffered in the Decompression Input
FIFO (DI FIFO) and decompressed. The output data
is made available on the 32-bit data port via the
Decompression Output FIFO (DO FIFO) or the 8-
bit Video Output port. The decompression engine
runs on the 33 MHz clock and is capable of
processing an uncompressed byte every other clock.
The two FIFOs are organized as 16×32 each.
For data transfers through the two ports, the
“effective” FIFO sizes dif fer according to their data
bus widths. The table below shows the size of the
data port and the “effective” FIFO size fo r the
various configurations supported by the device.
Table 1: Data Bus and FIFO Sizes Supported
Table 2: Connection to Host Microprocessors
D[31:0]
DRIVEN
TEST
CLK
RSTN
PROCMODE[1:0]
PD[7:0]
PA[5:0]
CSN
DIR
RDYN
INTRN
VOACKN
VOD[7:0]
VOREQN
VOEORN
VOEOTN
(To Pri n ter)
DATA
PORT
DI
FIFO
16x32
CLOCK
DECOMPRESSOR
MICROPROCESSOR INT ERFACE
DO
FIFO
16x32
VOD
PORT
AHA3422
StarLiteTM
888
32
32 32
6
8
DOREQN
DIREQN
SD
DOACKN
DIACKN
DATA PORT CONTROL
OPERATION DATA BUS WIDTH PORT EFFECTIVE FIFO SIZE
Decompression Data In/Out 32 Data Port 16 x 32
Decompression Data In/Out 16 Data Port 16 x 16
Decompressed Data Out 8 Video Out 16 x 8
PIN NAM E i960 Cx i960Kx IDT3 08 1 Motorola
MCFS102(ColdFIRE)
PA A LAD Latched Address Latched Address
CSN CS CS System Dependent Decoded Chip Select
DIR W/R W/R WR R/W
PD D LAD A/D A/D[7:0]
SD WAIT READY System Dependent System Dependent
RDYN No Connect READY ACK TA
DRIVEN DEN System Dependent System Dependent System Dependent
CLOCK PCLK No Connect SYSCLK BCLOCK
PS3422-0600 Page 3 of 44
Advanced Hardware Architectures, Inc.
Movement of data for decompression is
performed using synchronous DMA over the 32-bit
data port. The V ideo port also supports synchronous
DMA mode transfers. The DMA strobe conditions
are configurable for the 32-bit data port depending
upon the system processor and the available DMA
controller.
Data transfer for decompression is synchronous
over the two data ports functioning as DMA
masters. T o initiate a transfer out of the V ideo port,
the device asserts V OREQN, the external device
responds with VOACKN and begins to transfer data
over the VOD bus on each succeeding rising edge of
the clock until VOREQN is deasserted. The 32-bit
port relies on the FIFO Threshold settings to
determine the transfer.
The sections below describe the various
configurations, programming and other special
considerations in developing a decompression
system using AHA3422.
2.0 SYSTEM CONFIGURATION
This section provides information on
connecting the device to various microprocessors.
Data throughput is internally controlled by
writing a control code to the Control register. If this
feature is not used, the system must control data
throughput to remain within the specified limit of 16
MBytes/sec. The control code for this device is 0x0E.
2.1 MICROPROCESSOR INTERFACE
The device i s capable of i nte rf aci ng directly to
various processors for embedded application. T able 2
and Table 3 show how to connect t o var iou s host
microprocessors.
All regi ster accesse s are performed on the 8 -bit
PD bus. The PD bus is the lo west byte of the 32-bit
micropr ocessor bu s. During reads of the inte rnal
registers, the upper 24 bits are not driven. System
designers should terminate these lines with Pullup
resistors.
The part provides four modes of operation for
the microprocessor port. Both active high and active
low writ e enabl e si gnals are al lowed a s well as two
modes for c hip se lect. T he mode of oper atio n is set
by the PROCMODE[1:0] pins. The
PROCMODE[1] signal select s whe n CSN must be
active and also ho w long an access last s.
When PROCMODE[1] is high, CSN
determines the length of the ac cess. CSN must be at
least 5 clocks in length. On a read, valid data is
driven ont o PD[7:0] during th e 5th clock . If CSN is
longer than 5 clocks, then valid data continues to b e
driven out onto PD[7:0]. When CSN goes inactive
(high), PD[7:0] goes tristate (asynchronously) and
RDYN is driven high asynchronously . CSN must be
high for at least two clocks. RDYN is always driven
(it is not tristated when PRO CMO DE[1] is high). The
mode is typical of processors such as the Motorola
68xxx.
When PROCMODE[1] is low, accesses are
fixed at 5 cl ocks, PD[7: 0] is onl y driven dur ing the
fifth cloc k, and RDYN is drive n high for the first 4
clocks and low during the fifth clock. RDYN is
tristated at all other times. Write data must be driven
the clock afte r CSN is sampled low. Acce sses may
be back to back with no delays in between. This
mode is typical of RISC processors such as the i960.
PROCMODE[0] determines the polarity of the
DIR pin. If PROCMODE[0] is high, then the DIR
pin is an active low write enable. If PROCMODE[0]
is low, then the DIR pin is an active high write
enable. Figure 2 through Figure 5 illustrate the
detailed timing diagrams for the microprocesso r
interface.
For additional notes on interfacing to various
microprocessors, refer to AHA A pplication No te
(ANDC16), Designer’ s Guide for StarLiteTM Family
Products. AHA Applications Engineering is
availa ble to support with othe r processors not in the
Designer’s Guide.
Table 3: Microprocessor Port Configuration
PROCMODE[1:0] DIR CYCLE LENGTH EXAMPLE PROCESSOR
00 Active high write fixed i960
01 Active lo w write fixed
10 Active high write variable
11 Active low write variable 68xxx, MIPS R3000
Page 4 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”)
Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”)
Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”)
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0 D1
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0
A2
D1
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0
PS3422-0600 Page 5 of 44
Advanced Hardware Architectures, Inc.
Figure 5: Microprocessor Port Read (PROC MO DE[1: 0] = “11”)
3.0 FUNCTIONAL DESCRIPTION
This secti on de scr ibes the var ious data port s,
special handling, data formats and clocking structure.
3.1 DATA PORTS
The device contains one data input port, DI, and
one data output port, DO, on the same 32-bit data bus,
D[31:0]. Data transfers are controlled by external
DMA control. The logical conditions under which data
is written to the input FIFO or read from the output
FIFO are set by the DSC (Data Strobe Condition) field
of the System Configuration 1 register.
A strobe condition defines under what logical
conditions the input FIFO is written or the output
FIFO read. DIACKN, DOACKN, and SD pins
combine to strobe data in a manner similar to DMA
control le rs. The DMA Mode sub-section describes
the various data strobe options.
3.2 DMA MODE
On the rising edge of CLOCK when the strobe
condition is met, the port with the active
acknowledge either strobes data into or out of the
chip. No more than one port may assert acknowledge
at any one time. T able 4 shows the various conditions
that may be programmed into register DSC.
Figure 6 through Figure 11 illustrate the DMA
mode timings for singl e, fou r word and ei ght word
burst transfers for DSC=100 selection. For other
DSC settings, please refer to Appendix A. Note that
the only di ffere nce between odd and even val ues of
DSC is the polarity of SD. Waveforms are only
shown for polarities of SD corresponding to specific
systems.
Table 4: Internal Strobe Conditions for DMA Mode
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0
DSC[2:0] LOGIC EQUATION SYSTEM CONFIGURATION
000 i960Cx with int ernal DMA controll er. SD is connecte d to
WAITN.
001 No speci fic system
010 General purpose DMA controller
011 i960Kx with external, bus master type DMA controller.
SD is connected to RDYN.
100 No speci fic system
101 No speci fic system
110 No specific system
111 N o specific system
ACKN()& ACKNdelayed
()& SD()
ACKN()& ACKNdelayed
()& SD()
ACKN()& SD()
ACKN()& SD()
ACKNdelayed
()& SDdelayed
()
ACKNdelayed
()& SDdelayed
()
ACKN()& ACKNdelayed
()
ACKN()& ACKNdelayed
()
CKNdelayed ACKN delayed 1 clo ck=
SDdelayed SD delayed 1 clock=
Page 6 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100
Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100
Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
DD0 D1
CLOCK
ACKN
SD
DRIVEN
DD1D0
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3
PS3422-0600 Page 7 of 44
Advanced Hardware Architectures, Inc.
Figure 9: DMA Mode Timing for Four Word Burst Read, One Wa it State, Strobe Condition
of DSC=100
Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=100
Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
DD1D0 D2 D3
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3 D4 D5 D6 D7
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3 D4 D5 D6 D7
Page 8 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
3.3 PAD WORD HANDLING IN
BURST MODE
A method is available to delete pad words during
decompression. Pad words may be deleted by using
the Decompression Pause on Record Boundaries bit
(DPOR), in the Decompression Control register.
After the part is paused, the DI FIFO must be reset by
asserting the DIRST bit in the Port Control register.
Decompressor must also be reset by asserting DDR
bit in Decompression Control register.
3.4 DMA REQUEST SIGNALS
AND STATUS
The part requests data using request pins
(DIR EQN , DOREQN) . The req ues ts a re co nt rol le d
by programmable FIFO thresholds. Both input and
output FIFOs have programmable empty and full
thresholds set in the Input FIFO Thr e shol d and
Output FIFO Threshold registers. By requesting
only when a FIFO can sustain a certain burst size, the
bus is used more efficiently.
Operation of these request signals should not be
confused with the request signals on the video port.
DIREQN active indicates space available in the input
FIFO and DOREQN active indicates data is available
in the output FIFO. These request signals being
inactive do not prevent data transfers. The data
transfers are controlled solely with the particular
acknowledge signal being active.
The input request, DIREQN, operates under the
following prioritized rules, listed in order of highest
to low est:
1) If the FIFO reset in the Port Control
register i s activ e, the requ est is inactive .
2) If a FIFO overflow interrupt is active, the
request is inactive.
3) If the FIFO is at or below the empty
threshold, the request remains active.
4) I f the FIFO is at or above the full threshold,
the reque st stays inactiv e.
The output request, DOREQN, operates under
the following prioritized rul es, li sted in orde r of
highest to lowest:
1) If the FIFO res et in th e Port Control
register is active, the request is inactive.
2) If the out put FIFO un derflow interrupt is
active, the request is inactive.
3) If an EOR is present in the output FIFO, the
request goes active.
4) If the output FIFO is at or above the full
threshold, the reques t goes acti ve.
5) If an EOR is read (strobed) out of the FIFO,
the request goes inactive during the same
clock as the strobe (if ERC=0), oth erwise it
goes inactive on the next clock.
6) I f the output FIFO is at or below t he empty
threshold, the reques t goes in act iv e.
3.4.1 FIFO THRESHOLD
For maxi mum efficiency, the FIFO t hreshold
should be set in such a way that the decompressor
seldom runs out of data from the DI FIFO or
completely fills the output FIFO. The FIFO is 16
words deep.
For example, in a system with fixed 8-word
bursts, good values for the thresholds are:
IET=3, IFT=4, OFT=D, OET=C
Setting the input full threshold to one higher
than the input empty threshold simply guarantees
that the request deasserts as soon as possible. The
latency between a word being strobed in and the
request changing due to a FIFO threshold condition
is 3 c l oc k s . Th i s sh o ul d be ke pt in mi nd when
programming threshold values. Refer to Section 4.0
of AHA Ap p l i c at i o n Not e (ANDC16) , Designer’s
Guide for StarLiteTM Family Products for a more
thorough discussion of FIFO thresholds. The
following figure shows an example of an input FIFO
crossing its full threshold.
PS3422-0600 Page 9 of 44
Advanced Hardware Architectures, Inc.
Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO)
Note: DIREQN deassert ed when threshold counter exceeded IFT=4, but additional words are read a s lo ng as
ACKN is asserted.
Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010
3.4.2 REQUEST DURING AN END-OF-RECORD
The request deasserts at an EOR in one of two
ways. If ERC bit in System Configura tion 1 is zero,
the reque st dea sserts as ynch ronously d uring the
clock where the EOR is strobed out of the FIFO.
This leads to a long output delay for REQN, but may
be necessary in some systems. For DSC values of 4
or 5, the reque st deasse rts the first cloc k after the
acknowledge pulse for the EOR. If ERC is set to
one, then the request deasserts synchronously the
clock after the EOR is strobed out. The minimum
low time on the requ est in this case is one cloc k.
The request delay varies between the different
strobe conditions. See Section 8.0 AC Electrical
Specifications for further details.
3.4.3 REQ UE ST STATUS BITS
An external microprocessor ca n also rea d the
value of each request using the DIREQ and DOREQ
bits in the Decom pression P ort Status register.
Please note the request status bits are active high
while the pins are active low.
3.5 DATA FORMAT
The w idth of th e D bus is selec ted wi th the
WIDE bit in System Configuration 0. If WIDE=1,
then D is a 32-bit bus. If WIDE=0, D is a 16-bit bus.
If the bus is configured to be 16-bits wide
(WIDE=0), all data transfers occur on D[15:0] and
the upper 16 bits of the bus, D[31:16], should be
terminated with Pullup resistors. If WIDE=0, the
FIFO is sixteen words deep.
CLOCK
D
CIACKN
CIREQN
Threshold
12345
678
12345678
9
Counter
EOR-2
CLOCK
D
CIACKN
REQN
EOR-1 EOR
(ERC=0)
EORN
REQN
(ERC=1)
Page 10 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
Since the compression algorithm is byte
oriented, it is necessary for AHA3422 to know the
ordering of the bytes within the word. The
DECOMP BIG bit in System Configuration 0 selects
between b ig endian and li t tl e e ndian byte or der in g.
Little end ian stores the fi rst byte in the lower eig ht
bits of a word (D[7:0]). Big endian stores the first
byte i n the uppermost eight bits of a word (D[ 31:2 4]
for WIDE=1, D[15:8] for WI DE=0) .
3.6 ODD BYTE HANDLING
All data transfers to or from the device are
perfor med on the D bu s on wo rd bounda ries . Since
no provision is made for single byte transfers,
occasionally words will contain pad bytes.
Following is a descr ipt io n of when t hes e pad byt es
are necessary for each of the data interfaces.
3.6.1 INPUT, PAD BYTES AND ERROR
CHECKING
The device recognizes the end of a record by the
appeara nce of a speci al End-o f-Record sequen ce in
the data stream. Once this is seen, the remaining
bytes in the current word are treated as pad bytes
and discarded. The word following the end of the
record is the beginning of the next record.
The Decompression Record Length (DRLEN)
regist er can be u sed to pr ovi de error c hecking. The
expected length of the decompressed record is
programmed into the DRLEN register. The
decompressor then counts down from the value in
DRLEN to zero.
A DERR interrupt is is sued if an E OR is not
read out of the decompressor when the counter
expires or if an EOR occurs before the counter
expires (i.e., when the record lengths do not match).
If the DERR interrupt is masked, use of the DRLEN
register is optional.
When operating in pass-t hrough mode, there is
no End-of-Record codeword for the decompressor
to see. In pass-through mode, the user must set the
record length in the DRLEN register.
3.6.2 OUTPUT AND PAD BYTES
When the decompressor detects an End-of-
Record codeword, it will add enough pad bytes of
value 0x00 to complete the current word as defined
by the WIDE bit in the System Configuration 0
register. For example, if a record ends on a byte
other than the last byte in a word, the final word
contains 1, 2 or 3 pad bytes. This applies to the 32-
bit data port only, not the VOD port . The VOD port
never outputs pad bytes since it is 8-bits wide.
3.7 VIDEO INTERFACE
3.7.1 VIDEO OUTPUT
The vide o output por t i s ena bl ed by the VDOE
bit in th e Syste m Configurat ion 1 regi st er. The port
uses VOREQN to ind icate that the by te on
VOD[7:0] is valid. An 8-bit word is read each clock
when both VOREQN and VOACKN are sampled
low on a rising edge of CLOCK. Pad bytes at an end
of recor d are discarded by the video output port and
do not appear on VOD[7:0]. When the byte on
VOD[7:0] is the last byte in a record, the VOEORN
signal goes low. Unlike a DMA transfer, there are no
pad bytes after an End-of-Record.
VOEOTN operates similar to VOEORN. It flags
the end of an output transfer of one or more
decompressed records. VOEOTN is asserted when the
End-of-Record is at the output of the DO FIFO and the
decompression record count has decremented to zero.
The port requests whenever a valid byte is
present on t he output. The va lues in OET a nd OFT
are all ignored. The decompression output FIFO is
16 bytes deep in this mode. The video output port
can output up to one byte per clock. The DMA
interface cannot access the decompression output
FIFO when VDOE is set.
Figure 14: Timing Diagram, Video Output
CLOCK
VOREQN
VOACKN
VOD[7:0] 0 31 2 4 5
VOEORN/
VOEOTN
PS3422-0600 Page 11 of 44
Advanced Hardware Architectures, Inc.
3.8 ALGORITHM
AHA3422 ef ficientl y imple ments an algori th m
optimized f or bitonal i mages. For some compar ison
data ref er t o the AHA Applica ti on Note (AN DC13),
Compr ession Performance: StarLiteTM:
ENCODEB2 on Bitonal Images. A software
emulat ion of the algorithm is availa ble for
evaluation.
3.9 DECOMPRESSI ON ENGINE
The decompression engine is enabled with the
DCOMP bit in the Deco mpr ession Contr ol register .
When the engine is enabled , it takes data fro m the
DI FIFO as it become s available. This dat a is either
decompressed by the engine or passed through
unaltered. Pass-through mode is selected with the
DPASS bit. DPASS may only be changed when
DCOMP is set to zero and DEMP is set to one. The
contents of the dictionary are preserved when
DCOMP is changed. However, when DPASS is
changed, the contents are lost. Consequently,
AHA3422 cannot be changed from pass-through
mode to decompr ession mode or vice versa without
losing the contents of the dictionary.
The decompressor can be instructed to halt at the
end of a record or an en d of multip le-record transfer.
If the DPOR bit is set, the decompressor stops taking
data out of the DI FIFO i mmediat ely after t he l ast
byte of a r ecor d, and t he DCOMP bit i s c lear ed. I f
DPOT bit is set the decompress or halts at the end of
the multiple-record transfer . The DEMP bit indicates
the decompres sor has e mptied of all data . Decom-
pression i s r est art ed by setti ng the DCOMP bit. If
DPOR or DPOT is set and data from a se cond record
enters the FIFO immediately after the first record,
bytes from the second r ecord will ha ve en tered the
decompressor pri or t o decoding the EOR. An imp li-
cation of this is that bytes from the second record will
remain in the decompressor and prevent DEMP from
setting after a ll of t he dat a f rom th e fi rst record has
left t he decompresso r . This dif fer s from opera tion of
the compress ion engine. In e it her mode, a DEOR
interru pt is genera ted when t he last byt e of a de com-
pressed r ecor d is rea d out of the chi p, and DEOT
when the last byte of a transfer is read out of the chip.
The decompressor takes data from the
decompression input FIFO at a maximum rate of
16 MBytes/sec. AHA3422 can maintain this data
rate a s long as the deco mpressi on input FIFO is not
empty or the decompression output FIFO is not full.
Caveat: Changing the mode for the
decompressor between records or multiple -record
transfers must be done with the data of the following
record or transfer held off until the DEOR status bit
is true for the current record and the Decompression
Control registers have been reprogrammed. This
reprogramming can occur automatically with
prearming.
3.10 PREARMING
Prearming is the ability to write certain
registers that apply to th e next recor d while the
device is processing the current record. These
regist er s may be prearmed for recor d bounda ri es.
Prearming is automat ic, meaning ther e is no way to
disable it. If a prea rmable register is written whil e
the part is busy processing a record, at the end of the
record the part takes its program fr om the regi ster
value last written. Decompression Control register
has a corresponding prearm register.
The lower 3 bytes of Decompression Length
register are prearmable. If the most significant byte
of this register is written to, the counter is
immediately loaded with the current 4 byte value. if
the most significant byte is not written to the counter,
the counter gets reloaded at the end of the current
record.
3.11 INTERRUPTS
Five conditions are reported in the Interrupt
Stat us/ Control 0 and Status/Con trol 1 registers as
individual bits. All interrupts are maskable by
setti ng the corres ponding bit s in the Int errupt Mas k
register . A one in the Interrupt Mask register means
the corresponding bit in the Interrupt Status/Control
register is masked and does not affect the interrupt
pin (INTRN). The INTRN pin is active whenever
any unmasked interrupt bit is set to a one.
An E nd-of-Record inter r upt is poste d when a
word containing an end-of-record is strobed out of
the decompr ession output FIFO (DEOR). A DEOR
interr upt is also report ed if an end- of-reco rd is read
from the video output port. A decompression end of
transfer interrupt will be posted if this is the last
record of a transfer. End-of-Transfer interrupt
(DEOT) is posted when an EOR occurs that causes
the counter to decrement to zero.
Two FIFO error conditions are also reported.
Overflowing the input FIFO generates a DIOF
interrupt. An overflow can only be cleared by
resetting the FIFO via the Port Control register.
Underflowing the output FIFO (reading when it
is not ready) generates a DOUF. The underflow
interrupt is cleared by writing a one to DOUF . In the
event of an und erflow, the FIFO mu st be reset .
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3.12 DUPLEX PRINTING
Duplex Printing is the ability to print on both
sides of the page. AHA3422 supports this with
endian control.
During decompression of this reversed page the
BIG bit in this register must be programmed to the
same value used when this page of data was
compressed. Use of this feature has virtually no
effect on the decompression ratio when compared to
decompressing in forward order.
3.13 BLANK BANDS
Setting DBLANK in the Decompression
Control register cause s the next re cord o utput from
the Decompre ssor to be comprise d of a repeat ing 8-
bit pattern defined by the Pattern register.
DBLANK automatically clears at the end of the
next record. This command bit may be prearmed by
writing to the Decompression Control Prearm
regist er . When progr amming the device to generate
blank records the system must not send data to be
decompressed until the device has reached the end
of record for the blank record.
3.14 LOW POWER MODE
The devi ce is a data -driven system. When n o
data transfers are taking place, only the clock and
on-chip RAMs includ ing the FIFOs re qui re power.
To reduce power consumption to its absolute
minimum, the user can stop the clock when it is
high. With the system clock stopped and at a high
level, the current consumption is due to leakage.
Control and Status registers are preserved in this
mod e. Reinitia lization of Control registers are not
necessary when switching from Low Power to
Normal operating mode.
3.15 TEST M ODE
In order to facilitate board level testing, the
device provides the ability to tristate all outputs.
When the TEST0 pin is high, all outputs of the chip
are tristated. When TEST0 is low , the chip returns to
normal operation.
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4.0 REGISTER DESCRIPTIONS
The microprocessor configures, controls and monitors IC operation through the use of the registers
defined in this sect ion. The bit s labeled “res” are re served and must b e s et t o zer o when writ ing t o regis ters
unless otherwise noted.
Always progr am th e cont rol regi st er ( addr es s 0x3F) with a val ue of 0x0E f ol lowi ng powe r on and any
hard reset. This should be done prior to accessing any other registers.
A summar y of registers is list ed bel ow.
Table 5: Internal Registers
ADDRESS R/W DESCRIPTION FUNCTION DEFAULT
AFTER
RSTN PREARM
0x00 R/W System Configuration 0 Big Endian vs. Little Endian,
32-bit vs. 16-bit Undefined No
0x01 R/W System Configuration 1 Data Strobe Condition, EOR
Request Control, VDO Port
Enable 0x00 No
0x02 R/W Input FIFO Thresholds Input FIFO Empt y Threshold ,
Full Threshold Undefined No
0x03 R/W Output FIFO Thresholds Outp ut FIFO Empty
Threshold, Full Threshold Undefined No
0x04 R Reserved Reserved Undefined
0x05 R Decompression Ports Status FIFO St at us, Reque st St atus,
EOR Status Undefined No
0x06 R/W Port Control 1 Reset Individual FIFOs 0x0F No
0x07 R/W Interrupt Status/Control 0 EOR, Overflow, Underflow 0x00 No
0x09 R/W Interr upt Mask 0 Interru pt Mask bit s 0xFF No
0x0A R Version Die Version Number 0x21 No
0x0C R/W Decompression Record
Length 0 Bytes Remaining, Byte 0 0xFF Yes
0x0D R/W Decompression Record
Length 1 Bytes Remaining, Byte 1 0xFF Yes
0x0E R/W Decompression Record
Length 2 Bytes Remaining, Byte 2 0xFF Yes
0x0F R/W Decompression Record
Length 3 Bytes Remaining, Byte 3 0xFF No
0x10 R Reserved Reserved Undefined
0x11 R Reserved Reserved Undefined
0x12 R Reserved Reserved Undefined
0x13 R Reserved Reserved Undefined
0x14 R Reserved Reserved 0x04
0x15 R Reserved Reserved 0x00
0x16 R Reserved Reserved Undefined
0x17 R Reserved Reserved Undefined
0x18 R/W Decompression Control
Pause on Record Boundaries,
Enable Decompression
Engine, Decompression
Engine Empty St at us,
Dictionary Reset, Enable
Pass-Through Mode, Pause
End-of-Transfer, Generate
Blank Record, Enable P rearm
0x04 Yes
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0x1A R/W Decompression Reserved 1 Reserved 0x00 No
0x1C R/W Decompression Line Length 0 Line Length Register Lower
8bits Undefined No
0x1D R/W Decompression Line Length 1 Line Length Register Upper
3bits Undefined No
0x20 R Reserved Reserved FF
0x21 R Reserved Reserved FF
0x27 R/W Interr upt Stat us/C ontro l 1 Decompres sion EOT I nterr upt 0x00 No
0x29 R/W Interrupt Mask 1 Interrupt Mask bit for DEOT 0xFF No
0x2C R/W Decompression Record Count 0 Decompressor number of
records in a transf er 0xFF No
0x2D R/W Decompression Record Count 1 Decompressor number of
records in a transf er 0xFF No
0x30 R Reserved Reserved 0x00
0x31 R Reserved Reserved 0x00
0x32 R Reserved Reserved 0x00
0x33 R Reserved Reserved 0x00
0x34 R Reserved Reserved 0x00
0x35 R/W Pattern 8-bit pattern for blank record
generation Undefined No
0x38 R/W Decompression Control Prearm Prearm Register for
Decompression Control 0x00 No
0x3A R/W Decompression Reserved 2 Reserved 0x00 No
0x3F R/W Control Progra m to 0x0E 0x0F No
ADDRESS R/W DESCRIPTION FUNCTION DEFAULT
AFTER
RSTN PREARM
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4.1 SYSTEM CONFIGURATION 0, ADDRESS 0x00 - READ/WRITE
After re set, its contents are undefi ned. It must be writt en before an y input or output dat a movement may
be performed. A fter changing this re gister, reset FIFOs vi a the Port Control register.
BIG- Selects between little or big endian byte order for the decompressor. See table.
res - Bits must always be writ ten with zeros.
WIDE - Selects between 32 and 16-bit D buses.
4.2 SYSTEM CONFIGURATION 1, ADDRESS 0x01 - READ/WRITE
This register is cleared by reset.
DSC[2:0] - Data Strobe Condition . Contr ol t he cond it ion used to str obe da ta into and out of the dat a por ts
on the D bus . T a ble 4 shows the p rogramming for t he strobe cond ition for va rious DMA modes.
res - Bits must always be writ ten with zeros.
ERC - EOR Request Cont rol. Det ermine s when DOREQN deass erts at an End-of- Record . If ERC=0,
then the request deasserts asynchronously during the clock when an EOR is strobed out. If
ERC=1, then the request deasserts synchronously the clock after an EOR is strobed out. See
Figure 17 through Figure 20.
VDOE - VDO Port Enable. When this bit is set, the data from the decompression output FIFO goes to
the VDO port. When the bit is clear, the decompressed data is read by DMA on the D bus.
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x00 res WIDE res BIG res
COMP BIG or
DECOMP BIG WIDE DESCRIPTION
0 0 Little Endian data order 16-bit words
D[15:8] D[7:0]
Byte 1 Byte 0
0 1 Little Endian data order 32-bit words
D[31:24] D[23:16] D[15:8] D[7:0]
Byte 3 Byte 2 Byte 1 Byte 0
1 0 Big Endian data order 16-bit words
D[15:8] D[7:0]
Byte 0 Byte 1
1 1 Big Endian data order 32-bit words
D[31:24] D[23:16] D[15:8] D[7:0]
Byte 0 Byte 1 Byte 2 Byte 3
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x01 res VDOE ERC res DSC[2:0]
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4.3 INPUT FIFO THRESHOLDS, ADDRESS 0x02 - READ/WRITE
After re set, its contents are undefi ned. It must be writt en before an y input or output dat a movement may
be performed.
IET[3:0] - Empty thre shold f or the i nput FIF O. If t he number of words i n the i nput FIFO ( DI) is l ess th an
or equal to this number, the request for that channel is asserted.
IFT[3:0] - Full thr eshold for the input FIFO. I f the number of words in t he input FI FO (DI) is great er than
or equal to this number, the request for the channel is deasserted.
4.4 OUTPUT FIFO THRESHOLDS, ADDRESS 0x03 - READ/WRITE
After re set, its contents are undefi ned. It must be writt en before an y input or output dat a movement may
be performed.
OET[3:0] - Empty threshold for the output FIFO. If the number of words in the output FIFO (DO) is less
than or equal to this number , the request for the channel is deasserted (except in the case of an
End-of-Record).
OFT[3:0] - Full threshold for the output FIFO. If the number of words in the output FIFO (DO) is greater
than or equal to this number, the reque st for that channel is asserted.
4.5 DECOMPRESSION PORTS STATUS, ADDRESS 0x05 - READ ONLY
This is a read onl y regist er. Wri ting to thi s regis ter has no eff ect. Afte r reset , its cont ents are undefine d.
DIFT - Decompression input FIFO ful l threshol d. This sign al is activ e when the DI FIFO is at or above
the progr ammed FI FO full threshold. After r eset and the Input FIFO Threshold register has
been written, this bit contains a zero.
DIREQ - Decompress ion input request signal stat e. Reports the current state for the DIREQN pin. Notice
that this bit is active high while the pin is active low. Therefore, the value of this bit is always
the inverse of the value of the signal. After reset this bit contains a zero.
DOET - Decompression output FIFO empty threshold. This bit is active when the DO FIFO is at or
below the programmed FIFO empty threshold. After reset and the Output FIFO Threshold
register has been written, this bit contains a one.
DOREQ - Decompression output request signal state. Reports the current state for the DOREQN pin.
Notice that this bit is active high while the pin is active low. Therefore, the value of this bit is
always the inverse of the value of the signal. After reset this bit contains a zero.
DEOR - Decompression output end of re cord. This bi t is active wh en the output FIFO cont ains the End -
of-Record code. After reset this bit contains a zero.
res - Bits must always be writ ten with zeros.
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x02 IFT[3:0] IET[3:0]
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x03 OFT[3:0] OET[3:0]
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x05 DOEMP DIEMP res DEOR DOREQ DOET DIREQ DIFT
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DIEMP - Decompression input empty. This bit is active when the DI FIFO is empty. After reset this bit
contains a one.
DOEMP - Decompression output empty. This bit is active when the DO FIFO is empty . After reset this bit
contains a one.
4.6 PORT CONTROL, ADDRESS 0x06 - READ/WRITE
This register is initialized to 0x0F after reset.
DIRST - Decompression input reset. Setting this bit to a one resets the DI FIFO and clears the state
machines in the decompression input port. The reset condition remains active until the
microprocessor writes a zero to this bit.
DORST - Decompression output reset. Setting this bit to a one resets the DO FIFO and clears the state
machines in the decompression output port. The reset condition remains active until the
microprocessor writes a zero to this bit.
res - Bits must always be writ ten with zeros.
4.7 INTERRUPT STATUS/CONTROL 0, ADDRESS 0x07 - READ/WRITE
This register is initialized to 0x00 after reset.
DEOR - Decompression End-of-Re cord interrupt. This bit is set when the last byte of a record is strobed
out of the decompression DMA or video output port. The microprocessor must write a one to
this bit to clear this interrupt.
DERR - Decompression Error. This bit is set if an EOR leaves the decompressor before DRLEN has
counted down to zero or if DRLEN counts to zero and the last byte is not an EOR. DERR is
only active in decompression mode (DPASS=0). The microprocessor must write a one to this
bit to clear this interrupt.
res - Bits must always be writ ten with zeros.
DIOF - Decompression Input FIFO Overflow. This interrupt is generated when a write to an already
full DI FI FO is performed. Dat a written in thi s condition is lost. The on ly means of recovery
from this error is to reset the FIFO with the DIRST bit. Resetting the FIFO causes this interrupt
to clear. DIREQN is inactive while the interrupt is set.
DOUF - Decompression Output FIFO underflow. This interru pt is generate d when a read from an empty
DO FIFO is performed. Once this interrupt is set, the DO FIFO must be reset with the DORST
bit. The micropro cessor mus t write a one to this bit to clear thi s in terrupt. DOREQN i s inact ive
while the interrupt is set.
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x06 res DORST DIRST res
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x07 DOUF res DIOF res DERR DEOR res
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4.8 INTERRUPT MASK 0, ADDRESS 0x09 - READ/WRITE
This registe r is initial i zed to 0xF F after res et.
DEORM - Decompression End-of-Record Interrupt Mask. When set to a one, prevents Decompression
End-of-Record from causing INTRN to go active.
DERRM - Decompress ion Error Mask. When set t o a one, pr eve nt s a dec ompre ssion erro r (DERR) fro m
causing INTRN to go active.
res - Bits must always be writ ten with zeros.
DIOFM - Decompression Input FIFO Overflow Mask. When set to a one, prevents a decompression
input FIFO overflow (DIOF) from causing INTRN to go active.
DOUFM - Decompression Output FIFO Underflow Mask. When set to a one, prevents a decompression
output FIFO underflow (DOUF) from causing INTRN to go active.
4.9 VERSION, ADDRESS 0x0A - READ ONLY
VERSION[7:0] - Contains version number of the die.
4.10 DECOMPRESSION RECORD LENGTH, ADDRESS 0x0C, 0x0D, 0x0E, 0x0F -
READ/WRITE
These registers are initialized to 0xFF after reset.
DRLEN[31:0]-Decompression Record Length. Contains the number of bytes in a decompressed record.
These registers provide different functions depending on whether the decompressor is in pass-
through or decompression mode. In decompression mode, the data itself contains EOR
information and DRLEN is only used for error checking. DRLEN is decremented each time a
byte leaves the decompressor.
In decompression mode, a DERR interrupt is issued if an EOR is not read out of the
decompressor when the counter expires or if an EOR occurs before the counter expires (i.e.,
when the record lengths do not match). If the DERR interrupt is masked, use of the DRLEN
register is optional in decompression mode.
In pass-through mode, DRLEN determines the size of records read out of the decompressor.
The counter is decremented for each byte read into the decompressor.
In either mode, the counter reloads when it reaches zero or when DRLEN[31:24] is written.
Reading DRLEN returns the number of bytes left in the count. The lower three bytes of this
register may be prearmed since the counter is automatically reloaded at the end of a record
when the part is not programme d to pause on End -of-Record. The upp er byte is not prea rmable
since writing to this byte triggers an immediate reload to the counter.
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x09 DOUFM res DIOFM res DERRM DEORM res
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x0A VERSION[7:0]
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x0C DRLEN[7:0]
0x0D DRLEN[15:8]
0x0E DRLEN[23:16]
0x0F DRLEN[31:24]
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4.11 DECOMPRESSION CONTROL, ADDRESS 0x18 - READ/WRITE
This register is initialized to 0x04 after reset. This register can be prearmed.
DPOR - Decompression Pause on record bo undaries. When this bit is set to one, t he decompressor stops
taking data from the input FIFO once a record boundary is found. Upon finding the record
boundary, DCOMP is clea red. This bit may only be cha nged when DCOMP is set to zero. Afte r
system reset or DDR, this bit is cleared.
DCOMP - Decompression. Setting this bit to a one enables the decompression engine (or pass-through
mode if DPASS is set) to take data from the decompression input FIFO. If this bit is cleared,
decompression stops. The bit is automatically cleared at the end of a record if DPOR is set.
Decompress ion can be r est ar ted withou t l oss of data by s et ti ng DCOMP. After sys tem r ese t or
DDR, this bit is cleared.
DEMP - Decompress ion engine empty. This bit is set whe n the decompressi on engine is cl eared of data.
Writing to this bit has no effect. After syste m reset, this bit is set.
DDR - Decompression Dictionary Reset. Setting this bit immediately resets the decompressor
including the decompression dictionary. The reset condition remains active until the
microprocessor writes a zero to this bit.
DPASS - Decompression pass-through mode. While this bit is set, data is passed directly through the
decompression engine without any effect on the data. This bit may only be changed when
decompression is disabled (DCOMP=0) and the decompression engine is empty of data
(DEMP=1). The pass-th rough operat ion is sta rted by sett ing DCOMP. To stop the pass-through
operation, DCOMP should be cleared (to pause operation) and then DPASS may be cleared.
DPOT - Decompression Pause on Transfer Boundaries. When this bit is set the decompressor stops
taking data from the input FIFO once a decompression end of transfer boundary is found
indicated by the Decompression Record Counter decrementing to zero.
DBLANK -Decompression Blank record. The data in the next record output from the decompressor is a
repeating byte pattern using the 8-bit data defined in the PATTERN register. DBLANK
automatically clears at the end of the record when the Decompression Record Count
decrements to zero. When using DBLANK to generate a blank record the device must not
contain data to be deco mpressed an d the system must not send data t o be decompresse d for any
future re cords u ntil the pa rt has r eached the End- of-Rec ord fo r t he bla nk rec ord. Also, t he user
must not set the DCOMP bit when the DBLANK bit is set.
DPREARM -Prearm Enable . When this bit is set , Decompression Control Prear m register is loaded in to the
Decompression Control register when the next end of record leaves the decompressor.
4.12 DECOMPRESSION RESERVE D, ADDRESS 0x1A, 0X3A - READ/WRITE
This regi ster is used for p roduction tes ting o nly. Initialized to 0 x00 af ter reset.
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x18 DPREARM DBLANK DPOT DPASS DDR DEMP DCOMP DPOR
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x1A res
0x3A res
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4.13 DECOMPRESSION LINE LENGTH, ADDRESS 0x1C, 0x1D - READ/WRITE
This register contains information necessary for the decompression operation. It must be set prior to any
decompres sion ope rati on. It sho uld only be ch anged bet ween rec ords when DCOMP is clear ed and DEMP
is set. These registers are und efine d after reset.
res - Bits must always be writ ten with zeros.
LINE[ 10:0]-Line length . The numbe r of byt es i n the scan li ne. Minimum value is 16 . For s can l in e le ngt hs
larger than the maximum allowed, set to 16.
4.14 INTERRUPT STATUS/CONTROL 1, ADDRESS 0x27 - READ/WRITE
This register is initialized to 0x00 after reset.
DEOT - Decompression End- of-T ransfer In terrupt. Thi s bit is set wh en a decompressi on end of trans fer
condition is reached indicated by the Decompression Record Counter counting down to zero.
The m icroprocessor must writ e a one to thi s bit to clear this inter rupt.
res - Bits must always be writ ten with zeros.
4.15 INTERRUPT MASK 1, ADDRESS 0x29 - READ/WRITE
This registe r is initial i zed to 0xF F after res et.
DEOTM - Decompression End-of-Transfer Interrupt Mask. When set to a one, prevents Decompression
End-of-Transfer from causing INTRN to go active.
res - Bits must always be writ ten with zeros.
res - Bits must always be writ ten with zeros.
4.16 DECOMPRESSION RECORD COUNT , ADDRESS 0x2C, 0x2D - READ/WRITE
These registers are initialized to 0xFFFF after reset.
DRC[15:0] -Decompression Record Count is the number of records in the current transfer. The internal record
counter latches the value in this register when DRC[15:8] is written. The internal counter is
decremented as the last byte of the record is decompressed. At the End-of-Transfer , the value in
this register is reloaded into the internal record counter . Reading this register address returns the
internal record counter value. Expiration of this counter causes the DEOT interrupt to be posted.
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x1C LINE[7:0]
0x1D res LINE[10:8]
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x27 res DEOT res
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x29 res DEOTM res
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x2C DRC[7:0]
0x2D DRC[15:8]
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4.17 PATTERN, ADDRESS 0x35 - READ/WRITE
This registe r is und efined after reset.
PATTERN[7:0]-Pattern is the 8-bit da ta used to genera te blank bands or records. If DBLANK is set, the part
outputs this register value repeatedly for the entire record (or band).
4.18 DECOMPRESSION CONTROL PREARM, ADDRESS 0x38 - READ/WRITE
This register initializes to 0x00 after reset. This register is cleared when the prearm loads into the
Decompression Control register, thus providing a method for the user to verify that the prearm loaded.
Note, the user must not change modes of operation between decompression, pass-through and blank
when there is data in the decompressor. See Decompression Control register for bit descriptions. This
register is the prearm register for the Decompression Control register.
res - Bits must always be writ ten with zeros.
4.19 CONTROL, ADDRESS 0x3F - READ/WRITE
This register must be written with 0x0E before a decompression or pass-through operation begins.
Default a fter reset is 0x0 F.
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x35 PATTERN[7:0]
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x38 NDPREARM NDBLANK NDPOT NDPASS NDDR res NDCOMP NDPOR
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0x3F CONTROL CODE
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5.0 SIGNAL DESCRIPTIONS
This section contains descriptions for all the pins. Each signal has a type code associated with it. The
type codes are described in the following table.
5.1 MICROPROCESSOR INTERFACE
TYPE CODE DESCRIPTION
I Input only pin
O Output only pin
I/O Input/Output pin
S Synchronous signal
A Asynchronous signal
MICROPROCESSOR INTERFACE
SIGNAL TYPE DESCRIPTION
PD[7:0] I/O
SProcessor Data. Data for all microprocessor reads and writes of
registe rs wit hi n AHA3422 are per for med on t hi s b us. This bu s may
be tied to the Data bus, D[31:0], provided microprocessor accesses
do not occur at the same time as DMA accesses.
PA[5:0] I
SProcessor Address Bus. Used to address internal registers within
AHA3422.
CSN I
SChip Select. Selects AHA3422 as the source or destination of the
current microproce ssor bu s cycle. CSN n eeds only b e active for one
clock cycle to start a microprocessor access.
DIR I
SDirection. This signal indicates whether the access to the register
specified by the P A bus is a read or a write. The polarity of this signal
is programmed with the PROCMODE0 pin.
RDYN O
A,S Ready. Indicat es val id dat a is on the data bus duri ng rea d opera ti on
and completion of write operation. Its operation depends on
PROCMODE[1:0] settings.
INTRN O
SInterrupt. The compression and decompression processes generate
interrupts that are reported with this signal. INTRN is low whenever
any non-masked bits are set in the Interrupt Status/Control register.
PROCMODE[1:0] I
SMicroprocessor Port Configuration Mode. Selects the polarity of the
DIR pin and operation of the CSN pin. Refer to Section 2.1
Microprocessor Interface for details. (Figure 2 through Figure 5)
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5.2 DATA INTERFACE
5.3 VIDEO INTERFACE
DATA INTERFACE
SIGNAL TYPE DESCRIPTION
D[31:0] I/O
SData for all channels is transmitted on this bus. The ACKN is used to
distinguish between the four channels. Data being written to AHA3422 is
latched on the rising edge of CLOCK when the strobe condition is met.
Data setup and hold times are relative to CLOCK. If the bus is configured
to 16-bit transfers (WIDE=0), data is carried on D[15:0]. In this case,
D[31:16] should be terminated with pullup resistors.
DRIVEN I
ADrive En able. Active low output driver enable. This input must be low in
order to drive data onto D[31:0] in accordance with the current strobe
condition.
SD I
SStrobe Delay. Active high. Allows insertion of wait states for DMA
access to the FIFOs. The strobe condition, as programmed in the DSC
field of System Configuration 1, enables this signal and selects its
polarity.
DIREQN O
SDecompression Input Data Request, active low. When this signal is
active, it indicates the ability of the DI port to accept data.
DIACKN I
SDecompression Input Data Acknowledge. Active low decompression
data in put. Whe n this si gnal is ac tive, it indicate s the d ata on D is f or the
decompression input port. Data on D is latched on the rising edge of
CLOCK when the strobe condition is met.
DOREQN O
A, S Decompression Output Data Request, active low. When this signal is
active, it indicates the a bility of the DO port to tran smit data.
DOACKN I
SDecompression Output Data Acknowledge. The definition of DOACKN
varies with the data strobe condition in System Configuration 1. See
Table 4.
VIDEO INTERFACE
SIGNAL TYPE DESCRIPTION
VOREQN O
SVideo Output Request. Active low output indicating that the byte on
VOD[7:0] is valid.
VOACKN I
SV ideo Output Acknowledge. Active low input indicating that the external
system is ready to read VOD[7:0].
VOD[7:0] O
SVideo Output Data. The value on this output bus is read when both
VOREQN and VOACKN are low.
VOEORN O
SVideo Output End of Record is active low indicating the byte on
VOD[7:0] contains the last byte in a record.
VOEOTN O
SVideo Output End of Transfer is active low indicating the byte on
VOD[7:0] contains the last byte in a multi-record transfer.
Page 24 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
5.4 SYSTEM CONTROL
SYSTEM CONTROL
SIGNAL TYPE DESCRIPTION
CLOCK I System Clock. This signal is connected to the clock of the
microprocessor. The In tel i960Cx cal ls this pin P CLK.
RSTN I
APower on Rese t. Active low reset signal . The devic e must be rese t before
any DMA or microprocessor activity is attempted. RSTN should be a
minimum of 10 CLOCK periods.
TEST0 I
ABoard Test mode. When TEST is high, all outputs are tristated. When
TEST is low, the chip performs normally.
TEST1 I
AUsed for production tests. This input should always be tied low.
PS3422-0600 Page 25 of 44
Advanced Hardware Architectures, Inc.
6.0 PINOUT
*Note: the pins marked VDD or VSS can be connected to either VDD or VSS but should not be left unconnected.
PIN SIGNAL PIN SIGNAL PIN SIGNAL
1 VDD or VSS* 44 VSS 87 VOD[7]
2 VDD or VSS* 45 VSS 88 NC
3 VDD or VSS* 46 VDD 89 VDD
4 VDD or VSS* 47 CLOCK 90 VSS
5 VDD or VSS* 48 VSS 91 VOACKN
6 INTRN 49 VDD 92 TEST0
7 VSS 50 VDD 93 PA[0]
8 VDD 51 VSS 94 PA[1]
9 DRIVEN 52 VDD 95 PA[2]
10 SD 53 D[15] 96 PA[3]
11 DOACKN 54 D[16] 97 VDD
12 VDD 55 D[17] 98 PA[5]
13 DIACKN 56 D[18] 99 VSS
14 VDD 57 D[19] 100 PA[4]
15 VSS 58 D[20] 101 NC
16 VDD 59 D[21] 102 VOEOTN
17 DOREQN 60 D[22] 103 PROCMODE[1]
18 NC 61 D[23] 104 PROCMODE[0]
19 DIREQN 62 D[24] 105 CSN
20 NC 63 VSS 106 VDD
21 NC 64 VDD 107 VSS
22 D[0] 65 D[25] 108 DIR
23 VSS 66 D[26] 109 RSTN
24 VSS 67 D[27] 110 PD[7]
25 VDD 68 D[28] 111 PD[6]
26 VDD 69 D[29] 112 PD[5]
27 D[1] 70 D[30] 113 VDD
28 D[2] 71 VDD 114 VSS
29 D[3] 72 VDD 115 PD[4]
30 D[4] 73 VSS 116 PD[3]
31 D[5] 74 VSS 117 PD[2]
32 D[6] 75 D[31] 118 PD[1]
33 D[7] 76 VOREQN 119 PD[0]
34 D[8] 77 VOEORN 120 VDD
35 D[9] 78 VOD[0] 121 VSS
36 D[10] 79 VOD[1] 122 RDYN
37 D[11] 80 VOD[2] 123 VDD
38 VSS 81 VDD 124 VDD or VSS*
39 VDD 82 VSS 125 VDD or VSS*
40 D[12] 83 VOD[3] 126 VDD or VSS*
41 D[13] 84 VOD[4] 127 VDD
42 D[14] 85 VOD[5] 128 VSS
43 TEST1 86 VOD[6]
Page 26 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
Figure 15: Pinout
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
34
33
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PA[3]
PA[2]
PA[1]
PA[0]
TEST0
VOACKN
VSS
VDD
NC
VOD[7]
VOD[6]
VOD[5]
VOD[4]
VOD[3]
VSS
VDD
VOD[2]
VOD[1]
VOD[0]
VOEORN
VOREQN
D[31]
VSS
VSS
VDD
VDD
D[30]
D[29]
D[28]
D[27]
D[26]
D[25]
VDD
VSS
D[24]
D[23]
D[22]
D[21]
D[20]
D[19]
D[18]
D[17]
D[16]
D[15]
VDD
VSS
VDD
VDD
VSS
CLOCK
VDD
VSS
VSS
TEST1
D[14]
D[13]
D[12]
VDD
VSS
D[11]
D[10]
D[9]
D[8]
D[7]
*I
*I
*I
*I
*I
INTRN
VSS
VDD
DRIVEN
SD
DOACKN
VDD
DIACKN
VDD
VSS
VDD
DOREQN
NC
DIREQN
NC
NC
D[0]
VSS
VSS
VDD
VDD
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
VDD
PA[5]
VSS
PA[4]
NC
VOEOTN
PROCMODE[1]
PROCMODE[0]
CSN
VDD
VSS
DIR
RSTN
PD[7]
PD[6]
PD[5]
VDD
VSS
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]
VDD
VSS
RDYN
VDD
*I
*I
*I
VDD
VSS
NC = No Connect
AHA3422A-033 PQC
*I = Connect to VDD or VSS
PS3422-0600 Page 27 of 44
Advanced Hardware Architectures, Inc.
7.0 DC ELECTRICAL SPECIFICATIONS
7.1 OPERATING CONDITIONS
Notes:
1) Dynamic current; no data transfers
2) Stat ic current (clock high)
3) Timings referenced to this load
4) ILOAD = 0 mA
7.2 ABSOLUTE MAXIMUM ST RESS RATINGS
OPERATING CONDITIONS
SYMBOL PARAMETER MIN MAX UNITS NOTES
Vdd Supply voltage 4.75 5.25 V
Idd Supply current (active) 300 mA 4
Idd Supply current (standby) 80 mA 1, 4
Idd Supply current (low power) 1 mA 2, 4
Ta Ambient temperature 0 70 °C
Vil Input low voltage:
PROCMODE[1:0], TEST0, TEST1
Other sig nals Vss-0.5
Vss-0.5 0.3×Vdd
0.8 V
Vih Input high voltage:
PROCMODE[1:0], TEST0, TEST1
Other sig nals 0.7×Vdd
2.0 Vdd+0.5
Vdd+0.5 V
Iil Input leakage current -10 10 µA
Vol Output low voltage (Iol=-4mA) 0.4 V
Voh Output high voltage (Ioh=4mA) 2.4 V
Voh Output high voltage (Ioh=100µA) Vdd-0.8 V
Iol Output low current 4 mA
Ioh Output high current -4 mA
Ioz Output leakage current -10 10 µA
Ioz High impedance leakage current -10 10 µA
Cin Input capacitance 5 pF
Cout Output capacitance 7 pF
Cio Input/Output capacitance 7 pF
Comax Maximum capacitance load for all
signals (including self loading) 50 pF 3
ABSOLUTE MAXIMUM STRESS RATINGS
SYMBOL PARAMETER MIN MAX UNITS NOTES
Tstg Storage temperature -50 150 °C
Vdd Supply voltage -0.5 7 V
Vin Input voltage Vss-0.5 Vdd+0.5 V
Page 28 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
8.0 AC ELECTRICAL SPECIFICATIONS
Notes:
1) Production test condition is 50 pF. Output delay is decreased 2 ns with 25 pF load guaranteed by design or
characterization.
2) All timings are referenced to 1.4 volts.
Figure 16: Data Interface Timing
Table 6: Data Port Timing Requirements
Figure 17: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0
NUMBER PARAMETER MIN MAX UNITS
1 DIACKN, DOACKN and SD setup time 8 ns
2 DIACKN, DOACKN and SD hold time 2 ns
3 D-bus input setup time 8 ns
4 D-bus input hold time 2 ns
5 REQN delay (non-EOR case) 18 ns
6 REQN hold (non-EOR case) 2 ns
CLOCK
D
REQN
D/
COEORN
ACKN/
SD
Valid 0
Valid
Va lid 1
1 2
3 4
6
5
7
8
CLOCK
ACKN
REQN
D
SD
EOR-1 EOR
1
2
PS3422-0600 Page 29 of 44
Advanced Hardware Architectures, Inc.
Figure 18: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1
Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0
Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1
Table 7: Request vs. EOR Timing
NUMBER PARAMETER MIN MAX UNITS
1 ACKN, SD to REQN ERC=0 16 n s
2 CLOCK to REQN ERC=0 16 ns
3 CLOCK to REQN DSC=0-3, 6, 7; ERC=1 16 ns
4 CLOCK to REQN DSC=4, 5; ERC=0 16 ns
5 CLOCK to REQN DSC=4, 5; ERC=1 16 ns
CLOCK
ACKN
REQN
D
SD
EOR-1 EOR
3
CLOCK
ACKN
REQN
D
SD
EOR-1 EOR
4
CLOCK
ACKN
REQN
D
SD
EOR-1 EOR
5
Page 30 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
Figure 21: O utput Enable Timing
Table 8: Output Enable Timing Requirements
Figure 22: Video Output Port Timing
Table 9: Video Output Port Timing Requirements
NUMBER PARAMETER MIN MAX UNITS
1 DRIVEN to D valid 15 ns
2 DRIVEN to D tristate 10 ns
3 Signal to D valid 15 ns
4 Sig nal to D tris tate 10 ns
5 CLOCK to D tristate (DSC=100, 101) 15 ns
NUMBER PARAMETER MIN MAX UNITS
1 VOREQN delay 16 ns
2 VOREQN hold 2 ns
3 VOACKN setup 8 ns
4 VOACKN hold 2 ns
5 VOD delay 16 ns
6 VOD hold 2 ns
7 VOEORN hold 2 ns
8 VOEORN delay 16 ns
CLOCK
ACKN
DRIVEN
D
2
1 3 4 5
CLOCK
VOACKN
VOD[7:0]
VOREQN
1 2
43
6
VOEORN
5
7 8
PS3422-0600 Page 31 of 44
Advanced Hardware Architectures, Inc.
Figure 23: Microprocessor Interface Timing (PROCMODE[1]=0)
Figure 24: Microprocessor Interface Timing (PROCMODE[1]=1)
CLOCK
CSN
PA
RDYN
DIR
READ
1
1
212
3 4
6
910
910
15
14
34
78
910
12 13
Valid tristate
Valid
tristate
910
Valid
PD
DIR
PD
WRITE
234512
CLOCK
CSN
PA
RDYN
DIR
READ
1
PD
DIR
PD
WRITE
123 5N4
Valid
Valid
A0
3
2
4
16
17
12
7
14 15
9
13
tristate
10
Page 32 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
Table 10: Microprocessor Interface Timing Requirements
Figure 25: Interrupt Timing
Table 11: Interrupt Timing Requirements
Figure 26: Clock Timing
Table 12: Clock Timing Requirements
NUMBER PARAMETER MIN MAX UNITS
1 PA setup time 8 ns
2 PA hold time 2 ns
3 CSN setup time 8 ns
4 CSN hold time 2 ns
6 CSN to valid RDYN 15 ns
7 RDYN valid delay 16 ns
8 RDYN drive disable 10 ns
9 DIR setup time 8 ns
10 DIR hold time 2 ns
12 PD valid delay 16 ns
13 PD drive disable 12 ns
14 PD setup time 8 ns
15 PD hol d time 2 ns
16 CSN high to PD tristate 10 ns
17 CSN high to RDYN high 15 ns
NUMBER PARAMETER MIN MAX UNITS
1 INTRN delay time 15 ns
2 INTRN hold time 2 ns
NUMBER PARAMETER MIN MAX UNITS
1 CLOCK rise time 2 ns
2 CLOCK fall time 2 ns
3 CLOCK high time 12 ns
4 CLOCK low time 12 ns
5 CLOCK period 30 ns
CLOCK
INTRN
1 2
CLK
1
34
5
2
2.0V
1.4V
0.8V
PS3422-0600 Page 33 of 44
Advanced Hardware Architectures, Inc.
Figure 27: Power On Reset Timing
Table 13: Power On Reset Timing Requirements
Notes:
1) RSTN signal can be asynchronous to the CLOCK signal. It is internally synchronized to the rising edge of
CLOCK.
NUMBER PARAMETER MIN MAX UNITS
1 RSTN low pulsewidth 10 clocks
2 RSTN setup to CLOCK rise 15 ns
3 RSTN hold time 2 ns
CLOCK
RSTN
23
1
Page 34 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
9.0 PACKAGE SPECIFICATIONS
JEDEC outline is MO-1 08
L
A
A
DETAIL A
A2
A1
E1
D1
P
P
D
B
E
125
126
127
128
3231302928
AHA3422A-033 PQC
97
98
99
100
(LCA)
(LCB)
PS3422-0600 Page 35 of 44
Advanced Hardware Architectures, Inc.
10.0 ORDERING INFORMATION
10.1 AVAILABLE PARTS
10.2 PART NUMBERING
Device Number:
3422
Revision Letter:
A
Packa ge Material Codes:
P Plastic
Package Type Codes:
Q Quad Flat Pack
Test Specifications:
C Commercial 0°C to +70°C
PLASTIC QUAD FLAT PACK PACKAGE DIMENSIONS
SYMBOL
NUMBER OF PIN AND SPECIFICATION DIMENSION
128
SB
MIN NOM MAX
(LCA) 32
(LCB) 32
A 3.7 4.07
A1 0.25 0.33
A2 3.2 3.37 3.6
D 30.95 31.2 31.45
D1 27.99 28 28.12
E 30.95 31.2 31.45
E1 27.99 28 28.12
L 0.73 0.88 1.03
P0.8
B 0.3 0.35 0.4
PART NUMBER DESCRIPTION
AHA3422A-033 PQC 16 MBytes/sec Lossless Decompressor IC
AHA 3422 A- 033 P Q C
Manufacturer Device
Number Revision
Level Speed
Designation Package
Material Package
Type Test
Specification
Page 36 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
11.0 RELATED TECHNICAL PUBLICATIONS
DOCUMENT # DESCRIPTION
PS3410C AHA Product Specification – AHA341 0C S t a r L i t eTM 25 MBytes/sec Simultaneo us
Lossless Data Compression/Decompression Coprocessor IC
PS3411 AHA Product Specification – AHA34 11 Sta r L i t eTM 33 MBytes/sec Simultaneous
Compressor/Decompressor IC
PS3431 AHA Product Specification – AHA3431 Sta r Li t e TM 40 MBytes/sec Simultaneous
Compressor/Decompressor IC, 3.3V
PB3410C AHA Product Brief – AHA3410C StarLiteTM 25 MBytes/sec Simultaneous Lossless Data
Compression/Decompression Coprocessor IC
PB3411 AHA Product Brief – AHA3411 StarLiteTM 33 MBytes/sec Simultaneous Compressor/
Decompress or IC
PB3422 AHA Product Brief – AHA3422 StarLiteTM 16 MBytes/sec Lossless Decompressor IC
PB3431 AHA Product Brief – AHA3431 S t a r L i t eTM 40 MBytes/sec Simultaneous Comp ressor/
Decompressor IC, 3.3V
ABDC18 AHA Application Brief – AHA3410C, AHA3411 and AHA3431 Device Differences
ANDC12 AHA Application Note – AHA3410C StarLiteTM Designer’s Guide
ANDC13 AHA Application Note – Compression Performance on Bitonal Images
ANDC14 AHA Application Note – StarLite TM Evaluation Software
ANDC15 AHA Application Note – ENCODEB2 Compression Algorithm Description
ANDC16 AHA Application Note – Designer’s Guide for StarLiteTM Famil y P rod uct s: AHA3411,
AHA3422 and AHA3431
ANDC17 AHA Application Note – StarLiteTM Compression on Continuous Tone Images
GLGEN1 General Glossary of Te rms
STARSW StarLiteTM Evaluation Software (WindowsTM)
PS3422-0600 Page 37 of 44
Advanced Hardware Architectures, Inc.
APPENDIX A: ADDITIONAL TIMING DIAGRAMS FOR DMA MODE TRANSFERS
Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000
Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000
Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=000
CLOCK
ACKN
SD
DRIVEN
DD0 D1
CLOCK
ACKN
SD
DRIVEN
DD1D0
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3
Page 38 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=000
Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=000
Figure A6: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=000
CLOCK
ACKN
SD
DRIVEN
DD1D0 D2 D3
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3 D4 D5 D6 D7
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3 D4 D5 D6 D7
PS3422-0600 Page 39 of 44
Advanced Hardware Architectures, Inc.
Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010
Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010
Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=010
CLOCK
ACKN
SD
DRIVEN
DD0 D1
CLOCK
ACKN
SD
DRIVEN
DD1D0
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3
Page 40 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=010
Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=010
Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wa it State, Strobe Condition
of DSC=010
CLOCK
ACKN
SD
DRIVEN
DD1D0 D2 D3
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3 D4 D5 D6 D7
CLOCK
ACKN
SD
DRIVEN
DD2D1 D3 D4 D5 D6 D7D0
PS3422-0600 Page 41 of 44
Advanced Hardware Architectures, Inc.
Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011
Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011
Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=011
CLOCK
ACKN
SD
DRIVEN
DD0 D1
CLOCK
ACKN
SD
DRIVEN
DD1D0
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3
Page 42 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=011
Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=011
Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wa it State, Strobe Condition
of DSC=011
CLOCK
ACKN
SD
DRIVEN
DD1D0 D2 D3
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3 D4 D5 D6 D7
CLOCK
ACKN
SD
DRIVEN
DD2D1 D3 D4 D5 D6 D7D0
PS3422-0600 Page 43 of 44
Advanced Hardware Architectures, Inc.
Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111
Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111
CLOCK
ACKN
SD
DRIVEN
DD0 D1 D2
CLOCK
ACKN
SD
DRIVEN
DD1D0 D2
Page 44 of 44 PS3422-0600
Advanced Hardware Arc h itectur es, Inc.
APPENDIX B: SEQUENTIAL REGISTER TABLE
ADDRESS DESCRIPTION
00 System Configuration 0
01 System Configuration 1
02 Input FIFO Thresholds
03 Output FIFO Thresholds
04 Reserved
05 Decompression Ports Status
06 Port Control
07 Interrupt Status/Control 0
09 Interrupt Mask 0
0A Version
0C Decompression Record Length 0
0D Decompression Record Length 1
0E Decompression Record Length 2
0F Decompression Record Length 3
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
16 Reserved
17 Reserved
18 Decompression Control
1A Decompression Reserved 1
1C Decompression Line Le ngth 0
1D Decompressio n Line Le ngth 1
20 Reserved
21 Reserved
27 Interrupt Status/Control 1
29 Interrupt Mask 1
2C Decompression Record Count 0
2D Decompression Record Count 1
30 Reserved
31 Reserved
32 Reserved
33 Reserved
34 Reserved
35 Pattern
38 Decompression Control Prearm
3F Control
