K3P6V1000B-TC CMOS MASK ROM
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM
The K3P6V1000B-TC is a fully static mask programmable ROM
fabricated using silicon gate CMOS process technology, and is
organized either as 4,194,304x8 bit(byte mode) or as
2,097,152x16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device includes page read mode function, page read mode
allows 8 words(or 16 bytes) of data to read fast in the same
page, CE and A3 ~ A20 should not be changed.
This device operates with a 3.3V power supply, and all inputs
and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P6V1000B-TC is packaged in a 44-TSOP2.
GENERAL DESCRIPTIONFEATURES
• Switchable organization
4,194,304 x 8(byte mode)
2,097,152 x 16(word mode)
• Fast access time
Random Access Time : 100ns(Max.)
Page Access Time : 30ns(Max.)
• 8 words/ 16 bytes page access
• Supply voltage : single +3.3V
• Current consumption
Operating : 60mA(Max.)
Standby : 30µA(Max.)
• Fully static operation
• All inputs and outputs TTL compatible
• Three state outputs
• Package
-. K3P6V1000B-TC : 44-TSOP2-400
PIN CONFIGURATION
N.C
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
Q0
Q8
Q1
Q9
Q4
Q12
Q5
Q13
Q6
VSS
Q14
Q7
Q15/A-1
FUNCTIONAL BLOCK DIAGRAM
K3P6V1000B-TC
1
244
43
3
442
41
5
640
39
7
838
37
9
10 36
35
11
12 34
33
13
14 32
31
15
16 30
29
17
18 28
27
19
20 26
25
21
22 24
23
TSOP2
Q2
Q10
Q3
Q11
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BHE
VCC
A20 X
A0~A2
AND
DECODER
BUFFERS
A3
Y
AND
DECODER
BUFFERS
MEMORY CELL
SENSE AMP.
CONTROL
LOGIC
MATRIX
(2,097,152x16/
4,194,304x8)
DATA OUT
BUFFERS
A-1
CE
OE
BHE
.
.
.
.
.
.
.
.
Q0/Q8Q7/Q15
. . .
Pin Name Pin Function
A0 - A2Page Address Inputs
A3 - A20 Address Inputs
Q0 - Q14 Data Outputs
Q15 /A-1 Output 15(Word mode)/
LSB Address(Byte mode)
BHE Word/Byte selection
CE Chip Enable
OE Output Enable
VCC Power (3.3V)
VSS Ground
N.C No Connection
K3P6V1000B-TC CMOS MASK ROM
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item Symbol Min Typ Max Unit
Supply Voltage VCC 3.0 3.3 3.6 V
Supply Voltage VSS 000V
MODE SELECTION
CE OE BHE Q15/A-1 Mode Data Power
HXXXStandby High-Z Standby
LHX X Operating High-Z Active
L L HOutput Operating Q0~Q15 : Dout Active
LInput Operting Q0~Q7 : Dout
Q8~Q14 : Hi-Z Active
CAPACITANCE(TA=25°C, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item Symbol Test Conditions Min Max Unit
Output Capacitance COUT VOUT=0V -12 pF
Input Capacitance CIN VIN=0V -12 pF
ABSOLUTE MAXIMUM RATINGS
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Item Symbol Rating Unit Remark
Voltage on Any Pin Relative to VSS VIN -0.3 to +4.5 V-
Temperature Under Bias TBIAS -10 to +85 °C-
Storage Temperature TSTG -55 to +150 °C-
DC CHARACTERISTICS
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
Parameter Symbol Test Conditions Min Max Unit
Operating Current ICC Cycle=5MHz, all outputs open
CE=OE=VIL, VIN=0.45V to 2.4V (AC Test Condition) -60 mA
Standby Current(TTL) ISB1 CE=VIH, all outputs open 500 µA
Standby Current(CMOS) ISB2 CE=VCC, all outputs open 30 µA
Input Leakage Current ILI VIN=0 to VCC -10 µA
Output Leakage Current ILO VOUT=0 to VCC -10 µA
Input High Voltage, All Inputs VIH 2.0 VCC+0.3 V
Input Low Voltage, All Inputs VIL -0.3 0.6 V
Output High Voltage Level VOH IOH=-400µA2.4 -V
Output Low Voltage Level VOL IOL=2.1mA -0.4 V
K3P6V1000B-TC CMOS MASK ROM
TEST CONDITIONS
Item Value
Input Pulse Levels 0.45V to 2.4V
Input Rise and Fall Times 10ns
Input and Output timing Levels 1.5V
Output Loads 1 TTL Gate and CL=100pF
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V±0.3V, unless otherwise noted.)
READ CYCLE
NOTE : Page Address is determined as below.
Word mode(BHE=VIH) ; A0, A1, A2
Byte mode(BHE=VIL) ; A -1, A0, A1, A2
Item Symbol K3P6V1000B-TC(E)10 K3P6V1000B-TC(E)12 K3P6V1000B-TC(E)15 Unit
Min Max Min Max Min Max
Read Cycle Time tRC 100 120 150 ns
Chip Enable Access Time tACE 100 120 150 ns
Address Access Time tAA 100 120 150 ns
Page Address Access Time tPA 30 50 70 ns
Output Enable Access Time tOE 30 50 70 ns
Output or Chip Disable to
Output High-Z tDF 20 20 30 ns
Output Hold from Address Change tOH 0 0 0 ns
K3P6V1000B-TC CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
CE
OE
DOUT
A0~A20
A-1(*1)
D0~D7
D8~D15(*2)
PAGE READ
OE
ADD
DOUT
CE
ADD
A0,A1,A2
A3~A20
VALID DATA VALID DATA VALID DATA VALID DATA
1 st 2 nd 3 rd
tDF(*3)
ADD1 ADD2
VALID DATA VALID DATA
tOH
tDF(*3)
tRC
tACE
tOE tAA
NOTES :
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
tAA tPA
A -1(*1)
D0~D7
D8~D15(*2)
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