ICs for Communications
Memory Time Switch Large
MTSL
PEB 2047
PEB 2047-16
Version 2.1
Data Sheet 03.95
Edition 03. 95
This edition was realized using the software
system FrameMaker‚.
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
© Siemens AG 1995.
All Ri g h ts Re s e rv e d .
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cesses and circuits implemented within com-
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nent and shall not be co nsidered as assured
characteristics.
Terms of delivery and rights to change design
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Components used in life -support devi ces
or systems must b e expressl y autho rized
for such purpose!
Critical components1 of the Semiconductor
Group of Siemens AG, may only be used in
life-support devices or systems2 with the ex-
press written approval of the Semiconductor
Group of Siemens AG.
1 A critical component is a component used
in a life-support device or system whose
failure can reasonably be expected to
cause the failure of that life-support device
or system, or to affect its safety or effec-
tiveness of that device or system.
2 Life support devices or systems are in-
tended (a) to be implanted in the human
body, or (b) to support and/or maintain
and sustain human life. If they fail, it is rea-
sonable to assume that the health of the
user may be endangered.
Data Classification
Maximum Ratings
Maximum ratings are ab solute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not
otherwise specified, typical characteristics apply at TA = 25°C and the given supply
voltage.
Operating Range
In the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about "P roce ssing Guide lines " and
"Quality Assurance" for ICs, see our "Product Overview".
PEB 2047
PEB 2047-16
Revision History: Current Version: 03.95
Previous Version: Data Book 01.94
Page
(in Version
01.94)
Page
(in new
Version)
Subjects (changes since last revision)
124 5 Version 2.1
127 8 Pin No. 6: INT open drain output
135 16 Figure 8: Improved
142 23 STAR: FSAD(2:1) position
143 25 MASK: Write address
148 31 Figure 12: 2 × Data Rate, Figure 13: 1 × Data Rate
153 36 Abs. Max. Ratings: VS definition
154 37 tLA min. = 15 ns, tAH min. = 15 ns, tRWD min. = 0 ns
157 40 Figure 23: tRWD
158 41 tS min. = 15 ns
159 42 Sequence of 1., 2. and 3. bit of frame
PEB 2047
PEB 2047-16
Semiconductor Group 4
Table of Contents Page
1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.3 General Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.4 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.1 MTSL Internal Timing and Channel Delay . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3 Operational Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.1 Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.2 Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3 Indirect Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.4 Frame Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1 Mode Register (MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2 Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.3 Status Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.4 Interrupt Status Register (ISTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.5 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.6 Indirect Access Register (IAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.7 Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
6 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.1 Determination of MTSL Frame Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.2 Example for a MTSL Design guaranteeing
Constant Frame Delay for all Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . .48
7 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Semiconductor Group 5 03.95
Memory Time Swi tch Large
(MTSL) PEB 2047
PEB 2047-16
Preliminary Data CMOS IC
Type Ordering Code Package
PEB 2047-N V2.1 Q67100-H6238 P-LCC-44 (SMD)
PEF 2047-N-16 V2.1 Q67100-H6301 P-LCC-44 (SMD)
P-LCC-44
1Features
●Non-blocking time/space switc h for 2048-, 4096-, 8192- or
16 384-kbit/s PCM systems
●Different modes programmable for input and output
separately
●Configurable for a 4096-kHz, 8192-kHz or 16 384-kHz
device clock
●Switching of up to 1024 incoming PCM channels to up to
1024 outgoing PCM channels
●16 input and 8 output PCM lines
●Tristate function for further expansion and tandem
operation
●µP read-access to PCM data
●Programmable clock shift with half clock step resolution for
input and output
●Individual line delay measurement and clock shift
mechanism for 8 PCM inputs
●Built-in selftest
●8-bit Motorola or Intel type µP interface
●Constant or minimal channel-delay programmable on a per
time-slot basis
●In-operation adjustment of bit-sampling without bit errors
●Low power consumption
●Single 5 V power supply
Important Note: All 16 384-MHz features described in this
data sheet are only available with the PEB 2047-16!
PEB 2047
PEB 2047-16
Semiconductor Group 6
Pin Configuration
(top view)
18 19 20 21 22 23 24 25 26 27 28
IN 14/FS6
IN 13/FS5
V
A0
CS
RD/DS
WR/R/W
AD0
AD1
A1
29 AD2
30 AD3
31 AD4
32 AD5
33 AD8
34 AD7
35 OUT5
36 OUT4
37 OUT1
38 OUT0
39 RES7
8
9
10
11
12
13
14
15
16
17
4041424344123456
INT
IN 15/FS7
IN 11/FS3
SP
ALE
CLK
OUT2
OUT3
OUT7
V
SS
ITP03766
DD
PEB 2047
MTSL
OUT6
IN3
IN7
IN6
IN2
IN1
IN5
IN4
IN0
IN 12/FS4
IN 8/FS0
IN 9/FS1
IN 10/FS2
Semiconductor Group 7
PEB 2047
PEB 2047-16
1.1 Pin Definitions and Functions
Pin No. Symbol Input (I)
Output (O) Function
1VSS I Ground (0 V)
3SPI Synchronization Pulse: The MTSL is synchronized to
the PCM system via this line.
14
11
10
7
13
12
9
8
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
I
I
I
I
I
I
I
I
PCM-Input Ports: Serial data is received at standard
TTL levels.
15
16
17
4
20
19
18
5
IN8/FS0
IN9/FS1
IN10/FS2
IN11/FS3
IN12/FS4
IN13/FS5
IN14/FS6
IN15/FS7
I
I
I
I
I
I
I
I
PCM-Input Ports or Frame (Measuring Inputs): These
inputs can additionally be used as frame evaluation
inputs.
21
28 A0
A1 I
IAddress Bus Bit 0, 1: These inputs interface to the
systems address bus to select an internal register for a
read or write access. These pins are only active if a
demultiplexed µP interface mode is selected.
22 CS IChip Select: A low level selects the MTSL for a register
access operation.
23 VDD ISupply Voltage: 5 V ± 5 %.
39 RES I Reset: A high signal on this input forces the MTSL into
reset state.
25 R/W
WR
I
I
Read/Write: When “high”, identifies a valid µP access a s
a read operation. When “low”, identifies a valid µP
access as a write operation (Motorola bus mode).
Write: This signal indicates a write operation (Siemens/
Intel bus mode).
24 DS
RD
I
I
Data Strobe: The rising edge marks the end of a valid
read or write operation (Motorola bus mode).
Read: This signal indicates a read operation (Siemens/
Intel bus mode).
PEB 2047
PEB 2047-16
Semiconductor Group 8
Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O) Function
26
27
29
30
31
32
33
34
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Address Data Bus: If the multiplexed address/data µP-
interface bus mode is selected these pins transfer data
and addresses between the µP and the MTSL.
If a demultip lexed mo de is u sed, these bits i nterface with
the system data bus.
38
37
43
42
36
35
41
40
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
O
O
O
O
O
O
O
O
PCM-Output Port: Serial data is sent by these lines at
standard CMOS- or TTL levels. These pins can be
tristated.
44 CLK I Clock: 4096-kHz, 8192-kHz or 16 384-kHz device clock.
2ALEI Address Latch Enable: In the Intel type multiplexed µP-
interface mode a logical high on this line indicates an
address of an MTSL internal register on the external
address/data bus. In the Intel type demultiplexed µP-
interface mode this line is hardwired to VSS, in the
demultiplexed Motorola ty pe µP-interface mode it should
be connected to VDD.
6INT(OD) Interrupt Line: Active low open drain output.
Semiconductor Group 9
PEB 2047
PEB 2047-16
1.2 Logic Symbol
Figure 1
Functional Symbol
1.3 General Device Overview
The Siemens Memory Time Switch Large MTSL (PEB 2047) is an expansion of the MTSC
(PEB 2045) regarding capacity and/or functionality. It is a monolithic CMOS switching device
capable of connecting maximally 1024 PCM-input time-slots to 1024 output time-slots. A constant
frame delay of one frame can be selected for wideband applications (e.g. ISDN H-Channels),
whereas for example for voice channels a minimal frame delay is programmable. In order to
manage the problem of different line delays, eight of the PCM inputs can be used as frame
measurement inputs and eight different input offsets are allowed. Thus a frame wander can be
compensated by adjusting the input offset during operation. A special circuitry guarantees that no
bit error will occur, when reprogramming the input offsets.
The MTSL on-chip connection memory and data-memory are accessed via the 8-bit standard µP-
interface (Motorola or Intel type).
A built-in selftest mechanism – also activated by the µP – ensures proper device operation in the
system.
The PEB 2047 is fabricated using the advanced CMOS technology from Siemens and is mounted
in a P-LCC-44 package. Inputs and outputs are TTL-compatible.
AD (7 : 0)
OUT (7 : 0)
IN (15 : 0)
VV
SP CLK
DD SS
PCM Interface
µ
ALE
WR
RD
CS
A0
A1
INT
P Interface
ITL03767
PEB 2047
PEB 2047
PEB 2047-16
Semiconductor Group 10
1.4 System Integration
The main application field for the MTSL (PEB 2047) are central switches with high switching
capacity. Two p ossibili ties exist to im plement a non -blocking s witch for 1024 input and 1 024 output
channels.
With a 16 384-kHz device clo ck only one MTSL is needed (figure 2), with a 8192-kHz device clock
two chips in parallel realize the same functionality (figure 3).
Figure 2
Memory Time Switch for a Non-Blocking 1024-Channel Switch (16 MHz)
Figure 3
Memory Time Switch for a Non-Blocking 1024-Channel Switch (8 MHz)
8PCM OUT
8 MHz8 MHz
PCM IN 8
ITS03768
MTSL
CLK
384 kHz 16
4
4
PCM OUT
8 MHz8 MHz
PCM IN 8
ITS03769
MTSL
CLK
CLK
MTSL
8192 kHz
Semiconductor Group 11
PEB 2047
PEB 2047-16
Due to the tristate capability of the MTSL larger switches can be easily formed.
Figure 4 and 5 show how 4 devices operating with a 16 384-kHz clock or 8 devices operating with
a 8192-kHz clock can be arranged to form non-blocking 2048-channel switches.
Figure 4
Memory Time Switch for a Non-Blocking 2048-Channel Switch with Four Devices (16-MHz
device clock)
Figure 5
Memory Time Switch for a Non-Blocking 2048-Channel Switch with Eight Devices (8-MHz
device clock)
8
PCM OUT
8 MHz8 MHz
PCM IN
8
8 8
MTSL MTSL
MTSL MTSL
ITS03770
4
4
PCM OUT
8 MHz8 MHz
PCM IN
8
11 21
12 22
1424
1323
8
4
4
MTSL MTSL
MTSL MTSL
MTSL
MTSL
MTSL
MTSL
ITS03771
PEB 2047
PEB 2047-16
Semiconductor Group 12
2 Functional Description
The MTSL is a memory time switch device. Operating with a device clock of 8192 kHz it can connect
any of 1024 PCM-inp ut cha nnels to any of 512 output c hannel s. Wit h a dev ice cloc k of 16 384 k Hz
all 1024 PCM channels can be switched to the output. Additionally a 2048-kbit/s mode with a
capacity of 512 × 256 time-slots and a clock frequency of 4096 kHz is possible for systems, which
need the frame integrity feature.
A general block-diagram of the MTSL is shown in figure 7.
The input information of a complete frame is stored in one o f the two on-c hip 8-Kb it da ta me mories
DM0 and DM1. The incoming 1024 channels of 8 bits each are written in sequence into fixed
positions of DM0 or DM1. This is controlled by the input counter in the timing control block with a
8-kHz repetition rate. If MTSL-A1 compatible operation (i.e. no frame integrity guaranteed) is
wished, only one of the two data memories is used. Otherwise DM0 and DM1 are filled alternating
with input frames.
For outputting, the connection memory (CM) is read in sequence. Each l ocation in the CM points to
a location in the data memory. The byte in this data memory location is transferred into the current
output time-slot. The read access to the CM is controlled by an output counter. An additional bit
(D12) in each location of the CM controls the access to the data memories DM0 and DM1. Three
address pointers – two switching aligned to the input frame (DMI, IADP), one switching aligned to
the output frame (DMO) – are working in conjunction with D12 implementing the constant/minimal
delay function (see fi gure 6).
Figure 6
ITD03772
FRAME (N-1) FRAME N FRAME (N+1)
SP
DMO
DMI
IADP 01
61 62 63
01
63
0
63
0
FRAME N FRAME N+1 FRAME N+2
.......... .......... ..........
FRAME (N-1) FRAME (N-1) FRAME N
READ TS0 from DM READ TS0 from DM READ TS0 from DM
WRITES TS0 to DM WRITES TS63 to DM WRITES TS63 to DM
Semiconductor Group 13
PEB 2047
PEB 2047-16
Constant delay (D12 = 0): read output time-slot from data memory (not DMO)
Minimal delay (D12 = 1): if number of input time-slot to be switched to current output ≤ IADP
then read output time-slot from data memory DMI
else read output time-slot from data memory (not DMI)
The synchronization of this procedure will be achieved by a rising edge of the synchron pulse SP,
which is always sampled with the falling edge of the device clock.
Different modes of operation are configurable at the PCM-input interface (see table 3).
Furthermore, 8 PCM-input lines can be aligned with individual clock shift values to compensate
different line d elays. If more than 8 inputs are used one clock shift value controls up to two ports at
the same time.
The input lines IN8 to IN15 can be used as additional frame-measurement inputs (FS(0:7)). After
synchronizing the device by the SP pulse the FS inputs can be evaluated on a per port basis. This
evaluation procedure is started by a microprocessor command. As a result the input counter value
on the rising edge of the FS signal can be read from an inte rnal re gister. Thus del ay c ompen satio n
is easily managed by program ming appropriate clock shi ft values and/or a possible software offse t.
During operation of the chip a frame length check is also supplied, which controls correct
synchronization by the SP pulse and generates an interrupt in case of lost or achieved
synchronization.
The output buffer operation is controlled by mode selection and the chosen clock-rate (4096 kHz,
8192 kHz or 16 384 kHz) (see table 2). Shifting of the output frame is also possible, but all output-
lines are affected the same way.
The unused output ports are tristated by mode selection, whereas unused time-slots are tristated by
an additional bit in the control memory. By using this tristate capability the MTSL can be easily
expanded to a time switch of any size (see figure 2 to 5).
PEB 2047
PEB 2047-16
Semiconductor Group 14
Figure 7
Block Diagra m MTSL
The standard 8-bit µP interface can communicate with Intel multiplexed/demultiplexed
microprocessors as well as with Motorola demultiplexed processors. It gives access to the internal
registers an d to the c ontrol- a nd data mem ory. Fi ve directl y a ddress able registers are provided. All
other registers and the memories are accessed by a simple three byte indirect access method
(similar to the MTSC PEB 2045).
ITB03741
Interface
µ
P
MOD
CMDR
STAR
MASK
ISTA
IAR CM
Memory
Connection
CS
Reg.
Timing Control Output Buffer
Input Buffer
Data
Memory
DM0 DM1
AD0...
AD7
A0...A1
ALE
RD
WR
CS
INT
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8/FS0
IN9/FS1
IN10/FS2
IN11/FS3
IN12/FS4
IN13/FS5
IN14/FS6
IN15/FS7
OUT0 OUT7RES CLKSP
Semiconductor Group 15
PEB 2047
PEB 2047-16
2.1 MTSL Internal Timing and Channel Delay
Figure 7 shows the chip internal timing of writing and reading the data memory for all possible
operation modes.
Control Memory Reset
Initialization of the device after a hardware reset (RES) is easily done with a µP-command “control
memory reset”. After finishing this procedure all control memory channels contain the information
“tristated”.
Evaluate Frame Measurement Signal
A command and an address (0 … 7) will be given by the µP. The rising edge of the corresponding
frame measurement signal (FS0 … FS7) will be evaluated. The exact timing of the FS edge can
then be read from an internal 12-bit register (resolution of a complete 8-kHz frame in half 16-MHz
clock periods).
MTSL-Selftest
The switching path of the MTSL includi ng input buffer, da ta memory, co ntrol memory, output buffer
and timing control can be tested in the system by a built-in selftest. The two data memories DM0
and DM1 require two test procedures. Activating this mechanism takes (2 ×2.5) ms (4096 kHz),
(2 ×1.25) ms (8192 kHz) or (2 × 0.625) ms (16 384 kHz). Finally the result “selftest ok/selftest not
ok” can be read from the internal status register.
After test completion the control-memory is also reset.
2.2 Special Functions
The activity of all special funct ions can be read in the status register. Completion of these functions
is indicated by interrupts.
PEB 2047
PEB 2047-16
Semiconductor Group 16
Figure 8
Data Memory Timing
ITD06636
Data Rate/Mbit/s x 1.024
Clock Freq./MHz x 1.024
Input
Device Clock
2244
8844
16---
TS2 TS3 TS4 TS5
TS4
TS1 TS2
TS5 TS6 TS7 TS8 TS9 TS10 TS11
or TS0 & TS1
IN0...IN7
IN0...IN15
TS0
or
8--16
-8-4
TS0...TS3
IN0, IN2, IN4, IN6
WA Possible Write Periods
BW
B
A
W
R
Write
Read
Data-Memory
Data-Memory
Possible Read Periods
0
RR
1
R
2
R
3
R
4
R
5
R
6
R
7
OUT#
TS#33333333
TS2TS1
TS5TS4TS3TS2
TS11TS10TS9TS8TS7TS6TS5TS4
-8-16
48
42
Output
84 TS2 TS3 TS4 TS5
A
A
76TS#
OUT# RRRR
3
R
2
R
1
RR0
676767
1
RR
3
R
5
R
7
OUT#
TS#
B
5
6
R
4
R
2
RR0
5555555
11
0
RR
2
RR
10
B
TS#
OUT# RR
3
RR1
0123
1320
10 1110 1110 11
2-Mbit Mode Normal Mode
--
--
--
* Possible read and write periods are aligned to output time-slots
1)
1)
Semiconductor Group 17
PEB 2047
PEB 2047-16
For a system operating with 8192-kHz device clock and 8192-Mbit/s/8192 Mbit/s input/output data
rate the following frame delay table can be deduced from the timing diagram:
Table 1
From this table it can be seen, that it is not possible to achieve the constant delay of one frame for
all switching paths. Those input time-slots, which are written to the data memory later than they
should have been read (for exam ple in the above c onfiguration TS124 – TS127 switc hed to TS0 or
TS1, OUT1, 2, 3), will be delayed by three frames!
Input Time-Slot Switched to Output Time-Slot
Switched
to
OUT1, 2, 3
0– 1
2– 3
4– 5
.
.
.
118 – 119
120 – 121
122 – 123
124 – 125
126 – 127
6 – 127
8 – 127
10 – 127
.
.
.
124 – 127
126 – 127
–
–
–
0– 5
0– 7
0– 9
.
.
.
0 – 123
0 – 125
0 – 127
2 – 127
4 – 127
–
–
–
.
.
.
–
–
–
0– 1
0– 3
Switched
to
OUT0
0– 1
2– 3
4– 5
.
.
.
118 – 119
120 – 121
122 – 123
124 – 125
126 – 127
7 – 127
9 – 127
11 – 127
.
.
.
125 – 127
127
–
–
–
0– 6
0– 8
0– 10
.
.
.
0 – 124
0 – 126
1 – 127
3 – 127
5 – 127
–
–
–
.
.
.
–
–
0
0– 2
0– 4
Delay/number of
frames minimal delay 0 1 2
constant delay 1 1 3
PEB 2047
PEB 2047-16
Semiconductor Group 18
3 Operational Description
3.1 Initialization Procedure
For a proper initialization of the MTSL the following procedure is recommended:
First a reset pulse (RES) of at least two CLK clock-periods has to be applied. All registers contain
now their reset values. In the next step the connection-memory CM is initialized by the commands
CMDR:STP (1:0) = 01 (CM reset) or CMDR:STP (1:0) = 11 (MTSL selftest).
After having programmed a CM-reset command, it takes 4096-clock period s until all tristate-control
entries in the CM contain the value “1” (tristated).
If a selftest-command was given, it takes 10 240-clock periods to achieve the same effect.
Furthermore the register b it STAR:STOK (selftest o.k. ) should still be s et to “1” in this case, in or der
to prove that there is no fault on the chip. From version V2.1 up, the selftest command must be given
for each data memory (DM0, DM1) separately. DM1 is tested, when register OPCR contains the
reset value FFH, DM0 is tested by programming OPCR to FBH.
The activity of the procedures can be monitored in STAR:PACT and an interrupt will indicate their
completion.
In all cases it is important, that the outputs are tristated by MOD:PSB = 0.
3.2 Operation Mode
The operation mode of the device is fixed by programming MOD:OMD (1:0) and MOD:IMD (2:0)
and by the device clock used at pin CLK (see table 2 and 3).
3.3 Indirect Access Register
The connection-memory, data-memory and indirect registers are accessible through the indirect
access register (IAR) . An indirect access is performed by reading and/or writing three consecutive
bytes to/from IAR. An incomplete three-byte access is indicated by STAR:Z = 1. After having read
and/or written the third byte the operation selected by IAR :C (1:0), WR/RDQ is started and the bit
STAR:B is set to 1. It takes at most 4.5 clock periods (8.5 clock periods for a “read data memory”)
until the operation is performed and STAR:B is reset.
Semiconductor Group 19
PEB 2047
PEB 2047-16
3.4 Frame Evaluation
Suppose the following timing at PCM input IN5 (mode 2):
Figure 9
If the device i s i n s ynch ronize d sta te (STAR:PSS = 1) and the command “frame evaluation at FS5”
(CMDR = 58H) is programmed, the second following rising edge of FS5 is evaluated and creates the
following result in register FER:
D (11) = 0
D (10:1) = 3E7H
D (0) = 0
D0 is fixed to 0 and doesn’t have a meaning in 8-MHz clock operation modes.
The actual offset of the incoming frame can now be calculated according to the formulas given in
table 9.
ITD03773
SP
CLK
FS 5
IN 5 TS 127 TS 0
PEB 2047
PEB 2047-16
Semiconductor Group 20
3.5 Input Offset and Output Offset
Based on the results of the frame evaluation procedures the input offsets can be adjusted by
programming ICSR (7:0) corresponding to inputs IN (7:0). If data oversampling is used, the values
of ICSR (7:0) can be adjusted within some limits during operation without producing bit errors:
a) clockrate = 2 ×datarate
possible adjustment is one half clockperiod forward or backward.
Figure 10
b) clockrate = 4 × datarate
possible adjustment is one clockperiod backward or two clockperiods forward.
Figure 11
The output offset is the same for all output lines and is fixed in register OCSR.
ITD03774
CLK
1
2
-1
2
0+
Data
ITD03775
CLK
11
2
-- 1
2
00+ 1+
3
2
++2
Data
Semiconductor Group 21
PEB 2047
PEB 2047-16
4 Detailed Register Description
4.1 Mode Register (MOD)
Access in the multiplexed µP-interface mode: Read/write, address: 0H
Access in a demultiplexed µP-interface mode: Read/write, address: 0H
Reset value: 00H
PSB PCM Stand By; a logical 0 switches the PCM-interface outputs to high
impedance.
MD2 If set to “1”, the PEB 2047 is able to switch channels with 2048-kHz data rate,
when operating with 8.192 MHz (switchin g capacity 512 × 512 time-slots) or
4.096 MHz (switching capacity 512 ×256 time-slots).
OMD1 … OMD0 Output Mode 1 a nd 0; these bi ts defi ne the PCM-out put mod e acc ording to
the following table.
1) Input and out put mode co m binations w hic h us e t he s am e device clock fre quency hav e to be s elec t ed.
Bit 7 Bit 0
PSB MD2 0 OMD1 OMD0 IMD2 IMD1 IMD0
Table 2
Output Modes
Device Clock
[kHz] Output Mode
OMD (1:0)1) Port Numbers Number of Ports ×
Data Rate/kbit/s
4.096 0 OUT (7:0) 8 × 2048
1 OUT7, OUT5, OUT3, OUT1,
OUT2, OUT0 4 × 2048 /
2 × 4096
3 OUT (3:0) 4 × 4096
8.192 0 OUT (7:0) 8 × 4096
1 OUT7, OUT5, OUT3, OUT1,
OUT2, OUT0 4 × 4096 /
2 × 8192
3 OUT (3:0) 4 × 8192
16.384 0 OUT (7:0) 8 × 8192
1 OUT7, OUT5, OUT3, OUT1,
OUT2, OUT0 4 × 8192 /
2 × 16384
3 OUT (3:0) 4 × 16384
PEB 2047
PEB 2047-16
Semiconductor Group 22
IMD2 … IMD0: Input Mode 2, 1 and 0; these bits define the PCM-input mode according to
the following table.
1) Input and out put mode co m inat ions which us e th e sa m e dev ic e c loc k freq uency have to be se lec te d.
Table 3
Input Modes
Device Clock
[kHz] MD2 Input Mode
IMD (2:0)1) Port Numbers Number of Ports ×
Data Rate/kbit/s
4.096 1 0 IN (15:0) 16 × 2048
1 1 IN (15:12), IN (7:4) /
IN (3:0) 8 × 2048 /
4 × 4096
1 2 IN (7:0) 8 × 4096
8.192 0 0 IN (15:0) 16 × 4096
0 1 IN (15:12), IN (7:4) /
IN (3:0) 8 × 4096 /
4 × 8192
0 2 IN (7:0) 8 × 8192
1 4 IN (15:0) 16 × 2048
1 5 IN (15:12), IN (7:4) /
IN (3:0) 8 × 2048 /
4 × 4096
1 6 IN (7:0) 8 × 4096
16.384 0 4 IN (15:0) 16 × 4096
0 5 IN (15:12), IN (7:4) /
IN (3:0) 8 × 4096 /
4 × 8192
0 6 IN (7:0) 8 × 8192
0 3 IN6, IN4 /
IN (3:0) 2 × 16384 /
4 × 8192
0 7 IN6, IN4, IN2, IN0 4 × 16984
Semiconductor Group 23
PEB 2047
PEB 2047-16
4.2 Command Register (CMDR)
Access in the multiplexed µP-interface mode: Write, address 2H
Access in a demultiplexed µP-interface mode: Write, address 1H
Address: 01H
FSAD (2:0) Frame Synchronization signal Address 2 to 0; Address of the chosen FS
signal 0 to 7 to be evaluated by the procedure started by SFE.
SFE Start Frame Evaluation ; a one in this bit position starts the frame evaluation
procedure. A read operation on register FER will stop an unfinished frame
evaluation procedure.
RI Reset Incomplete instruction; if a three byte indirect register access is not
completed the internal logic must be initiali zed again before a new three byte
access is possible.
STP0 … STP1 Start Procedure 1 and 0.
The following procedures can be activated by these bits:
Note: Before activating one of these procedures MOD:PSB has to be set to 0. During selftest or CM
reset the devic e will ignore the external synchron ization pulse and the user has no access to
the internal data memory.
Bit 7 Bit 0
0 FSAD2 FSAD1 FSAD0 SFE RI STP1 STP0
Table 4
STP Commands
STP1 STP0 Function
X
0
1
0
1
1
No operation
Start control memory reset procedure
Start selftest procedure
PEB 2047
PEB 2047-16
Semiconductor Group 24
4.3 Status Register (STAR)
Access in the multiplexed µP-interface mode: Read, address: 2H
Access in a demultiplexed µP-interface mode: Read, address: 1H
Reset value: 01H
ZIncomplete instruction; a three byte indirect instruction is not completed (Z = 1).
FSAD (2:0) Frame Synchronization signal Address 2 to 0: see CMDR.
BBusy; an indirect access is active (memories or indirect registers); the three byte
indirect access register is not accessible.
PACT Procedure Active; one of the procedures started by th e µP (selftest, CM reset or
frame evaluation) is active.
PSS PCM Synchronization Status; the PCM interface is synchronized (logical 1) or
not synchronized (logical 0).
STOK Se lftes t O.K.; after a selftest procedure this bit is set to 1, if no faults are detected.
Note: This bit is only valid, if no power failure or inappropriate clocking occurred during
the test (see ISTA:IR); this bit is set to 1 by a start selftest command or by
hardware reset.
Bit 7 Bit 0
Z FSAD2 FSAD1 FSAD0 B PACT PSS STOK
Semiconductor Group 25
PEB 2047
PEB 2047-16
4.4 Interrupt Status Register (ISTA)
Access in the multiplexed µP-interface mode: Read, address: 4H
Access in a demultiplexed µP-interface mode: Read, address: 2H
Reset value: 00H
FEC Frame Evaluation Completed ; t he i ndirec t reg ister FER con tains a val id offset and can be
read; this bit is reset by reading ISTA.
PC Procedure Completed; the procedure started from the command register (CM reset or
MTSL selftest) is finished; this bit is reset by reading ISTA.
IR Initialization Request. The connection memory has to be programmed due to a loss of data
(IR = 1). The IR bit is set after power failure or inappropriate clocking. This bit is reset by
reading ISTA. It can only be retriggered again after a selftest or CM-reset procedure.
PFI PCM-Framing Interrupt; this bit being logical 1 indicates the loss or gain of synchronization.
Synchronization is considered lost by the MTSL if the SP signal is not r epeated within the
correct period. Synchronization is considered achieved, if two consecutive SP pulses with
the correct period have been received. PFI is reset by reading ISTA.
4.5 Mask Register (MASK)
Access in the multiplexed µP-interface mode: Write, address: 4H
Access in a demultiplexed µP-interface mode: Write, address: 2H
Reset value: 00H
A logical 1 disables the corresponding interrupt as described in ISTA. A masked interrupt is stored
internally and reported in ISTA immediately, if the mask is released.
Bit 7 Bit 0
0000FECPCIRPFI
Bit 7 Bit 0
0000FECPCIRPFI
PEB 2047
PEB 2047-16
Semiconductor Group 26
4.6 Indirect Access Register (IAR)
Access in the multiplexed µP-interface mode: Read/write, address: 6H
Access in a demultiplexed µP-interface mode: Read/write, address: 3H
Reset value: Only the control bits C (1:0) and WR/RDQ are initialized to 0.
An indirect access is performed by reading/writing three consecutive bytes (first byte = extended
control byte, second byte = data byte, third byte = address byte) to/from IAR.
C (1:0) Code values to determine the type of access.
WR/RDQ If set to 1 a write access is performed; otherwise a read access is activated.
Bit 7 Bit 0
C1 C0 /
D12 WR/
RDQ IA9 IA8 /
D11 D10 D9 D8
control byte
D7 D6 D5 D4 D3 D2 D1 D0
data byte
IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA0
address byte
Semiconductor Group 27
PEB 2047
PEB 2047-16
D12 This bit is only used as a data bit in a read or write control memory operation.
Dependent on the contents of register OPCR D12 is interpreted as absolute
address for data memories DM0 and DM1 (OPCR = FFH) or as a switch for
constant (D12 = 0) and minimal (D12 = 1) delay (OPCR = FCH).
D11 This bit is only used as data bit in a read operation of the FER register.
D (10:0) Data value for read/write access; if the control-memory is accessed D10 is used as
a tristate control bit (0 = active, 1 = high impedance).
The incoming PCM data are transformed onto the data-memory (control memory data D12,
D (10: 0)) in the fo ll owing way :
TSN Time-Slot Number
PN Port Number
TSC Tristate Control Value (0 = active, 1 = high impedance)
MD Minimal Delay (1 = minimal, 0 = constant frame delay), if OPCR:OC (1:0) = 00B.
Absolute address of data memories DM0, DM1 if OPCR:OC (1:0) = 11B.
Table 5
Indirect Access Codes
C1 C0 WR/RDQ Function Max. Access Time
Clock Periods
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
0
0
0
1
No operation
Write control memory D12 = 0
Write control memory D12 = 1
Read control memory
Read data memory
Read indirect register
Write indirect register
–
4.5
4.5
4.5
8.5
4.5
4.5
PEB 2047
PEB 2047-16
Semiconductor Group 28
Note: D9 must be set to “0”, if MOD = MD2 is set, i.e. in 2-Mbit applications.
PN ÷ 2 means, you have to multiply D (2:1) by two to generate the correct input numbers.
IA9 … IA0 Indirect Address for a read/write access
If a indirect register is accessed only IA (3:0) are interpreted as address bits.
Table 6
Input Time-Slot Mapping
Input
Mode D (10:0) Valid for Inputs
0,4 IN (15:0)
1,5 IN (15:12), IN
(7:4)
IN (3:0)
2,6 IN (7:0)
7IN6, IN4, IN2,
IN0
3IN (3:0)
IN6, IN4
1) D3 and D0 c ont ain the invert ed values in th es e ca s es .
D12 D10 D9 D8 D7 D6 D5 D4 D31) D2 D1 D0
MD TSC TSN PN
D12 D10 D9 D4 D31) 1D1D0
MD TSC TSN PN
D12 D10 D9 D3 0 D1 D0
MD TSC TSN PN
D12 D10 D9 D3 D2 D1 D0
MD TSC TSN PN
D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0*
MD TSC TSN (7:2) TS N0 PN ÷ 2 TSN1
D12 D10 D9 D3 0 D1 D0
MD TSC TSN PN
D12 D10 D9 D4 D3 1 D1 D0*
MD TSC TSN (7:2) TSN0 PN ÷ 2TSN1
Semiconductor Group 29
PEB 2047
PEB 2047-16
The control memory address is transformed to the output time-slots:
Note: IA9 is only valid within applications with a 16.384-MHz device clock. If a 8.192 or
4.096-MHz clock is used, it is internally fixed to 0.
IA8 must be set to “0”, if MOD:MD2 is set, i.e. in 2-Mbit applications.
Table 7
Output Time-Slot Mapping
Output
Mode Valid for
Outputs
0OUT (7:0)
1OUT7, OUT5,
OUT3, OUT1
OUT2, OUT0
3OUT (3:0)
IA9 IA8 IA3 IA2 IA1 IA0
TSN PN
IA9 IA8 IA3 IA2 IA1 1
TSN PN
IA9 IA8 IA2 IA1 0
TSN PN
IA9 IA8 IA2 IA1 IA0
TSN PN
PEB 2047
PEB 2047-16
Semiconductor Group 30
4.7 Indirect Registers
Input Clock Shift Registers ICSR (7:0)
Read/write at indirect address IA (3:0) = 0H … 7H
Reset value: 40H
ADSR Add Shift Register; a three bit shift register is inserted into the corresponding
input(s).
ICS4 … ICS0 Input Clock Shift; the value of ICS (4:0) determines the number of cl ock cycles by
which the bit sampling point is shifted forward in all input modes.
Note: ICS4 has to be set to “0” in input modes 0, 1 and 2.
RRE Receive on Rising Edge
These eight registers determine the individual clock shift of inputs IN0 to IN7.
If more than eight inputs are used, two inputs are controlled by one ICSR register:
ICSR0 controls IN0, IN8
ICSR1 ” IN1, IN9
ICSR2 ” IN2, IN10
..
..
..
ICSR7 ” IN7, IN15
Bit 7 Bit 0
ADSR 1 ICS4 ICS3 ICS2 ICS1 ICS0 RRE
Semiconductor Group 31
PEB 2047
PEB 2047-16
Input Timing
Figure 12
Device Clock = 2 × Data Rate
Figure 13
Device Clock = Data Rate
SP
CLK
TS 0, Bit 7
ICS (4 : 0) RRE
0
1
0
00
00
02
TS 0, Bit 7
TS 0, Bit 7
IN#
IN#
IN#
TS 0, Bit 6
H
H
H
ITD03777
SP
CLK
TS 0,
Bit 7
ICS (4 : 0) RRE
0
1
0
00
00
01
TS 0,
Bit 7
TS 0,
Bit 7
IN#
IN#
IN#
Bit 6 Bit 6
H
H
H
PEB 2047
PEB 2047-16
Semiconductor Group 32
Figure 14
Device Clock = 4 × Data Rate
Operation Control Register (OPCR)
Read/write at indirect address IA (3:0) = DH
Reset value: FFH
SDM Select Data Memory; only used in configuration with OC (1:0) = 11B
OC (1:0) Operation Control; OC (1:0) determine the usage of the two data memory blocks
according to the table below.
Table 8
Bit 7 Bit 0
11111SDMOC1OC0
OC1 OC0 Function
1 1 Only one data memory block i s used; the absol ute address is gi ven by SDM; bit
D12 in the control memory is also interpreted as absolute address.
0 0 Both data memory blocks are used; bit D12 in the control memory controls the
constant or minimal frame delay function.
01Reserved
10Reserved
ITD03778
SP
CLK
TS 0, Bit 7
ICS (4 : 0) RRE
0
1
0
00
00
04
TS 0, Bit 7
TS 0, Bit 7
IN#
IN#
IN#
H
H
H
Semiconductor Group 33
PEB 2047
PEB 2047-16
Output Clock Shift Register (OSCR)
Read/write at indirect address IA (3:0) = EH
Reset value: 20H
This register determines the clock shift for all outputs.
OCS (3:0) Output Clock Shift
XFE Transmit on Falling Edge
Figure 15
Output Timing and Clock Shift
Bit 7 Bit 0
VN2 VN1 VN0 OCS3 OCS2 OCS1 OCS0 XFE
ITD03779
SP
CLK
Device Clock
= 2 x Data Rate
Device Clock
= Data Rate
TS0, Bit7 TS0, Bit6
TS0, Bit7 TS0, Bit6
TS0, Bit7 TS0, Bit6
TS0, Bit7
TS0, Bit7
TS0, Bit7
OCSR (3: 0) XFE
00
01
10
0
1
1
0
0
0
H
H
H
H
H
H
PEB 2047
PEB 2047-16
Semiconductor Group 34
VN (2:0) Version Number according to the table below:
Frame Evaluation Register (FER)
Read at indirect address IA (3:0) = FH
Reset value = XXX
After a frame evaluation p rocedure this 1 2-bit register contains the input counter offset b etween the
SP frame and a n evaluated FS0 … FS7 frame. The eval uation is perfo rmed at the sec ond followin g
rising edge of FS after the command CMDR:SFE = 1 was programmed.
D11 The FS-rising edge was sa mpled durin g the cl ock-high p hase (D11 = 1), o r during
the clock-low phase (D11 = 0).
D (10:0) The FS-rising edge was sampled at:
input counter value + 1 if D 11 = 1
input counter value + 2 if D 11 = 0
With a device clock of 8 MHz D0 is fixed to 0 and D (10:1) contain the input counter
value.
The actual offset between the SP frame and an evaluated FS frame can be calculated by the
following formulas:
Table 9
Version Number
VN2 VN1 VN0 Device Versions
000A1
0 0 1 V2.1 (B1)
Bit 7 Bit 0
D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
CLK × 1.024 MHz Offset Value/Number of Clock Periods D11 FS-Rising Edge at
8 (D (10:1)H + 01DH)MOD1024
(D (10:1)H + 01EH)MOD1024
0
1CLK low
CLK high
16 (D (10:0)H + 03DH)MOD2048
(D (10:0)H + 03EH)MOD2048
0
1CLK low
CLK high
4 (D (9:1)H + 01DH)MOD512
(D (9:1)H + 01EH)MOD512
0
1CLK low
CLK high
Semiconductor Group 35
PEB 2047
PEB 2047-16
Definition of the calculated offset value:
Figure 16
Formulas for Offset Calculation
Note: The device must be synchronized to SP (STAR: PSS = 1) in order to generate a correct result
in FER.
ITD03780
SP
CLK
012345678910
..
Offset Value
PEB 2047
PEB 2047-16
Semiconductor Group 36
5 Electrical Characteristics
Note: Stresses above those lis ted here m ay ca use pe rmanent d amage to the dev ice. Exposure to
absolute maximum ratings conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Parameter Symbol Limit Values Unit
Ambient temperature under bias TA0 to 70 °C
Storage temperature Tstg – 65 to 125 °C
Voltage at any pin with respect to ground VS– 0.4 to VDD +0.4 V
Maximum voltage on any pin Vmax 7V
DC Characteristics
Ambient temperature under bias range; VDD = 5 V ± 5 %, VSS = 0 V.
Parameter Symbol Limit Values Unit Test Condition
min. max.
L-input voltage VIL – 0.4 0.8 V
H-input voltage VIH 2.2 VDD + 0.4 V
L-output voltage VOL 0.45 V IOL = 2 mA
H-output voltage
H-output voltage VOH
VOH
2.4
VDD – 0.5 V
VIOH = – 400 µA
IOH = – 100 µA
Operational power supply current
fCLK = 8192 kHz
fCLK = 16384 kHz ICC
ICC
20
34 mA
mA
VDD = 5 V,
inputs at 0 V or VDD, no
output loads
Input leakage current
Output leakage current ILI
ILO
10
10 µA
µA0 V < VIN < VDD to 0 V
0 V < VOUT < VDD to 0 V
Capacitances
TA = 25 °C, VDD = 5 V ± 5 %, VSS = 0 V.
Parameter Symbol Limit Values Unit
min. max.
Input capacitance CIN 10 pF
Output capacitance COUT 15 pF
I/O capacitance CIO 20 pF
Semiconductor Group 37
PEB 2047
PEB 2047-16
AC Characteristics
Ambient temperature under bias range, VDD = 5 V ± 5 %.
Inputs are driven at 2.4 V for a l ogical 1 and at 0.4 V for a logical 0. Ti ming measurements a re made
at 2.0 V for a lo gical 1 and a t 0.8 V for a logical 0. The AC testing i nput/output waveforms are s hown
below.
Figure 17
I/O Waveform for AC Tests
µP-Interface Timing Parameters
Parameter Symbol Limit Values Unit
min. max.
ALE pulse width tAA 30 ns
Address setup time to ALE tAL 10 ns
Address hold time from ALE tLA 15 ns
Address latch setup time to WR, RD tALS 0ns
Address setup time to WR, RD tAS 10 ns
Address hold time from WR, RD tAH 15 ns
RD delay after WR setup tDSD 0ns
RD pulse width tRR 120 ns
Data output delay from RD tRD 100 ns
Data float from RD tDF 25 ns
RD control interval tRI 70 ns
WR pulse width tWW 60 ns
Data setup time to WR + CS tDW 30 ns
Data hold time from WR + CS tWD 10 ns
WR control interval tWI 70 ns
R/W delay after RD setup tRWD 0ns
ITS00568
= 150 pf
Load
C
Test
Under
Device
2.0
0.80.8
2.0 Test Points
PEB 2047
PEB 2047-16
Semiconductor Group 38
Figure 18
µP-Read Cycle
Figure 19
µP-Write Cycle
ITT00712
RD x CS
AD0 - AD7
t
RD
Data
t
DF
RR
tt
RI
ITT00713
WR x CS
AD0 -AD7
t
DW
Data
t
WD
WW
tt
WI
Semiconductor Group 39
PEB 2047
PEB 2047-16
Figure 20
Multiplexed Address Timing
Figure 21
Demultiplexed Address Timing
ITT00714
WR x CS
AD0 - AD7
t
LA
CSxRD or
Address
ALE
t
ALS
t
AL
t
AA
t
AD
ITT00715
WR x CS
A0 - A5
t
AH
t
AS
Address
CSxRD or
PEB 2047
PEB 2047-16
Semiconductor Group 40
Motorola Bus Mode
Figure 22
µP-Read Cycle
Figure 23
µP-Write Cycle
Figure 24
Address Timing
ITT00716
CS x DS
D0 - D7
t
RD
Data
t
DF
DSD
t
RR
tt
RI
R/W
t
RWD
ITT00717
CS x DS
AD0 - AD7
t
DW
Data
t
WD
DSD
t
WW
tt
WI
R/W
RWD
t
ITT00718
CS x DS
AD0
t
AH
t
AS
- AD5
Semiconductor Group 41
PEB 2047
PEB 2047-16
PCM-Interface Characteristics
Parameter Symbol Limit Values Unit Condition
min. max.
Clock period
Clock period low
Clock period high
tCP
tCPL
tCPH
120
50
50
ns
ns
ns
PEB 2047
Clock period
Clock period low
Clock period high
tCP
tCPL
tCPH
60
27
23
ns
ns
ns
PEB 2047-16
Frame setup time
Frame hold time tFS
tFH
15
20 ns
ns
Serial data input setup time
Serial data input hold time
tS
tH
15
20
ns
ns
PCM-input data
frequency 8192 kHz
Serial data input setup time
Serial data input hold time
tS
tH
15
20
ns
ns
PCM-input data
frequency 16496 kHz
only PEB 2047-16
PCM-serial data output delay
time tD30 ns
PEB 2047
PEB 2047-16
Semiconductor Group 42
Figure 25
AC Characteristics at the PCM Interface
ITD03781
1st Bit
of Frame
of Frame
1st Bit
1st Bit
of Frame
1st Bit
of Frame
1st Bit
of Frame
1st Bit
1st Bit
t
CPL
t
CPH
t
CP
t
FH
t
FS
t
FS
t
FH
t
D
S
tt
H
H
t
t
S
S
tt
H
S
tt
H
t
D
D
t
CLK
SP
OUT
(OSCR:XFE = 0)
(ISCR:RRE = 0)
IN
IN
(ICSR:RRE = 1)
(OSCR:XFE = 1)
OUT
Clock Rate
= 4 x Data Ratex Data Ratex Data Rate= 2 x Data Rate
Clock Rate
OUT
(OCSR:XFE = 1)
(ICSR:RRE = 1)
IN
IN
(OCSR:RRE = 0)
(OCSR:XFE = 0)
OUT
of Frame
of Frame
2nd Bit
of Frame
of Frame
2nd Bit
of Frame
2nd Bit
1st Bit
of Frame 2nd Bit
of Frame
D
t
3rd Bit
of Frame
of Frame
3rd Bit
Semiconductor Group 43
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Figure 26
AC Characteristics at the PCM Interface
t
FS
FH
t
t
FS
FH
t
t
CPL
CPH
t
t
CP
t
S
H
t
t
H
S
t
ITD03782
IN
(ICSR:RRE=1)
(ICSR:RRE = 0)
IN
SP
CLK
Clock Rate
= 4 x Data Rate
1st Bit
of Frame
of Frame
1st Bit
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Semiconductor Group 44
6 Applications
6.1 Determination of MTSL Frame Delay
When switching time slots from the input of the MTSL to its output, the question often arises whether
the incoming channel is transmitted in the same frame (0 frame delay), the next frame (1 frame
delay), or even in the frame thereafter (2 frames delay).
Because framing delay is different depending on the selected output port, delay tim ings hav e to b e
calculated separately for all outputs.
The following text advises how to do this calculation and delivers a value for MINIMAL or
CONSTANT delay. A CONSTANT delay may be programmed by the control byte bit D12 of IAR-
register.
Instructions for Use
1. Determine the data rate for the input data strea m and for the output data stream. e.g. 4 Mbit/s for
input data stream; 4 Mbit/s for output data stream.
2. Select a device clock. Please note, that not all ouput ports are available for every choice of the
device clock (refer to the following table) !! e.g. 8 MHz.
3. Determine the constant Td for your special configuration by selecting the corresponding row in
the table below (a, b, c or d):
e.g. for a 4 Mbit/s input- /o utput- data stream with 8 M Hz device cl ock row a) has to be selecte d.
The table delivers a value Td= 4 for line OUT0 and Td= 3 for OUT1 … 7.
A big value for Td also means a big internal switching delay.
1) 2, 4 has the meaning 2,048 Mbit/s or 4,096 Mbit/s
Input Data
Rate [Mbit/s] Output Data
Rate [Mbit/s] Device
CLK [MHz] Td for
OUT0 Td for
OUT1 Td for
OUT2 …3 Td for
OUT4 …7
a) 2, 41)
4, 8 2
44
843 3 3
b) 2, 41)
4, 8 4
84
87 6 6 not available !!
c) 2
4, 8, 16 4
88
16 65 5 5
d) 2, 41)
4, 8, 16 8
16 8
16 11 10 10 not available !!
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4. Determine the constant M.
The value for M can be determined by selecting the corresponding row in the table below (a, b
or c) for your configuration.
e.g. for a 4 Mbit/s input- /o utput- data stream with 8 M Hz device cl ock row a) has to be selecte d.
The table delivers the value M = 1.
5. Determine the constant K.
The value for K can be determi ned by selecting the corresponding row in the table be low (a, b or
c) for your configuration.
e.g. for a 4 Mbit/s input- /output- data stream with 8 MHz device clock row a) has to be selected
and the table delivers the value K = 1.
The Constant M for Different Data Rates…
Input Data Rate
[Mbit/s] Output Data Rate
[Mbit/s] Device
CLK [MHz] M
a) 2, 4
4, 8 2
44
81
b) 2, 4
4, 8
2
4, 8, 16
4
8
4
8
4
8
8
16
2
c) 2, 4
4, 8, 16 8
16 8
16 4
Input
Data Rate
[Mbit/s]
Output
Data Rate
[Mbit/s]
Device CLK
[MHz] Number of Input TS [K]
Sampled at the same Time
a) 2
2
4
4
2, 4
4, 8
4, 8
8, 16
4
8
8
16
1
b) 4
8
8
2, 4
4, 8
8, 16
4
8
16
2
c) 16 8, 16 16 4
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Semiconductor Group 46
6. By inserting the obtained values for K, M and Td in the table below, minimal and constant frame
delays may be calculated for every timeslot (TS).
The other constants inserted are:
n: This constant is a max. counter value that is obtained by integer di vision of Td by M.
maxi: Is the maximal number of input time slots – 1
maxo: Is the maximal number of output time slots – 1
Please note: A negative value means no entry in the table!
Example
The example below will demonstrate the usage for a system with 8 MH z device CLK and 4 Mbit/s
input and output data streams.
Before starting the calculation the value n must be found by integer division of Td by M. With the
values Td = 4 and M = 1 the value for n = 4. With Td = 3 and M = 1 the value for n = 3.
The maximal number of input time slots : maxi = 64 – 1 = 63
The maximal number of output time slots: maxo = 64 – 1 = 63
Input TS Minimal Delay
= 0 Frame
for Output TS
Minimal Delay
= 1 frame
for Output TS
Minimal Delay
= 2 Frames
for Output TS
0 × K…(1 × K–1)
1 × K…(2 × K–1)
2 × K…(3 × K–1)
3 × K…(4 × K–1)
.
.
maxi+1–(n+1) ×
K … maxi-n × K
Td+(0 × M) … maxo
Td+(1 × M) … maxo
Td+(2 × M) … maxo
Td+(3 × M) … maxo
…
.
maxo + 1 – (n + 1) ×
M+T
d
… maxo
0…(T
d–1+0 × M)
0…(T
d–1+1 × M)
0…(T
d–1+2 × M)
0…(T
d–1+3 × M)
…
.
0 … maxo – (n + 1) ×
M+T
d
–
maxi+1–n × K … maxi –
(n–1) × K
.
.
maxi+1–2 × K … maxi-1 × K
maxi+1–1 × K … maxi-0 × K
–Td– n × M…maxo
.
.
T
d– 2 × M…maxo
T
d– 1 × M…maxo
0…(T
d– n × M–1)
.
.
0…(T
d– 2 × M–1)
0…(T
d– 1 × M–1)
constant delay
in [frames] 113
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Frame Delay for OUT0 with Td = 4, K = 1, M = 1, n = 4, maxo = 63, maxi = 63:
Input TS Minimal Delay
= 0 frame
for Output TS
Mminimal Delay
= 1 Frame
for Output TS
Minimal Delay
= 2 Frames
for Output TS
0
1
2
.
.
59
4…63
5…63
6…63
.
.
63
0…3
0…4
0…5
.
.
0 … 62
–
60
61
62
63
–0…63
1…63
2…63
3…63
–
0
0…1
0…2
constant delay
in [frames] 113
Frame Delay for OUT1 … 7 with Td = 3, K = 1, M = 1, n = 4, maxo = 63, maxi = 63:
Input TS Minimal Delay
= 0 frame
for Output TS
Minimal Delay
= 1 Frame
for Output TS
Minimal Delay
= 2 Frames
for Output TS
0
1
2
.
.
60
3…63
4…63
5…63
.
63
0…2
0…3
0…4
.
.
0…62
–
61
62
63
–0…63
1…63
2…63
– 0
0
0…1
constant delay
in [frames] 113
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Semiconductor Group 48
6.2 Example for a MTSL Design guaranteeing Constant Frame Delay for all Time Slots
In order to achieve a constant frame delay of all PCM channels switched from input to output, the
following work-around is suggested. The device is operated with a 16-MHz clock and 8 × 8 MHz
PCM lives for input and output respectively. The effective switch capacity is reduced to 512 × 512.
Figure 27
MTSL Operation Mode with Constant Frame Delay (frame delay = 1)
The general idea in this configuratio n is to switc h all in put ti me-sl ots, which wou ld b e pas sed to th e
output in the same frame (input TS# + OFFSET < output TS #), to OUT [4:7] followed by a switch
from IN [4:7] to the de sired output time-slo t at OUT [0 :3]. Thus a constant frame del ay of on e frame
can be achieved (refer to table 10).
IN0 OUT0
IN1 OUT1
IN2 OUT2
IN3 OUT3
IN4 OUT4
IN5 OUT5
IN6 OUT6
IN7 OUT7
MTSL
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For a 8 MHz/8 MHz-system for example the following frame delay table can be deduced from the
timing diagram:
Table 10
Frame Delay
Input Time-Slot Switched to Output Time-Slot
IN0 ... IN4 or
(IN4 ... IN7
switched to
OUT1 ... OUT3)
0–1
2– 3
4– 5
.
.
.
118 – 119
120 – 121
122 – 123
124 – 125
126 – 127
6 – 127
8 – 127
10 – 127
.
.
.
124 – 125
126 – 127
–
–
–
0– 5
0– 7
0– 9
.
.
.
0 – 123
0 – 125
0 – 127
2 – 127
4 – 127
–
–
.–
.
.
.
–
–
–
0– 1
0– 3
IN4 ... IN7
switched to
OUT0
0– 1
2– 3
4– 5
.
.
.
120
121
122 – 123
124 – 125
126 – 127
7 – 127
9 – 127
11 – 127
.
.
.
127
–
–
–
–
0– 6
0– 8
0– 10
.
.
.
0 – 126
0 – 127
1 – 127
3 – 127
5 – 127
–
–
–
.
.
.
–
.–
0
0– 2
0– 4
Delay/Number of
frames 012
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Semiconductor Group 50
7 Package Outlines
Plastic Package, P-LCC-44 (SMD)
(Plastic Leaded Chip Carrier)
GPL05102
Sorts of Packing
Package outline s for tu bes , tra ys et c . are co nt ained in our
Data Book “Package Information”. Dimensio ns i n m m
SMD = Su rfa ce Mounted Device
