MCP3004/3008 2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface Features Description * * * * * The Microchip Technology Inc. MCP3004/3008 devices are successive approximation 10-bit Analogto-Digital (A/D) converters with on-board sample and hold circuitry. The MCP3004 is programmable to provide two pseudo-differential input pairs or four single-ended inputs. The MCP3008 is programmable to provide four pseudo-differential input pairs or eight single-ended inputs. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are specified at 1 LSB. Communication with the devices is accomplished using a simple serial interface compatible with the SPI protocol. The devices are capable of conversion rates of up to 200 ksps. The MCP3004/3008 devices operate over a broad voltage range (2.7V - 5.5V). Low-current design permits operation with typical standby currents of only 5 nA and typical active currents of 320 A. The MCP3004 is offered in 14-pin PDIP, 150 mil SOIC and TSSOP packages, while the MCP3008 is offered in 16pin PDIP and SOIC packages. * * * * * * * * * * 10-bit resolution 1 LSB max DNL 1 LSB max INL 4 (MCP3004) or 8 (MCP3008) input channels Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 200 ksps max. sampling rate at VDD = 5V 75 ksps max. sampling rate at VDD = 2.7V Low power CMOS technology 5 nA typical standby current, 2 A max. 500 A max. active current at 5V Industrial temp range: -40C to +85C Available in PDIP, SOIC and TSSOP packages Applications Package Types Sensor Interface Process Control Data Acquisition Battery Operated Systems PDIP, SOIC, TSSOP Functional Block Diagram VDD VSS VREF CH0 CH1 CH0 CH1 CH2 CH3 NC NC DGND 1 2 3 4 5 6 7 MCP3004 * * * * 14 13 12 11 10 9 8 VDD VREF AGND CLK DOUT DIN CS/SHDN PDIP, SOIC Input Channel Max DAC Comparator 10-Bit SAR Sample and Hold Control Logic CS/SHDN DIN CLK Shift Register 1 2 3 4 5 6 7 8 MCP3008 CH7* CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 16 15 14 13 12 11 10 9 VDD VREF AGND CLK DOUT DIN CS/SHDN DGND DOUT * Note: Channels 4-7 are available on MCP3008 Only (c) 2008 Microchip Technology Inc. DS21295D-page 1 MCP3004/3008 NOTES: DS21295D-page 2 (c) 2008 Microchip Technology Inc. MCP3004/3008 1.0 Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings VDD ..................................................................................7.0V All Inputs and Outputs w.r.t. VSS ............- 0.6V to VDD + 0.6V Storage Temperature ................................... -65C to +150C Ambient temperature with power applied.......-65C to +150C Soldering temperature of leads (10 seconds) ............. +300C ESD Protection On All Pins (HBM) ................................... 4 kV ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TA = -40C to +85C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TA = +25C. Parameter Sym Min Typ Max Units tCONV -- -- 10 clock cycles Conditions Conversion Rate Conversion Time Analog Input Sample Time tSAMPLE Throughput Rate fSAMPLE 1.5 -- -- clock cycles 200 75 ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V DC Accuracy Resolution 10 bits Integral Nonlinearity INL -- 0.5 1 LSB Differential Nonlinearity DNL -- 0.25 1 LSB Offset Error -- -- 1.5 LSB Gain Error -- -- 1.0 LSB Total Harmonic Distortion -- -76 dB VIN = 0.1V to 4.9V@1 kHz Signal-to-Noise and Distortion (SINAD) -- 61 dB VIN = 0.1V to 4.9V@1 kHz Spurious Free Dynamic Range -- 78 dB VIN = 0.1V to 4.9V@1 kHz No missing codes over temperature Dynamic Performance Reference Input Voltage Range 0.25 -- VDD V Note 2 Current Drain -- 100 0.001 150 3 A A CS = VDD = 5V V Analog Inputs Input Voltage Range for CH0 or CH1 in Single-Ended Mode VSS -- VREF Input Voltage Range for IN+ in pseudo-differential mode Input Voltage Range for IN- in pseudo-differential mode IN- -- VREF+IN- VSS-100 -- VSS+100 mV Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 "Maintaining Minimum Clock Speed", "Maintaining Minimum Clock Speed", for more information. (c) 2008 Microchip Technology Inc. DS21295D-page 3 MCP3004/3008 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TA = -40C to +85C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TA = +25C. Parameter Sym Min Typ Max Units -- 0.001 1 A Switch Resistance -- 1000 -- See Figure 4-1 Sample Capacitor -- 20 -- pF See Figure 4-1 -- -- V -- 0.3 VDD V V Leakage Current Conditions Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage VIH Low Level Input Voltage VIL High Level Output Voltage VOH 4.1 -- -- Low Level Output Voltage VOL -- -- 0.4 V IOL = 1 mA, VDD = 4.5V ILI -10 -- 10 A VIN = VSS or VDD Input Leakage Current Output Leakage Current 0.7 VDD IOH = -1 mA, VDD = 4.5V ILO -10 -- 10 A VOUT = VSS or VDD CIN, COUT -- -- 10 pF VDD = 5.0V (Note 1) TA = 25C, f = 1 MHz fCLK -- -- 3.6 1.35 MHz MHz VDD = 5V (Note 3) VDD = 2.7V (Note 3) Clock High Time tHI 125 -- -- ns Clock Low Time tLO 125 -- -- ns CS Fall To First Rising CLK Edge tSUCS 100 -- -- ns CS Fall To Falling CLK Edge tCSD -- -- 0 ns Data Input Setup Time tSU 50 -- -- ns Data Input Hold Time tHD 50 -- -- ns CLK Fall To Output Data Valid tDO -- -- 125 200 ns ns VDD = 5V, See Figure 1-2 VDD = 2.7V, See Figure 1-2 CLK Fall To Output Enable tEN -- -- 125 200 ns ns VDD = 5V, See Figure 1-2 VDD = 2.7V, See Figure 1-2 CS Rise To Output Disable tDIS -- -- 100 ns See Test Circuits, Figure 1-2 CS Disable Time tCSH 270 -- -- ns DOUT Rise Time tR -- -- 100 ns See Test Circuits, Figure 1-2 (Note 1) DOUT Fall Time tF -- -- 100 ns See Test Circuits, Figure 1-2 (Note 1) Pin Capacitance (All Inputs/Outputs) Timing Parameters Clock Frequency Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 "Maintaining Minimum Clock Speed", "Maintaining Minimum Clock Speed", for more information. DS21295D-page 4 (c) 2008 Microchip Technology Inc. MCP3004/3008 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TA = -40C to +85C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TA = +25C. Parameter Sym Min Typ Max Units Conditions Operating Voltage VDD 2.7 -- 5.5 V Operating Current IDD -- 425 225 550 A VDD = VREF = 5V, DOUT unloaded VDD = VREF = 2.7V, DOUT unloaded Standby Current IDDS -- 0.005 2 A CS = VDD = 5.0V Power Requirements Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 "Maintaining Minimum Clock Speed", "Maintaining Minimum Clock Speed", for more information. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 -- +85 C Operating Temperature Range TA -40 -- +85 C Storage Temperature Range TA -65 -- +150 C Thermal Resistance, 14L-PDIP JA -- 70 -- C/W Thermal Resistance, 14L-SOIC JA -- 108 -- C/W Thermal Resistance, 14L-TSSOP JA -- 100 -- C/W Thermal Resistance, 16L-PDIP JA -- 70 -- C/W Thermal Resistance, 16L-SOIC JA -- 90 -- C/W Conditions Temperature Ranges Thermal Package Resistances TCSH CS TSUCS THI TLO CLK TSU DIN THD MSB IN TEN DOUT FIGURE 1-1: TR TDO NULL BIT MSB OUT TF TDIS LSB Serial Interface Timing. (c) 2008 Microchip Technology Inc. DS21295D-page 5 MCP3004/3008 Test Point 1.4V VDD 3 k Test Point VDD/2 3 k DOUT DOUT 100 pF CL = 100 pF tEN Waveform tDIS Waveform 1 VSS Voltage Waveforms for tR, tF tDIS Waveform 2 Voltage Waveforms for tEN VOH VOL DOUT tF tR Voltage Waveforms for tDO CS 1 CLK 2 3 B9 DOUT CLK tEN tDO Voltage Waveforms for tDIS DOUT CS FIGURE 1-2: 4 Load Circuit for tR, tF, tDO. VIH DOUT Waveform 1* 90% TDIS DOUT Waveform 2 * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-3: DS21295D-page 6 10% Load circuit for tDIS and tEN. (c) 2008 Microchip Technology Inc. MCP3004/3008 2.0 TYPICAL PERFORMANCE CHARACTERISTICS The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25C. 1.0 1.0 0.8 0.6 0.4 0.4 Positive INL 0.2 INL (LSB) INL (LSB) VDD = VREF = 2.7 V 0.8 0.6 0.0 -0.2 Negative INL -0.4 Positive INL 0.2 0.0 -0.2 Negative INL -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 25 50 75 100 125 150 175 200 225 250 0 25 Sample Rate (ksps) FIGURE 2-1: vs. Sample Rate. 50 75 100 Sample Rate (ksps) Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). VDD = VREF = 2.7 V fSAMPLE = 75 ksps 0.8 0.6 INL(LSB) INL(LSB) 1.0 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 Positive INL 0.4 Positive INL 0.2 0.0 -0.2 Negative INL -0.4 Negative INL -0.6 -0.8 -1.0 0 1 2 3 4 5 0.0 6 0.5 1.0 VREF (V) FIGURE 2-2: vs. VREF. Integral Nonlinearity (INL) 2.0 2.5 3.0 FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V). 0.5 0.5 VDD = VREF = 5 V fSAMPLE = 200 ksps 0.4 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 0.4 0.3 0.3 0.2 0.2 INL (LSB) INL (LSB) 1.5 VREF (V) 0.1 0.0 -0.1 0.1 0.0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 0 128 256 384 512 640 768 896 1024 Digital Code FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). (c) 2008 Microchip Technology Inc. 0 128 256 384 512 640 768 896 1024 Digital Code FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). DS21295D-page 7 MCP3004/3008 Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25C. 0.6 0.6 0.4 0.4 INL (LSB) INL (LSB) Positive INL 0.2 0.0 -0.2 VDD = VREF = 2.7 V fSAMPLE = 75 ksps Positive INL 0.2 0.0 Negative INL -0.2 Negative INL -0.4 -0.4 -0.6 -0.6 -50 -25 0 25 50 75 -50 100 -25 0 FIGURE 2-7: vs. Temperature. 25 50 75 100 Temperature (C) Temperature (C) Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). 0.6 0.6 VDD = VREF = 2.7 V 0.4 0.2 DNL (LSB) DNL (LSB) 0.4 Positive DNL 0.0 Negative DNL -0.2 0.2 Positive DNL 0.0 Negative DNL -0.2 -0.4 -0.4 -0.6 -0.6 0 25 50 75 100 125 150 175 200 225 0 250 25 Sample Rate (ksps) FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. 0.8 0.8 0.6 0.2 0.0 Negative DNL -0.4 0.0 -0.2 -0.6 -0.8 1 2 3 4 VREF (V) FIGURE 2-9: (DNL) vs. VREF. DS21295D-page 8 Differential Nonlinearity 5 Negative DNL -0.4 -0.8 -1.0 Positive DNL 0.2 -0.6 0 100 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 0.4 Positive DNL DNL (LSB) DNL (LSB) 0.6 -0.2 75 FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). 1.0 0.4 50 Sample Rate (ksps) -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VREF(V) FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V). (c) 2008 Microchip Technology Inc. MCP3004/3008 Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25C. 1.0 1.0 VDD = VREF = 5 V fSAMPLE = 200 ksps VDD = VREF = 2.7 V fSAMPLE = 75 ksps 0.8 0.6 0.6 0.4 0.4 DNL (LSB) DNL (LSB) 0.8 0.2 0.0 -0.2 0.2 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 128 256 384 512 640 768 896 1024 0 128 256 384 Digital Code 512 640 768 896 1024 Digital Code FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD =2.7V). FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part). 0.6 0.6 0.4 0.4 VDD = VREF = 2.7 V fSAMPLE = 75 ksps DNL (LSB) DNL (LSB) Positive DNL 0.2 0.0 -0.2 0.2 Positive DNL 0.0 Negative DNL -0.2 Negative DNL -0.4 -0.4 -0.6 -0.6 -50 -25 0 25 50 75 -50 100 -25 Temperature (C) 25 50 75 100 Temperature (C) FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature. FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). 2.0 8 1.5 7 VDD = 2.7 V fSAMPLE = 75 ksps 1.0 Offset Error (LSB) Gain Error (LSB) 0 0.5 0.0 -0.5 VDD = 5 V fSAMPLE = 200 ksps -1.0 -1.5 6 VDD = 5 V fSAMPLE = 200 ksps 5 4 3 VDD = 2.7 V fSAMPLE = 75 ksps 2 1 -2.0 0 0 1 2 3 4 5 0 1 VREF(V) FIGURE 2-15: Gain Error vs. VREF. (c) 2008 Microchip Technology Inc. 2 3 4 5 VREF (V) FIGURE 2-18: Offset Error vs. VREF. DS21295D-page 9 MCP3004/3008 Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25C. 1.2 0.0 VDD = VREF = 2.7 V fSAMPLE = 75 ksps -0.2 -0.3 -0.4 VDD = VREF = 5 V fSAMPLE = 200 ksps -0.5 VDD = VREF = 5 V fSAMPLE = 200 ksps 1.0 Offset Error (LSB) Gain Error (LSB) -0.1 0.8 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 0.6 0.4 0.2 0.0 -0.6 -50 -25 0 25 50 75 -50 100 -25 0 FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Temperature. 80 50 75 100 Offset Error vs. 80 VDD = VREF = 5 V fSAMPLE = 200 ksps 70 VDD = VREF = 5 V fSAMPLE = 200 ksps 70 60 60 SINAD (dB) SNR (dB) 25 Temperature (C) Temperature (C) 50 40 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 30 50 30 20 20 10 10 0 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 40 0 1 10 100 1 10 FIGURE 2-20: Input Frequency. 100 Input Frequency (kHz) Input Frequency (kHz) Signal-to-Noise (SNR) vs. FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency. 0 70 -10 60 THD (dB) -30 SINAD (dB) -20 VDD = VREF = 2.7 V fSAMPLE = 75 ksps -40 -50 -60 -70 -80 VDD = VREF = 5 V fSAMPLE = 200 ksps -90 VDD = VREF = 5 V fSAMPLE = 200 ksps 50 40 30 20 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 10 0 -100 1 10 100 Input Frequency (kHz) FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. DS21295D-page 10 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Signal Level (dB) FIGURE 2-24: Signal-to-Noise and Distortion (SINAD) vs. Input Signal Level. (c) 2008 Microchip Technology Inc. MCP3004/3008 Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25C. 10.00 10.0 9.8 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 9.50 9.25 VDD = VREF = 5 V fSAMPLE = 200 ksps 9.00 0.0 0.5 1.0 1.5 2.0 2.5 VDD = VREF = 5V fSAMPLE = 200 ksps ENOB (rms) ENOB (rms) 9.75 3.0 3.5 4.0 4.5 5.0 VDD = VREF = 2.7V fSAMPLE = 75 ksps 1 10 Input Frequency (kHz) VREF (V) FIGURE 2-25: (ENOB) vs. VREF. Effective Number of Bits VDD = VREF = 5 V fSAMPLE = 200 ksps 90 SFDR (dB) 80 70 60 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 50 40 FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. Power Supply Rejection (dB) 100 30 20 10 0 1 10 0 VDD = VREF = 5 V fSAMPLE = 200 ksps -10 -20 -30 -40 -50 -60 -70 1 100 10 VDD = VREF = 5 V FSAMPLE = 200 ksps FINPUT = 10.0097 kHz 4096 points 20000 40000 60000 80000 100000 Frequency (Hz) FIGURE 2-27: Frequency Spectrum of 10 kHz Input (Representative Part). (c) 2008 Microchip Technology Inc. 1000 10000 FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 VDD = VREF = 2.7 V fSAMPLE = 75 ksps fINPUT = 1.00708 kHz 4096 points Amplitude (dB) Amplitude (dB) FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. 0 100 Ripple Frequency (kHz) Input Frequency (kHz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 100 0 5000 10000 15000 20000 25000 30000 35000 Frequency (Hz) FIGURE 2-30: Frequency Spectrum of 1 kHz Input (Representative Part, VDD = 2.7V). DS21295D-page 11 MCP3004/3008 550 550 500 500 450 450 400 400 350 350 IDD (A) IDD (A) Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25C. 300 250 200 VREF = VDD All points at fCLK = 3.6 MHz except at VREF = VDD = 2.5 V, fCLK = 1.35 MHz 150 100 50 300 250 200 150 VREF = VDD All points at fCLK = 3.6 MHz except at VREF = VDD = 2.5 V, fCLK = 1.35 MHz 100 50 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 6.0 2.5 3.0 3.5 FIGURE 2-31: FIGURE 2-34: IDD vs. VDD. 500 450 400 IREF (A) IDD (A) 350 300 VDD = VREF = 5 V 250 200 VDD = VREF = 2.7 V 150 100 50 0 10 100 1000 120 110 100 90 80 70 60 50 40 30 20 10 0 4.5 5.0 5.5 6.0 VDD = VREF = 2.7 V 10 10000 IREF vs. VDD. VDD = VREF = 5 V 100 1000 10000 Clock Frequency (kHz) Clock Frequency (kHz) FIGURE 2-32: 4.0 VDD (V) VDD (V) IDD vs. Clock Frequency. FIGURE 2-35: IREF vs. Clock Frequency. 550 500 VDD = VREF = 5 V fCLK = 3.6 MHz 450 140 IREF (A) IDD (A) 350 300 250 200 150 50 100 80 60 40 VDD = VREF = 2.7 V fCLK = 1.35 MHz 100 VDD = VREF = 5 V fCLK = 3.6 MHz 120 400 VDD = VREF = 2.7 V fCLK = 1.35 MHz 20 0 0 -50 -25 0 25 50 75 100 -50 -25 Temperature (C) FIGURE 2-33: DS21295D-page 12 IDD vs. Temperature. 0 25 50 75 100 Temperature (C) FIGURE 2-36: IREF vs. Temperature. (c) 2008 Microchip Technology Inc. MCP3004/3008 Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25C. 2.0 70 Analog Input Leakage (nA) VREF = CS = VDD 60 IDDS (pA) 50 40 30 20 10 0 1.8 VDD = VREF = 5 V 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 2-37: -50 -25 0 25 50 75 100 Temperature (C) FIGURE 2-39: Analog Input Leakage Current vs. Temperature. IDDS vs. VDD. 100.00 VDD = VREF = CS = 5 V IDDS (nA) 10.00 1.00 0.10 0.01 -50 -25 0 25 50 75 100 Temperature (C) FIGURE 2-38: IDDS vs. Temperature. (c) 2008 Microchip Technology Inc. DS21295D-page 13 MCP3004/3008 NOTES: DS21295D-page 14 (c) 2008 Microchip Technology Inc. MCP3004/3008 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows. TABLE 3-1: PIN FUNCTION TABLE MCP3004 MCP3008 PDIP, SOIC, TSSOP PDIP, SOIC 1 1 CH0 Analog Input 2 2 CH1 Analog Input 3 3 CH2 Analog Input 4 4 CH3 Analog Input - 5 CH4 Analog Input - 6 CH5 Analog Input - 7 CH6 Analog Input - 8 CH7 Analog Input 3.1 Symbol 7 9 DGND 8 10 CS/SHDN 9 11 DIN 10 12 DOUT Serial Data In Serial Data Out 13 CLK 14 AGND 13 15 VREF Reference Voltage Input 14 16 VDD +2.7V to 5.5V Power Supply 5,6 - NC No Connection Digital Ground (DGND) Serial Clock Analog Ground 3.5 Serial Data Input (DIN) The SPI port serial data input pin is used to load channel configuration data into the device. Analog Ground (AGND) Analog inputs (CH0 - CH7) Analog inputs for channels 0 - 7, respectively, for the multiplexed inputs. Each pair of channels can be programmed to be used as two independent channels in single-ended mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN. See Section 4.1 "Analog Inputs", "Analog Inputs", and Section 5.0 "Serial Communication", "Serial Communication", for information on programming the channel configuration. 3.4 Chip Select/Shutdown Input 11 Analog ground connection to internal analog circuitry. 3.3 Digital Ground 12 Digital ground connection to internal digital circuitry. 3.2 Description 3.6 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. 3.7 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low. When pulled high, it will end a conversion and put the device in low-power standby. The CS/SHDN pin must be pulled high between conversions. Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and clock out each bit of the conversion as it takes place. See Section 6.2 "Maintaining Minimum Clock Speed", "Maintaining Minimum Clock Speed", for constraints on clock speed. (c) 2008 Microchip Technology Inc. DS21295D-page 15 MCP3004/3008 NOTES: DS21295D-page 16 (c) 2008 Microchip Technology Inc. MCP3004/3008 4.0 DEVICE OPERATION The MCP3004/3008 A/D converters employ a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock once CS has been pulled low. Following this sample time, the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3004/3008. See Section 6.2 "Maintaining Minimum Clock Speed", "Maintaining Minimum Clock Speed", for information on minimum clock rates. Communication with the device is accomplished using a 4-wire SPI-compatible interface. 4.2 Reference Input For each device in the family, the reference input (VREF) determines the analog input voltage range. As the reference input is reduced, the LSB size is reduced accordingly. EQUATION 4-1: V REF LSB Size = -----------1024 The theoretical digital output code produced by the A/D converter is a function of the analog input signal and the reference input, as shown below. EQUATION 4-2: 4.1 Analog Inputs The MCP3004/3008 devices offer the choice of using the analog input channels configured as single-ended inputs or pseudo-differential pairs. The MCP3004 can be configured to provide two pseudo-differential input pairs or four single-ended inputs. The MCP3008 can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is done as part of the serial command before each conversion begins. When used in the pseudodifferential mode, each channel pair (i.e., CH0 and CH1, CH2 and CH3 etc.) are programmed as the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to (VREF + IN-). The IN- input is limited to 100 mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise, which is present on both the IN+ and IN- inputs. LSB SIZE CALCULATION DIGITAL OUTPUT CODE CALCULATION 1024 x V IN Digital Output Code = -------------------------V REF Where: VIN = analog input voltage VREF = analog input voltage When using an external voltage reference device, the system designer should always refer to the manufacturer's recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the operation of the A/D converter. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be 3FFh. If the voltage level at INis more than 1 LSB below VSS, the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, the 3FFh code will not be seen unless the IN+ input level goes above VREF level. For the A/D converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 10-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. This diagram illustrates that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, larger source impedances increase the offset, gain and integral linearity errors of the conversion (see Figure 4-2). (c) 2008 Microchip Technology Inc. DS21295D-page 17 MCP3004/3008 VDD RSS Sampling Switch VT = 0.6V CHx CPIN 7 pF VA VT = 0.6V SS ILEAKAGE 1 nA RS = 1 k CSAMPLE = DAC capacitance = 20 pF VSS Legend VA = Signal Source ILEAKAGE = Leakage Current At The Pin Due To Various Junctions RSS = Source Impedance SS = sampling switch CHx = Input Channel Pad RS = sampling switch resistor CPIN = Input Pin Capacitance VT = Threshold Voltage FIGURE 4-1: CSAMPLE = sample/hold capacitance Analog Input Model. Clock Frequency (Mhz) 4 VDD = VREF = 5 V fSAMPLE = 200 ksps 3 2 1 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 0 100 1000 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. DS21295D-page 18 (c) 2008 Microchip Technology Inc. MCP3004/3008 5.0 SERIAL COMMUNICATION Communication with the MCP3004/3008 devices is accomplished using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 5-1). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single-ended or differential input mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 5-1 and Table 5-2 show the configuration bits for the MCP3004 and MCP3008, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. Once the D0 bit is input, one more clock is required to complete the sample and hold period (DIN is a "don't care" for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 10 clocks will output the result of the conversion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 10 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as is shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 "Using the MCP3004/3008 with Microcontroller (MCU) SPI Ports", "Using the MCP3004/ 3008 with Microcontroller (MCU) SPI Ports", for more details on using the MCP3004/3008 devices with hardware SPI ports. (c) 2008 Microchip Technology Inc. TABLE 5-1: CONFIGURE BITS FOR THE MCP3004 Control Bit Selections Input Configuration Single/ D2* D1 D0 Diff Channel Selection 1 X 0 0 single-ended CH0 1 X 0 1 single-ended CH1 1 X 1 0 single-ended CH2 1 X 1 1 single-ended CH3 0 X 0 0 differential CH0 = IN+ CH1 = IN- 0 X 0 1 differential CH0 = INCH1 = IN+ 0 X 1 0 differential CH2 = IN+ CH3 = IN- 0 X 1 1 differential CH2 = INCH3 = IN+ * D2 is "don't care" for MCP3004 TABLE 5-2: CONFIGURE BITS FOR THE MCP3008 Control Bit Selections Input Configuration Channel Selection 0 single-ended CH0 1 single-ended CH1 1 0 single-ended CH2 1 1 single-ended CH3 1 0 0 single-ended CH4 1 1 0 1 single-ended CH5 1 1 1 0 single-ended CH6 1 1 1 1 single-ended CH7 0 0 0 0 differential CH0 = IN+ CH1 = IN- 0 0 0 1 differential CH0 = INCH1 = IN+ 0 0 1 0 differential CH2 = IN+ CH3 = IN- 0 0 1 1 differential CH2 = INCH3 = IN+ 0 1 0 0 differential CH4 = IN+ CH5 = IN- 0 1 0 1 differential CH4 = INCH5 = IN+ 0 1 1 0 differential CH6 = IN+ CH7 = IN- 0 1 1 1 differential CH6 = INCH7 = IN+ Single /Diff D2 1 0 0 1 0 0 1 0 1 0 1 D1 D0 DS21295D-page 19 MCP3004/3008 tCYC tCYC tCSH CS tSUCS CLK DIN DOUT Start D2 D1 D0 SGL/ DIFF HI-Z Null Bit B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 * tCONV tSAMPLE D2 Start Don't Care SGL/ DIFF HI-Z tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB first data, then followed with zeros indefinitely. See Figure 5-2 below. ** tDATA: during this time, the bias current and the comparator powers down while the reference input becomes a high-impedance node. FIGURE 5-1: Communication with the MCP3004 or MCP3008. tCYC CS tCSH tSUCS Power Down CLK DIN DOUT Start Don't Care D2 D1 D0 SGL/ DIFF HI-Z Null B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9* Bit HI-Z (MSB) tSAMPLE tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator powers down while the reference input becomes a high-impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: DS21295D-page 20 Communication with MCP3004 or MCP3008 in LSB First Format. (c) 2008 Microchip Technology Inc. MCP3004/3008 6.0 APPLICATIONS INFORMATION 6.1 Using the MCP3004/3008 with Microcontroller (MCU) SPI Ports As is shown in Figure 6-1, the first byte transmitted to the A/D converter contains seven leading zeros before the start bit. Arranging the leading zeros this way induces the 10 data bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D converter on the falling edge of clock number 14. Once the second eight clocks have been sent to the device, the MCU receive buffer will contain five unknown bits (the output is at high-impedance for the first two clocks), the null bit and the highest order 2 bits of the conversion. Once the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Employing this method ensures simpler manipulation of the converted data. With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3004/3008 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending `leading zeros' before the start bit. As an example, Figure 6-1 and Figure 6-2 shows how the MCP3004/ 3008 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the `low' state, while Figure 6-2 shows the similar case of SPI Mode 1,1, where the clock idles in the `high' state. CS SCLK Figure 6-2 shows the same thing in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D converter outputs data on the falling edge of the clock and the MCU latches data from the A/D converter in on the rising edge of the clock. MCU latches data from A/D converter on rising edges of SCLK 1 2 3 4 5 6 DIN MCU Transmitted Data (Aligned with falling 0 edge of clock) X = "Don't Care" Bits 8 9 10 11 12 13 14 15 16 17 0 ? 0 NULL BIT B9 B8 ? 0 ? 0 ? 0 ? 0 ? Start Bit 1 ? Data stored into MCU receive register after transmission of first 8 bits SGL/ DIFF D2 D1 DO X ? ? ? 18 19 20 21 22 23 24 Don't Care HI-Z DOUT MCU Received Data (Aligned with rising ? edge of clock) 7 Data is clocked out of A/D converter on falling edges SGL/ D2 D1 DO Start DIFF ? X X B7 X 0 B9 B8 ? (Null) Data stored into MCU receive register after transmission of second 8 bits B6 B5 B4 B3 B2 B1 B0 X X X X X X X X B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of last 8 bits FIGURE 6-1: SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 0,0: SCLK idles low). (c) 2008 Microchip Technology Inc. DS21295D-page 21 MCP3004/3008 MCU latches data from A/D converter on rising edges of SCLK CS 1 SCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D converter on falling edges DIN Start Don't Care NULL BIT B9 HI-Z DOUT Start Bit MCU Transmitted Data (Aligned with falling 0 edge of clock) MCU Received Data (Aligned with rising edge of clock) X = "Don't Care" Bits FIGURE 6-2: 6.2 SGL/ D2 D1 DO DIFF 0 ? 0 ? 0 ? 0 ? 0 ? ? SGL/ DIFF D2 1 0 ? ? ? Data stored into MCU receive register after transmission of first 8 bits ? D1 DO X ? ? X ? B8 X X Maintaining Minimum Clock Speed 0 (Null) B9 B8 X X X X X X X B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of last 8 bits Data stored into MCU receive register after transmission of second 8 bits Low-pass (anti-aliasing) filters can be designed using Microchip's free interactive FilterLab(R) software. FilterLab will calculate capacitor and resistors values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see AN699, "Anti-Aliasing Analog Filters for Data Acquisition Systems". VDD If the signal source for the A/D converter is not a lowimpedance source, it will have to be buffered or inaccurate conversion results may occur (see Figure 42). It is also recommended that a filter be used to eliminate any signals that may be aliased back in to the conversion results, as is illustrated in Figure 6-3, where an op amp is used to drive, filter and gain the analog input of the MCP3004/3008. This amplifier provides a low-impedance source for the converter input, plus a low-pass filter, which eliminates unwanted highfrequency noise. 10 F 4.096V Reference 0.1 F MCP1541 1 F 1 F VIN R1 C1 R2 C2 Buffering/Filtering the Analog Inputs DS21295D-page 22 X SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 1,1: SCLK idles high). When the MCP3004/3008 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 10 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz). Failure to meet this criterion may introduce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. 6.3 B6 B5 B4 B3 B2 B1 B0 B7 MCP601 IN+ V REF MCP3004 IN- + - R R3 4 FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing filter for the signal being converted by the MCP3004. (c) 2008 Microchip Technology Inc. MCP3004/3008 6.4 Layout Considerations When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1 F is recommended. Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or bypass capacitor. Extra precautions should be taken to keep traces with highfrequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating return current paths and associated errors (see Figure 6-4). For more information on layout tips when using A/D converters, refer to AN688, "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection VDD MCP3004/08 Digital Side Analog Side -SPI Interface -Shift Register -Control Logic -Sample Cap -Capacitor Array -Comparator Substrate 5 - 10 DGND AGND 0.1 F Device 4 Device 1 If no ground plane is utilized, both grounds must be connected to VSS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D converter. Analog Ground Plane FIGURE 6-5: Separation of Analog and Digital Ground Pins. Device 3 Device 2 FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths. 6.5 Utilizing the Digital and Analog Ground Pins The MCP3004/3008 devices provide both digital and analog ground connections to provide additional means of noise reduction. As is shown in Figure 6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate which has a resistance of 5 -10. (c) 2008 Microchip Technology Inc. DS21295D-page 23 MCP3004/3008 NOTES: DS21295D-page 24 (c) 2008 Microchip Technology Inc. MCP3004/3008 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 14-Lead PDIP (300 mil) Example: MCP3004 I/P e3 XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) 0819256 Example: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4mm) * MCP3004 3 ISL e^^ XXXXXXXXXXX 0819256 Example: XXXXXXXX 3004 YYWW I819 NNN 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2008 Microchip Technology Inc. DS21295D-page 25 MCP3004/3008 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3008) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 16-Lead SOIC (150 mil) (MCP3008) XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN DS21295D-page 26 MCP3008-I/P e3 0819256 Example: MCP3008 3 I/SL e^^ XXXXXXXXXX 0819256 (c) 2008 Microchip Technology Inc. MCP3004/3008 3 % & %! % 4" ) ' % 4 $% %"% %% 255)))& &5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 6% & 9&% 7!&( $ 7+8- 7 7 % ; % % 7: 1+ < < 0 , 0 1 % % 0 < < - , ,0 ""4 !" % 4 !" ="% ""4="% - 0 > : 9% ,0 0 0 0 % % 9 0 , 4 > 0 9"="% ( 0 ? ( > 1 < < , 9" 6 9 ) 9"="% : ) * !"#$%! & '(!%&! %( %")% % % " *$%+ % % , & "-" %!"& "$ % ! "$ % ! & "% -/0 1+21 & %#%! ))% !%% %#". " (c) 2008 Microchip Technology Inc. ) +01 DS21295D-page 27 MCP3004/3008 ! " ! ##$% &' !"( 3 % & %! % 4" ) ' % 4 $% %"% %% 255)))& &5 4 D N E E1 NOTE 1 1 2 3 e h b A2 A h c L A1 L1 6% & 9&% 7!&( $ 99- - 7 7 7: ; % : 8 % < < 0 < < < 0 ""4 4 %" $$* 1+ : ="% - ""4="% - ,1+ : 9% >?01+ + &$ @ 3 % A %9% 9 3 % % 9 3 % 0 ?1+ 0 < 0 < -3 I B < >B < 0 9"="% ( , < 0 " $% D 0B < 0B " $%1 %% & E 0B < 9" 4 0B !"#$%! & '(!%&! %( %")% % % " *$%+ % % , & "-" %!"& "$ % ! "$ % ! %#"0&& " & "% -/0 1+2 1 & %#%! ))% !%% -32 $ & '! !)% !%% '$ $ &% ! DS21295D-page 28 ) +?01 (c) 2008 Microchip Technology Inc. MCP3004/3008 ) ! " ! ##$% &' !"( 3 % & %! % 4" ) ' % 4 $% %"% %% 255)))& &5 4 (c) 2008 Microchip Technology Inc. DS21295D-page 29 MCP3004/3008 *+ !+#, ! " !* & *!!" 3 % & %! % 4" ) ' % 4 $% %"% %% 255)))& &5 4 D N E E1 NOTE 1 1 2 e b A2 A c A1 L L1 6% & 9&% 7!&( $ 99- - 7 7 7: ; % : 8 % < < > 0 0 < 0 ""4 4 %" $$ ?01+ : ="% - ""4="% - , ""49% 0 0 3 %9% 9 0 ? 0 3 % % 9 3 % 9" 4 ?1+ 0 -3 I B < >B < 9"="% ( < , !"#$%! & '(!%&! %( %")% % % " & "-" %!"& "$ % ! "$ % ! %#"0&& " , & "% -/0 1+2 1 & %#%! ))% !%% -32 $ & '! !)% !%% '$ $ &% ! DS21295D-page 30 ) +>1 (c) 2008 Microchip Technology Inc. MCP3004/3008 - 3 % & %! % 4" ) ' % 4 $% %"% %% 255)))& &5 4 N NOTE 1 E1 1 2 3 D E A A2 L A1 c b1 e b eB 6% & 9&% 7!&( $ 7+8- 7 7 % ; ? % % 7: 1+ < < 0 , 0 1 % % 0 < < - , ,0 ""4 !" % 4 !" ="% ""4="% - 0 > : 9% ,0 00 0 0 % % 9 0 , 4 > 0 9"="% ( 0 ? ( > 1 < < , 9" 6 9 ) 9"="% : ) * !"#$%! & '(!%&! %( %")% % % " *$%+ % % , & "-" %!"& "$ % ! "$ % ! & "% -/0 1+2 1 & %#%! ))% !%% %#". " (c) 2008 Microchip Technology Inc. ) +1 DS21295D-page 31 MCP3004/3008 - ! " ! ##$% &' !"( 3 % & %! % 4" ) ' % 4 $% %"% %% 255)))& &5 4 D N E E1 NOTE 1 1 3 2 e b h h c A2 A L A1 L1 6% & 9&% 7!&( $ 99- - 7 7 7: ; ? % : 8 % < < 0 < < < 0 ""4 4 %" $$* 1+ : ="% - ""4="% - ,1+ : 9% 1+ + &$ @ 3 % A %9% 9 3 % % 9 3 % 0 ?1+ 0 < 0 < -3 I B < >B < 0 9"="% ( , < 0 " $% D 0B < 0B " $%1 %% & E 0B < 9" 4 0B !"#$%! & '(!%&! %( %")% % % " *$%+ % % , & "-" %!"& "$ % ! "$ % ! %#"0&& " & "% -/0 1+2 1 & %#%! ))% !%% -32 $ & '! !)% !%% '$ $ &% ! DS21295D-page 32 ) +>1 (c) 2008 Microchip Technology Inc. MCP3004/3008 3 % & %! % 4" ) ' % 4 $% %"% %% 255)))& &5 4 (c) 2008 Microchip Technology Inc. DS21295D-page 33 MCP3004/3008 NOTES: DS21295D-page 34 (c) 2008 Microchip Technology Inc. MCP3004/3008 APPENDIX A: REVISION HISTORY Revision D (December 2008) The following is the list of modifications: 1. Updates to Section 7.0 "Packaging Information". Revision C (January 2007) The following is the list of modifications: 1. Updates to the packaging diagrams. Revision B (May 2002) The following is the list of modifications: 1. Undocumented changes. Revision A (February 2000) * Initial release of this document. (c) 2008 Microchip Technology Inc. DS21295D-page 35 MCP3004/3008 NOTES: DS21295D-page 36 (c) 2008 Microchip Technology Inc. MCP3004/3008 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device Examples: a) b) MCP3004: 4-Channel 10-Bit Serial A/D Converter MCP3004T: 4-Channel 10-Bit Serial A/D Converter (Tape and Reel) MCP3008: 8-Channel 10-Bit Serial A/D Converter MCP3008T: 8-Channel 10-Bit Serial A/D Converter (Tape and Reel) c) d) a) Temperature Range I Package P SL ST = -40C to +85C (Industrial) b) MCP3004-I/P: Industrial Temperature, PDIP package. MCP3004-I/SL: Industrial Temperature, SOIC package. MCP3004-I/ST: Industrial Temperature, TSSOP package. MCP3004T-I/ST: Industrial Temperature, TSSOP package, Tape and Reel. MCP3008-I/P: Industrial Temperature, PDIP package. MCP3008-I/SL: Industrial Temperature, SOIC package. = Plastic DIP (300 mil Body), 14-lead, 16-lead = Plastic SOIC (150 mil Body), 14-lead, 16-lead = Plastic TSSOP (4.4mm), 14-lead (c) 2008 Microchip Technology Inc. DS21295D-page 37 MCP3004/3008 NOTES: DS21295D-page 38 (c) 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2008 Microchip Technology Inc. DS21295D-page 39 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 01/02/08 DS21295D-page 40 (c) 2008 Microchip Technology Inc.