STM32F103x4 STM32F103x6 Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces Features ARM 32-bit CortexTM-M3 CPU Core - 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access - Single-cycle multiplication and hardware division Memories - 16 or 32 Kbytes of Flash memory - 6 or 10 Kbytes of SRAM Clock, reset and supply management - 2.0 to 3.6 V application supply and I/Os - POR, PDR, and programmable voltage detector (PVD) - 4-to-16 MHz crystal oscillator - Internal 8 MHz factory-trimmed RC - Internal 40 kHz RC - PLL for CPU clock - 32 kHz oscillator for RTC with calibration Low power - Sleep, Stop and Standby modes - VBAT supply for RTC and backup registers 2 x 12-bit, 1 s A/D converters (up to 16 channels) - Conversion range: 0 to 3.6 V - Dual-sample and hold capability - Temperature sensor DMA - 7-channel DMA controller - Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs Up to 51 fast I/O ports - 26/37/51 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant April 2011 TFBGA64 (5 x 5 mm LQFP64 (10 x 10 mm) LQFP48 (7 x 7 mm) VFQFPN48 (7 x 7 mm) VFQFPN36 (6 x 6 mm) Debug mode - Serial wire debug (SWD) & JTAG interfaces 6 timers - Two 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 16-bit, motor control PWM timer with deadtime generation and emergency stop - 2 watchdog timers (Independent and Window) - SysTick timer 24-bit downcounter 6 communication interfaces - 21 x I2C interface (SMBus/PMBus) - 2 x USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - 1 x SPI (18 Mbit/s) - CAN interface (2.0B Active) - USB 2.0 full-speed interface CRC calculation unit, 96-bit unique ID Packages are ECOPACK(R) Table 1. Device summary Reference Part number STM32F103x4 STM32F103C4, STM32F103R4, STM32F103T4 STM32F103x6 STM32F103C6, STM32F103R6, STM32F103T6 Doc ID 15060 Rev 5 1/87 www.st.com 1 Contents STM32F103x4, STM32F103x6 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 ARM(R) CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . . 14 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17 2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.16 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) . . 19 2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.24 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 6 Contents Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 33 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 33 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 54 5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.17 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 82 Doc ID 15060 Rev 5 3/87 Contents STM32F103x4, STM32F103x6 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F103xx low-density device features and peripheral counts. . . . . . . . . . . . . . . . . . . 10 STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Low-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 34 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 38 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 39 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Doc ID 15060 Rev 5 5/87 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. 6/87 STM32F103x4, STM32F103x6 USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 75 VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 76 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . 77 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 78 LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 80 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F103xx performance line VFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F103xx performance line VFQFPN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 37 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 37 Typical current consumption on VBAT with RTC on versus temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 72 Power supply and reference decoupling(VREF+ connected to VDDA) . . . . . . . . . . . . . . . . . 73 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Recommended footprint (dimensions in mm)(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 VFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Recommended footprint (dimensions in mm)(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 77 Doc ID 15060 Rev 5 7/87 List of figures Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 8/87 STM32F103x4, STM32F103x6 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 78 Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 79 LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 80 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x4 and STM32F103x6 low-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The low-density STM32F103xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 2 Description The STM32F103x4 and STM32F103x6 performance line family incorporates the highperformance ARM CortexTM-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 32 Kbytes and SRAM up to 6 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN. The STM32F103xx low-density performance line family operates from a 2.0 to 3.6 V power supply. It is available in both the -40 to +85 C temperature range and the -40 to +105 C extended temperature range. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx low-density performance line family includes devices in four different package types: from 36 pins to 64 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx low-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs. Doc ID 15060 Rev 5 9/87 Description 2.1 STM32F103x4, STM32F103x6 Device overview Table 2. STM32F103xx low-density device features and peripheral counts Peripheral STM32F103Cx STM32F103Rx Flash - Kbytes 16 32 16 32 16 32 SRAM - Kbytes 6 10 6 10 6 10 2 2 2 2 2 2 Communication Timers STM32F103Tx General-purpose Advanced-control 1 1 SPI 1 1 1 1 1 1 I2C 1 1 1 1 1 1 USART 2 2 2 2 2 2 USB 1 1 1 1 1 1 CAN 1 1 1 1 1 1 GPIOs 12-bit synchronized ADC Number of channels 26 37 51 2 10 channels 2 10 channels 2 16 channels CPU frequency 72 MHz Operating voltage Operating temperatures Packages 10/87 1 2.0 to 3.6 V Ambient temperatures: -40 to +85 C /-40 to +105 C (see Table 9) Junction temperature: -40 to + 125 C (see Table 9) VFQFPN36 Doc ID 15060 Rev 5 LQFP48, VFQFPN48 LQFP64, TFBGA64 STM32F103x4, STM32F103x6 STM32F103xx performance line block diagram TPIU Trace Controlle r pbu s Trace/trig SW/JTAG Ibus Cortex-M3 CPU Fmax : 7 2M Hz Dbus Syst em NVIC AHB:F max =48/72 MHz @VDDA SUPPLY SUPERVISION NRST VDDA VSSA Rst PVD Int @VDD PLL & CLOCK MANAGT XTAL OSC 4-16 MHz AHB2 APB2 GPIOA GPIOB PC[15:0] GPIOC PD[2:0] GPIOD 4 Chann els 3 co mpl. channels ETR and BKIN IWDG Stand by in terface @VDDA VBAT @VBAT AHB2 APB 1 RTC AWU Back up reg OSC32_IN OSC32_OUT TAMPER-RTC Backu p i nterf ace TIM1 MOSI,MISO, SCK,NSS as AF OSC_IN OSC_OUT RC 8 MHz RC 40 kHz EXTI WAKEUP PA[ 15:0] SPI USART1 @VDDA 16 AF VREF+ PCLK1 PCLK2 HCLK FCLK VDD = 2 to 3.6V VSS @VDD 64 bit XTAL 32 kHz PB[ 15:0] RX,TX, CTS, RTS, Smart Card as AF Flash 32 KB APB2 : F max =48 / 72 MHz 51AF POR / PDR VOLT. REG. 3.3V TO 1.8V SRAM 10 KB GP DMA 7 ch annels POWER 12bit ADC1 IF APB1 : Fmax =24 / 36 MHz NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF Flash obl interface TRACECLK TRACED[0:3] as AS BusM atrix Figure 1. Description TIM2 4 Chann els TIM3 4 Chann els USART2 I2C bx CAN USB 2.0 FS RX,TX, CTS, RTS, CK, SmartCard as AF SCL,SDA,SMBA as AF USBDP/CAN_TX USBDM/CAN_RX SRAM 512B WWDG 12bi t ADC2 IF Temp sensor ai15175c 1. TA = -40 C to +105 C (junction temperature up to 125 C). 2. AF = alternate function on I/O port pin. Doc ID 15060 Rev 5 11/87 Description STM32F103x4, STM32F103x6 Figure 2. Clock tree 8 MHz HSI RC HSI USB Prescaler /1, 1.5 /2 USBCLK to USB interface 48 MHz HCLK to AHB bus, core, memory and DMA 72 MHz max PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 72 MHz /1, 2..512 max PLLCLK Clock Enable (3 bits) APB1 Prescaler /1, 2, 4, 8, 16 to Cortex System timer FCLK Cortex free running clock 36 MHz max PCLK1 to APB1 peripherals Peripheral Clock HSE Enable (13 bits) TIM2, TIM3 to TIM2, TIM3 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock CSS Enable (3 bits) APB2 Prescaler /1, 2, 4, 8, 16 PLLXTPRE OSC_OUT OSC_IN 4-16 MHz 72 MHz max HSE OSC /2 Peripheral Clock Enable (11 bits) TIM1 timer to TIM1 If (APB2 prescaler =1) x1 TIM1CLK else x2 Peripheral Clock /128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz PCLK2 to APB2 peripherals to RTC LSE RTCCLK ADC Prescaler /2, 4, 6, 8 Enable (1 bit) to ADC ADCCLK RTCSEL[1:0] LSI RC 40 kHz to Independent Watchdog (IWDG) LSI IWDGCLK Main Clock Output /2 MCO PLLCLK HSI Legend: HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal HSE SYSCLK MCO ai15176 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with USBCLK running at 48 MHz. 3. To have an ADC conversion time of 1 s, APB2 must be at 14 MHz, 28 MHz or 56 MHz. 12/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 2.2 Description Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low- and high-density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with the other members of the STM32F103xx family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F103xx family Low-density devices Pinout 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash High-density devices 256 KB Flash 384 KB Flash 512 KB Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM 144 100 64 48 36 2 x USARTs 2 x 16-bit timers 1 x SPI, 1 x I2C, USB, CAN, 1 x PWM timer 2 x ADCs 3 x USARTs 3 x 16-bit timers 2 x SPIs, 2 x I2Cs, USB, CAN, 1 x PWM timer 2 x ADCs 5 x USARTs 4 x 16-bit timers, 2 x basic timers 3 x SPIs, 2 x I2Ss, 2 x I2Cs USB, CAN, 2 x PWM timers 3 x ADCs, 2 x DACs, 1 x SDIO FSMC (100 and 144 pins) 1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices. Doc ID 15060 Rev 5 13/87 Description STM32F103x4, STM32F103x6 2.3 Overview 2.3.1 ARM(R) CortexTM-M3 core with embedded Flash and SRAM The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F103xx performance line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory 16 or 32 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM Six or ten Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 Nested vectored interrupt controller (NVIC) The STM32F103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels. 14/87 Closely coupled NVIC gives low-latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Description This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected to the 16 external interrupt lines. 2.3.7 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed APB domain is 36 MHz. See Figure 2 for details on the clock tree. 2.3.8 Boot modes At startup, boot pins are used to select one of three boot options: Boot from User Flash Boot from System Memory Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. 2.3.9 Power supply schemes VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 11: Power supply scheme. 2.3.10 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains Doc ID 15060 Rev 5 15/87 Description STM32F103x4, STM32F103x6 in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 11: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 2.3.11 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. 2.3.12 Low-power modes The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup. Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: 16/87 The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 2.3.13 Description DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and advanced-control timers TIMx and ADC. 2.3.14 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long-term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.15 Timers and watchdogs The low-density STM32F101xx performance line devices include an advanced-control timer, two general-purpose timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the advanced-control and general-purpose timers. Table 4. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM1 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 Yes TIM2, TIM3 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No Doc ID 15060 Rev 5 17/87 Description STM32F103x4, STM32F103x6 Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for Input capture Output compare PWM generation (edge- or center-aligned modes) One-pulse mode output If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIMx) There are up to two synchronizable general-purpose timers embedded in the STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 18/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Description SysTick timer This timer is dedicated for OS, but could also be used as a standard downcounter. It features: 2.3.16 A 24-bit downcounter Autoreload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source IC bus The IC bus interface can operate in multimaster and slave modes. It can support standard and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. It can be served by DMA and they support SM Bus 2.0/PM Bus. 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The other available interface communicates at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816 compliant and have LIN Master/Slave capability. All USART interfaces can be served by the DMA controller. 2.3.18 Serial peripheral interface (SPI) The SPI interface is able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPI interface can be served by the DMA controller. 2.3.19 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. 2.3.20 Universal serial bus (USB) The STM32F103xx performance line embeds a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). Doc ID 15060 Rev 5 19/87 Description 2.3.21 STM32F103x4, STM32F103x6 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed 2.3.22 ADC (analog-to-digital converter) Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: Simultaneous sample and hold Interleaved sample and hold Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers. 2.3.23 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC12_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.24 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 20/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Pinouts and pin description STM32F103xx performance line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 3. VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 3 Pinouts and pin description ai14392 Doc ID 15060 Rev 5 21/87 Pinouts and pin description Figure 4. STM32F103x4, STM32F103x6 STM32F103xx performance line TFBGA64 ballout 1 A 2 PC14PC13OSC32_IN TAMPER-RTC 3 4 5 6 7 8 PB9 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PB8 BOOT0 PD2 PC11 PC10 PA12 C OSC_IN VSS_4 PB7 PB5 PC12 PA10 PA9 PA11 D OSC_OUT VDD_4 PB6 VSS_3 VSS_2 VSS_1 PA8 PC9 E NRST PC1 PC0 VDD_3 VDD_2 VDD_1 PC7 PC8 F VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14 G VREF+ PA0-WKUP PA3 PA6 PB1 PB2 PB10 PB13 H VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12 AI15494 22/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 STM32F103xx performance line LQFP48 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 5. Pinouts and pin description 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 ai14393b VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 STM32F103xx performance line VFQFPN48 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 3 34 4 33 5 32 6 VFQFPN48 7 31 30 8 29 9 28 10 27 11 26 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 Figure 6. ai18300 Doc ID 15060 Rev 5 23/87 Pinouts and pin description PB7 PB6 PB5 PB4 PB3 PA15 PA14 36 BOOT0 STM32F103xx performance line VFQFPN36 pinout VSS_3 Figure 7. STM32F103x4, STM32F103x6 35 34 33 32 31 30 29 28 VDD_3 1 27 VDD_2 OSC_IN/PD0 2 26 VSS_2 OSC_OUT/PD1 3 25 PA13 NRST 4 24 PA12 23 PA11 VSSA 5 VDDA 6 22 PA10 PA0-WKUP 7 21 PA9 PA1 8 20 PA8 PA2 9 10 11 12 13 14 15 PA3 PA4 PA5 PA6 PA7 PB0 QFN36 19 18 VDD_1 VSS_1 17 PB2 PB1 16 ai14654 24/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Low-density STM32F103xx pin definitions VFQFPN36 Main function(3) (after reset) TFBGA64 Type(1) Alternate functions(4) LQFP64 LQFP48/ VFQFPN48 Pins I / O Level(2) Table 5. Pinouts and pin description 1 1 B2 - VBAT S VBAT 2 2 A2 - PC13-TAMPERRTC(5) I/O PC13(6) TAMPER-RTC 3 3 A1 - PC14-OSC32_IN(5) I/O PC14(6) OSC32_IN 4 4 B1 - PC15OSC32_OUT(5) I/O PC15(6) OSC32_OUT 5 5 C1 2 OSC_IN I OSC_IN 6 6 D1 3 OSC_OUT O OSC_OUT 7 7 E1 4 NRST I/O NRST - 8 E3 - PC0 I/O PC0 ADC12_IN10 - 9 E2 - PC1 I/O PC1 ADC12_IN11 - 10 F2 - PC2 I/O PC2 ADC12_IN12 - 11 - - PC3 I/O PC3 ADC12_IN13 S VREF+ Pin name (7) Default Remap - - G1 - VREF+ 8 12 F1 5 VSSA S VSSA 9 13 H1 6 VDDA S VDDA 10 14 G2 7 PA0-WKUP I/O PA0 WKUP/USART2_CTS/ ADC12_IN0/ TIM2_CH1_ETR(8) 11 15 H2 8 PA1 I/O PA1 USART2_RTS/ ADC12_IN1/ TIM2_CH2(8) 12 16 F3 9 PA2 I/O PA2 USART2_TX/ ADC12_IN2/ TIM2_CH3(8) 13 17 G3 10 PA3 I/O PA3 USART2_RX/ ADC12_IN3/TIM2_CH4(8) - 18 C2 - VSS_4 S VSS_4 - 19 D2 - VDD_4 S VDD_4 14 20 H3 11 PA4 I/O PA4 SPI1_NSS(8)/ USART2_CK/ADC12_IN4 15 21 F4 12 PA5 I/O PA5 SPI1_SCK(8)/ ADC12_IN5 16 22 G4 13 PA6 I/O PA6 SPI1_MISO(8)/ ADC12_IN6/TIM3_CH1(8) TIM1_BKIN 17 23 H4 14 PA7 I/O PA7 SPI1_MOSI(8)/ ADC12_IN7/TIM3_CH2(8) TIM1_CH1N - 24 H5 PC4 I/O PC4 ADC12_IN14 Doc ID 15060 Rev 5 25/87 Pinouts and pin description Low-density STM32F103xx pin definitions (continued) 25 H6 18 26 F5 15 Pin name Type(1) TFBGA64 - VFQFPN36 LQFP64 LQFP48/ VFQFPN48 Pins I / O Level(2) Table 5. STM32F103x4, STM32F103x6 Alternate functions(4) Main function(3) (after reset) Default Remap PC5 I/O PC5 ADC12_IN15 PB0 I/O PB0 ADC12_IN8/TIM3_CH3(8) TIM1_CH2N PB1 ADC12_IN9/TIM3_CH4(8) TIM1_CH3N 19 27 G5 16 PB1 I/O 20 28 G6 17 PB2 I/O FT PB2/BOOT1 21 29 G7 - PB10 I/O FT PB10 TIM2_CH3 22 30 H7 - PB11 I/O FT PB11 TIM2_CH4 23 31 D6 18 VSS_1 S VSS_1 24 32 E6 19 VDD_1 S VDD_1 25 33 H8 - PB12 I/O FT PB12 TIM1_BKIN(8) 26 34 G8 - PB13 I/O FT PB13 TIM1_CH1N (8) 27 35 F8 - PB14 I/O FT PB14 TIM1_CH2N (8) 28 36 F7 - PB15 I/O FT PB15 TIM1_CH3N(8) - 37 F6 - PC6 I/O FT PC6 TIM3_CH1 38 E7 - PC7 I/O FT PC7 TIM3_CH2 39 E8 - PC8 I/O FT PC8 TIM3_CH3 - 40 D8 - PC9 I/O FT PC9 TIM3_CH4 29 41 D7 20 PA8 I/O FT PA8 USART1_CK/ TIM1_CH1/MCO 30 42 C7 21 PA9 I/O FT PA9 USART1_TX(8)/ TIM1_CH2(8) 31 43 C6 22 PA10 I/O FT PA10 USART1_RX(8)/ TIM1_CH3 32 44 C8 23 PA11 I/O FT PA11 USART1_CTS/ CAN_RX(8)/ TIM1_CH4 / USBDM 33 45 B8 24 PA12 I/O FT PA12 USART1_RTS/ CAN_TX(8) / TIM1_ETR / USBDP 34 46 A8 25 PA13 I/O FT JTMS/SWDIO 35 47 D5 26 VSS_2 S VSS_2 36 48 E5 27 VDD_2 S VDD_2 37 49 A7 28 PA14 I/O FT JTCK/SWCLK 38 50 A6 29 PA15 I/O FT JTDI - 51 B7 PC10 I/O FT PC10 - 52 B6 PC11 I/O FT PC11 - 53 C5 PC12 I/O FT PC12 26/87 Doc ID 15060 Rev 5 PA13 PA14 TIM2_CH1_ETR/ PA15 / SPI1_NSS STM32F103x4, STM32F103x6 Low-density STM32F103xx pin definitions (continued) VFQFPN36 Main function(3) (after reset) TFBGA64 Type(1) Alternate functions(4) LQFP64 LQFP48/ VFQFPN48 Pins I / O Level(2) Table 5. Pinouts and pin description 5 5 C1 2 PD0 I/O FT 6 6 D1 3 PD1 I/O FT OSC_OUT(9) 54 B5 - PD2 I/O FT PD2 39 55 A5 30 PB3 I/O FT JTDO TIM2_CH2 / PB3/ TRACESWO SPI1_SCK 40 56 A4 31 PB4 I/O FT NJTRST TIM3_CH1 /PB4 SPI1_MISO 41 57 C4 32 PB5 I/O PB5 I2C1_SMBA TIM3_CH2 / SPI1_MOSI 42 58 D3 33 PB6 I/O FT PB6 I2C1_SCL(8)/ USART1_TX PB7 I2C1_SDA(8) USART1_RX Pin name I/O FT Default Remap OSC_IN(9) TIM3_ETR 43 59 C3 34 PB7 44 60 B4 35 BOOT0 45 61 B3 - PB8 I/O FT PB8 I2C1_SCL /CAN_RX 46 62 A3 - PB9 I/O FT PB9 I2C1_SDA / CAN_TX 47 63 D4 36 VSS_3 S VSS_3 48 64 E4 1 VDD_3 S VDD_3 I BOOT0 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2, respectively. Refer to Table 2 on page 10. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. Doc ID 15060 Rev 5 27/87 Memory mapping 4 STM32F103x4, STM32F103x6 Memory mapping The memory map is shown in Figure 8. Figure 8. Memory map 0xFFFF FFFF APB memory space 0xFFFF FFFF reserved 0x4002 3400 CRC 7 0x4002 3000 reserved 0xE010 0000 0xE000 0000 0x4002 2400 Cortex-M3 Internal Peripherals Flash Interface 0x4002 2000 reserved 0x4002 1400 0x4002 1000 6 RCC reserved 0x4002 0400 DMA 0x4002 0000 reserved 0xC000 0000 0x4001 3C00 0x4001 3800 0x4001 3400 5 USART1 reserved SPI 0x4001 3000 TIM1 0x4001 2C00 0xA000 0000 ADC2 0x4001 2800 ADC1 0x4001 2400 reserved 4 0x4001 1800 0x1FFF FFFF Port D reserved 0x4001 1400 0x1FFF F80F Port C 0x8000 0000 Option Bytes 0x4001 1000 Port B 0x1FFF F800 0x4001 0C00 Port A 0x4001 0800 EXTI 3 System memory 0x4001 0400 AFIO 0x4001 0000 reserved 0x1FFF F000 0x6000 0000 0x4000 7400 PWR 0x4000 7000 BKP 0x4000 6C00 2 reserved 0x4000 6800 reserved 0x4000 0000 bxCAN 0x4000 6400 Peripherals 0x4000 6000 shared 512 byte USB/CAN SRAM USB Registers 0x4000 5C00 reserved 0x4000 5800 1 0x4000 5400 I2C reserved 0x2000 0000 0x4000 4800 SRAM 0x4000 4400 0x0801 FFFF 0x4000 3400 USART2 reserved IWDG 0 Flash memory 0x4000 3000 WWDG 0x4000 2C00 RTC 0x0800 0000 0x0000 0000 Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins Reserved 0x4000 2800 0x4000 0800 reserved 0x4000 0400 TIM3 0x4000 0000 TIM2 ai15177c 28/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Doc ID 15060 Rev 5 29/87 Electrical characteristics Figure 9. STM32F103x4, STM32F103x6 Pin loading conditions Figure 10. Pin input voltage STM32F103xx pin STM32F103xx pin C = 50 pF VIN ai14141 5.1.6 ai14142 Power supply scheme Figure 11. Power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers) OUT GP I/Os IN Level shifter Po wer swi tch 1.8-3.6V IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 5 x 100 nF + 1 x 4.7 F VDD 1/2/3/4/5 VDDA VREF 10 nF + 1 F Regulator VSS VREF+ ADC 10 nF + 1 F VREF- Analog: RCs, PLL, ... VSSA ai15496 Caution: 30/87 In Figure 11, the 4.7 F capacitor must be connected to VDD3. Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 5.1.7 Electrical characteristics Current consumption measurement Figure 12. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6. Symbol VDD - VSS VIN (2) |VDDx| |VSSX - VSS| VESD(HBM) Voltage characteristics Ratings Min Max -0.3 4.0 Input voltage on five volt tolerant pin VSS - 0.3 VDD + 4.0 Input voltage on any other pin VSS - 0.3 4.0 External main supply voltage (including VDDA and VDD)(1) Variations between different VDD power pins 50 Variations between all the different ground pins 50 Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 7: Current characteristics for the maximum allowed injected current values. Doc ID 15060 Rev 5 31/87 Electrical characteristics Table 7. STM32F103x4, STM32F103x6 Current characteristics Symbol Ratings Max. Total current into VDD/VDDA power lines (source)(1) IVDD Total current out of VSS ground lines (sink) IVSS 150 (1) 150 Output current sunk by any I/O and control pin IIO 25 - 25 Output current source by any I/Os and control pin (3) Injected current on five volt tolerant pins IINJ(PIN)(2) Injected current on any other pin IINJ(PIN) Unit mA -5/+0 (4) 5 Total injected current (sum of all I/O and control pins) (5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.18: 12-bit ADC characteristics. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage values. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 8. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Table 9. Symbol Unit -65 to +150 C 150 C General operating conditions Parameter Conditions Min Max fHCLK Internal AHB clock frequency 0 72 fPCLK1 Internal APB1 clock frequency 0 36 fPCLK2 Internal APB2 clock frequency 0 72 Standard operating voltage 2 3.6 2 3.6 2.4 3.6 1.8 3.6 VDD VDDA(1) VBAT 32/87 Value Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Must be the same potential as VDD(2) Backup operating voltage Doc ID 15060 Rev 5 Unit MHz V V V STM32F103x4, STM32F103x6 Table 9. Symbol Electrical characteristics General operating conditions (continued) Parameter Conditions Min TFBGA64 PD Max Unit 308 Power dissipation at TA = 85 C LQFP64 for suffix 6 or TA = 105 C for LQFP48 suffix 7(3) 444 mW 363 VFQFPN36 1000 Ambient temperature for 6 suffix version Maximum power dissipation -40 85 Low power dissipation(4) -40 105 Ambient temperature for 7 suffix version Maximum power dissipation -40 105 Low power dissipation -40 125 6 suffix version -40 105 7 suffix version -40 125 C TA TJ (4) C Junction temperature range C 1. When the ADC is used, refer to Table 46: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 81). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 81). 5.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 10. Symbol tVDD 5.3.3 Operating conditions at power-up / power-down Parameter Conditions Min VDD rise time rate 0 VDD fall time rate 20 Max Unit s/V Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Doc ID 15060 Rev 5 33/87 Electrical characteristics Table 11. Embedded reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD VPVDhyst STM32F103x4, STM32F103x6 (2) VPOR/PDR VPDRhyst (2) Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V PVD hysteresis 100 Power on/power down reset threshold Falling edge 1.8(1) 1.88 1.96 V Rising edge 1.84 1.92 2.0 V PDR hysteresis 40 TRSTTEMPO(2) Reset temporization 1 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. 34/87 mV Doc ID 15060 Rev 5 2.5 mV 4.5 ms STM32F103x4, STM32F103x6 5.3.4 Electrical characteristics Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions Min Typ Max Unit -40 C < TA < +105 C 1.16 1.20 1.26 V -40 C < TA < +85 C 1.16 1.20 1.24 V 5.1 17.1(2) s 10 mV 100 ppm/C ADC sampling time when TS_vrefint(1) reading the internal reference voltage Internal reference voltage VRERINT(2) spread over the temperature range TCoeff(2) VDD = 3 V 10 mV Temperature coefficient 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 12: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Doc ID 15060 Rev 5 35/87 Electrical characteristics Table 13. STM32F103x4, STM32F103x6 Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK TA = 105 C 72 MHz 45 46 48 MHz 32 33 36 MHz 26 27 24 MHz 18 19 16 MHz 13 14 8 MHz 7 8 72 MHz 30 31 48 MHz 23 24 External clock(2), all 36 MHz peripherals disabled 24 MHz 19 20 13 14 16 MHz 10 11 8 MHz 6 7 External clock(2), all peripherals enabled IDD Unit TA = 85 C Supply current in Run mode mA 1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 14. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions Supply current in Run mode Unit TA = 85 C TA = 105 C 72 MHz 41 42 48 MHz 27 28 36 MHz 20 21 24 MHz 14 15 16 MHz 10 11 8 MHz 6 7 72 MHz 27 28 48 MHz 19 20 External clock(2), all 36 MHz peripherals disabled 24 MHz 15 16 10 11 16 MHz 7 8 8 MHz 5 6 External clock(2), all peripherals enabled IDD fHCLK 1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 36/87 Doc ID 15060 Rev 5 mA STM32F103x4, STM32F103x6 Electrical characteristics Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 45 40 Consumption (mA) 35 30 72 MHz 25 36 MHz 16 MHz 20 8 MHz 15 10 5 0 - 45C 25 C 70 C 85 C 105 C Temperature (C) Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled 30 Consumption (mA) 25 20 72 MHz 36 MHz 15 16 MHz 8 MHz 10 5 0 - 45C 25 C 70 C 85 C 105 C Temperature (C) Doc ID 15060 Rev 5 37/87 Electrical characteristics Table 15. STM32F103x4, STM32F103x6 Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK Unit TA = 85 C TA = 105 C 72 MHz 26 27 48 MHz 17 18 36 MHz 14 15 24 MHz 10 11 16 MHz 7 8 8 MHz 4 5 72 MHz 7.5 8 48 MHz 6 6.5 36 MHz 5 5.5 24 MHz 4.5 5 16 MHz 4 4.5 8 MHz 3 4 1. based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 38/87 Doc ID 15060 Rev 5 mA STM32F103x4, STM32F103x6 Table 16. Electrical characteristics Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = Unit = 2.0 V = 2.4 V = 3.3 V 85 C 105 C Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode Regulator in Low Power mode, low- IDD Max speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Supply current Low-speed internal RC oscillator in Standby ON, independent watchdog OFF mode Low-speed internal RC oscillator and independent watchdog OFF, lowspeed oscillator and RTC OFF Backup IDD_VBAT domain supply Low-speed oscillator and RTC ON current - 21.3 21.7 160 200 - 11.3 11.7 145 185 - 2.75 3.4 - - - 2.55 3.2 - - - 1.55 1.9 3.2 4.5 0.9 1.1 1.4 1.9(2) 2.2 A 1. Typical values are measured at TA = 25 C. 2. Based on characterization, not tested in production. Figure 15. Typical current consumption on VBAT with RTC on versus temperature at different VBAT values Consumption ( A ) 2.5 2 2V 1.5 2.4 V 1 3V 0.5 3.6 V 0 -40 C 25 C 70 C 85 C 105 C Temperature (C) ai17351 Doc ID 15060 Rev 5 39/87 Electrical characteristics STM32F103x4, STM32F103x6 Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V 120 Consumption (A) 100 80 3.3 V 60 3.6 V 40 20 0 -45 C 25 C 85 C 105 C Temperature (C) Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V 90 80 Consumption (A) 70 60 50 3.3 V 3.6 V 40 30 20 10 0 -45 C 25 C 85 C Temperature (C) 40/87 Doc ID 15060 Rev 5 105 C STM32F103x4, STM32F103x6 Electrical characteristics Figure 18. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V 4.5 4 Consumption (A) 3.5 3 2.5 3.3 V 2 3.6 V 1.5 1 0.5 0 -45 C 25 C 85 C 105 C Temperature (C) Typical current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load). All peripherals are disabled except if it is explicitly mentioned. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). Ambient temperature and VDD supply voltage conditions summarized in Table 9. Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 Doc ID 15060 Rev 5 41/87 Electrical characteristics Table 17. STM32F103x4, STM32F103x6 Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions (3) External clock IDD Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK All peripherals All peripherals disabled enabled(2) 72 MHz 31.3 24.5 48 MHz 21.9 17.4 36 MHz 17.2 13.8 24 MHz 11.2 8.9 16 MHz 8.1 6.6 8 MHz 5 4.2 4 MHz 3 2.6 2 MHz 2 1.8 1 MHz 1.5 1.4 500 kHz 1.2 1.2 125 kHz 1.05 1 64 MHz 27.6 21.6 48 MHz 21.2 16.7 36 MHz 16.5 13.1 24 MHz 10.5 8.2 16 MHz 7.4 5.9 8 MHz 4.3 3.6 4 MHz 2.4 2 2 MHz 1.5 1.3 1 MHz 1 0.9 500 kHz 0.7 0.65 125 kHz 0.5 0.45 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 42/87 Doc ID 15060 Rev 5 Unit mA mA STM32F103x4, STM32F103x6 Table 18. Electrical characteristics Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions Supply current in Sleep mode All peripherals All peripherals enabled(2) disabled 72 MHz 12.6 5.3 48 MHz 8.7 3.8 36 MHz 6.7 3.1 24 MHz 4.8 2.3 16 MHz 3.4 1.8 8 MHz 2 1.2 4 MHz 1.5 1.1 2 MHz 1.25 1 1 MHz 1.1 0.98 500 kHz 1.05 0.96 125 kHz 1 0.95 64 MHz 10.6 4.2 48 MHz 8.1 3.2 36 MHz 6.1 2.5 24 MHz Running on high 16 MHz speed internal RC (HSI), AHB prescaler 8 MHz used to reduce the 4 MHz frequency 2 MHz 4.2 1.7 2.8 1.2 1.4 0.55 0.9 0.5 0.7 0.45 1 MHz 0.55 0.42 500 kHz 0.48 0.4 125 kHz 0.4 0.38 External clock IDD fHCLK (3) Unit mA 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 15060 Rev 5 43/87 Electrical characteristics STM32F103x4, STM32F103x6 On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed under the following conditions: all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - with all peripherals clocked off - with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 6 Table 19. Peripheral current consumption(1) Peripheral Typical consumption at 25 C TIM2 1.2 TIM3 1.2 USART2 0.35 I2C 0.39 USB 0.65 CAN 0.72 GPIO A 0.47 GPIO B 0.47 GPIO C 0.47 GPIO D 0.47 ADC1(2) 1.81 ADC2 1.78 TIM1 1.6 SPI 0.43 USART1 0.85 APB1 APB2 Unit mA mA 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1. 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. 44/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Table 20. Electrical characteristics High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 25 MHz fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) tr(HSE) tf(HSE) Cin(HSE) 5 ns OSC_IN rise or fall time (1) 20 OSC_IN input capacitance(1) 5 DuCy(HSE) Duty cycle IL V pF 45 OSC_IN Input leakage current VSS VIN VDD 55 % 1 A 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 21. Symbol Low-speed external user clock characteristics Parameter Conditions Min fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS tw(LSE) tw(LSE) OSC32_IN high or low time(1) 450 Typ Max Unit 32.768 1000 kHz 0.7VDD VDD V tr(LSE) tf(LSE) Cin(LSE) ns OSC32_IN rise or fall time(1) 50 OSC32_IN input capacitance(1) 5 DuCy(LSE) Duty cycle IL 0.3VDD 30 OSC32_IN Input leakage current VSS VIN VDD pF 70 % 1 A 1. Guaranteed by design, not tested in production. Doc ID 15060 Rev 5 45/87 Electrical characteristics STM32F103x4, STM32F103x6 Figure 19. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 Figure 20. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE EXTER NAL CLOCK SOURC E fLSE_ext STM32F103xx ai14144b High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 46/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Table 22. Symbol Electrical characteristics HSE 4-16 MHz oscillator characteristics(1) (2) Parameter fOSC_IN Conditions Typ Max Unit 4 8 16 MHz Oscillator frequency RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) i2 HSE driving current (4) 200 k 30 pF RS = 30 VDD = 3.3 V, VIN = VSS with 30 pF load Oscillator transconductance gm tSU(HSE Min Startup startup time 1 25 mA mA/V VDD is stabilized 2 ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 21). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 21. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator CL2 REXT(1) RF OSC_OU T Bias controlled gain STM32F103xx ai14145 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Doc ID 15060 Rev 5 47/87 Electrical characteristics Table 23. Symbol STM32F103x4, STM32F103x6 LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (2) Parameter Conditions Min Typ Max Unit RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS) RS = 30 K 15 pF I2 LSE driving current VDD = 3.3 V VIN = VSS 1.4 A gm Oscillator transconductance tSU(LSE)(3) 5 5 VDD is stabilized Startup time M A/V TA = 50 C 1.5 TA = 25 C 2.5 TA = 10 C 4 TA = 0 C 6 TA = -10 C 10 TA = -20 C 17 TA = -30 C 32 TA = -40 C 60 s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. 48/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Electrical characteristics Figure 22. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator Bias controlled gain RF STM32F103xx OSC32_OU T CL2 ai14146 5.3.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. High-speed internal (HSI) RC oscillator Table 24. Symbol HSI oscillator characteristics(1) Parameter fHSI Frequency DuCy(HSI) Duty cycle Conditions Min Typ 8 45 User-trimmed with the RCC_CR register(2) ACCHSI Max Accuracy of the HSI oscillator Factorycalibrated(4) tsu(HSI)(4) HSI oscillator startup time IDD(HSI)(4) HSI oscillator power consumption Unit MHz 55 % 1(3) % TA = -40 to 105 C -2 2.5 % TA = -10 to 85 C -1.5 2.2 % TA = 0 to 70 C -1.3 2 % TA = 25 C -1.1 1.8 % 1 2 s 100 A 80 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Refer to application note AN2868 "STM32F10xxx internal RC oscillator (HSI) calibration" available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. Doc ID 15060 Rev 5 49/87 Electrical characteristics STM32F103x4, STM32F103x6 Low-speed internal (LSI) RC oscillator Table 25. LSI oscillator characteristics (1) Symbol fLSI(2) Parameter Frequency tsu(LSI)(3) LSI oscillator startup time IDD(LSI)(3) LSI oscillator power consumption Min Typ Max Unit 30 40 60 kHz 85 s 1.2 A 0.65 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 50/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Table 26. Electrical characteristics Low-power mode wakeup timings Symbol Parameter tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Typ Unit Wakeup from Sleep mode 1.8 s Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low power mode) 5.4 Wakeup from Standby mode 50 s s 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. 5.3.8 PLL characteristics The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 27. PLL characteristics Value Symbol Parameter Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.0 25 MHz PLL input clock duty cycle 40 60 % fPLL_OUT PLL multiplier output clock 16 72 MHz tLOCK PLL lock time 200 s Jitter Cycle-to-cycle jitter 300 ps fPLL_IN 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 28. Symbol tprog tERASE tME Flash memory characteristics Min(1) Typ Max(1) Unit 16-bit programming time TA = -40 to +105 C 40 52.5 70 s Page (1 KB) erase time TA = -40 to +105 C 20 40 ms Mass erase time TA = -40 to +105 C 20 40 ms Parameter Conditions Doc ID 15060 Rev 5 51/87 Electrical characteristics Table 28. Symbol IDD Vprog STM32F103x4, STM32F103x6 Flash memory characteristics (continued) Max(1) Unit Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V 20 mA Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V 50 A 3.6 V Parameter Supply current Conditions Programming voltage Min(1) Typ 2 1. Guaranteed by design, not tested in production. Table 29. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 1 kcycle(2) at TA = 105 C 10 10 kcycles (2) at TA = 55 C Unit Typ Max kcycles Years 20 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 30. They are based on the EMS levels and classes defined in application note AN1709. 52/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Table 30. Electrical characteristics EMS characteristics Symbol Parameter Level/ Class Conditions VFESD VDD = 3.3 V, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK = 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 C, fHCLK = 72 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 31. Symbol SEMI EMI characteristics Parameter Peak level Conditions VDD = 3.3 V, TA = 25 C Monitored frequency band Max vs. [fHSE/fHCLK] Unit 8/48 MHz 8/72 MHz 0.1 to 30 MHz 12 12 30 to 130 MHz 22 19 130 MHz to 1GHz 23 29 SAE EMI Level 4 4 Doc ID 15060 Rev 5 dBV - 53/87 Electrical characteristics 5.3.11 STM32F103x4, STM32F103x6 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 32. ESD absolute maximum ratings Symbol Ratings Conditions VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 C conforming to JESD22-A114 TA = +25 C conforming to JESD22-C101 Electrostatic discharge VESD(CDM) voltage (charge device model) Class Maximum value(1) 2 Unit 2000 V II 500 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 33. Symbol LU 54/87 Electrical sensitivities Parameter Static latch-up class Conditions TA = +105 C conforming to JESD78A Doc ID 15060 Rev 5 Class II level A STM32F103x4, STM32F103x6 5.3.12 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 34 Table 34. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13 -0 +0 Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 Doc ID 15060 Rev 5 Unit mA 55/87 Electrical characteristics 5.3.13 STM32F103x4, STM32F103x6 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 35. Symbol VIL VIH Vhys Ilkg I/O static characteristics Parameter Conditions Min Typ Max Unit Standard IO input low level voltage -0.3 0.28*(VDD-2 V)+0.8 V V IO FT(1) input low level voltage -0.3 0.32*(VDD-2V)+0.75 V V Standard IO input high level voltage 0.41*(VDD-2 V)+1.3 V VDD+0.3 V IO FT(1) input high level voltage 5.5 VDD > 2 V 0.42*(VDD-2 V)+1 V VDD 2 V V 5.2 Standard IO Schmitt trigger voltage hysteresis(2) 200 mV IO FT Schmitt trigger voltage hysteresis(2) 5% VDD(3) mV Input leakage current (4) VSS VIN VDD Standard I/Os 1 A VIN = 5 V I/O FT 3 RPU Weak pull-up equivalent resistor(5) VIN = VSS 30 40 50 k RPD Weak pull-down equivalent resistor(5) VIN = VDD 30 40 50 k CIO I/O pin capacitance 5 1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). 56/87 Doc ID 15060 Rev 5 pF STM32F103x4, STM32F103x6 Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and in Figure 25 and Figure 26 for 5 V tolerant I/Os. Figure 23. Standard I/O input characteristics - CMOS port 6)(6), 6 6 $$ ENT 6 )( #-/3 7)(MIN 7),MAX 6 6 )( $$ QUIREM NDARD RE )NPUT RANGE NOT GUARANTEED 6 6), $$ 6 $$ IREMENT 6 ), RD REQU #-/3 STANDA STA 6$$ 6 AIB Figure 24. Standard I/O input characteristics - TTL port 6)(6), 6 7)(MIN 44, REQUIREMENTS 6)( 6 6 6 )( $$ )NPUT RANGE NOT GUARANTEED 7),MAX 6 ),6 $$ 44, REQUIREMENTS 6),6 6$$ 6 AI Doc ID 15060 Rev 5 57/87 Electrical characteristics STM32F103x4, STM32F103x6 Figure 25. 5 V tolerant I/O input characteristics - CMOS port 6)(6), 6 6 $$ TS 6 )( UIREMEN ARD REQ 3 STAND #-/ 6 ),6 $$ T 6 ),6 $$ REQUIRMEN /3 STANDARD #- 6 )(6 $$ )NPUT RANGE NOT GUARANTEED 6$$ 6 6$$ AIB Figure 26. 5 V tolerant I/O input characteristics - TTL port 6)(6), 6 44, REQUIREMENT 6 )(6 6 6 )( $$ 7)(MIN 7),MAX )NPUT RANGE NOT GUARANTEED 6 ), 6 $$ 44, REQUIREMENTS 6 ),6 6$$ 6 AI 58/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Electrical characteristics Output driving current The GPIOs (general-purpose inputs/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 7). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7). Output voltage levels Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 36. Symbol Output voltage characteristics Parameter VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL (1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions CMOS port(2), IIO = +8 mA 2.7 V < VDD < 3.6 V TTL port(2) IIO =+ 8mA 2.7 V < VDD < 3.6 V IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V Min Max Unit 0.4 V VDD-0.4 0.4 V 2.4 1.3 V VDD-1.3 0.4 V VDD-0.4 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. Doc ID 15060 Rev 5 59/87 Electrical characteristics STM32F103x4, STM32F103x6 Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 27 and Table 37, respectively. Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 37. I/O AC characteristics(1) MODEx[1:0] Symbol bit value(1) Parameter Conditions Min fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out - tEXTIpw frequency(2) Output high to low level fall time Output low to high level rise time Unit 2 MHz 125(3) CL = 50 pF, VDD = 2 V to 3.6 V ns 125(3) fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 Max 10 MHz 25(3) CL = 50 pF, VDD = 2 V to 3.6 V ns 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 50 MHz CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) Pulse width of external signals detected by the EXTI controller 10 ns ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 27. 3. Guaranteed by design, not tested in production. 60/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Electrical characteristics Figure 27. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% External Output on 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50 pF ai14131 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 35). Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 38. Symbol NRST pin characteristics Parameter Conditions Min Typ Max VIL(NRST)(1) NRST Input low level voltage -0.5 0.8 VIH(NRST)(1) NRST Input high level voltage 2 VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis VF(NRST) V Weak pull-up equivalent resistor(2) RPU (1) Unit 200 VIN = VSS 30 NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse 300 40 mV 50 k 100 ns ns 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Doc ID 15060 Rev 5 61/87 Electrical characteristics STM32F103x4, STM32F103x6 Figure 28. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal reset Filter 0.1 F STM32F10x ai14132d 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 38. Otherwise the reset will not be taken into account by the device. 5.3.15 TIM timer characteristics The parameters given in Table 39 are guaranteed by design. Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 39. Symbol tres(TIM) fEXT ResTIM tCOUNTER TIMx(1) characteristics Parameter Conditions Min Max 1 tTIMxCLK 13.9 ns Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz 0 fTIMxCLK/2 MHz 0 36 MHz 16 bit 65536 tTIMxCLK 910 s 65536 x 65536 tTIMxCLK 59.6 s Timer resolution 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.0139 selected tMAX_COUNT Maximum possible count fTIMxCLK = 72 MHz 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. 62/87 Doc ID 15060 Rev 5 Unit STM32F103x4, STM32F103x6 5.3.16 Electrical characteristics Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9. The STM32F103xx performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 40. Refer also to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 40. I2C characteristics Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0(3) 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 th(STA) Start condition hold time 4.0 0.6 tsu(STA) Repeated Start condition setup time 4.7 0.6 tsu(STO) Stop condition setup time 4.0 0.6 s tw(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 s Cb Capacitive load for each bus line s ns 300 s 400 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than 4 MHz to achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Doc ID 15060 Rev 5 63/87 Electrical characteristics STM32F103x4, STM32F103x6 Figure 29. I2C bus AC waveforms and measurement circuit VDD 4 .7 k VDD 4 .7 k 100 100 IC bus STM32F10x SDA SCL Start repeated Start Start tsu(STA) SDA tf(SDA) tr(SDA) th(STA) tsu(SDA) tw(SCLL) tsu(STO:STA) Stop th(SDA) SCL tw(SCLH) tr(SCL) tsu(STO) tf(SCL) ai14133d 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 41. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 2 1. RP = External pull-up resistance, fSCL = I C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. 64/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 42. Symbol fSCK 1/tc(SCK) SPI characteristics Parameter Conditions Min Max Unit Master mode 18 Slave mode 18 8 ns 70 % SPI clock frequency MHz tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 tsu(NSS)(1) NSS setup time Slave mode 4tPCLK th(NSS)(1) Slave mode 2tPCLK NSS hold time (1) Master mode, fPCLK = 36 MHz, tw(SCKH) SCK high and low time tw(SCKL)(1) presc = 4 tsu(MI) (1) tsu(SI)(1) th(MI) Master mode 5 Slave mode 5 Master mode 5 Slave mode 4 60 Data input setup time (1) th(SI)(1) 50 Data input hold time ns ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK tdis(SO)(1)(3) Data output disable time Slave mode 2 10 tv(SO) (1) Data output valid time Slave mode (after enable edge) 25 (1) Data output valid time Master mode (after enable edge) 5 tv(MO) th(SO)(1) th(MO)(1) Slave mode (after enable edge) 15 Master mode (after enable edge) 2 Data output hold time 1. Based on characterization, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Doc ID 15060 Rev 5 65/87 Electrical characteristics STM32F103x4, STM32F103x6 Figure 30. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 31. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 66/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Electrical characteristics Figure 32. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT B I T1 OUT M SB OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 43. USB startup time Symbol tSTARTUP(1) Parameter USB transceiver startup time Max Unit 1 s 1. Guaranteed by design, not tested in production. Doc ID 15060 Rev 5 67/87 Electrical characteristics Table 44. STM32F103x4, STM32F103x6 USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V V Input levels VDD USB operating voltage(2) VDI(4) Differential input sensitivity I(USBDP, USBDM) 0.2 VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 Output levels VOL Static output level low RL of 1.5 k to 3.6 V(5) VOH Static output level high RL of 15 k to VSS(5) 0.3 V 2.8 3.6 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by design, not tested in production. 5. RL is the load connected on the USB drivers Figure 33. USB timings: definition of data signal rise and fall time Crossover points Differen tial data lines VCRS VS S Table 45. tr tf ai14137 USB: Full-speed electrical characteristics(1) Symbol Parameter Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Driver characteristics tr tf trfm VCRS Rise time(2) (2) Fall time Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 5.3.17 CAN (controller area network) interface Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). 68/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 5.3.18 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. Note: It is recommended to perform a calibration after each power-up. Table 46. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Power supply 2.4 3.6 V VREF+(3) Positive reference voltage 2.4 VDDA V IVREF(3) Current on the VREF input pin 220(1) A VDDA 160(1) fADC ADC clock frequency 0.6 14 MHz fS(2) Sampling rate 0.05 1 MHz 823 kHz 17 1/fADC VREF+ V 50 k fADC = 14 MHz fTRIG(2) External trigger frequency VAIN(3) Conversion voltage range RAIN(2) External input impedance RADC(2) Sampling switch resistance 1 k CADC(2) Internal sample and hold capacitor 8 pF tCAL(2) Calibration time 0 (VSSA tied to ground) See Equation 1 and Table 47 for details fADC = 14 MHz tlat(2) Injection trigger conversion latency fADC = 14 MHz tlatr(2) Regular trigger conversion latency fADC = 14 MHz tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) 5.9 s 83 1/fADC 0.214 3 (4) s 1/fADC 0.143 2 fADC = 14 MHz s 1/fADC 0.107 17.1 s 1.5 239.5 1/fADC 1 s 18 s 0 fADC = 14 MHz (4) 1 0 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. In devices delivered in VFQFPN and LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA), see Table 5 and Figure 4. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 46. Doc ID 15060 Rev 5 69/87 Electrical characteristics STM32F103x4, STM32F103x6 Equation 1: RAIN max formula: TS R AIN < ------------------------------------------------------------- - R ADC N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 47. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (s) RAIN max (k) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Based on characterization, not tested in production. Table 48. Symbol ADC accuracy - limited test conditions(1) (2) Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(3) fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V TA = 25 C Measurements made after ADC calibration 1.3 2 1 1.5 0.5 1.5 0.7 1 0.8 1.5 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. 3. Based on characterization, not tested in production. 70/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Electrical characteristics ADC accuracy(1) (2) (3) Table 49. Symbol Parameter ET Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) 2 5 1.5 2.5 1.5 3 1 2 1.5 3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. 4. Based on characterization, not tested in production. Figure 34. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET (3) 7 (1) 6 5 4 EO EL 3 ED 2 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA Doc ID 15060 Rev 5 ai14395b 71/87 Electrical characteristics STM32F103x4, STM32F103x6 Figure 35. Typical connection diagram using the ADC VDD RAIN(1) VAIN VT 0.6 V AINx Cparasitic VT 0.6 V IL1 A STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) ai14150c 1. Refer to Table 46 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown inFigure 36 or Figure 37, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA) 34-&XX 62%& SEE NOTE & N& 6$$! & N& 633! AI 1. The VREF+ input is available only on the TFBGA64 package. 72/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Electrical characteristics Figure 37. Power supply and reference decoupling(VREF+ connected to VDDA) 34-&X 6$$! 62%& SEE NOTE & N& 633! AI 1. The VREF+ input is available only on the TFBGA64 package. 5.3.19 Temperature sensor characteristics Table 50. TS characteristics Symbol TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) Parameter Min VSENSE linearity with temperature Typ Max Unit 1 2 C Average slope 4.0 4.3 4.6 mV/C Voltage at 25 C 1.34 1.43 1.52 V 10 s 17.1 s Startup time 4 ADC sampling time when reading the temperature 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Doc ID 15060 Rev 5 73/87 Package characteristics STM32F103x4, STM32F103x6 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 74/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Package characteristics Figure 38. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) Figure 39. Recommended footprint (dimensions in mm)(1)(2) Seating plane C ddd C 1.00 4.30 A2 A 27 19 A1 A3 E2 28 18 b 27 18 28 0.50 4.10 19 4.30 4.10 4.80 4.80 e D2 D 36 10 9 1 36 0.75 0.30 10 6.30 ai14870b Pin # 1 ID R = 0.20 1 9 L E ZR_ME 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life. Table 51. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max 0.800 0.900 1.000 0.0315 0.0354 0.0394 A1 0.020 0.050 0.0008 0.0020 A2 0.650 1.000 0.0256 0.0394 A3 0.250 A 0.0098 b 0.180 0.230 0.300 0.0071 0.0091 0.0118 D 5.875 6.000 6.125 0.2313 0.2362 0.2411 D2 1.750 3.700 4.250 0.0689 0.1457 0.1673 E 5.875 6.000 6.125 0.2313 0.2362 0.2411 E2 1.750 3.700 4.250 0.0689 0.1457 0.1673 e 0.450 0.500 0.550 0.0177 0.0197 0.0217 L 0.350 0.550 0.750 0.0138 0.0217 0.0295 ddd 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15060 Rev 5 75/87 Package characteristics STM32F103x4, STM32F103x6 Figure 40. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package Figure 41. Recommended footprint outline(1) (dimensions in mm)(1)(2) ddd C Seating Plane A2 A C 0.75 A1 A3 5.80 37 48 D 36 1 Pin no. 1 ID R = 0.20 e 5.60 37 48 0.20 1 36 5.80 5.60 e 6.20 0.30 12 E E2 b 6.20 25 13 0.55 24 0.50 L 7.30 ai15799 12 25 24 13 L b Bottom View D2 V0_ME 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life. Table 52. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max 0.800 0.900 1.000 0.0315 0.0354 0.0394 A1 0.020 0.050 0.0008 0.0020 A2 0.650 1.000 0.0256 0.0394 A3 0.250 A 0.0098 b 0.180 0.230 0.300 0.0071 0.0091 0.0118 D 6.850 7.000 7.150 0.2697 0.2756 0.2815 D2 2.250 4.700 5.250 0.0886 0.1850 0.2067 E 6.850 7.000 7.150 0.2697 0.2756 0.2815 E2 2.250 4.700 5.250 0.0886 0.1850 0.2067 e 0.450 0.500 0.550 0.0177 0.0197 0.0217 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 76/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Package characteristics Figure 42. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline(1) Figure 43. Recommended footprint(1)(2) A A2 48 33 A1 0.3 49 E 32 0.5 b E1 12.7 10.3 10.3 e 64 17 1.2 1 16 7.8 D1 c 12.7 L1 D ai14909 L ai14398b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 53. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 Max 0.0630 0.15 0.0020 0.0059 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15060 Rev 5 77/87 Package characteristics STM32F103x4, STM32F103x6 Figure 44. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline B D D1 A A e A1 F H F G F E E1 E D C B A e 1 2 3 A1 ball pad corner A3 4 5 6 7 8 Ob (64 balls) A4 A2 Seating C plane Bottom view ME_R8 1. Drawing is not to scale. Table 54. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ A A1 Max Min 1.200 0.150 Max 0.0472 0.0059 A2 0.785 0.0309 A3 0.200 0.0079 A4 0.600 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 E 3.500 4.850 5.000 0.1378 5.150 0.1909 0.1969 E1 3.500 0.1378 e 0.500 0.0197 F 0.750 0.0295 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.050 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 78/87 Typ Doc ID 15060 Rev 5 0.2028 STM32F103x4, STM32F103x6 Package characteristics Figure 45. Recommended PCB design rules for pads (0.5 mm pitch BGA) Pitch 0.5 mm D pad 0.27 mm Dsm 0.35 mm typ (depends on the soldermask registration tolerance) Solder paste 0.27 mm aperture diameter Dpad Dsm ai15495 1. Non solder mask defined (NSMD) pads are recommended 2. 4 to 6 mils solder paste screen printing process Doc ID 15060 Rev 5 79/87 Package characteristics STM32F103x4, STM32F103x6 Figure 46. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline(1) Figure 47. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.50 0.25 mm Gage plane C 1.20 D 36 0.30 25 37 D1 24 k D3 A1 L 25 36 9.70 0.20 7.30 5.80 L1 7.30 24 37 48 13 12 1 1.20 5.80 E3 E1 E 9.70 ai14911b 48 Pin 1 identification 13 1 12 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 55. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 8.800 D1 6.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 9.000 9.200 0.3465 0.3543 0.3622 7.000 7.200 0.2677 0.2756 0.2835 5.500 0.0059 0.0079 0.2165 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.500 0.2165 e 0.500 0.0197 L 0.450 L1 k ccc 0.600 0.750 0.0177 1.000 0 3.5 0.0236 0.0295 0.0394 7 0.080 0 3.5 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 80/87 Min Doc ID 15060 Rev 5 7 STM32F103x4, STM32F103x6 6.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 32. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 56. Package thermal characteristics Symbol JA 6.2.1 Parameter Value Thermal resistance junction-ambient TFBGA64 - 5 x 5 mm / 0.5 mm pitch 65 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch 55 Thermal resistance junction-ambient VFQFPN 48 -7 x 7 mm / 0.5 mm pitch 16 Thermal resistance junction-ambient VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch 18 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Doc ID 15060 Rev 5 81/87 Package characteristics 6.2.2 STM32F103x4, STM32F103x6 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 57: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 20 x 8 mA x 0.4 V + 8 x 20 mA x 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 56 TJmax is calculated as follows: - For LQFP64, 45 C/W TJmax = 82 C + (45 C/W x 447 mW) = 82 C + 20.115 C = 102.115 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 57: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA x 3.5 V= 70 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW 82/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Package characteristics Using the values obtained in Table 56 TJmax is calculated as follows: - For LQFP64, 45 C/W TJmax = 115 C + (45 C/W x 134 mW) = 115 C + 6.03 C = 121.03 C This is within the range of the suffix 7 version parts (-40 < TJ < 125 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 57: Ordering information scheme). Figure 48. LQFP64 PD max vs. TA 700 PD (mW) 600 500 Suffix 6 400 Suffix 7 300 200 100 0 65 75 85 95 105 115 125 135 TA (C) Doc ID 15060 Rev 5 83/87 Ordering information scheme 7 STM32F103x4, STM32F103x6 Ordering information scheme Table 57. Ordering information scheme Example: STM32 F 103 C 4 T 7 A xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count T = 36 pins C = 48 pins R = 64 pins Flash memory size 4 = 16 Kbytes of Flash memory 6 = 32 Kbytes of Flash memory Package H = BGA T = LQFP U = VFQFPN Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Internal code "A" or blank(1) Options xxx = programmed parts TR = tape and real 1. For STM32F103x6 devices with a blank Internal code, please refer to the STM32F103x8/B datasheet available from the ST website: www.st.com. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 84/87 Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 8 Revision history Revision history Table 58. Document revision history Date Revision 22-Sep-2008 1 Initial release. 2 "96-bit unique ID" feature added and I/O information clarified on page 1. Timers specified on page 1 (Motor control capability mentioned). Table 4: Timer feature comparison added. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column, plus small additional changes in Table 5: Low-density STM32F103xx pin definitions. Figure 8: Memory map modified. References to VREF- removed: - Figure 1: STM32F103xx performance line block diagram modified, - Figure 11: Power supply scheme modified - Figure 34: ADC accuracy characteristics modified - Note modified in Table 49: ADC accuracy. Table 20: High-speed external user clock characteristics and Table 21: Low-speed external user clock characteristics modified. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 17 shows a typical curve (title modified). ACCHSI max values modified in Table 24: HSI oscillator characteristics. TFBGA64 package added (see Table 54 and Table 44). Small text changes. 30-Mar-2009 Changes Doc ID 15060 Rev 5 85/87 Revision history Table 58. STM32F103x4, STM32F103x6 Document revision history (continued) Date 24-Sep-2009 20-May-2010 19-Apr-2011 86/87 Revision Changes 3 Note 5 updated and Note 4 added in Table 5: Low-density STM32F103xx pin definitions. VRERINT and TCoeff added to Table 12: Embedded internal reference voltage. Typical IDD_VBAT value added in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 15: Typical current consumption on VBAT with RTC on versus temperature at different VBAT values added. fHSE_ext min modified in Table 20: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator characteristics and Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Table 24: HSI oscillator characteristics modified. Conditions removed from Table 26: Low-power mode wakeup timings. Note 1 modified below Figure 21: Typical application with an 8 MHz crystal. Figure 28: Recommended NRST pin protection modified. Jitter added to Table 27: PLL characteristics on page 51. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.10: EMC characteristics on page 52. CADC and RAIN parameters modified in Table 46: ADC characteristics. RAIN max values modified in Table 47: RAIN max for fADC = 14 MHz. Small text changes. 4 Added VFQFPN48 package. Updated note 2 below Table 40: I2C characteristics Updated Figure 29: I2C bus AC waveforms and measurement circuit Updated Figure 28: Recommended NRST pin protection Updated Section 5.3.12: I/O current injection characteristics 5 Updated footnotes below Table 6: Voltage characteristics on page 31 and Table 7: Current characteristics on page 32 Updated tw min in Table 20: High-speed external user clock characteristics on page 45 Updated startup time in Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 48 Added Section 5.3.12: I/O current injection characteristics Updated Section 5.3.13: I/O port characteristics Doc ID 15060 Rev 5 STM32F103x4, STM32F103x6 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15060 Rev 5 87/87