PIC16F819-I/PTSL - Microchip Technology

SSP MODULE

The PIC® microcontrollers you have received all exhibit

anomalous behavior in their Synchronous Serial Port

(SSP) modules, as described in this document. They

otherwise conform functionally to the descriptions pro-

vided in their respective Device Data Sheets and Ref-

erence Manuals, as amended by silicon release errata

for particular devices.

Users are encouraged to review the latest device data

sheets and errata available for additional information

concerning an individual device. These documents

may be obtained directly from the Microchip corporate

web site, at www.microchip.com.

Silicon Errata

These issues are expected to be resolved in future

silicon revisions of the designated parts.

The silicon issues identified in this “Silicon Errata” section

affect all silicon revisions of the following devices:

1. Module: I2C™ (Slave Mode)

In its current implementation, the module may fail

to correctly recognize certain Repeated Start

conditions. For this discussion, a Repeated Start is

defined as a Start condition presented to the bus

after an initial valid Start condition has been recog-

nized and the Start status bit (SSPSTAT<3>) has

been set and before a valid Stop condition is

received.

If a Repeated Start is not recognized, a loss of

synchronization between the Master and Slave

may occur; the condition may continue until the

module is reset. A NACK condition, generated by

the Slave for any reason, will not reset the module.

This failure has been observed only under two

circumstances:

• A Repeated Start occurs within the frame of a

data or address byte. The unexpected Start

condition may be erroneously interpreted as a

data bit, provided that the required conditions

for setup and hold times are met.

• A Repeated Start condition occurs between two

back-to-back slave address matches in the

same Slave, with the R/W bit set to Read (= 1)

in both cases. (This circumstance is regarded

as being unlikely in normal operation.)

Work around

A time-out routine should be used to monitor the

module’s operation. The timer is enabled upon the

receipt of a valid Start condition; if a time-out

occurs, the module is reset. The length of the time-

out period will vary from application to application

and will need to be determined by the user.

Two methods are suggested to reset the module:

1. Change the mode of the module to something

other than the desired mode by changing the set-

tings of bits, SSPM3:SSPM0 (SSPCON<3:0>);

then, change the bits back to the desired

configuration.

2. Disable the module by clearing the SSPEN bit

(SSPCON<5>); then, re-enable the module by

setting the bit.

Other methods may be available.

• PIC14000 • PIC16C923

• PIC16C62 • PIC16C924

• PIC16C62A • PIC16C925

• PIC16C62B • PIC16C926

• PIC16C63 • PIC16CR62

• PIC16C63A • PIC16CR63

• PIC16C64 • PIC16CR64

• PIC16C64A • PIC16CR65

• PIC16C65 • PIC16CR72

• PIC16C65A • PIC16CR72A

• PIC16C65B • PIC16F72

• PIC16C66 • PIC16F73

• PIC16C67 • PIC16F74

• PIC16C717 • PIC16F76

• PIC16C72 • PIC16F77

• PIC16C72A • PIC16F87

• PIC16C73 • PIC16F88

• PIC16C73A • PIC16F818

• PIC16C73B • PIC16F819

• PIC16C74 • PIC18F2331

• PIC16C74A • PIC18F2431

• PIC16C74B • PIC18F4331

• PIC16C76 • PIC18F4431

• PIC16C77

SSP Module Silicon/Data Sheet Errata

SSP MODULE

Clarifications/Corrections to the Data

Sheets

1. Module: SSP (SPI Mode)

The description of the operation of the CKE bit

(SSPSTAT<6>) is clarified. Please substitute the

description in Register 1, below, for all occurrences of

the existing text for the SSPSTAT register, bit 6 (new

text in bold).

2. Module: SSP (SPI Slave Mode)

The description of the operation of SPI Slave mode is

clarified as follows:

Before enabling the module in SPI Slave mode, the

state of the clock line (SCK) must match the polarity

selected for the Idle state. The clock line can be

observed by reading the SCK pin. The polarity of the

Idle state is determined by the CKP bit (SSPCON<4>).

This foregoing text should be added to the appropriate

subsections of the “SSP Module” chapter, entitled “SPI

Mode” and read in context with any discussions of SPI

Slave mode.

In the case of DS30234D, the text applies to both

implementations of SPI mode, as described in

Sections 11.2 and 11.3.

Note: This correction applies to the Data Sheets

for the following devices:

• PIC16C62B/72A (DS35008B)

• PIC16C63A/65B/73B/74B (DS30605C)

• PIC16C923/924 (DS30444E)

• PIC16C925/926 (DS39544A)

• PIC16F72 (DS39597B)

• PIC16F73/74/76/77 (DS30325B)

• PIC18F2331/2431/4331/4431

(DS39616B)

In addition, this clarification applies only to

the following devices in the PIC16C6X

Data Sheet (DS30234D):

•PIC16C66

•PIC16C67

In addition, this clarification applies only to

the following devices in the PIC16C7X

Data Sheet (DS30390E):

•PIC16C76

•PIC16C77

Any devices not explicitly listed in this

section do not implement SPI mode and

are not affected by this clarification.

Note: This text refers only to the operation of the

CKE bit in SPI mode; its operation in I2C

mode is unchanged.

Note: This correction applies to the Data Sheets

for the following devices:

• PIC16C6X (DS30234D), except

PIC16C61 (does not implement the

SSP module)

• PIC16C62B/72A (DS35008B)

• PIC16C63A/65B/73B/74B (DS30605C)

• PIC16C72/73/73A/74/74A/76/77

(DS30390E)

• PIC16C923/924 (DS30444E)

• PIC16C925/926 (DS39544A)

• PIC16F72 (DS39597B)

• PIC16F73/74/76/77 (DS30325B)

• PIC18F2331/2431/4331/4431

(DS39616B)

Any other devices not explicitly listed in this

section do not implement SPI mode and

are not affected by this clarification.

bit 6 CKE: SPI Clock Edge Select bit

1 = Transmit occurs on transition from active to Idle clock state

0 = Transmit occurs on transition from Idle to active clock state

Note: Polarity of clock state is set by the CKP bit (SSPCON<4>).

SSP MODULE

3. Module: SSP (I2C Mode) The description of the I2C pins related to the TRIS

bits is clarified. To ensure proper communication

of the I2C Slave mode, the TRIS bits (TRISx [SDA,

SCL]) corresponding to the I2C pins must be set to

‘1’. If any TRIS bits (TRISx<7:0>) of the port con-

taining the I2C pins (PORTx [SDA, SCL]) are

changed in software during I2C communication

using a Read-Modify-Write instruction (BSF, BCF),

then the I2C mode may stop functioning properly

and I2C communication may suspend. Do not

change any of the TRISx bits (TRIS bits of the port

containing the I2C pins) using the instruction BSF

or BCF during I2C communication. If it is absolutely

necessary to change the TRISx bits during

communication, the following method can be

used:

Note: This correction applies to the Data Sheets

for the following devices:

• PIC14000 (DS40122B)

• PIC16C6X (DS30234D) except

PIC16C61 (does not implement SSP

module)

• PIC16C62B/72A (DS35008B)

• PIC16C63A/65B/73B/74B (DS30605C)

• PIC16C72/73/73A/74/74A/76/77

(DS30390E)

• PIC16C923/924 (DS30444E)

• PIC16C925/926 (DS39544A)

• PIC16F72 (DS39597B)

• PIC16F73/74/76/77 (DS30325B)

MOVF TRISC, W ; Example for a 40-pin part such as the PIC16F73

IORLW 0x18 ; Ensures <4:3> bits are ‘11’

ANDLW B’11111001’ ; Sets <2:1> as output, but will not alter other bits

; User can use their own logic here, such as IORLW, XORLW and ANDLW

MOVWF TRISC

SSP MODULE

REVISION HISTORY

Revision A Document (7/2002):

Original version (I2C Slave Issue).

Revision B Document (1/2003):

Clarification of original issue to include Restart

conditions. Addition of data sheet clarification 1 (SPI

Mode, CKE bit).

Revision C Document (3/2003):

Addition of data sheet clarification 2 (SPI Slave Mode,

operation).

Revision D Document (9/2004):

Updated list of affected devices for silicon issue 1 (I2C

– Slave Mode) and 2 (SSP – SPI, Slave Mode),

removed silicon issue 3 (I2C – Slave Mode). Updated

list of affected devices for data sheet clarification 1

(SSP – SPI Mode) and 2 (SSP – SPI Slave Mode).

Added data sheet clarification 3 (SSP – I2C Mode).

Revision E Document (7/2006):

Removed silicon issue 2 (SSP – SPI Slave Mode).

Revision F Document (2/2007):

Added four devices to list of devices affected by the

silicon errata and clarified the related language.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

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intended manner and under normal conditions.

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