SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DWide Operating Voltage Range of 2 V to 6 V
DOutputs Can Drive Up To 10 LSTTL Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 12 ns
D±4-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
DContain Eight Flip-Flops With Single-Rail
Outputs
DDirect Clear Input
DIndividual Data Input to Each Flip-Flop
DApplications Include:
− Buffer/Storage Registers
− Shift Registers
− Pattern Generators
description
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54HC273 ...J OR W PACKAGE
SN74HC273 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
CLR
5Q
5D 8Q
4Q
GND
CLK VCC
SN54HC273 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube of 20 SN74HC273N SN74HC273N
SOIC − DW
Tube of 25 SN74HC273DW
HC273
SOIC − DW Reel of 2000 SN74HC273DWR HC273
−40°C to 85°C
SOP − NS Reel of 2000 SN74HC273NSR HC273
−40°C to 85°CSSOP − DB Reel of 2000 SN74HC273DBR HC273
Tube of 70 SN74HC273PW
TSSOP − PW Reel of 2000 SN74HC273PWR HC273
TSSOP − PW
Reel of 250 SN74HC273PWT
HC273
CDIP − J Tube of 20 SNJ54HC273J SNJ54HC273J
−55°C to 125°CCFP − W Tube of 85 SNJ54HC273W SNJ54HC273W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HC273FK SNJ54HC273FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
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&)$#!" #&(! ! 01 (( &%!%" % !%"!%)
$(%"" !+%-"% !%)* (( !+% &)$#!" &)$#!
&#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"*
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related
directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has
no effect at the output.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
CLR CLK D
OUTPUT
Q
L X X L
H↑HH
H↑LL
H L X Q0
logic diagram (positive logic)
CLK
1D
3
1D
C1
R
1Q
2
2D
4
1D
C1
R
2Q
5
3D
7
1D
C1
R
3Q
6
4D
8
1D
C1
R
4Q
9
5D
13
1D
C1
R
5Q
12
6D
14
1D
C1
R
6Q
15
7D
17
1D
C1
R
7Q
16
8D
18
1D
C1
R
8Q
19
CLR
11
1
logic diagram, each flip-flop (positive logic)
CLK(I)
R
Q
C
C
D
C
C
C
C
C
C
TG TG
TG
TG
C
C
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC273 SN74HC273
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage VCC = 4.5 V 3.15 3.15 V
VIH
High-level input voltage
VCC = 6 V 4.2 4.2
V
VCC = 2 V 0.5 0.5
V
IL
Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VIL
Low-level input voltage
VCC = 6 V 1.8 1.8
V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
∆t/∆vInput transition rise/fall time VCC = 4.5 V 500 500 ns
∆t/∆v
Input transition rise/fall time
VCC = 6 V 400 400
ns
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC273 SN74HC273
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
I
OH
= −20 µA4.5 V 4.4 4.499 4.4 4.4
V
OH
V
I
= V
IH
or V
IL
IOH = −20 µA
6 V 5.9 5.999 5.9 5.9 V
VOH
VI = VIH or VIL
IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84
V
IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
I
OL
= 20 µA4.5 V 0.001 0.1 0.1 0.1
V
OL
V
I
= V
IH
or V
IL
IOL = 20 µA
6 V 0.001 0.1 0.1 0.1 V
VOL
VI = VIH or VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
V
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci2 V to 6 V 3 10 10 10 pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C SN54HC273 SN74HC273
UNIT
V
CC MIN MAX MIN MAX MIN MAX
UNIT
2 V 544
f
clock
Clock frequency 4.5 V 27 18 21 MHz
fclock
Clock frequency
6 V 32 21 25
MHz
2 V 80 120 100
CLR low 4.5 V 16 24 20
tw
Pulse duration
CLR low
6 V 14 20 17
ns
twPulse duration 2 V 80 120 100 ns
CLK high or low 4.5 V 16 24 20
CLK high or low
6 V 14 20 17
2 V 100 150 125
Data 4.5 V 20 30 25
tsu
Setup time before CLK↑
Data
6 V 17 25 21
ns
tsu Setup time before CLK↑2 V 100 150 125 ns
CLR inactive 4.5 V 20 30 25
CLR inactive
6 V 17 25 21
2 V 0 0 0
t
h
Hold time, data after CLK↑4.5 V 0 0 0 ns
th
Hold time, data after CLK
6 V 0 0 0
ns
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 p F (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C SN54HC273 SN74HC273
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 511 4 4
f
max
4.5 V 27 50 18 21 MHz
fmax
6 V 32 60 21 25
MHz
2 V 55 160 240 200
t
PHL
CLR Any 4.5 V 15 32 48 40 ns
tPHL
CLR
Any
6 V 12 27 41 34
ns
2 V 56 160 240 200
t
pd
CLK Any 4.5 V 15 32 48 40 ns
tpd
CLK
Any
6 V 13 27 41 34
ns
2 V 38 75 110 95
t
t
Any 4.5 V 8 15 22 19 ns
tt
Any
6 V 6 13 19 16
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per flip-flop No load 35 pF
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50% VCC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com 29-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-8409901VRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
5962-8409901VSA ACTIVE CFP W 20 25 TBD Call TI N / A for Pkg Type
84099012A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
8409901RA ACTIVE CDIP J 20 1 TBD Call TI Call TI
8409901SA ACTIVE CFP W 20 1 TBD Call TI Call TI
JM38510/65601BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
JM38510/65601BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
M38510/65601BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
M38510/65601BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
SN54HC273J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SN74HC273DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI
SN74HC273DBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273DWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74HC273N3 OBSOLETE PDIP N 20 TBD Call TI Call TI
SN74HC273NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 29-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74HC273NSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273NSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273PW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI
SN74HC273PWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273PWT ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273PWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC273PWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SNJ54HC273FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54HC273J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SNJ54HC273W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com 29-Aug-2012
Addendum-Page 3
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC273, SN54HC273-SP, SN74HC273 :
•Catalog: SN74HC273, SN54HC273
•Automotive: SN74HC273-Q1, SN74HC273-Q1
•Military: SN54HC273
•Space: SN54HC273-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC273DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74HC273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74HC273DWRG4 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74HC273NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
SN74HC273PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74HC273PWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC273DBR SSOP DB 20 2000 367.0 367.0 38.0
SN74HC273DWR SOIC DW 20 2000 600.0 144.0 84.0
SN74HC273DWRG4 SOIC DW 20 2000 367.0 367.0 45.0
SN74HC273NSR SO NS 20 2000 367.0 367.0 45.0
SN74HC273PWR TSSOP PW 20 2000 367.0 367.0 38.0
SN74HC273PWT TSSOP PW 20 250 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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