INTEGRATED CIRCUITS DATA SHEET OM4068 LCD driver for low multiplex rates Product specification File under Integrated Circuits, IC12 1998 Jun 18 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates FEATURES APPLICATIONS * Single-chip LCD controller/driver * Telecom equipment * Static/duplex/triplex drive modes with up to 32/64/96 LCD segments drive capability per device * Portable instruments * Selectable backplane drive configuration: static or 2 or 3 backplane multiplexing * Automotive equipment. * Alarm systems * Selectable display bias configuration drive: static, 12 or 1 3 GENERAL DESCRIPTION The OM4068 is a low-power CMOS LCD driver, designed to drive Liquid Crystal Displays (LCDs) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to three backplanes and up to 32 segment lines and can be easily cascaded for larger LCD applications. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower power consumption. A 3-line bus structure enables serial data transfer with most microprocessors/microcontrollers. All inputs are CMOS compatible. * 32 segment drivers * Serial data input (word length 32 to 96 bits) * On-chip generation of intermediate LCD bias voltages * 2 MHz fast serial bus interface * CMOS compatible * Compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers * May be cascaded for large LCD applications * Logic supply voltage range (VDD - VSS) of 2.5 to 5.5 V * Display supply voltage range (VLCD - VSS) of 3.5 to 6.5 V * Low power consumption, suitable for battery operated systems * No external components needed by the oscillator * Manufactured in silicon gate CMOS process. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION OM4068H(1) QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 OM4068P DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1 OM4068U/5(2) die unsawn wafer - OM4068U tray chip in tray - Notes 1. Gull Wing package. 2. For details see Chapter "Bonding pad locations". 1998 Jun 18 2 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates BLOCK DIAGRAM BP1 handbook, full pagewidth BP2 SEG1 to SEG32(1) BP3 32 DISPLAY SEGMENT OUTPUTS BACKPLANE OUTPUTS 4 M0 M1 4 LCD VOLTAGE SELECTOR (CONTROL LOGIC) DISPLAY LATCH SCE 4 VLCD SCLK BIAS VOLTAGE GENERATOR SHIFT REGISTER SDIN SDOUT OM4068 POWER-ON RESET TIMING GENERATOR OSCILLATOR MBK817 VSS VDD (1) SEG1, SEG6, SEG15 and SEG25 are not available in DIP40 package. Fig.1 Block diagram. 1998 Jun 18 3 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates PINNING See notes 1 to 8. PIN SYMBOL DESCRIPTION QFP44 DIP40 VLCD 4 19 LCD supply voltage VDD 5 20 positive supply voltage VSS 6 21 ground M0 7 22 drive mode select input 0 M1 8 23 drive mode select input 1 SDIN 9 24 serial bus data input SCLK 10 25 serial bus clock input SCE 11 26 serial bus clock enable SDOUT 12 27 serial bus data output BP1 13 28 LCD backplane driver output 1 BP2 14 29 LCD backplane driver output 2 BP3 15 30 LCD backplane driver output 3 SEG1 16 - LCD segment driver output 1 SEG2 17 31 LCD segment driver output 2 SEG3 18 32 LCD segment driver output 3 SEG4 19 33 LCD segment driver output 4 SEG5 20 34 LCD segment driver output 5 SEG6 21 - LCD segment driver output 6 SEG7 22 35 LCD segment driver output 7 SEG8 23 36 LCD segment driver output 8 SEG9 24 37 LCD segment driver output 9 SEG10 25 38 LCD segment driver output 10 SEG11 26 39 LCD segment driver output 11 SEG12 27 40 LCD segment driver output 12 SEG13 28 1 LCD segment driver output 13 SEG14 29 2 LCD segment driver output 14 SEG15 30 - LCD segment driver output 15 SEG16 31 3 LCD segment driver output 16 SEG17 32 4 LCD segment driver output 17 SEG18 33 5 LCD segment driver output 18 SEG19 34 6 LCD segment driver output 19 SEG20 35 7 LCD segment driver output 20 SEG21 36 8 LCD segment driver output 21 SEG22 37 9 LCD segment driver output 22 SEG23 38 10 LCD segment driver output 23 SEG24 39 11 LCD segment driver output 24 SEG25 40 - LCD segment driver output 25 SEG26 41 12 LCD segment driver output 26 1998 Jun 18 4 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates PIN SYMBOL DESCRIPTION QFP44 DIP40 SEG27 42 13 LCD segment driver output 27 SEG28 43 14 LCD segment driver output 28 SEG29 44 15 LCD segment driver output 29 SEG30 1 16 LCD segment driver output 30 SEG31 2 17 LCD segment driver output 31 SEG32 3 18 LCD segment driver output 32 Notes 1. SEG1 to SEG32 (LCD segment driver outputs) output the multi-level signals for the LCD segments. 2. BP0, BP1 and BP2 (LCD backplane driver outputs) output the multi-level signals for the LCD backplanes. 3. VLCD (LCD power supply): power supply for the LCD. 4. SDIN (serial data line): input for the bus data line. 5. SCL (serial clock line): input for the bus clock line. 6. SDOUT (serial data output): output of the shift register to allow serial cascading of the OM4068 with other devices. 7. SCE (serial clock enable): input for enable/disable acquisition on the data input line. If disabled, data on the serial bus are not accepted by the device. 8. M0 and M1 (display mode select inputs): inputs to select the LCD drive configurations; static, duplex or triplex. 1998 Jun 18 5 Philips Semiconductors Product specification OM4068 SEG30 1 33 SEG18 SEG31 2 32 SEG17 SEG32 3 31 SEG16 VLCD 4 30 SEG15 VDD 5 29 SEG14 VSS 6 M0 7 27 SEG12 M1 8 26 SEG11 SDIN 9 25 SEG10 OM4068H 28 SEG13 6 SEG7 22 SEG6 21 SEG5 20 SEG4 19 SEG3 18 SEG2 17 SEG1 16 BP3 15 23 SEG8 BP2 14 SCE 11 BP1 13 24 SEG9 SDOUT 12 SCLK 10 Fig.2 Pin configuration (QFP44). 1998 Jun 18 34 SEG19 35 SEG20 36 SEG21 37 SEG22 38 SEG23 39 SEG24 40 SEG25 41 SEG26 42 SEG27 handbook, full pagewidth 43 SEG28 44 SEG29 LCD driver for low multiplex rates MBK814 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates handbook, halfpage SEG13 1 40 SEG12 SEG14 2 39 SEG11 SEG16 3 38 SEG10 SEG17 4 37 SEG9 SEG18 5 36 SEG8 SEG19 6 35 SEG7 SEG20 7 34 SEG5 SEG21 8 33 SEG4 SEG22 9 32 SEG3 SEG23 10 31 SEG2 OM4068P SEG24 11 30 BP3 SEG26 12 29 BP2 SEG27 13 28 BP1 SEG28 14 27 SDOUT SEG29 15 26 SCE SEG30 16 25 SCLK SEG31 17 24 SDIN SEG32 18 23 M1 VLCD 19 22 M0 VDD 20 21 VSS MBK815 Fig.3 Pin configuration (DIP40). 1998 Jun 18 7 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates The display configurations possible with the OM4068 depend on the number of active backplane outputs required; a selection of display configurations is given in Table 1. FUNCTIONAL DESCRIPTION The OM4068 is a low-power LCD driver designed to interface with any microprocessor/microcontroller and a wide variety of LCDs. It can drive any static or multiplexed LCD containing up to three backplanes and up to 96 segments. Table 1 A typical system (MUX 1 : 3) is shown in Fig.4. Selection of display configurations NUMBER OF 7-SEGMENTS NUMERIC DOT MATRIX BACKPLANES DISPLAY SEGMENTS DIGITS INDICATOR SYMBOLS 3 96 12 12 96 dots (3 x 32) 2 64 8 8 64 dots (2 x 32) 1 32 4 4 32 dots (1 x 32) handbook, full pagewidthV DD SDIN VDD VLCD 32 segment drivers(1) SCLK HOST MICROPROCESSOR/ MICROCONTROLLER SCE OM4068 3 backplanes LCD PANEL (up to 96 elements) MBK818 M1 M0 VSS SDOUT VSS (1) 28 segment drivers for DIP40 package. Fig.4 Typical system configuration. The host microprocessor/microcontroller maintains the 3-line bus communication channel with OM4068. The internal oscillator requires no external components. The appropriate intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip. 1998 Jun 18 The only other connections required to complete the system are to the power supplies (VSS, VDD and VLCD) and suitable capacitors to decouple the VLCD and VDD pins to VSS. 8 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates The bias levels depend on the multiplex rate and are selected automatically when the display configuration is selected using M1 and M0. Power-on reset The on-chip power-on reset block initializes the chip after power-on or power failures. The OM4068 resets to a starting condition as follows: LCD voltage selector * All backplane and segment outputs are set to VSS (display off) The LCD voltage selector (control logic) coordinates the multiplexing of the LCD in accordance with the selected drive or display configuration. The operation of the voltage selector is controlled by the input pins M0 and M1 (see Table 2). * All shift registers and latches are set in 3-state * SDOUT (allowing serial cascading) is set to logic 0 (with SCE LOW) * Power-down mode. Table 2 Data transfers on the serial bus should be avoided for 0.5 ms following power-on to allow completion of the reset action. Power-down After power-on the chip is in power-down mode as long as the serial clock is not active. During power-down all static currents are switched off (no internal oscillator, no timing and no bias level generation) and all LCD-outputs are 3-stated. The power-on reset functions remain enabled. M1 M0 DRIVE MODE 0 0 test mode (not user accessible) 0 1 static drive (1 : 1) 1 0 duplex drive (1 : 2) 1 1 triplex drive (1 : 3) For multiplex rates of 1 : 2 three bias levels are used including VLCD and VSS. Four bias level are used for the 1 : 3 multiplex rate. The various biasing configurations together with the biasing characteristics as functions of VOP = VLCD - VSS and the resulting discrimination ratios (D), are given in Table 3. The power-down mode is disabled at the first rising edge of the serial clock SCLK. LCD bias voltage generator A practical value for VOP is determinated by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In static mode a suitable choice is VOP > 3Vth. The intermediate bias voltages for the LCD display are generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system power consumption. The full-scale LCD voltage VOP equals VLCD - VSS. The optimum value of VOP depends on the LCD threshold voltage (Vth) and the number of bias levels. Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors (13bias) connected between VLCD and VSS. The centre resistor can be switched out of the circuit to provide a 12bias voltage level for the 1 : 2 multiplex configuration. 1998 Jun 18 Drive mode selection 9 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates Table 3 LCD drive modes: summary of characteristics NUMBER OF LCD DRIVE MODE BACKPLANES Static 1 1:2 1:3 LEVELS LCD BIAS CONFIGURATION V off ( rms ) ----------------------V OP V on ( rms ) ----------------------V OP V on ( rms ) D = ---------------------V off ( rms ) 2 static 0 1 - 3 1 2 0.354 0.791 2.2236 4 1 3 0.333 0.638 1.915 2 3 LCD drive mode waveforms The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig.5. Tframe handbook, full pagewidth VLCD BP1 VSS SEG - BP1 VLCD VLCD 0V SEG N (off) VSS -VLCD VLCD VLCD SEG N + 1 (on) VSS 0V -VLCD MBK819 BACKPLANE DRIVER OUTPUT BP1 SEGMENTS SEG N off SEG N + 1 on Fig.5 Static drive mode waveforms (VOP = VLCD - VSS). 1998 Jun 18 10 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates 1 : 2 MULTIPLEX DRIVE MODE When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies, as shown in Fig.6. Tframe VLCD handbook, full pagewidth BP1 1/2VLCD VSS VLCD BP2 1/2VLCD SEG - BP1 VSS SEG N 1/2VLCD VSS VLCD SEG N + 1 1/2VLCD VSS VLCD SEG N + 2 0V 0V -1/2VLCD -1/2VLCD -VLCD -VLCD VLCD 1/2VLCD VLCD 1/2VLCD 0V 0V -1/2VLCD -1/2VLCD -VLCD -VLCD VLCD 1/2VLCD VLCD 1/2VLCD 1/2VLCD 0V 0V VSS -1/2VLCD -1/2VLCD -VLCD -VLCD VLCD 1/2VLCD VLCD 1/2VLCD VLCD SEG N + 3 VLCD 1/2VLCD VLCD 1/2VLCD VLCD SEG - BP2 1/2VLCD VSS 0V 0V -1/2VLCD -1/2VLCD -VLCD -VLCD Tframe BACKPLANE DRIVER OUTPUTS MBK820 Tframe SEGMENTS SEG N SEG N + 1 SEG N + 2 SEG N + 3 BP1 off on off on BP2 off off on on Fig.6 Waveforms for 1 : 2 multiplex drive mode (VOP = VLCD - VSS). 1 : 3 MULTIPLEX DRIVE MODE When three backplanes are provided in the LCD, the 1 : 3 multiplex mode applies, as shown in Fig.7. 1998 Jun 18 11 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates handbook, full pagewidth SEG N SEG N + 1 SEG N + 2 SEG N + 3 SEG N + 4 SEG N + 5 SEG N + 6 SEG N + 7 Tframe Tframe Tframe Tframe VLCD VLCD VLCD VLCD 2/3VLCD 1/3VLCD VSS 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD -VLCD -VLCD -VLCD VLCD VLCD VLCD VLCD 2/3VLCD 1/3VLCD VSS 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD -VLCD -VLCD -VLCD VLCD VLCD VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD -VLCD -VLCD -VLCD VLCD VLCD VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD -VLCD -VLCD -VLCD VLCD VLCD VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD -VLCD -VLCD -VLCD VLCD VLCD VLCD VLCD 2/3VLCD 1/3VLCD VSS 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD -VLCD -VLCD -VLCD VLCD VLCD VLCD VLCD 2/3VLCD 1/3VLCD VSS 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD -VLCD -VLCD -VLCD VLCD VLCD VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD 2/3VLCD 0V -2/3VLCD -VLCD -VLCD -VLCD VLCD 2/3VLCD 1/3VLCD VSS VLCD 2/3VLCD 1/3VLCD VSS VLCD 2/3VLCD 1/3VLCD VSS VLCD 2/3VLCD 1/3VLCD VSS SEG - BP1 BACKPLANE DRIVER OUTPUTS VLCD 2/3VLCD 1/3VLCD VSS VLCD 2/3VLCD 1/3VLCD VSS MBK821 SEG - BP3 SEG - BP2 VLCD 2/3VLCD 1/3VLCD VSS BP1 BP2 SEGMENTS N N+1 N+2 N+3 N+4 N+5 N+6 N+7 BP1 off on off on off on off on BP2 off off on on off off on on BP3 off off off off on on on on Fig.7 Waveforms for 1 : 3 multiplex drive motive (VOP = VLCD - VSS). 1998 Jun 18 12 BP3 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates Oscillator Interface to microprocessor unit: serial interface The internal logic and the multi-level LCD drive signals of the OM4068 are generated by the built-in RC oscillator. No external components are required. A three-line bus structure enables serial unidirectional data transfer with microprocessors/microcontrollers. The three lines are a serial data input line (SDIN), a serial clock line (SCLK) and a data line enable (SCE). All inputs are CMOS compatible. These lines must always be in a defined state VSS or VDD. Floating inputs could damage the chip. In order to minimize radio frequency interference, the oscillator operates with symmetrical and slew-rate limited capacitor charge/discharge. The oscillator runs continuously once the power down state after power-on has been left. handbook, full pagewidth On the bus, one data bit is transferred during each clock pulse. The data on the SDIN line remains stable during the whole clock period. Data changes arrive with the falling edge of the serial clock SCLK (see Fig.8). SDIN SDOUT SCLK data line stable; data valid change of data allowed MBK822 Fig.8 Bit transfer on bus. numbers and the LCD display segments is shown in Table 4. Shift register Data present on the SDIN pin is shifted into a shift register with the rising edge of the serial clock SCLK in a synchronous manner. The shift register serves to transfer display information from the serial bus to the (display) latch while previous data is displayed. Data from the last stage of the register is supplied to the SDOUT pin to allow serial cascading of the OM4068 with other peripheral devices. Depending on the display driving mode selected, SDOUT corresponds to bit 32, 64 or 96 of the register (see Fig.10). Data on the SDOUT pin is shifted out with the falling edge of the SCLK clock. SDOUT is therefore delayed by 12SCLK cycle before it is applied to the SDIN pin of the next IC in the serial chain (see Fig.8). The shift register is organized as three 32-bit shift registers. Depending on the display driving mode selected (see Table 3), one, two or three registers are used and cascaded resulting in a shift register length of 32, 64 or 96 bits. Figure 9 shows the shift register organization with the display data bits after a shift operation is completed. The shift sequence begins with data bit D32 and finishes with data bit D1. The correspondence between the data bit The clock enable SCE signal must be HIGH in order to enable the shift operation. SDOUT output is latched with the last data after SCE returned to HIGH (shift operation terminated). SDOUT is in 3-state mode when SCE is LOW. 1998 Jun 18 13 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates Display latch Timing The 96-bit display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch and the LCD segment outputs. An LCD segment is activated when the corresponding data bit in the display latch is HIGH. The timing of the OM4068 organizes the internal data flow of the device. This includes the transfer of display data from the shift register to the display segments outputs. The timing also generates the LCD frame frequency which is derived from the clock frequency generated in the internal clock generator: f osc f fr(LCD) = -----------2400 Display latches are in HOLD mode (SCE HIGH) during the shift operation to maintain the display data constant. Data are latched into the display latch with the internal frame clock. Thus there is a delay of up to one half frame before new data are latched after signal SCE returns to zero. Shift register configuration handbook, full pagewidth 32 1 64 96 96-bit shift register 32-bit register SDIN D1A SDOUT D32A driving mode: static; (M1, M0) = 01 32-bit register SDIN D1A 32-bit register D32A D1B SDOUT D32B driving mode: duplex (1 : 2); (M1, M0) = 10 32-bit register SDIN D1A 32-bit register D32A D1B 32-bit register D32B D1C driving mode: triplex (1 : 3); (M1, M0) = 11 Fig.9 Display data bit position in shift register. 1998 Jun 18 14 SDOUT D32C MBK823 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates handbook, full pagewidth SDIN D32A D32B D32C M0 MUX M1 SCLK SDOUT Fig.10 Shift register structure. 1998 Jun 18 15 MBK825 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates Table 4 Relationships between data bit numbers and the LCD segment outputs DRIVING MODE SEGMENT NUMBER STATIC SEG1 D1A D1A D1B D1A D1B D1C SEG2 D2A D2A D2B D2A D2B D2C SEG3 D3A D3A D3B D3A D3B D3C SEG4 D4A D4A D4B D4A D4B D4C SEG5 D5A D5A D5B D5A D5B D5C SEG6 D6A D6A D6B D6A D6B D6C SEG7 D7A D7A D7B D7A D7B D7C SEG8 D8A D8A D8B D8A D8B D8C SEG9 D9A D9A D9B D9A D9B D9C SEG10 D10A D10A D10B D10A D10B D10C DUPLEX TRIPLEX SEG11 D11A D11A D11B D11A D11B D11C SEG12 D12A D12A D12B D12A D12B D12C SEG13 D13A D13A D13B D13A D13B D13C SEG14 D14A D14A D14B D14A D14B D14C SEG15 D15A D15A D15B D15A D15B D15C SEG16 D16A D16A D16B D16A D16B D16C SEG17 D17A D17A D17B D17A D17B D17C SEG18 D18A D18A D18B D18A D18B D18C SEG19 D19A D19A D19B D19A D19B D19C SEG20 D20A D20A D20B D20A D20B D20C SEG21 D21A D21A D21B D21A D21B D21C SEG22 D22A D22A D22B D22A D22B D22C SEG23 D23A D23A D23B D23A D23B D23C SEG24 D24A D24A D24B D24A D24B D24C SEG25 D25A D25A D25B D25A D25B D25C SEG26 D26A D26A D26B D26A D26B D26C SEG27 D27A D27A D27B D27A D27B D27C SEG28 D28A D28A D28B D28A D28B D28C SEG29 D29A D29A D29B D29A D29B D29C SEG30 D30A D30A D30B D30A D30B D30C SEG31 D31A D31A D31B D31A D31B D31C SEG32 D32A D32A D32B D32A D32B D32C Segment outputs The LCD drive section includes 32 segment outputs SEG1 to SEG32 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplex backplane signals and with data in the display latch. When less than 32 segments are required the unused segment outputs should be left open-circuit. 1998 Jun 18 16 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates Backplane outputs The LCD drive section includes three backplane outputs (BP1 to BP3) which should be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than three backplane outputs are required the unused outputs should be left open-circuit. In 1 : 2 multiplex drive mode, BP3 is set to 12VLCD. In static drive mode BP3 and BP2 are set to VSS. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage -0.5 +6.5 V VLCD LCD supply voltage -0.5 +7.5 V VI input voltage (any input) -0.5 VDD + 0.5 V VO output voltage (BP1, BP2, BP3, S1 to S32 and VLCD) -0.5 VLCD + 0.5 V II DC input current -10 +10 mA IO DC output current -10 +10 mA IDD, ISS, ILCD VDD, VSS or VLCD current -50 +50 mA Ptot(pack) total power dissipation per package - 500 mW P/out power dissipation per output - 10 mW Tamb operating ambient temperature -40 +105 C Tstg storage temperature -65 +150 C Tj junction temperature - 150 C Ves electrostatic handling note 1 -2000 +2000 V note 2 -150 +150 V Notes 1. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor (human body model). 2. Equivalent to discharging a 200 pF capacitor via a 0.75 H series inductor (machine model). HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices"). 1998 Jun 18 17 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates DC CHARACTERISTICS VDD = 2.5 to 5.5 V; VSS = 0 V; VLCD = 3.5 to 6.5 V; Tamb = -40 to +105 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage VSS + 2.5 - 5.5 V VLCD LCD supply voltage VSS + 3.5 - 6.5 V IDD supply current power-down state; note 1 - 4 10 A normal mode; fosc = intern; notes 2 and 3 - 12 25 A power-down state; note 1 - - 1.5 A normal mode; fosc = intern; notes 3 and 4 - - 40 A note 5 0.8 1.25 1.6 V ILCD VPOR VLCD current power-on reset voltage level Logic VIL LOW-level input voltage VSS - 0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD V IOL LOW-level output current (SDOUT) VOL = 0.5 V; VDD = 5 V 1.0 - - mA IOH HIGH-level output current (SDOUT) VOH = VDD - 0.5 V; VDD = 5 V - - -1 mA Ipu pull-up current M1 and M0 VI = VSS 0.04 0.15 1 A IL leakage current VI = VDD or VSS -1 - +1 A Segment and backplane outputs R(o)seg segment output resistance SEG1 to SEG32 note 6 - 15 40 k R(o)back backplane output resistance BP1 to BP3 note 6 - 15 40 k Vseg(bias)(tol) bias tolerance SEG1 to SEG32 note 7 -100 0 +100 mV note 7 -100 0 +100 mV Vback(bias)(tol) bias tolerance BP1, BP2 and BP3 Notes 1. Power-down state. After power-on the chip is in power-down state as long as the serial clock is not activated. During power-down all static currents are switched off except the power-on reset block. 2. Output SDOUT is open-circuit; inputs at VDD or VSS; bus inactive. 3. Drive mode: static, duplex and triplex. 4. LCD outputs are open-circuit, CL = 50 pF typical, inputs at VDD or VSS; bus inactive. 5. Resets all logic when VDD < VPOR. 6. Resistance of output terminal (S1 to S32 and BP1, BP2 and BP3) with a load current of 20 A; outputs measured one at a time. 7. LCD outputs open-circuits. 1998 Jun 18 18 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates AC CHARACTERISTICS VDD = 2.5 to 5.5 V; VSS = 0 V; VLCD = 5.0 V; Tamb = -40 to +105 C; unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT ffr(LCD) LCD frame frequency (internal clock) 50 84 175 Hz fosc oscillator frequency (not available at any pin) 116 224 405 kHz Bus timing characteristics: serial bus interface; note 1 fSCLK SCLK clock frequency 0 - 2.1 MHz tSCLKL SCLK clock LOW period 190 - - ns tSCLKH SCLK clock HIGH period 190 - - ns tsu(D) data set-up time 100 - - ns th(D) data hold time 100 - - ns tr SCLK, SDIN rise time - 10 - ns tf SCLK, SDIN fall time - 10 - ns tsu(en)(SDEH-SCLKH) enable set-up time (SDE HIGH to SCLK HIGH) 250 - - ns tsu(dis)(SCLKL-SDEL) disable set-up time (SCLK LOW to SDE LOW) 250 - - ns 100 - - ns tPHL(SDOUT) SDOUT HIGH-to-LOW propagation delay Note 1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. handbook, full pagewidth SDOUT tSCLKH tSCLKL tPHL(SDOUT) tr tf SCLK th(D) tsu(D) SDIN tsu(en)(SDEH-SCLKH) tsu(dis)(SCLKL-SDEL) SCE MBK824 Fig.11 Serial data timing. 1998 Jun 18 19 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates 2.01 mm SEG31 2 SEG32 3 VLCD 4 VDD 5 VSS SEG20 SEG19 SEG21 SEG22 SEG26 SEG23 SEG27 SEG24 SEG28 SEG25 SEG29 handbook, full pagewidth SEG30 BONDING PAD LOCATIONS 1 44 43 42 41 40 39 38 37 36 35 34 OM4068 6 M0 7 M1 8 SDIN 9 21 22 SEG6 SEG18 32 SEG17 31 SEG16 30 SEG15 29 SEG14 28 SEG13 27 SEG12 26 SEG11 25 SEG10 24 SEG9 23 SEG8 SEG7 20 SEG5 SEG4 SEG3 15 16 17 18 19 SEG2 14 SEG1 13 BP3 y 12 BP2 0 11 BP1 0 SDOUT x SCE SCLK 10 33 2.03 mm MBK816 Dimensions in mm. Bonding pad dimensions: 80 x 80 m. Fig.12 Bonding pad locations. 1998 Jun 18 20 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates Table 5 Bonding pad locations (dimensions in m). All x/y coordinates are referenced to bottom left corner of chip (see Fig.12). SYMBOL PAD x SYMBOL y PAD x y VDD 5 43.100 970.500 SEG28 43 550.550 1711.100 VSS 6 42.900 791.850 SEG29 44 430.550 1711.100 M0 7 43.100 661.750 SEG30 1 300.550 1711.100 2 43.100 1460.050 M1 8 43.100 531.750 SEG31 SDIN 9 43.100 401.750 SEG32 3 43.100 1274.950 SCLK 10 43.100 271.750 VLCD 4 43.100 1158.700 SCE 11 310.450 43.100 Alignment marks SDOUT 12 447.350 43.100 C1 - 1769.6 1696.9 BP1 13 604.800 43.100 C2 - 1770.1 58.4 BP2 14 714.850 43.100 F - 172.0 1705.2 BP3 15 824.850 43.100 SEG1 16 924.850 43.100 SEG2 17 1024.850 43.100 SEG3 18 1124.850 43.100 SEG4 19 1224.850 43.100 SEG5 20 1327.250 43.100 SEG6 21 1432.450 43.100 SEG7 22 1532.650 43.100 SEG8 23 1783.600 293.850 SEG9 24 1783.600 458.850 SEG10 25 1783.600 603.850 SEG11 26 1783.600 703.850 SEG12 27 1783.600 803.850 SEG13 28 1783.600 903.850 SEG14 29 1783.600 1003.850 SEG15 30 1783.600 1103.850 SEG16 31 1783.600 1203.850 SEG17 32 1783.600 1323.850 SEG18 33 1783.600 1453.850 SEG19 34 1514.600 1711.100 SEG20 35 1370.550 1711.100 SEG21 36 1270.500 1711.100 SEG22 37 1170.500 1711.100 SEG23 38 1070.500 1711.100 SEG24 39 970.550 1711.100 SEG25 40 870.550 1711.100 SEG26 41 770.550 1711.100 SEG27 42 660.550 1711.100 1998 Jun 18 21 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates PACKAGE OUTLINES QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT307-2 1998 Jun 18 EUROPEAN PROJECTION 22 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates seating plane DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 ME D A2 L A A1 c e Z w M b1 (e 1) b MH 21 40 pin 1 index E 1 20 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.7 0.51 4.0 1.70 1.14 0.53 0.38 0.36 0.23 52.50 51.50 inches 0.19 0.020 0.16 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 D (1) e e1 L ME MH w Z (1) max. 14.1 13.7 2.54 15.24 3.60 3.05 15.80 15.24 17.42 15.90 0.254 2.25 0.56 0.54 0.10 0.60 0.14 0.12 0.62 0.60 0.69 0.63 0.01 0.089 E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT129-1 051G08 MO-015AJ 1998 Jun 18 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-14 23 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. REPAIRING SOLDERED JOINTS If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. QFP REFLOW SOLDERING Reflow soldering techniques are suitable for all QFP packages. 1998 Jun 18 24 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Jun 18 25 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates NOTES 1998 Jun 18 26 Philips Semiconductors Product specification OM4068 LCD driver for low multiplex rates NOTES 1998 Jun 18 27 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 415106/1200/01/pp28 Date of release: 1998 Jun 18 Document order number: 9397 750 03802