Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5607B Rev. 5, 08/2010 MPC5607B 100 LQFP 14 mm x 14 mm MPC5607B Microcontroller Data Sheet * Single issue, 32-bit CPU core complex (e200z0h) - Compliant with the Power Architecture(R) technology embedded category - Enhanced instruction set allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. * Up to 1.5 MB on-chip code flash memory supported with the flash memory controller * 64 (4 x 16) KB on-chip data flash memory with ECC * Up to 96 KB on-chip SRAM * Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity on certain family members (Refer to Table 1 for details.) * Interrupt controller (INTC) capable of handling 204 selectable-priority interrupt sources * Frequency modulated phase-locked loop (FMPLL) * Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters * 16-channel eDMA controller with multiple transfer request sources using DMA multiplexer * Boot assist module (BAM) supports internal Flash programming via a serial link (CAN or SCI) * Timer supports I/O channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS) * 2 analog-to-digital converters (ADC): one 10-bit and one 12-bit * Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the eMIOS or PIT * Up to 6 serial peripheral interface (DSPI) modules * Up to 10 serial communication interface (LINFlex) modules * Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers * 1 inter-integrated circuit (I2C) interface module (c) Freescale Semiconductor, Inc., 2010. All rights reserved. 176 LQFP 24 mm x 24 mm 144 LQFP 20 mm x 20 mm 208 MAPBGA 17 mm x 17 mm * Up to 149 configurable general purpose pins supporting input and output operations (package dependent) * Real-Time Counter (RTC) - Clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds - Optional support for RTC with clock source from external 32 kHz crystal oscillator, supporting wakeup with 1 sec resolution and maximum timeout of 1 hour * Up to 8 periodic interrupt timers (PIT) with 32-bit counter resolution * Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus * Device/board boundary scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) * On-chip voltage regulator (VREG) for regulation of input supply for all internal levels Table of Contents 1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7 3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .31 4.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.2.1 NVUSRO[PAD3V5V] field description . . . . . . . .31 4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description 32 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .32 4.4 Recommended operating conditions . . . . . . . . . . . . . .33 4.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .36 4.5.1 External ballast resistor recommendations . . . .36 4.5.2 Package thermal characteristics . . . . . . . . . . . .36 4.5.3 Power considerations. . . . . . . . . . . . . . . . . . . . .37 4.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .38 4.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . .38 4.6.3 I/O output DC characteristics. . . . . . . . . . . . . . .39 4.6.4 Output pin transition times . . . . . . . . . . . . . . . . .42 4.6.5 I/O pad current specification . . . . . . . . . . . . . . .42 4.7 RESET electrical characteristics. . . . . . . . . . . . . . . . . .49 4.8 Power management electrical characteristics. . . . . . . .51 4.8.1 Voltage regulator electrical characteristics . . . .51 4.8.2 Voltage monitor electrical characteristics. . . . . .53 4.9 Low voltage domain power consumption . . . . . . . . . . .55 4.10 Flash memory electrical characteristics . . . . . . . . . . . .56 4.10.1 Program/erase characteristics . . . . . . . . . . . . . .56 4.10.2 Flash power supply DC characteristics . . . . . . .58 5 6 7 4.10.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 59 4.11 Electromagnetic compatibility (EMC) characteristics. . 59 4.11.1 Designing hardened software to avoid noise problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.11.2 Electromagnetic interference (EMI) . . . . . . . . . 59 4.11.3 Absolute maximum ratings (electrical sensitivity)60 4.12 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.13 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 65 4.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 68 4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.17.2 Input impedance and ADC accuracy . . . . . . . . 69 4.17.3 ADC electrical characteristics . . . . . . . . . . . . . 74 4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 79 4.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 81 4.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 87 4.18.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 88 Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 90 5.1.1 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.1.2 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.1.3 100 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1.4 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . . 98 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 MPC5607B Microcontroller Data Sheet, Rev. 5 2 Freescale Semiconductor Introduction 1 Introduction 1.1 Document overview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. 1.2 Description This family of 32-bit system-on-chip (SoC) microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient e200z0 host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (Auxiliary Processor Unit), providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. Table 1. MPC5607B family comparison1 MPC5605B Feature MPC5606B CPU MPC5607B e200z0h Execution speed2 Up to 64 MHz Code Flash 768 KB 1 MB Data Flash 64 (4 x 16) KB SRAM 64 KB 80 KB MPU 8-entry eDMA 16 ch 10-bit ADC 96 KB Yes 3 dedicated 7 ch 15 ch 29 ch shared with 12-bit ADC 15 ch 29 ch 19 ch 12-bit ADC Yes dedicated4 5 ch shared with 10-bit ADC 19 ch Total timer eMIOS 1.5 MB I/O5 37 ch, 16-bit 64 ch, 16-bit Counter / OPWM / ICOC6 10 ch O(I)PWM / OPWFMB / OPWMCB / ICOC7 7 ch O(I)PWM / ICOC8 7 ch 14 ch OPWM / ICOC9 13 ch 33 ch SCI (LINFlex) 4 6 8 6 SPI (DSPI) 3 5 6 5 8 10 6 MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 3 Introduction Table 1. MPC5607B family comparison1 (continued) MPC5605B Feature MPC5606B CAN (FlexCAN) 6 2 I C 1 32 kHz oscillator GPIO10 Yes 77 121 149 Debug Package MPC5607B 121 149 149 JTAG 100 LQFP 144 LQFP 176 LQFP N2+ 144 LQFP 176 LQFP 176 LQFP 208 MAP BGA11 1 Feature set dependent on selected peripheral multiplexing; table shows example. Based on 105 C ambient operating temperature. 3 Not shared with 12-bit ADC, but possibly shared with other alternate functions. 4 Not shared with 10-bit ADC, but possibly shared with other alternate functions. 5 Refer to eMIOS section of device reference manual for information on the channel configuration and functions. 6 Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare. 7 Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare. 8 Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse width measurement. 9 Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare. 10 Maximum I/O count based on multiplexing with peripherals. 11 208 MAPBGA available only as development package for Nexus2+. 2 MPC5607B Microcontroller Data Sheet, Rev. 5 4 Freescale Semiconductor Block diagram 2 Block diagram Figure 1shows a top-level block diagram of the MPC5607B. SRAM 96 KB eDMA JTAG JTAG Port Code Flash 1.5 MB Data Flash 64 KB e200z0h Nexus (Master) Data NMI Nexus 2+ (Master) SIUL Voltage Regulator Interrupt requests from peripheral blocks NMI INTC Clocks SRAM Controller MPU Instructions Nexus Port 64-bit 2 x 3 Crossbar Switch (Master) Flash Controller (Slave) (Slave) Interrupt request with wakeup functionality (Slave) MPU Registers WKPU CMU FMPLL RTC STM SWT ECSM MC_RGM PIT MC_CGM MC_ME MC_PCU BAM SSCM I2C 6x FlexCAN Peripheral Bridge Interrupt Request SIUL Reset Control 19 ch 10-bit/12-bit ADC External Interrupt Request 29 ch 10-bit ADC 10 x LINFlex 64 ch eMIOS CTU 6x DSPI 5 ch 12-bit ADC IMUX GPIO & Pad Control I/O ... ... ... ... ... Legend: ADC BAM CMU CTU DSPI ECSM eDMA eMIOS Flash FlexCAN FMPLL I2C IMUX INTC JTAG LINFlex Analog-to-Digital Converter Boot Assist Module Clock Monitor Unit Cross Triggering Unit Deserial Serial Peripheral Interface Error Correction Status Module Enhanced Direct Memory Access Enhanced Modular Input Output System Flash memory Controller Area Network Frequency-Modulated Phase-Locked Loop Inter-Integrated Circuit bus Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support) MC_CGM MC_ME MC_PCU MC_RGM MPU NMI PIT RTC SIUL SRAM SSCM STM SWT WKPU XBAR Clock Generation Module Mode Entry Module Power Control Unit Reset Generation Module Memory Protection Unit Non-Maskable Interrupt Periodic Interrupt Timer Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Wakeup Unit Crossbar switch Figure 1. MPC5607B block diagram MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 5 Block diagram Table 2 summarizes the functions of the blocks present on the MPC5607B. Table 2. MPC5607B series block summary Block Function Analog-to-digital converter (ADC) Converts analog voltages to digital values Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Clock generation module (MC_CGM) Provides logic and control required for the generation of system and peripheral clocks Clock monitor unit (CMU) Monitors clock source (internal and external) integrity Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Crossbar switch (XBAR) Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices (DSPI) Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor (eDMA) via "n" programmable channels Enhanced modular input output system (eMIOS) Provides the functionality to generate or measure events Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Flash memory Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol Frequency-modulated phase-locked loop (FMPLL) Generates high-speed system clocks and supports programmable frequency modulation Inter-integrated circuit (I2CTM) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Internal multiplexer (IMUX) SIU subblock Allows flexible mapping of peripheral interface on the different pins of the device Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode LINFlex controller Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Memory protection unit (MPU) Provides hardware access control for all memory references generated in a device Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and modetransition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications MPC5607B Microcontroller Data Sheet, Rev. 5 6 Freescale Semiconductor Package pinouts and signal descriptions Table 2. MPC5607B series block summary (continued) Block Function Non-Maskable Interrupt (NMI) Handles external events that must produce an immediate response, such as power down detection Periodic interrupt timer (PIT) Produces periodic interrupts and triggers Power control unit (MC_PCU) Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called "power domains" which are controlled by the PCU Real-time counter (RTC) A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) Reset generation module (MC_RGM) Centralizes reset sources and manages the device reset sequence of the device Static random-access memory (SRAM) Provides storage for program code, constants, and variables System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration System status and configuration module (SSCM) Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable System timer module (STM) Provides a set of output compare events to support AUTOSAR (AUTomotive Open System ARchitecture) and operating system tasks System watchdog timer (SWT) Provides protection from runaway code WKPU (wakeup unit) The wakeup unit supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. 3 Package pinouts and signal descriptions 3.1 Package pinouts The available LQFP pinouts and the ballmap are provided in the following figures. For pin signal descriptions, please see Table 3. Figure 2 shows the MPC5607B in the 176 LQFP package. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 LQFP Top view 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PI[13] PI[12] PI[11] PI[10] PI[9] PI[8] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] VDD_HV_ADC1 VSS_HV_ADC1 PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC0 VSS_HV_ADC0 PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PJ[3] PJ[2] PJ[1] PJ[0] PI[15] PI[14] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] VDD_HV VSS_HV PD[8] PB[4] 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PB[3] PC[9] PC[14] EPC[15] PJ[4] VDD_HV VSS_HV PH[15] PH[13] PH[14] PI[6] PI[7] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PB[2] PC[8] PC[13] PC[12] PI[0] PI[1] PI[2] PI[3] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PI[4] PI[5] PH[12] PH[11] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] Package pinouts and signal descriptions Figure 2. 176 LQFP pin configuration (top view) MPC5607B Microcontroller Data Sheet, Rev. 5 8 Freescale Semiconductor Package pinouts and signal descriptions 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] Figure 3 shows the MPC5607B in the 144 LQFP package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 LQFP Top view 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] VDD_HV_ADC1 VSS_HV_ADC1 PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC0 VSS_HV_ADC0 PB[3] PC[9] PC[14] PC[15] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PB[3] PC[9] PC[14] PC[15] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] Figure 3. 144 LQFP pin configuration (top view) MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 9 Package pinouts and signal descriptions 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PE[12] Figure 4 shows the MPC5607B in the 100 LQFP package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 LQFP Top view 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] VDD_HV_ADC1 VSS_HV_ADC1 PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC0 VSS_HV_ADC0 PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[11] PC[10] PB[0] PB[1] PC[6] Figure 4. 100 LQFP pin configuration (top view) Figure 5 shows the MPC5607B in the 208 MAPBGA package. MPC5607B Microcontroller Data Sheet, Rev. 5 10 Freescale Semiconductor Package pinouts and signal descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A PC[8] PC[13] PH[15] PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[15] PH[11] NC NC A B PC[9] PB[2] PH[13] PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] PI[2] PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B C PC[14] PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] PI[3] PA[5] PI[5] PE[14] PE[12] PA[9] PA[8] C D PH[14] PI[6] PC[15] PI[7] PH[6] PE[4] PE[2] VDD_LV VDD_HV NC PA[6] PH[12] PG[10] PF[14] PE[13] PA[7] D E PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_HV E F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F G PE[9] PE[8] PE[10] PA[0] VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV PI[12] PI[13] MSEO G H VSS_HV PE[11] VDD_HV NC VSS_HV VSS_HV VSS_HV VSS_HV MDO3 MDO2 MDO0 MDO1 H J RESET VSS_LV NC NC VSS_HV VSS_HV VSS_HV VSS_HV PI[8] PI[9] PI[10] PI[11] J K EVTI NC VDD_BV VDD_LV VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV _ADC1 PG[12] PA[3] PG[13] K L PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L M PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M N PB[1] PF[9] PB[0] VDD_HV PJ[0] PA[4] VSS_LV EXTAL VDD_HV PF[0] PF[4] VSS_HV _ADC1 PB[11] PD[10] PD[9] PD[11] N P PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[14] VDD_LV XTAL PB[10] PF[1] PF[5] PD[0] PD[3] VDD_HV _ADC0 PB[6] PB[7] P R PF[12] PC[6] PF[10] PF[11] VDD_HV PA[15] PA[13] PI[14] XTAL32 PF[3] PF[7] PD[2] PD[4] PD[7] VSS_HV _ADC0 PB[5] R T NC NC NC MCKO NC PF[13] PA[12] PI[15] EXTAL 32 PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD_HV NOTE: The 208 MAPBGA is available only as development package for Nexus 2+. NC = Not connected Figure 5. 208 MAPBGA configuration MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 11 Package pinouts and signal descriptions 3.2 Pin muxing Table 3 defines the pin list and muxing for this device. Each entry of Table 3 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is indicated by AF0. Pad type RESET config.2 Pin No. I/O direction Peripheral Table 3. Functional port pin descriptions PA[0] PCR[0] AF0 AF1 AF2 AF3 -- GPIO[0] E0UC[0] CLKOUT E0UC[13] WKUP[19]4 SIUL eMIOS_0 MC_CGM eMIOS_0 WKUP I/O I/O O I/O I M Tristate 12 16 24 G4 PA[1] PCR[1] AF0 AF1 AF2 AF3 -- GPIO[1] E0UC[1] NMI5 -- WKUP[2]4 SIUL eMIOS_0 WKUP -- WKUP I/O I/O I -- I S Tristate 7 11 19 F3 PA[2] PCR[2] AF0 AF1 AF2 AF3 -- GPIO[2] E0UC[2] -- MA[2] WKUP[3]4 SIUL eMIOS_0 -- ADC_0 WKUP I/O I/O -- O I S Tristate 5 9 17 F2 PA[3] PCR[3] AF0 AF1 AF2 AF3 -- -- GPIO[3] E0UC[3] LIN5TX CS4_1 EIRQ[0] ADC1_S[0] SIUL eMIOS_0 LINFlex_5 DSPI_1 SIUL ADC_1 I/O I/O O O I I J Tristate 68 90 114 K15 PA[4] PCR[4] AF0 AF1 AF2 AF3 -- -- GPIO[4] E0UC[4] -- CS0_1 LIN5RX WKUP[9]4 SIUL eMIOS_0 -- DSPI_1 LINFlex_5 WKUP I/O I/O -- I/O I I S Tristate 29 43 51 N6 PA[5] PCR[5] AF0 AF1 AF2 AF3 GPIO[5] E0UC[5] LIN4TX -- SIUL eMIOS_0 LINFlex_4 -- I/O I/O O -- M Tristate 79 118 146 C11 PA[6] PCR[6] AF0 AF1 AF2 AF3 -- -- GPIO[6] E0UC[6] -- CS1_1 EIRQ[1] LIN4RX SIUL eMIOS_0 -- DSPI_1 SIUL LINFlex_4 I/O I/O -- O I I S Tristate 80 119 147 D11 Port pin PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 Port A MPC5607B Microcontroller Data Sheet, Rev. 5 12 Freescale Semiconductor Package pinouts and signal descriptions GPIO[7] E0UC[7] LIN3TX -- EIRQ[2] ADC1_S[1] SIUL eMIOS_0 LINFlex_3 -- SIUL ADC_1 I/O I/O O -- I I PCR[8] AF0 AF1 AF2 AF3 -- N/A6 -- GPIO[8] E0UC[8] E0UC[14] -- EIRQ[3] ABS[0] LIN3RX SIUL eMIOS_0 eMIOS_0 -- SIUL BAM LINFlex_3 I/O I/O I/O -- I I I PA[9] PCR[9] AF0 AF1 AF2 AF3 N/A6 GPIO[9] E0UC[9] -- CS2_1 FAB SIUL eMIOS_0 -- DSPI_1 BAM PA[10] PCR[10] AF0 AF1 AF2 AF3 -- GPIO[10] E0UC[10] SDA LIN2TX ADC1_S[2] PA[11] PCR[11] AF0 AF1 AF2 AF3 -- -- -- PA[12] PCR[12] PA[13] PA[14] RESET config.2 I/O direction AF0 AF1 AF2 AF3 -- -- Pin No. Pad type Function Peripheral Table 3. Functional port pin descriptions (continued) LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 J Tristate 71 104 128 D16 S Input, weak pull-up 72 105 129 C16 I/O I/O -- O I S Pulldown 73 106 130 C15 SIUL eMIOS_0 I2C_0 LINFlex_2 ADC_1 I/O I/O I/O O I J Tristate 74 107 131 B16 GPIO[11] E0UC[11] SCL -- EIRQ[16] LIN2RX ADC1_S[3] SIUL eMIOS_0 I2C_0 -- SIUL LINFlex_2 ADC_1 I/O I/O -- -- I I I J Tristate 75 108 132 B15 AF0 AF1 AF2 AF3 -- -- GPIO[12] -- E0UC[28] CS3_1 EIRQ[17] SIN_0 SIUL -- eMIOS_0 DSPI_1 SIUL DSPI_0 I/O -- I/O O I I S Tristate 31 45 53 T7 PCR[13] AF0 AF1 AF2 AF3 GPIO[13] SOUT_0 E0UC[29] -- SIUL DSPI_0 eMIOS_0 -- I/O O I/O -- M Tristate 30 44 52 R7 PCR[14] AF0 AF1 AF2 AF3 -- GPIO[14] SCK_0 CS0_0 E0UC[0] EIRQ[4] SIUL DSPI_0 DSPI_0 eMIOS_0 SIUL I/O I/O I/O I/O I M Tristate 28 42 50 P6 Port pin PCR Alternate register function1 PA[7] PCR[7] PA[8] MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 13 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) GPIO[15] CS0_0 SCK_0 E0UC[1] WKUP[10]4 RESET config.2 AF0 AF1 AF2 AF3 -- Pad type PCR[15] Function I/O direction PA[15] PCR Alternate register function1 Peripheral Port pin Pin No. SIUL DSPI_0 DSPI_0 eMIOS_0 WKUP I/O I/O I/O I/O I M Tristate 27 40 48 R6 LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 Port B PB[0] PCR[16] AF0 AF1 AF2 AF3 GPIO[16] CAN0TX E0UC[30] LIN0TX SIUL FlexCAN_0 eMIOS_0 LINFlex_0 I/O O I/O O M Tristate 23 31 39 N3 PB[1] PCR[17] AF0 AF1 AF2 AF3 -- -- -- GPIO[17] -- E0UC[31] -- WKUP[4]4 CAN0RX LIN0RX SIUL -- eMIOS_0 -- WKUP FlexCAN_0 LINFlex_0 I/O -- I/O -- I I I S Tristate 24 32 40 N1 PB[2] PCR[18] AF0 AF1 AF2 AF3 GPIO[18] LIN0TX SDA E0UC[30] SIUL LINFlex_0 I2C_0 eMIOS_0 I/O O I/O I/O M Tristate 100 144 176 B2 PB[3] PCR[19] AF0 AF1 AF2 AF3 -- -- GPIO[19] E0UC[31] SCL -- WKUP[11]4 LIN0RX SIUL eMIOS_0 I2C_0 -- WKUP LINFlex_0 I/O I/O I/O -- I I S Tristate 1 1 1 C3 PB[4] PCR[20] AF0 AF1 AF2 AF3 -- -- -- -- -- -- -- ADC0_P[0] ADC1_P[0] GPIO[20] -- -- -- -- ADC_0 ADC_1 SIUL -- -- -- -- I I I I Tristate 50 72 88 T16 PB[5] PCR[21] AF0 AF1 AF2 AF3 -- -- -- -- -- -- -- ADC0_P[1] ADC1_P[1] GPIO[21] -- -- -- -- ADC_0 ADC_1 SIUL -- -- -- -- I I I I Tristate 53 75 91 R16 MPC5607B Microcontroller Data Sheet, Rev. 5 14 Freescale Semiconductor Package pinouts and signal descriptions -- -- -- -- ADC0_P[2] ADC1_P[2] GPIO[22] -- -- -- -- ADC_0 ADC_1 SIUL -- -- -- -- I I I PCR[23] AF0 AF1 AF2 AF3 -- -- -- -- -- -- -- ADC0_P[3] ADC1_P[3] GPIO[23] -- -- -- -- ADC_0 ADC_1 SIUL -- -- -- -- I I I PB[8] PCR[24] AF0 AF1 AF2 AF3 -- -- -- -- GPIO[24] -- -- -- OSC32K_XTAL7 WKUP[25] ADC0_S[0] ADC1_S[4] SIUL -- -- -- OSC32K WKUP ADC_0 ADC_1 PB[9] PCR[25] AF0 AF1 AF2 AF3 -- -- -- -- GPIO[25] -- -- -- OSC32K_EXTAL7 WKUP[26] ADC0_S[1] ADC1_S[5] PB[10] PCR[26] AF0 AF1 AF2 AF3 -- -- -- PB[11] PCR[27] AF0 AF1 AF2 AF3 -- PCR Alternate register function1 PB[6] PCR[22] PB[7] RESET config.2 I/O direction AF0 AF1 AF2 AF3 -- -- -- Port pin Pin No. Pad type Function Peripheral Table 3. Functional port pin descriptions (continued) LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 I Tristate 54 76 92 P15 I Tristate 55 77 93 P16 I -- -- -- -- I I I I -- 39 53 61 R9 SIUL -- -- -- OSC32K WKUP ADC_0 ADC_1 I -- -- -- -- I I I I -- 38 52 60 T9 GPIO[26] -- -- -- WKUP[8]4 ADC0_S[2] ADC1_S[6] SIUL -- -- -- WKUP ADC_0 ADC_1 I/O -- -- -- I I I J Tristate 40 54 62 P9 GPIO[27] E0UC[3] -- CS0_0 ADC0_S[3] SIUL eMIOS_0 -- DSPI_0 ADC_0 I/O I/O -- I/O I J Tristate -- -- 97 N13 MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 15 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Peripheral I/O direction Pad type RESET config.2 Pin No. PB[12] PCR[28] AF0 AF1 AF2 AF3 -- GPIO[28] E0UC[4] -- CS1_0 ADC0_X[0] SIUL eMIOS_0 -- DSPI_0 ADC_0 I/O I/O -- O I J Tristate 61 83 101 M16 PB[13] PCR[29] AF0 AF1 AF2 AF3 -- GPIO[29] E0UC[5] -- CS2_0 ADC0_X[1] SIUL eMIOS_0 -- DSPI_0 ADC_0 I/O I/O -- O I J Tristate 63 85 103 M13 PB[14] PCR[30] AF0 AF1 AF2 AF3 -- GPIO[30] E0UC[6] -- CS3_0 ADC0_X[2] SIUL eMIOS_0 -- DSPI_0 ADC_0 I/O I/O -- O I J Tristate 65 87 105 L16 PB[15] PCR[31] AF0 AF1 AF2 AF3 -- GPIO[31] E0UC[7] -- CS4_0 ADC0_X[3] SIUL eMIOS_0 -- DSPI_0 ADC_0 I/O I/O -- O I J Tristate 67 89 107 L13 Port pin PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 Port C PC[0]8 PCR[32] AF0 AF1 AF2 AF3 GPIO[32] -- TDI -- SIUL -- JTAGC -- I/O -- I -- M Input, weak pull-up 87 126 154 A8 PC[1]8 PCR[33] AF0 AF1 AF2 AF3 GPIO[33] -- TDO -- SIUL -- JTAGC -- I/O -- O -- F9 Tristate 82 121 149 C9 PC[2] PCR[34] AF0 AF1 AF2 AF3 -- GPIO[34] SCK_1 CAN4TX DEBUG[0] EIRQ[5] SIUL DSPI_1 FlexCAN_4 SSCM SIUL I/O I/O O O I M Tristate 78 117 145 A11 PC[3] PCR[35] AF0 AF1 AF2 AF3 -- -- -- GPIO[35] CS0_1 MA[0] DEBUG[1] EIRQ[6] CAN1RX CAN4RX SIUL DSPI_1 ADC_0 SSCM SIUL FlexCAN_1 FlexCAN_4 I/O I/O O O I I I S Tristate 77 116 144 B11 MPC5607B Microcontroller Data Sheet, Rev. 5 16 Freescale Semiconductor Package pinouts and signal descriptions GPIO[36] E1UC[31] -- DEBUG[2] EIRQ[18] SIN_1 CAN3RX SIUL eMIOS_1 -- SSCM SIUL DSPI_1 FlexCAN_3 I/O I/O -- O I I I PCR[37] AF0 AF1 AF2 AF3 -- GPIO[37] SOUT_1 CAN3TX DEBUG[3] EIRQ[7] SIUL DSPI_1 FlexCAN_3 SSCM SIUL I/O O O O I PC[6] PCR[38] AF0 AF1 AF2 AF3 GPIO[38] LIN1TX E1UC[28] DEBUG[4] SIUL LINFlex_1 eMIOS_1 SSCM PC[7] PCR[39] AF0 AF1 AF2 AF3 -- -- GPIO[39] -- E1UC[29] DEBUG[5] LIN1RX WKUP[12]4 PC[8] PCR[40] AF0 AF1 AF2 AF3 PC[9] PCR[41] RESET config.2 I/O direction AF0 AF1 AF2 AF3 -- -- -- Pin No. Pad type Function Peripheral Table 3. Functional port pin descriptions (continued) LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 M Tristate 92 131 159 B7 M Tristate 91 130 158 A7 I/O O I/O O S Tristate 25 36 44 R2 SIUL -- eMIOS_1 SSCM LINFlex_1 WKUP I/O -- I/O O I I S Tristate 26 37 45 P3 GPIO[40] LIN2TX E0UC[3] DEBUG[6] SIUL LINFlex_2 eMIOS_0 SSCM I/O O I/O O S Tristate 99 143 175 A1 AF0 AF1 AF2 AF3 -- -- GPIO[41] -- E0UC[7] DEBUG[7] WKUP[13]4 LIN2RX SIUL -- eMIOS_0 SSCM WKUP LINFlex_2 I/O -- I/O O I I S Tristate 2 2 2 B1 PC[10] PCR[42] AF0 AF1 AF2 AF3 GPIO[42] CAN1TX CAN4TX MA[1] SIUL FlexCAN_1 FlexCAN_4 ADC_0 I/O O O O M Tristate 22 28 36 M3 PC[11] PCR[43] AF0 AF1 AF2 AF3 -- -- -- GPIO[43] -- -- MA[2] WKUP[5]4 CAN1RX CAN4RX SIUL -- -- ADC_0 WKUP FlexCAN_1 FlexCAN_4 I/O -- -- O I I I S Tristate 21 27 35 M4 Port pin PCR Alternate register function1 PC[4] PCR[36] PC[5] MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 17 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Peripheral I/O direction Pad type RESET config.2 Pin No. PC[12] PCR[44] AF0 AF1 AF2 AF3 -- -- GPIO[44] E0UC[12] -- -- EIRQ[19] SIN_2 SIUL eMIOS_0 -- -- SIUL DSPI_2 I/O I/O -- -- I I M Tristate 97 141 173 B4 PC[13] PCR[45] AF0 AF1 AF2 AF3 GPIO[45] E0UC[13] SOUT_2 -- SIUL eMIOS_0 DSPI_2 -- I/O I/O O -- S Tristate 98 142 174 A2 PC[14] PCR[46] AF0 AF1 AF2 AF3 -- GPIO[46] E0UC[14] SCK_2 -- EIRQ[8] SIUL eMIOS_0 DSPI_2 -- SIUL I/O I/O I/O -- I S Tristate 3 3 3 C1 PC[15] PCR[47] AF0 AF1 AF2 AF3 -- GPIO[47] E0UC[15] CS0_2 -- EIRQ[20] SIUL eMIOS_0 DSPI_2 -- SIUL I/O I/O I/O -- I M Tristate 4 4 4 D3 Port pin PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 Port D PD[0] PCR[48] AF0 AF1 AF2 AF3 -- -- -- GPIO[48] -- -- -- WKUP[27] ADC0_P[4] ADC1_P[4] SIUL -- -- -- WKUP ADC_0 ADC_1 I -- -- -- I I I I Tristate 41 63 77 P12 PD[1] PCR[49] AF0 AF1 AF2 AF3 -- -- -- GPIO[49] -- -- -- WKUP[28] ADC0_P[5] ADC1_P[5] SIUL -- -- -- WKUP ADC_0 ADC_1 I -- -- -- I I I I Tristate 42 64 78 T12 PD[2] PCR[50] AF0 AF1 AF2 AF3 -- -- GPIO[50] -- -- -- ADC0_P[6] ADC1_P[6] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I Tristate 43 65 79 R12 MPC5607B Microcontroller Data Sheet, Rev. 5 18 Freescale Semiconductor Package pinouts and signal descriptions GPIO[51] -- -- -- ADC0_P[7] ADC1_P[7] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I PCR[52] AF0 AF1 AF2 AF3 -- -- GPIO[52] -- -- -- ADC0_P[8] ADC1_P[8] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I PD[5] PCR[53] AF0 AF1 AF2 AF3 -- -- GPIO[53] -- -- -- ADC0_P[9] ADC1_P[9] SIUL -- -- -- ADC_0 ADC_1 PD[6] PCR[54] AF0 AF1 AF2 AF3 -- -- GPIO[54] -- -- -- ADC0_P[10] ADC1_P[10] PD[7] PCR[55] AF0 AF1 AF2 AF3 -- -- PD[8] PCR[56] PD[9] PCR[57] RESET config.2 I/O direction AF0 AF1 AF2 AF3 -- -- Pin No. Pad type Function Peripheral Table 3. Functional port pin descriptions (continued) LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 I Tristate 44 66 80 P13 I Tristate 45 67 81 R13 I -- -- -- I I I Tristate 46 68 82 T13 SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I Tristate 47 69 83 T14 GPIO[55] -- -- -- ADC0_P[11] ADC1_P[11] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I Tristate 48 70 84 R14 AF0 AF1 AF2 AF3 -- -- GPIO[56] -- -- -- ADC0_P[12] ADC1_P[12] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I Tristate 49 71 87 T15 AF0 AF1 AF2 AF3 -- -- GPIO[57] -- -- -- ADC0_P[13] ADC1_P[13] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I Tristate 56 78 94 N15 Port pin PCR Alternate register function1 PD[3] PCR[51] PD[4] MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 19 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Peripheral I/O direction Pad type RESET config.2 Pin No. PD[10] PCR[58] AF0 AF1 AF2 AF3 -- -- GPIO[58] -- -- -- ADC0_P[14] ADC1_P[14] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I Tristate 57 79 95 N14 PD[11] PCR[59] AF0 AF1 AF2 AF3 -- -- GPIO[59] -- -- -- ADC0_P[15] ADC1_P[15] SIUL -- -- -- ADC_0 ADC_1 I -- -- -- I I I Tristate 58 80 96 N16 PD[12] PCR[60] AF0 AF1 AF2 AF3 -- GPIO[60] CS5_0 E0UC[24] -- ADC0_S[4] SIUL DSPI_0 eMIOS_0 -- ADC_0 I/O O I/O -- I J Tristate -- -- 100 M15 PD[13] PCR[61] AF0 AF1 AF2 AF3 -- GPIO[61] CS0_1 E0UC[25] -- ADC0_S[5] SIUL DSPI_1 eMIOS_0 -- ADC_0 I/O I/O -- -- I J Tristate 62 84 102 M14 PD[14] PCR[62] AF0 AF1 AF2 AF3 -- GPIO[62] CS1_1 E0UC[26] -- ADC0_S[6] SIUL DSPI_1 eMIOS_0 -- ADC_0 I/O O I/O -- I J Tristate 64 86 104 L15 PD[15] PCR[63] AF0 AF1 AF2 AF3 -- GPIO[63] CS2_1 E0UC[27] -- ADC0_S[7] SIUL DSPI_1 eMIOS_0 -- ADC_0 I/O O I/O -- I J Tristate 66 88 106 L14 Port pin PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 Port E PE[0] PCR[64] AF0 AF1 AF2 AF3 -- -- GPIO[64] E0UC[16] -- -- WKUP[6]4 CAN5RX SIUL eMIOS_0 -- -- WKUP FlexCAN_5 I/O I/O -- -- I I S Tristate 6 10 18 F1 PE[1] PCR[65] AF0 AF1 AF2 AF3 GPIO[65] E0UC[17] CAN5TX -- SIUL eMIOS_0 FlexCAN_5 -- I/O I/O O -- M Tristate 8 12 20 F4 MPC5607B Microcontroller Data Sheet, Rev. 5 20 Freescale Semiconductor Package pinouts and signal descriptions GPIO[66] E0UC[18] -- -- EIRQ[21] SIN_1 SIUL eMIOS_0 -- -- SIUL DSPI_1 I/O I/O -- -- I I PCR[67] AF0 AF1 AF2 AF3 GPIO[67] E0UC[19] SOUT_1 -- SIUL eMIOS_0 DSPI_1 -- I/O I/O O -- PE[4] PCR[68] AF0 AF1 AF2 AF3 -- GPIO[68] E0UC[20] SCK_1 -- EIRQ[9] SIUL eMIOS_0 DSPI_1 -- SIUL PE[5] PCR[69] AF0 AF1 AF2 AF3 GPIO[69] E0UC[21] CS0_1 MA[2] PE[6] PCR[70] AF0 AF1 AF2 AF3 -- PE[7] PCR[71] PE[8] RESET config.2 I/O direction AF0 AF1 AF2 AF3 -- -- Pin No. Pad type Function Peripheral Table 3. Functional port pin descriptions (continued) LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 M Tristate 89 128 156 D7 M Tristate 90 129 157 C7 I/O I/O I/O -- I M Tristate 93 132 160 D6 SIUL eMIOS_0 DSPI_1 ADC_0 I/O I/O I/O O M Tristate 94 133 161 C6 GPIO[70] E0UC[22] CS3_0 MA[1] EIRQ[22] SIUL eMIOS_0 DSPI_0 ADC_0 SIUL I/O I/O O O I M Tristate 95 139 167 B5 AF0 AF1 AF2 AF3 -- GPIO[71] E0UC[23] CS2_0 MA[0] EIRQ[23] SIUL eMIOS_0 DSPI_0 ADC_0 SIUL I/O I/O O O I M Tristate 96 140 168 C4 PCR[72] AF0 AF1 AF2 AF3 GPIO[72] CAN2TX E0UC[22] CAN3TX SIUL FlexCAN_2 eMIOS_0 FlexCAN_3 I/O O I/O O M Tristate 9 13 21 G2 PE[9] PCR[73] AF0 AF1 AF2 AF3 -- -- -- GPIO[73] -- E0UC[23] -- WKUP[7]4 CAN2RX CAN3RX SIUL -- eMIOS_0 -- WKUP FlexCAN_2 FlexCAN_3 I/O -- I/O -- I I I S Tristate 10 14 22 G1 PE[10] PCR[74] AF0 AF1 AF2 AF3 -- GPIO[74] LIN3TX CS3_1 E1UC[30] EIRQ[10] SIUL LINFlex_3 DSPI_1 eMIOS_1 SIUL I/O O O I/O I S Tristate 11 15 23 G3 Port pin PCR Alternate register function1 PE[2] PCR[66] PE[3] MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 21 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Peripheral I/O direction Pad type RESET config.2 Pin No. PE[11] PCR[75] AF0 AF1 AF2 AF3 -- -- GPIO[75] E0UC[24] CS4_1 -- LIN3RX WKUP[14]4 SIUL eMIOS_0 DSPI_1 -- LINFlex_3 WKUP I/O I/O O -- I I S Tristate 13 17 25 H2 PE[12] PCR[76] AF0 AF1 AF2 AF3 -- -- -- GPIO[76] -- E1UC[19]10 -- EIRQ[11] SIN_2 ADC1_S[7] SIUL -- eMIOS_1 -- SIUL DSPI_2 ADC_1 I/O -- I/O -- I I I J Tristate 76 109 133 C14 PE[13] PCR[77] AF0 AF1 AF2 AF3 GPIO[77] SOUT_2 E1UC[20] -- SIUL DSPI_2 eMIOS_1 -- I/O O I/O -- S Tristate -- 103 127 D15 PE[14] PCR[78] AF0 AF1 AF2 AF3 -- GPIO[78] SCK_2 E1UC[21] -- EIRQ[12] SIUL DSPI_2 eMIOS_1 -- SIUL I/O I/O I/O -- I S Tristate -- 112 136 C13 PE[15] PCR[79] AF0 AF1 AF2 AF3 GPIO[79] CS0_2 E1UC[22] -- SIUL DSPI_2 eMIOS_1 -- I/O I/O I/O -- M Tristate -- 113 137 A13 Port pin PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 Port F PF[0] PCR[80] AF0 AF1 AF2 AF3 -- GPIO[80] E0UC[10] CS3_1 -- ADC0_S[8] SIUL eMIOS_0 DSPI_1 -- ADC_0 I/O I/O O -- I J Tristate -- 55 63 N10 PF[1] PCR[81] AF0 AF1 AF2 AF3 -- GPIO[81] E0UC[11] CS4_1 -- ADC0_S[9] SIUL eMIOS_0 DSPI_1 -- ADC_0 I/O I/O O -- I J Tristate -- 56 64 P10 PF[2] PCR[82] AF0 AF1 AF2 AF3 -- GPIO[82] E0UC[12] CS0_2 -- ADC0_S[10] SIUL eMIOS_0 DSPI_2 -- ADC_0 I/O I/O O -- I J Tristate -- 57 65 T10 MPC5607B Microcontroller Data Sheet, Rev. 5 22 Freescale Semiconductor Package pinouts and signal descriptions GPIO[83] E0UC[13] CS1_2 -- ADC0_S[11] SIUL eMIOS_0 DSPI_2 -- ADC_0 I/O I/O O -- I PCR[84] AF0 AF1 AF2 AF3 -- GPIO[84] E0UC[14] CS2_2 -- ADC0_S[12] SIUL eMIOS_0 DSPI_2 -- ADC_0 I/O I/O O -- I PF[5] PCR[85] AF0 AF1 AF2 AF3 -- GPIO[85] E0UC[22] CS3_2 -- ADC0_S[13] SIUL eMIOS_0 DSPI_2 -- ADC_0 PF[6] PCR[86] AF0 AF1 AF2 AF3 -- GPIO[86] E0UC[23] CS1_1 -- ADC0_S[14] PF[7] PCR[87] AF0 AF1 AF2 AF3 -- PF[8] PCR[88] PF[9] PF[10] RESET config.2 I/O direction AF0 AF1 AF2 AF3 -- Pin No. Pad type Function Peripheral Table 3. Functional port pin descriptions (continued) LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 J Tristate -- 58 66 R10 J Tristate -- 59 67 N11 I/O I/O O -- I J Tristate -- 60 68 P11 SIUL eMIOS_0 DSPI_1 -- ADC_0 I/O I/O O -- I J Tristate -- 61 69 T11 GPIO[87] -- CS2_1 -- ADC0_S[15] SIUL -- DSPI_1 -- ADC_0 I/O -- O -- I J Tristate -- 62 70 R11 AF0 AF1 AF2 AF3 GPIO[88] CAN3TX CS4_0 CAN2TX SIUL FlexCAN_3 DSPI_0 FlexCAN_2 I/O O O O M Tristate -- 34 42 P1 PCR[89] AF0 AF1 AF2 AF3 -- -- -- GPIO[89] E1UC[1] CS5_0 -- WKUP[22]4 CAN2RX CAN3RX SIUL eMIOS_1 DSPI_0 -- WKUP FlexCAN_2 FlexCAN_3 I/O I/O O -- I I I S Tristate -- 33 41 N2 PCR[90] AF0 AF1 AF2 AF3 GPIO[90] CS1_0 LIN4TX E1UC[2] SIUL DSPI_0 LINFlex_4 eMIOS_1 I/O O O I/O M Tristate -- 38 46 R3 Port pin PCR Alternate register function1 PF[3] PCR[83] PF[4] MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 23 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Peripheral I/O direction Pad type RESET config.2 Pin No. PF[11] PCR[91] AF0 AF1 AF2 AF3 -- -- GPIO[91] CS2_0 E1UC[3] -- WKUP[15]4 LIN4RX SIUL DSPI_0 eMIOS_1 -- WKUP LINFlex_4 I/O O I/O -- I I S Tristate -- 39 47 R4 PF[12] PCR[92] AF0 AF1 AF2 AF3 GPIO[92] E1UC[25] LIN5TX -- SIUL eMIOS_1 LINFlex_5 -- I/O I/O O -- M Tristate -- 35 43 R1 PF[13] PCR[93] AF0 AF1 AF2 AF3 -- -- GPIO[93] E1UC[26] -- -- WKUP[16]4 LIN5RX SIUL eMIOS_1 -- -- WKUP LINFlex_5 I/O I/O -- -- I I S Tristate -- 41 49 T6 PF[14] PCR[94] AF0 AF1 AF2 AF3 GPIO[94] CAN4TX E1UC[27] CAN1TX SIUL FlexCAN_4 eMIOS_1 FlexCAN_1 I/O O I/O O M Tristate -- 102 126 D14 PF[15] PCR[95] AF0 AF1 AF2 AF3 -- -- -- GPIO[95] E1UC[4] -- -- EIRQ[13] CAN1RX CAN4RX SIUL eMIOS_1 -- -- SIUL FlexCAN_1 FlexCAN_4 I/O I/O -- -- I I I S Tristate -- 101 125 E15 Port pin PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 Port G PG[0] PCR[96] AF0 AF1 AF2 AF3 GPIO[96] CAN5TX E1UC[23] -- SIUL FlexCAN_5 eMIOS_1 -- I/O O I/O -- M Tristate -- 98 122 E14 PG[1] PCR[97] AF0 AF1 AF2 AF3 -- -- GPIO[97] -- E1UC[24] -- EIRQ[14] CAN5RX SIUL -- eMIOS_1 -- SIUL FlexCAN_5 I/O -- I/O -- I I S Tristate -- 97 121 E13 PG[2] PCR[98] AF0 AF1 AF2 AF3 GPIO[98] E1UC[11] SOUT_3 -- SIUL eMIOS_1 DSPI_3 -- I/O I/O O -- M Tristate -- 8 16 E4 MPC5607B Microcontroller Data Sheet, Rev. 5 24 Freescale Semiconductor Package pinouts and signal descriptions GPIO[99] E1UC[12] CS0_3 -- WKUP[17]4 SIUL eMIOS_1 DSPI_3 -- WKUP I/O I/O O -- I PG[4] PCR[100] AF0 AF1 AF2 AF3 GPIO[100] E1UC[13] SCK_3 -- SIUL eMIOS_1 DSPI_3 -- I/O I/O I/O -- PG[5] PCR[101] AF0 AF1 AF2 AF3 -- -- GPIO[101] E1UC[14] -- -- WKUP[18]4 SIN_3 SIUL eMIOS_1 -- -- WKUP DSPI_3 PG[6] PCR[102] AF0 AF1 AF2 AF3 GPIO[102] E1UC[15] LIN6TX -- PG[7] PCR[103] AF0 AF1 AF2 AF3 -- -- PG[8] PCR[104] RESET config.2 I/O direction AF0 AF1 AF2 AF3 -- Pin No. Pad type Function Peripheral Table 3. Functional port pin descriptions (continued) LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 S Tristate -- 7 15 E3 M Tristate -- 6 14 E1 I/O I/O -- -- I I S Tristate -- 5 13 E2 SIUL eMIOS_1 LINFlex_6 -- I/O I/O O -- M Tristate -- 30 38 M2 GPIO[103] E1UC[16] E1UC[30] -- WKUP[20]4 LIN6RX SIUL eMIOS_1 eMIOS_1 -- WKUP LINFlex_6 I/O I/O I/O -- I I S Tristate -- 29 37 M1 AF0 AF1 AF2 AF3 -- GPIO[104] E1UC[17] LIN7TX CS0_2 EIRQ[15] SIUL eMIOS_1 LINFlex_7 DSPI_2 SIUL I/O I/O O I/O I S Tristate -- 26 34 L2 PG[9] PCR[105] AF0 AF1 AF2 AF3 -- -- GPIO[105] E1UC[18] -- SCK_2 WKUP[21]4 LIN7RX SIUL eMIOS_1 -- DSPI_2 WKUP LINFlex_7 I/O I/O -- I/O I I S Tristate -- 25 33 L1 PG[10] PCR[106] AF0 AF1 AF2 AF3 -- GPIO[106] E0UC[24] E1UC[31] -- SIN_4 SIUL eMIOS_0 eMIOS_1 -- DSPI_4 I/O I/O I/O -- I S Tristate -- 114 138 D13 PG[11] PCR[107] AF0 AF1 AF2 AF3 GPIO[107] E0UC[25] CS0_4 -- SIUL eMIOS_0 DSPI_4 -- I/O I/O O -- M Tristate -- 115 139 B12 Port pin PCR Alternate register function1 PG[3] PCR[99] MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 25 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Peripheral I/O direction Pad type RESET config.2 Pin No. PG[12] PCR[108] AF0 AF1 AF2 AF3 GPIO[108] E0UC[26] SOUT_4 -- SIUL eMIOS_0 DSPI_4 -- I/O I/O O -- M Tristate -- 92 116 K14 PG[13] PCR[109] AF0 AF1 AF2 AF3 GPIO[109] E0UC[27] SCK_4 -- SIUL eMIOS_0 DSPI_4 -- I/O I/O I/O -- M Tristate -- 91 115 K16 PG[14] PCR[110] AF0 AF1 AF2 AF3 GPIO[110] E1UC[0] LIN8TX -- SIUL eMIOS_1 LINFlex_8 -- I/O I/O O -- S Tristate -- 110 134 B14 PG[15] PCR[111] AF0 AF1 AF2 AF3 -- GPIO[111] E1UC[1] -- -- LIN8RX SIUL eMIOS_1 -- -- LINFlex_8 I/O I/O -- -- I M Tristate -- 111 135 B13 Port pin PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 Port H PH[0] PCR[112] AF0 AF1 AF2 AF3 -- GPIO[112] E1UC[2] -- -- SIN_1 SIUL eMIOS_1 -- -- DSPI_1 I/O I/O -- -- I M Tristate -- 93 117 F13 PH[1] PCR[113] AF0 AF1 AF2 AF3 GPIO[113] E1UC[3] SOUT_1 -- SIUL eMIOS_1 DSPI_1 -- I/O I/O O -- M Tristate -- 94 118 F14 PH[2] PCR[114] AF0 AF1 AF2 AF3 GPIO[114] E1UC[4] SCK_1 -- SIUL eMIOS_1 DSPI_1 -- I/O I/O I/O -- M Tristate -- 95 119 F16 PH[3] PCR[115] AF0 AF1 AF2 AF3 GPIO[115] E1UC[5] CS0_1 -- SIUL eMIOS_1 DSPI_1 -- I/O I/O I/O -- M Tristate -- 96 120 F15 PH[4] PCR[116] AF0 AF1 AF2 AF3 GPIO[116] E1UC[6] -- -- SIUL eMIOS_1 -- -- I/O I/O -- -- M Tristate -- 134 162 A6 PH[5] PCR[117] AF0 AF1 AF2 AF3 GPIO[117] E1UC[7] -- -- SIUL eMIOS_1 -- -- I/O I/O -- -- S Tristate -- 135 163 B6 MPC5607B Microcontroller Data Sheet, Rev. 5 26 Freescale Semiconductor Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Peripheral I/O direction Pad type RESET config.2 Pin No. PH[6] PCR[118] AF0 AF1 AF2 AF3 GPIO[118] E1UC[8] -- MA[2] SIUL eMIOS_1 -- ADC_0 I/O I/O -- O M Tristate -- 136 164 D5 PH[7] PCR[119] AF0 AF1 AF2 AF3 GPIO[119] E1UC[9] CS3_2 MA[1] SIUL eMIOS_1 DSPI_2 ADC_0 I/O I/O O O M Tristate -- 137 165 C5 PH[8] PCR[120] AF0 AF1 AF2 AF3 GPIO[120] E1UC[10] CS2_2 MA[0] SIUL eMIOS_1 DSPI_2 ADC_0 I/O I/O O O M Tristate -- 138 166 A5 PH[9]8 PCR[121] AF0 AF1 AF2 AF3 GPIO[121] -- TCK -- SIUL -- JTAGC -- I/O -- I -- S Input, weak pull-up 88 127 155 B8 PH[10]8 PCR[122] AF0 AF1 AF2 AF3 GPIO[122] -- TMS -- SIUL -- JTAGC -- I/O -- I -- M Input, weak pull-up 81 120 148 B9 PH[11] PCR[123] AF0 AF1 AF2 AF3 GPIO[123] SOUT_3 CS0_4 E1UC[5] SIUL DSPI_3 DSPI_4 eMIOS_1 I/O O I/O -- M Tristate -- -- 140 A14 PH[12] PCR[124] AF0 AF1 AF2 AF3 GPIO[124] SCK_3 CS1_4 E1UC[25] SIUL DSPI_3 DSPI_4 eMIOS_1 I/O I/O I/O -- M Tristate -- -- 141 D12 PH[13] PCR[125] AF0 AF1 AF2 AF3 GPIO[125] SOUT_4 CS0_3 E1UC[26] SIUL DSPI_4 DSPI_3 eMIOS_1 I/O O I/O -- M Tristate -- -- 9 B3 PH[14] PCR[126] AF0 AF1 AF2 AF3 GPIO[126] SCK_4 CS1_3 E1UC[27] SIUL DSPI_4 DSPI_3 eMIOS_1 I/O I/O I/O -- M Tristate -- -- 10 D1 PH[15] PCR[127] AF0 AF1 AF2 AF3 GPIO[127] SOUT_5 -- E1UC[17] SIUL DSPI_5 -- eMIOS_1 I/O O -- -- M Tristate -- -- 8 A3 Port pin PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 Port I MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 27 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Peripheral I/O direction Pad type RESET config.2 Pin No. PI[0] PCR[128] AF0 AF1 AF2 AF3 GPIO[128] E0UC[28] LIN8TX -- SIUL eMIOS_0 LINFlex_8 -- I/O I/O O -- S Tristate -- -- 172 A9 PI[1] PCR[129] AF0 AF1 AF2 AF3 -- -- GPIO[129] E0UC[29] -- -- WKUP[24]4 LIN8RX SIUL eMIOS_0 -- -- WKUP LINFlex_8 I/O I/O -- -- I I S Tristate -- -- 171 A10 PI[2] PCR[130] AF0 AF1 AF2 AF3 GPIO[130] E0UC[30] LIN9TX -- SIUL eMIOS_0 LINFlex_9 -- I/O I/O O -- S Tristate -- -- 170 B10 PI[3] PCR[131] AF0 AF1 AF2 AF3 -- -- GPIO[131] E0UC[31] -- -- WKUP[23]4 LIN9RX SIUL eMIOS_0 -- -- WKUP LINFlex_9 I/O I/O -- -- I I S Tristate -- -- 169 C10 PI[4] PCR[132] AF0 AF1 AF2 AF3 GPIO[132] E1UC[28] SOUT_4 -- SIUL eMIOS_1 DSPI_4 -- I/O I/O O -- S Tristate -- -- 143 A12 PI[5] PCR[133] AF0 AF1 AF2 AF3 GPIO[133] E1UC[29] SCK_4 -- SIUL eMIOS_1 DSPI_4 -- I/O I/O I/O -- S Tristate -- -- 142 C12 PI[6] PCR[134] AF0 AF1 AF2 AF3 GPIO[134] E1UC[30] CS0_4 -- SIUL eMIOS_1 DSPI_4 -- I/O I/O I/O -- S Tristate -- -- 11 D2 PI[7] PCR[135] AF0 AF1 AF2 AF3 GPIO[135] E1UC[31] CS1_4 -- SIUL eMIOS_1 DSPI_4 -- I/O I/O I/O -- S Tristate -- -- 12 D3 PI[8] PCR[136] AF0 AF1 AF2 AF3 -- GPIO[136] -- -- -- ADC0_S[16] SIUL -- -- -- ADC_0 I/O -- -- -- I J Tristate -- -- 108 J13 Port pin PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 MPC5607B Microcontroller Data Sheet, Rev. 5 28 Freescale Semiconductor Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Peripheral I/O direction Pad type RESET config.2 Pin No. PCR[137] AF0 AF1 AF2 AF3 -- GPIO[137] -- -- -- ADC0_S[17] SIUL -- -- -- ADC_0 I/O -- -- -- I J Tristate -- -- 109 J14 PI[10] PCR[138] AF0 AF1 AF2 AF3 -- GPIO[138] -- -- -- ADC0_S[18] SIUL -- -- -- ADC_0 I/O -- -- -- I J Tristate -- -- 110 J15 PI[11] PCR[139] AF0 AF1 AF2 AF3 -- -- GPIO[139] -- -- -- ADC0_S[19] SIN_3 SIUL -- -- -- ADC_0 DSPI_3 I/O -- -- -- I I J Tristate -- -- 111 J16 PI[12] PCR[140] AF0 AF1 AF2 AF3 -- GPIO[140] CS0_3 -- -- ADC0_S[20] SIUL DSPI_3 -- -- ADC_0 I/O I/O -- -- I J Tristate -- -- 112 G14 PI[13] PCR[141] AF0 AF1 AF2 AF3 -- GPIO[141] CS1_3 -- -- ADC0_S[21] SIUL DSPI_3 -- -- ADC_0 I/O I/O -- -- I J Tristate -- -- 113 G15 PI[14] PCR[142] AF0 AF1 AF2 AF3 -- -- GPIO[142] -- -- -- ADC0_S[22] SIN_4 SIUL -- -- -- ADC_0 DSPI_4 I/O -- -- -- I I J Tristate -- -- 76 R8 PI[15] PCR[143] AF0 AF1 AF2 AF3 -- GPIO[143] CS0_4 -- -- ADC0_S[23] SIUL DSPI_4 -- -- ADC_0 I/O I/O -- -- I J Tristate -- -- 75 T8 I/O I/O -- -- I J Tristate -- -- 74 N5 Port pin PI[9] PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 Port J PJ[0] PCR[144] AF0 AF1 AF2 AF3 -- GPIO[144] CS1_4 -- -- ADC0_S[24] SIUL DSPI_4 -- -- ADC_0 MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 29 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Peripheral I/O direction Pad type RESET config.2 Pin No. PJ[1] PCR[145] AF0 AF1 AF2 AF3 -- -- GPIO[145] -- -- -- ADC0_S[25] SIN_5 SIUL -- -- ---- ADC_0 DSPI_5 I/O -- -- -- I I J Tristate -- -- 73 P5 PJ[2] PCR[146] AF0 AF1 AF2 AF3 -- GPIO[146] CS0_5 -- -- ADC0_S[26] SIUL DSPI_5 -- -- ADC_0 I/O I/O -- -- I J Tristate -- -- 72 P4 PJ[3] PCR[147] AF0 AF1 AF2 AF3 -- GPIO[147] CS1_5 -- -- ADC0_S[27] SIUL DSPI_5 -- -- ADC_0 I/O I/O -- -- I J Tristate -- -- 71 P2 PJ[4] PCR[148] AF0 AF1 AF2 AF3 GPIO[148] SCK_5 E1UC[18] -- SIUL DSPI_5 eMIOS_1 -- I/O I/O -- -- M Tristate -- -- 5 A4 Port pin PCR Alternate register function1 Function LQFP 100 LQFP LQFP 144 LQFP LQFP 176 LQFP 208 MAP BGA3 1 Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 AF0; PCR.PA = 01 AF1; PCR.PA = 10 AF2; PCR.PA = 11 AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to `1', regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as "--". 2 The RESET configuration applies during and after reset. 3 208 MAPBGA available only as development package for Nexus2+ 4 All WKUP pins also support external interrupt capability. See the WKPU chapter of the MPC5607B Microcontroller Reference Manual for further details. 5 NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. 6 "Not applicable" because these functions are available only while the device is booting. See the BAM chapter of the MPC5607B Microcontroller Reference Manual for details. 7 Value of PCR.IBE bit must be 0 8 Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). It is up to the user to configure these pins as GPIO when needed. 9 PC[1] is a fast/medium pad but is in medium configuration by default. This pad is in Alternate Function 2 mode after reset which has TDO functionality. The reset value of PCR.OBE is `1', but this setting has no impact as long as this pad stays in AF2 mode. After configuring this pad as GPIO (PCR.PA = 0), output buffer is enabled as reset value of PCR.OBE = 1. 10 Not available in 100 LQFP package MPC5607B Microcontroller Data Sheet, Rev. 5 30 Freescale Semiconductor Electrical characteristics 4 Electrical characteristics This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" for System Requirement is included in the Symbol column. 4.1 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 4 are used and the parameters are tagged accordingly in the tables where appropriate. Table 4. Parameter classifications Classification tag Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate. 4.2 NVUSRO register Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register. For a detailed description of the NVUSRO register, please refer to the MPC5607B Microcontroller Reference Manual. 4.2.1 NVUSRO[PAD3V5V] field description Table 5 shows how NVUSRO[PAD3V5V] controls the device configuration. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 31 Electrical characteristics Table 5. PAD3V5V field description1 Value2 1 Description 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. 2 The DC electrical characteristics are dependent on the PAD3V5V bit value. 4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description Table 6 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. Table 6. OSCILLATOR_MARGIN field description1 Value2 1 2 Description 0 Low consumption configuration (4 MHz/8 MHz) 1 High margin configuration (4 MHz/16 MHz) See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. 4.3 Absolute maximum ratings Table 7. Absolute maximum ratings Value Symbol Parameter Conditions Unit Min Max VSS SR Digital ground on VSS_HV pins -- 0 0 V VDD SR Voltage on VDD_HV pins with respect to ground (VSS) -- -0.3 6.0 V VSS_LV SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) -- VDD_BV SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) -- Relative to VDD VSS_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (VSS) -- VDD_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) with respect to ground (VSS) -- VIN SR Voltage on any GPIO pin with respect to ground (VSS) Relative to VDD -- Relative to VDD VSS - 0.1 VSS + 0.1 -0.3 6.0 -0.3 VDD + 0.3 VSS - 0.1 VSS + 0.1 -0.3 6.0 V V V V VDD 0.3 VDD + 0.3 -0.3 6.0 -- VDD + 0.3 V MPC5607B Microcontroller Data Sheet, Rev. 5 32 Freescale Semiconductor Electrical characteristics Table 7. Absolute maximum ratings (continued) Value Symbol Parameter Conditions Unit Min Max IINJPAD SR Injected input current on any pin during overload condition -- -10 10 IINJSUM SR Absolute sum of all injected input currents during overload condition -- -50 50 IAVGSEG SR Sum of all the static I/O current within a supply VDD = 5.0 V 10%, segment PAD3V5V = 0 -- 70 VDD = 3.3 V 10%, PAD3V5V = 1 -- 64 -55 150 TSTORAGE SR Storage temperature -- mA mA C NOTE Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values. 4.4 Recommended operating conditions Table 8. Recommended operating conditions (3.3 V) Value Symbol Parameter Conditions Unit Min Max VSS SR Digital ground on VSS_HV pins -- 0 0 V VDD1 SR Voltage on VDD_HV pins with respect to ground (VSS) -- 3.0 3.6 V VSS_LV2 SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) -- VDD_BV3 SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) -- Relative to VDD -- VSS_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (VSS) VDD_ADC4 -- SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) with Relative to VDD respect to ground (VSS) VIN SR Voltage on any GPIO pin with respect to ground (VSS) -- Relative to VDD VSS 0.1 VSS + 0.1 3.0 3.6 V V VDD 0.1 VDD + 0.1 VSS 0.1 VSS + 0.1 3.05 3.6 V V VDD 0.1 VDD + 0.1 VSS 0.1 -- -- VDD + 0.1 V MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 33 Electrical characteristics Table 8. Recommended operating conditions (3.3 V) (continued) Value Symbol Parameter Conditions Unit Min Max IINJPAD SR Injected input current on any pin during overload condition -- 5 5 IINJSUM SR Absolute sum of all injected input currents during overload condition -- 50 50 SR VDD slope to ensure correct power up6 -- -- 0.25 V/s 40 85 C 40 110 40 105 40 130 40 125 40 150 TVDD TA C-Grade SR Ambient temperature under bias fCPU < 64 MHz7 mA Part TJ C-Grade SR Junction temperature under bias -- Part TA V-Grade SR Ambient temperature under bias fCPU < 64 MHz7 Part TJ V-Grade SR Junction temperature under bias -- Part TA M-Grade SR Ambient temperature under bias fCPU < 64 MHz7 Part TJ M-Grade SR Junction temperature under bias -- Part 1 2 3 4 5 6 7 100 nF capacitance needs to be provided between each VDD/VSS pair. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). Supply ramp slope on VDD_BV should always be faster or equal to slope of VDD_HV. Otherwise, device may enter regulator bypass mode if slope on VDD_BV is slower. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. Guaranteed by device validation This frequency includes the 4% frequency modulation guardband. Table 9. Recommended operating conditions (5.0 V) Value Symbol Parameter Conditions VSS SR Digital ground on VSS_HV pins -- VDD1 SR Voltage on VDD_HV pins with respect to ground (VSS) -- VSS_LV3 SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) 2 Voltage drop -- Unit Min Max 0 0 V 4.5 5.5 V 3.0 5.5 VSS 0.1 VSS + 0.1 V MPC5607B Microcontroller Data Sheet, Rev. 5 34 Freescale Semiconductor Electrical characteristics Table 9. Recommended operating conditions (5.0 V) (continued) Value Symbol VDD_BV4 Parameter SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) Conditions Max 4.5 5.5 Voltage drop 3.0 5.5 Relative to VDD 3.0 VDD + 0.1 -- 2 SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (VSS) -- VDD_ADC5 SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) with respect to ground (VSS) -- VSS_ADC VSS 0.1 VSS + 0.1 2 Voltage drop Relative to VDD VIN SR Voltage on any GPIO pin with respect to ground (VSS) Unit Min -- Relative to VDD 4.5 5.5 3.0 5.5 V V V VDD 0.1 VDD + 0.1 VSS 0.1 -- -- VDD + 0.1 V IINJPAD SR Injected input current on any pin during overload condition -- 5 5 IINJSUM SR Absolute sum of all injected input currents during overload condition -- 50 50 SR VDD slope to ensure correct power up6 -- -- 0.25 V/s 40 85 C -- 40 110 fCPU < 64 MHz7 40 105 -- 40 130 fCPU < 64 MHz7 40 125 -- 40 150 TVDD TA C-Grade SR Ambient temperature under bias fCPU < 64 MHz7 mA Part TJ C-Grade SR Junction temperature under bias Part TA V-Grade SR Ambient temperature under bias Part TJ V-Grade SR Junction temperature under bias Part TA M-Grade SR Ambient temperature under bias Part TJ M-Grade SR Junction temperature under bias Part 1 2 3 4 5 6 7 100 nF capacitance needs to be provided between each VDD/VSS pair. Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). While the supply voltage ramps up, the slope on VDD_BV should be less than 0.9VDD_HV in order to ensure the device does not enter regulator bypass mode. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Guaranteed by device validation. Please refer to Section 4.5.1, "External ballast resistor recommendations for minimum VDD slope to be guaranteed to ensure correct power up in case of external resistor usage. This frequency includes the 4% frequency modulation guardband. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 35 Electrical characteristics NOTE RAM data retention is guaranteed with VDD_LV not below 1.08 V. 4.5 Thermal characteristics 4.5.1 External ballast resistor recommendations External ballast resistor on VDD_BV pin helps in reducing the overall power dissipation inside the device. This resistor is required only when maximum power consumption exceeds the limit imposed by package thermal characteristics. As stated in Table 10 LQFP thermal characteristics, considering a thermal resistance of 144 LQFP as 48.3 C/W, at ambient temperature TA = 125 C, the junction temperature Tj will cross 150 C if the total power dissipation is greater than (150 - 125)/48.3 = 517 mW. Therefore, the total device current IDDMAX at 125 C/5.5 V must not exceed 94.1 mA (i.e., PD/VDD). Assuming an average IDD(VDD_HV) of 15-20 mA consumption typically during device RUN mode, the LV domain consumption IDD(VDD_BV) is thus limited to IDDMAX - IDD(VDD_HV), i.e., 80 mA. Therefore, respecting the maximum power allowed as explained in Section 4.5.2, "Package thermal characteristics, it is recommended to use this resistor only in the 125 C/5.5 V operating corner as per the following guidelines: If IDD(VDD_BV) < 80 mA, then no resistor is required. If 80 mA < IDD(VDD_BV) < 90 mA, then 4 resistor can be used. If IDD(VDD_BV) > 90 mA, then 8 resistor can be used. * * * Using resistance in the range of 4-8 , the gain will be around 10-20% of total consumption on VDD_BV. For example, if 8 resistor is used, then power consumption when IDD(VDD_BV) is 110 mA is equivalent to power consumption when IDD(VDD_BV) is 90 mA (approximately) when resistor not used. In order to ensure correct power up, the minimum VDD_BV to be guaranteed is 30 ms/V. If the supply ramp is slower than this value, then LVDHV3B monitoring ballast supply VDD_BV pin gets triggered leading to device reset. Until the supply reaches certain threshold, this low voltage monitor generates destructive reset event in the system. This threshold depends on the maximum IDD(VDD_BV) possible across the external resistor. 4.5.2 Package thermal characteristics Table 10. LQFP thermal characteristics1 Symbol C Parameter Conditions2 Value Pin count Unit Min Typ Max RJA CC D Thermal resistance, junction-to-ambient natural convection3 Single-layer board -- 1s Four-layer board -- 2s2p 100 -- -- 64 144 -- -- 64 176 -- -- 64 100 -- -- 49.7 144 -- -- 48.3 176 -- -- 47.3 C/W MPC5607B Microcontroller Data Sheet, Rev. 5 36 Freescale Semiconductor Electrical characteristics Table 10. LQFP thermal characteristics1 (continued) Symbol C Conditions2 Parameter Value Pin count Unit Min Typ Max RJB CC Thermal resistance, junction-to-board4 Single-layer board -- 1s Four-layer board -- 2s2p RJC CC Thermal resistance, junction-to-case5 Single-layer board -- 1s Four-layer board -- 2s2p 100 -- -- 36 144 -- -- 38 176 -- -- 38 100 -- -- 33.6 144 -- -- 33.4 176 -- -- 33.4 100 -- -- 23 144 -- -- 23 176 -- -- 23 100 -- -- 19.8 144 -- -- 19.2 176 -- -- 18.8 C/W C/W 1 Thermal characteristics are targets based on simulation. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C. 3 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA. 4 Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB. 5 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters are not available, the symbols are typed as RthJC. 2 4.5.3 Power considerations The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1: TJ = TA + (PD x RJA) Eqn. 1 Where: TA is the ambient temperature in C. RJA is the package junction-to-ambient thermal resistance, in C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 37 Electrical characteristics PD = K / (TJ + 273 C) Eqn. 2 K = PD x (TA + 273 C) + RJA x PD2 Eqn. 3 Therefore, solving equations 1 and 2: Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value of TA. 4.6 4.6.1 I/O pad electrical characteristics I/O pad types The device provides four main I/O pad types depending on the associated alternate functions: * * * * Slow pads - are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads - provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Fast pads - provide maximum speed. These are used for improved Nexus debugging capability. Input only pads - are associated with ADC channels and 32 kHz low power external crystal oscillator providing low input leakage. Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance. 4.6.2 I/O input DC characteristics Table 11 provides input DC electrical characteristics as described in Figure 6. VIN VDD VIH VHYS VIL PDIx = `1 (GPDI register of SIUL) PDIx = `0' Figure 6. I/O input DC electrical characteristics definition MPC5607B Microcontroller Data Sheet, Rev. 5 38 Freescale Semiconductor Electrical characteristics Table 11. I/O input DC electrical characteristics Symbol C Value Conditions1 Parameter Unit Min Typ Max VIH SR P Input high level CMOS (Schmitt Trigger) -- 0.65VDD -- VDD + 0.4 VIL SR P Input low level CMOS (Schmitt Trigger) -- 0.4 -- 0.35VDD -- 0.1VDD -- -- TA = 40 C -- 2 -- TA = 25 C -- 2 -- D TA = 105 C -- 12 500 P TA = 125 C -- 70 1000 -- -- -- 40 ns -- 1000 -- -- ns VHYS CC C Input hysteresis CMOS (Schmitt Trigger) ILKG CC P Digital input leakage No injection on adjacent pin P WFI2 SR P Wakeup input filtered pulse WNFI 2 SR P Wakeup input not filtered pulse V nA VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. 1 2 4.6.3 I/O output DC characteristics The following tables provide DC characteristics for bidirectional pads: * * * * Table 12 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 13 provides output driver characteristics for I/O pads when in SLOW configuration. Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 15 provides output driver characteristics for I/O pads when in FAST configuration. Table 12. I/O pull-up/pull-down DC electrical characteristics Symbol C Parameter Value Conditions1 Unit Min |IWPU| CC P Weak pull-up current absolute value C P |IWPD| CC P Weak pull-down current absolute value C P 1 2 VIN = VIL, VDD = 5.0 V 10% PAD3V5V = 0 Typ Max 10 -- 150 PAD3V5V = 1 10 -- 250 VIN = VIL, VDD = 3.3 V 10% PAD3V5V = 1 10 -- 150 VIN = VIH, VDD = 5.0 V 10% PAD3V5V = 0 10 -- 150 PAD3V5V = 1 10 -- 250 VIN = VIH, VDD = 3.3 V 10% PAD3V5V = 1 10 -- 150 2 A A VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 39 Electrical characteristics Table 13. SLOW configuration output buffer electrical characteristics Symbol VOH VOL 1 2 C Value Conditions1 Parameter Unit Min Typ Max Push Pull IOH = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) 0.8VDD -- -- C IOH = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 12 0.8VDD -- -- C IOH = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) VDD 0.8 -- -- Push Pull IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD C IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 12 -- -- 0.1VDD C IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- 0.5 CC P Output high level SLOW configuration CC P Output low level SLOW configuration V V VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 14. MEDIUM configuration output buffer electrical characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max Push Pull IOH = 3.8 mA, VOH CC C Output high level MEDIUM configuration VDD = 5.0 V 10%, PAD3V5V = 0 0.8VDD -- -- P IOH = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) 0.8VDD -- -- C IOH = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 12 0.8VDD -- -- C IOH = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) VDD 0.8 -- -- C IOH = 100 A, VDD = 5.0 V 10%, PAD3V5V = 0 0.8VDD -- V -- MPC5607B Microcontroller Data Sheet, Rev. 5 40 Freescale Semiconductor Electrical characteristics Table 14. MEDIUM configuration output buffer electrical characteristics (continued) Symbol C Parameter Value Conditions1 Unit Min VOL CC C Output low level Push Pull IOL = 3.8 mA, MEDIUM configuration VDD = 5.0 V 10%, PAD3V5V = 0 1 2 Typ Max -- -- 0.2VDD P IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD C IOL = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 12 -- -- 0.1VDD C IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- C IOH = 100 A, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 0.1VDD V 0.5 VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 15. FAST configuration output buffer electrical characteristics Symbol Parameter Value Conditions1 Unit Min Typ Max VOH CC P Output high level Push Pull IOH = 14 mA, FAST configuration VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) 0.8VDD -- -- C IOH = 7 mA, VDD = 5.0 V 10%, PAD3V5V = 12 0.8VDD -- -- C IOH = 11 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) VDD 0.8 -- -- -- -- 0.1VDD VOL 1 C CC P Output low level Push Pull IOL = 14 mA, FAST configuration VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) C IOL = 7 mA, VDD = 5.0 V 10%, PAD3V5V = 12 -- -- 0.1VDD C IOL = 11 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- 0.5 V V VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 41 Electrical characteristics 2 The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 4.6.4 Output pin transition times Table 16. Output pin transition times Symbol C Value Conditions1 Parameter Unit Min Typ Max Ttr CC D Output transition time output pin2 CL = 25 pF SLOW configuration T CL = 50 pF D CL = 100 pF D CL = 25 pF T CL = 50 pF Ttr VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF D Ttr VDD = 5.0 V 10%, PAD3V5V = 0 CC D Output transition time output MEDIUM configuration T pin2 CL = 25 pF CL = 50 pF D CL = 100 pF D CL = 25 pF T CL = 50 pF D CL = 100 pF CC D Output transition time output pin2 CL = 25 pF FAST configuration CL = 50 pF VDD = 5.0 V 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 VDD = 3.3 V 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 VDD = 5.0 V 10%, PAD3V5V = 0 CL = 100 pF CL = 25 pF CL = 50 pF VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF 1 2 4.6.5 -- -- 50 -- -- 100 -- -- 125 -- -- 50 -- -- 100 -- -- 125 -- -- 10 -- -- 20 -- -- 40 -- -- 12 -- -- 25 -- -- 40 -- -- 4 -- -- 6 -- -- 12 -- -- 4 -- -- 7 -- -- 12 ns ns ns VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified CL includes device and package capacitances (CPKG < 5 pF). I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 17. Table 18 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. MPC5607B Microcontroller Data Sheet, Rev. 5 42 Freescale Semiconductor Electrical characteristics Table 17. I/O supply segments Supply segment Package 1 208 MAPBGA1 1 2 3 4 5 6 Equivalent to 176 LQFP segment pad distribution 7 8 MCKO MDOn /MSEO 176 LQFP pin7 - pin27 pin28 - pin57 pin59 - pin85 pin86 - pin123 pin124 - pin150 pin151 - pin6 -- -- 144 LQFP pin20 - pin49 pin51 - pin99 pin100 - pin122 pin 123 - pin19 -- -- -- -- 100 LQFP pin16 - pin35 pin37 - pin69 pin70 - pin83 pin84 - pin15 -- -- -- -- 208 MAPBGA available only as development package for Nexus2+ Table 18. I/O consumption Symbol C Value Conditions1 Parameter Unit Min Typ Max ISWTSLW,2 CC D Dynamic I/O current for SLOW configuration ISWTMED2 CC D Dynamic I/O current for MEDIUM configuration ISWTFST2 CC D Dynamic I/O current for FAST configuration IRMSSLW CC D Root medium square I/O current for SLOW configuration CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 20 VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 16 VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 29 VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 17 VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 110 mA VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 50 VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 2.3 -- -- 3.2 -- -- 6.6 -- -- 1.6 -- -- 2.3 -- -- 4.7 -- -- 6.6 -- -- 13.4 -- -- 18.3 -- -- 5 -- -- 8.5 -- -- 11 CL = 100 pF, 2 MHz CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, 2 MHz IRMSMED CC D Root medium square I/O current for MEDIUM configuration CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz VDD = 5.0 V 10%, PAD3V5V = 0 CL = 100 pF, 13 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, 13 MHz mA mA mA mA MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 43 Electrical characteristics Table 18. I/O consumption (continued) Symbol C Value Conditions1 Parameter Unit Min Typ Max IRMSFST CC D Root medium square I/O current for FAST configuration CL = 25 pF, 40 MHz -- -- 22 -- -- 33 -- -- 56 -- -- 14 -- -- 20 CL = 100 pF, 40 MHz -- -- 35 VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 70 VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 65 CL = 25 pF, 64 MHz VDD = 5.0 V 10%, PAD3V5V = 0 CL = 100 pF, 40 MHz CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz IAVGSEG 1 2 SR D Sum of all the static I/O current within a supply segment VDD = 3.3 V 10%, PAD3V5V = 1 mA mA VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to125 C, unless otherwise specified Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. Table 19 provides the weight of concurrent switching I/Os. In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain below the 100%. Table 19. I/O weight1 176 LQFP PAD 144/100 LQFP Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 PB[3] 5% -- 6% -- 13% -- 15% -- PC[9] 4% -- 5% -- 13% -- 15% -- PC[14] 4% -- 4% -- 13% -- 15% -- PC[15] 3% 4% 4% 4% 12% 18% 15% 16% PJ[4] 3% 4% 3% 3% 12% 18% 15% 16% PH[15] 2% 3% 3% 3% 11% 16% 13% 14% PH[13] 3% 4% 3% 4% 11% 15% 13% 14% PH[14] 3% 4% 4% 4% 11% 15% 13% 13% PI[6] 4% -- 4% -- 10% -- 12% -- PI[7] 4% -- 4% -- 10% -- 12% -- PG[5] 4% -- 5% -- 10% -- 12% -- PG[4] 4% 6% 5% 5% 9% 13% 11% 12% PG[3] 4% -- 5% -- 9% -- 11% -- PG[2] 4% 6% 5% 5% 9% 12% 10% 11% PA[2] 4% -- 5% -- 8% -- 10% -- PE[0] 4% -- 5% -- 8% -- 9% -- MPC5607B Microcontroller Data Sheet, Rev. 5 44 Freescale Semiconductor Electrical characteristics Table 19. I/O weight1 (continued) 176 LQFP PAD 144/100 LQFP Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 PA[1] 4% -- 5% -- 8% -- 9% -- PE[1] 4% 6% 5% 6% 7% 10% 9% 9% PE[8] 4% 6% 5% 6% 7% 10% 8% 9% PE[9] 4% -- 5% -- 6% -- 8% -- PE[10] 4% -- 5% -- 6% -- 7% -- PA[0] 4% 6% 5% 5% 6% 8% 7% 7% PE[11] 4% -- 5% -- 5% -- 6% -- PG[9] 9% -- 10% -- 9% -- 10% -- PG[8] 9% -- 11% -- 9% -- 11% -- PC[11] 9% -- 11% -- 9% -- 11% -- PC[10] 9% 13% 11% 12% 9% 13% 11% 12% PG[7] 9% -- 11% -- 9% -- 11% -- PG[6] 10% 14% 11% 12% 10% 14% 11% 12% PB[0] 10% 14% 12% 12% 10% 14% 12% 12% PB[1] 10% -- 12% -- 10% -- 12% -- PF[9] 10% -- 12% -- 10% -- 12% -- PF[8] 10% 14% 12% 13% 10% 14% 12% 13% PF[12] 10% 15% 12% 13% 10% 15% 12% 13% PC[6] 10% -- 12% -- 10% -- 12% -- PC[7] 10% -- 12% -- 10% -- 12% -- PF[10] 10% 14% 11% 12% 10% 14% 11% 12% PF[11] 9% -- 11% -- 9% -- 11% -- PA[15] 8% 12% 10% 10% 8% 12% 10% 10% PF[13] 8% -- 10% -- 8% -- 10% -- PA[14] 8% 11% 9% 10% 8% 11% 9% 10% PA[4] 7% -- 9% -- 7% -- 9% -- PA[13] 7% 10% 8% 9% 7% 10% 8% 9% PA[12] 7% -- 8% -- 7% -- 8% -- PB[9] 1% -- 1% -- 1% -- 1% -- PB[8] 1% -- 1% -- 1% -- 1% -- PB[10] 5% -- 6% -- 6% -- 7% -- PF[0] 5% -- 6% -- 6% -- 8% -- PF[1] 5% -- 6% -- 7% -- 8% -- MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 45 Electrical characteristics Table 19. I/O weight1 (continued) 176 LQFP PAD 144/100 LQFP Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 PF[2] 6% -- 7% -- 7% -- 9% -- PF[3] 6% -- 7% -- 8% -- 9% -- PF[4] 6% -- 7% -- 8% -- 10% -- PF[5] 6% -- 7% -- 9% -- 10% -- PF[6] 6% -- 7% -- 9% -- 11% -- PF[7] 6% -- 7% -- 9% -- 11% -- PJ[3] 6% -- 7% -- 10% -- 12% -- PJ[2] 6% -- 7% -- 10% -- 12% -- PJ[1] 6% -- 7% -- 11% -- 13% -- PJ[0] 6% -- 7% -- 11% -- 13% -- PI[15] 6% -- 7% -- 12% -- 14% -- PI[14] 6% -- 7% -- 12% -- 14% -- PD[0] 1% -- 1% -- 1% -- 1% -- PD[1] 1% -- 1% -- 1% -- 1% -- PD[2] 1% -- 1% -- 1% -- 1% -- PD[3] 1% -- 1% -- 1% -- 1% -- PD[4] 1% -- 1% -- 1% -- 1% -- PD[5] 1% -- 1% -- 1% -- 1% -- PD[6] 1% -- 1% -- 1% -- 2% -- PD[7] 1% -- 1% -- 1% -- 2% -- PD[8] 1% -- 1% -- 1% -- 2% -- PB[4] 1% -- 1% -- 1% -- 2% -- PB[5] 1% -- 1% -- 1% -- 2% -- PB[6] 1% -- 1% -- 1% -- 2% -- PB[7] 1% -- 1% -- 1% -- 2% -- PD[9] 1% -- 1% -- 1% -- 2% -- PD[10] 1% -- 1% -- 1% -- 2% -- PD[11] 1% -- 1% -- 1% -- 2% -- PB[11] 1% -- 1% -- 1% -- 2% -- PD[12] 11% -- 13% -- 15% -- 18% -- PB[12] 11% -- 13% -- 15% -- 17% -- PD[13] 11% -- 13% -- 14% -- 17% -- PB[13] 11% -- 13% -- 14% -- 17% -- MPC5607B Microcontroller Data Sheet, Rev. 5 46 Freescale Semiconductor Electrical characteristics Table 19. I/O weight1 (continued) 176 LQFP PAD 144/100 LQFP Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 PD[14] 11% -- 13% -- 14% -- 17% -- PB[14] 11% -- 13% -- 14% -- 16% -- PD[15] 11% -- 13% -- 13% -- 16% -- PB[15] 11% -- 13% -- 13% -- 15% -- PI[8] 10% -- 12% -- 12% -- 15% -- PI[9] 10% -- 12% -- 12% -- 15% -- PI[10] 10% -- 12% -- 12% -- 14% -- PI[11] 10% -- 12% -- 12% -- 14% -- PI[12] 10% -- 12% -- 11% -- 13% -- PI[13] 10% -- 11% -- 11% -- 13% -- PA[3] 9% -- 11% -- 11% -- 13% -- PG[13] 9% 13% 11% 11% 10% 14% 12% 13% PG[12] 9% 13% 10% 11% 10% 14% 12% 12% PH[0] 6% 8% 7% 7% 6% 9% 7% 8% PH[1] 6% 8% 7% 7% 6% 8% 7% 7% PH[2] 5% 7% 6% 6% 5% 7% 6% 7% PH[3] 5% 7% 5% 6% 5% 7% 6% 6% PG[1] 4% -- 5% -- 4% -- 5% -- PG[0] 4% 5% 4% 5% 4% 5% 4% 5% PF[15] 4% -- 4% -- 4% -- 4% -- PF[14] 4% 6% 5% 5% 4% 6% 5% 5% PE[13] 4% -- 5% -- 4% -- 5% -- PA[7] 5% -- 6% -- 5% -- 6% -- PA[8] 5% -- 6% -- 5% -- 6% -- PA[9] 6% -- 7% -- 6% -- 7% -- PA[10] 6% -- 8% -- 6% -- 8% -- PA[11] 8% -- 9% -- 8% -- 9% -- PE[12] 8% -- 9% -- 8% -- 9% -- PG[14] 8% -- 9% -- 8% -- 9% -- PG[15] 8% 11% 9% 10% 8% 11% 9% 10% PE[14] 8% -- 9% -- 8% -- 9% -- PE[15] 8% 11% 9% 10% 8% 11% 9% 10% PG[10] 8% -- 9% -- 8% -- 9% -- MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 47 Electrical characteristics Table 19. I/O weight1 (continued) 176 LQFP PAD 144/100 LQFP Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 PG[11] 7% 11% 9% 9% 7% 11% 9% 9% PH[11] 7% 10% 9% 9% 7% 10% 9% 9% PH[12] 7% 10% 8% 9% 7% 10% 8% 9% PI[5] 7% -- 8% -- 7% -- 8% -- PI[4] 7% -- 8% -- 7% -- 8% -- PC[3] 6% -- 8% -- 6% -- 8% -- PC[2] 6% 8% 7% 7% 6% 8% 7% 7% PA[5] 6% 8% 7% 7% 6% 8% 7% 7% PA[6] 5% -- 6% -- 5% -- 6% -- PH[10] 5% 7% 6% 6% 5% 7% 6% 6% PC[1] 5% 19% 5% 13% 5% 19% 5% 13% PC[0] 6% 9% 7% 8% 7% 10% 8% 8% PH[9] 7% -- 8% -- 7% -- 9% -- PE[2] 7% 10% 8% 9% 8% 11% 9% 10% PE[3] 7% 10% 9% 9% 8% 12% 10% 10% PC[5] 7% 11% 9% 9% 8% 12% 10% 11% PC[4] 8% 11% 9% 10% 9% 13% 10% 11% PE[4] 8% 11% 9% 10% 9% 13% 11% 12% PE[5] 8% 11% 10% 10% 9% 14% 11% 12% PH[4] 8% 12% 10% 10% 10% 14% 12% 12% PH[5] 8% -- 10% -- 10% -- 12% -- PH[6] 8% 12% 10% 11% 10% 15% 12% 13% PH[7] 9% 12% 10% 11% 11% 15% 13% 13% PH[8] 9% 12% 10% 11% 11% 16% 13% 14% PE[6] 9% 12% 10% 11% 11% 16% 13% 14% PE[7] 9% 12% 10% 11% 11% 16% 14% 14% PI[3] 9% -- 10% -- 12% -- 14% -- PI[2] 9% -- 10% -- 12% -- 14% -- PI[1] 9% -- 10% -- 12% -- 15% -- PI[0] 9% -- 10% -- 12% -- 15% -- MPC5607B Microcontroller Data Sheet, Rev. 5 48 Freescale Semiconductor Electrical characteristics Table 19. I/O weight1 (continued) 176 LQFP PAD Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 SRE = 0 SRE = 1 PC[12] 8% 12% 10% 11% 12% 18% 15% 16% PC[13] 8% -- 10% -- 13% -- 15% -- PC[8] 8% -- 10% -- 13% -- 15% -- PB[2] 8% 11% 9% 10% 13% 18% 15% 16% 1 4.7 144/100 LQFP VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified RESET electrical characteristics The device implements a dedicated bidirectional RESET pin. VDD VDDMIN RESET VIH VIL device reset forced by RESET device start-up phase Figure 7. Start-up reset requirements MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 49 Electrical characteristics VRESET hw_rst VDD `1' VIH VIL `0' filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter unknown reset state device under hardware reset WFRST WNFRST Figure 8. Noise filtering on reset signal Table 20. Reset electrical characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max VIH SR P Input High Level CMOS (Schmitt Trigger) -- VIL SR P Input low Level CMOS (Schmitt Trigger) -- 0.4 -- 0.35VDD V VHYS CC C Input hysteresis CMOS (Schmitt Trigger) -- 0.1VDD -- -- V Push Pull, IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD V Push Pull, IOL = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 12 -- -- 0.1VDD Push Pull, IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- 0.5 VOL CC P Output low level 0.65VDD -- VDD + 0.4 V MPC5607B Microcontroller Data Sheet, Rev. 5 50 Freescale Semiconductor Electrical characteristics Table 20. Reset electrical characteristics (continued) Symbol C Parameter Value Conditions1 Unit Min Typ Max CL = 25 pF, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 10 CL = 50 pF, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 20 CL = 100 pF, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 40 CL = 25 pF, VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 12 CL = 50 pF, VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 25 CL = 100 pF, VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 40 WFRST SR P RESET input filtered pulse -- -- -- 40 ns WNFRST SR P RESET input not filtered pulse -- 1000 -- -- ns 10 -- 150 A 10 -- 150 10 -- 250 Ttr CC D Output transition time output pin3 MEDIUM configuration |IWPU| CC P Weak pull-up current absolute VDD = 3.3 V 10%, PAD3V5V = 1 value VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 5.0 V 10%, PAD3V5V = 14 ns VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the device reference manual). 3 C includes device and package capacitance (C L PKG < 5 pF). 4 The configuration PAD3V5 = 1 when V = 5 V is only transient configuration during power-up. All pads but RESET DD and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 1 2 4.8 4.8.1 Power management electrical characteristics Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved: * * * HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD power pin. BV: High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV power pin. Voltage values should be aligned with VDD. LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device: -- LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. -- LV_CFLA: Low voltage supply for code Flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 51 Electrical characteristics -- LV_DFLA: Low voltage supply for data Flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. -- LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. CREG2 (LV_COR/LV_CFLA) GND VDD VSS_LV VDD_BV VREF I CREG1 (LV_COR/LV_DFLA) Voltage Regulator VDD_BV CDEC1 (Ballast decoupling) VDD_LVn VDD_LV VDD_LV DEVICE VSS_LV GND VSS_LVn VSS_LV DEVICE GND VSS VDD_LV VDD GND CREG3 (LV_COR/LV_PLL) CDEC2 (supply/IO decoupling) Figure 9. Voltage regulator capacitance connection The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH. Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 4.4, "Recommended operating conditions). Table 21. Voltage regulator electrical characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max CREGn SR -- Internal voltage regulator external capacitance -- 200 -- 500 nF RREG SR -- Stability capacitor equivalent serial resistance -- -- -- 0.2 CDEC1 SR -- Decoupling capacitance2 ballast VDD_BV/VSS_LV pair: VDD_BV = 4.5 V to 5.5 V 1003 4704 -- nF VDD_BV/VSS_LV pair: VDD_BV = 3 V to 3.6 V 400 -- MPC5607B Microcontroller Data Sheet, Rev. 5 52 Freescale Semiconductor Electrical characteristics Table 21. Voltage regulator electrical characteristics (continued) Symbol C Parameter 10 100 -- nF VMREG CC P Main regulator output voltage Before exting from reset -- 1.32 -- V 1.15 1.28 1.32 -- -- 150 mA mA SR -- Main regulator current provided to VDD_LV domain IMREG = 200 mA -- -- 2 IMREG = 0 mA -- -- 1 VLPREG CC P Low power regulator output voltage After trimming 1.15 1.23 1.32 V ILPREG SR -- Low power regulator current provided to VDD_LV domain -- -- 15 mA -- -- 600 A ILPREG = 0 mA; TA = 55 C -- 5 -- After trimming 1.15 1.23 1.32 V -- -- 5 mA IULPREG = 5 mA; TA = 55 C -- -- 100 A IULPREG = 0 mA; TA = 55 C -- 2 -- -- -- 4006 VULPREG CC P Ultra low power regulator output voltage IULPREG SR -- Ultra low power regulator current provided to VDD_LV domain IULPREGINT CC D Ultra low power regulator module current consumption IDD_BV 6 4.8.2 -- CC D Low power regulator module current ILPREG = 15 mA; consumption TA = 55 C -- 5 -- CC D Main regulator module current consumption ILPREGINT 4 Max VDD/VSS pair IMREGINT 3 Typ SR -- Decoupling capacitance regulator supply IMREG 2 Unit Min CDEC2 After trimming 1 Value Conditions1 CC D In-rush current on VDD_BV during power-up5 -- -- mA VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical value is in the range of 470 nF. This value is acceptable to guarantee operation from 4.5 V to 5.5 V External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating range. In-rush current is seen only for short time during power-up and on standby exit (max 20s, depending on external capacitances to be load). The duration of the in-rush current depends on the capacitance placed on LV pins. BV decaps must be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc. Voltage monitor electrical characteristics The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the VDD and the VDD_LV voltage while device is supplied: MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 53 Electrical characteristics * * * * * * POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors VDD to ensure device reset below minimum functional supply LVDHV3B monitors VDD_BV to ensure device reset below minimum functional supply LVDHV5 monitors VDD when application uses device in the 5.0 V 10% range LVDLVCOR monitors power domain No. 1 LVDLVBKP monitors power domain No. 0 NOTE When enabled, power domain No. 2 is monitored through LVDLVBKP. VDD VLVDHVxH VLVDHVxL RESET Figure 10. Low voltage monitor vs reset Table 22. Low voltage monitor electrical characteristics Symbol Parameter VPORUP SR P Supply for functional POR module VPORH CC P Power-on reset threshold Value Conditions1 TA = 25 C, after trimming Unit Min Typ Max 1.0 -- 5.5 1.5 -- 2.6 VLVDHV3H CC T LVDHV3 low voltage detector high threshold -- -- 2.95 VLVDHV3L CC P LVDHV3 low voltage detector low threshold 2.7 -- 2.9 VLVDHV3BH CC P LVDHV3B low voltage detector high threshold -- -- 2.95 VLVDHV3BL CC P LVDHV3BL low voltage detector low threshold 2.7 -- 2.9 VLVDHV5H CC T LVDHV5 low voltage detector high threshold -- -- 4.5 VLVDHV5L CC P LVDHV5 low voltage detector low threshold 3.8 -- 4.4 VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold 1.08 -- -- CC P LVDLVBKP low voltage detector low threshold 1.08 -- 1.14 VLVDLVBKPL 1 C V VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified MPC5607B Microcontroller Data Sheet, Rev. 5 54 Freescale Semiconductor Electrical characteristics 4.9 Low voltage domain power consumption Table 23 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. Table 23. Low voltage power domain electrical characteristics1 Symbol C Parameter Typ Max -- 115 1404 mA fCPU = 8 MHz -- 12 -- fCPU = 16 MHz -- 27 -- T fCPU = 32 MHz -- 43 -- P fCPU = 48 MHz -- 56 -- fCPU = 64 MHz -- 70 -- TA = 25 C -- 10 18 TA = 125 C -- 17 28 TA = 25 C -- 350 900 TA = 55 C -- 750 -- D TA = 85 C -- 2 -- D TA = 105 C -- 4 -- TA = 125 C -- 7 14 TA = 25 C -- 30 100 TA = 55 C -- 75 -- D TA = 85 C -- 180 -- D TA = 105 C -- 315 -- TA = 125 C -- 560 1700 TA = 25 C -- 20 60 TA = 55 C -- 45 -- D TA = 85 C -- 100 -- D TA = 105 C -- 165 -- D TA = 125 C -- 280 900 CC T RUN mode typical average current6 T P IDDHALT CC C HALT mode current7 P IDDSTOP Unit Min IDDMAX3 CC D RUN mode maximum average current IDDRUN5 Value Conditions2 CC P STOP mode current8 D -- Slow internal RC oscillator (128 kHz) running Slow internal RC oscillator (128 kHz) running P IDDSTDBY2 CC P STANDBY2 mode current9 D Slow internal RC oscillator (128 kHz) running P IDDSTDBY1 CC T STANDBY1 mode D current10 Slow internal RC oscillator (128 kHz) running mA mA A mA A A 1 Except for IDDMAX, all consumptions in this table apply to VDD_BV only and do not include VDD_HV. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 3 Running consumption is given on voltage regulator supply (VDDREG). IDDMAX is composed of three components: IDDMAX = IDD(VDD_BV) + IDD(VDD_HV) + IDD(VDD_HV_ADC). It does not include a fourth component linked to I/Os toggling which is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation on-going on data flash. Note that this value can be significantly reduced by the application: switch off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. 4 Higher current may be sunk by device during power-up and standby exit. Please refer to in-rush current in Table 21. 2 MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 55 Electrical characteristics 5 RUN current measured with typical application with accesses on both Flash and RAM. Only for the "P" classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. 7 Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz on. 10 MHz XTAL clock. FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex: instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 to 9 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication), instance: 1 to 5 clocks gated. RTC/API ON. PIT ON. STM ON. ADC1 OFF. ADC0 ON but no conversion except two analog watchdogs. 8 Only for the "P" classification: No clock, FIRC 16 MHz off, SIRC 128 kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode. 9 Only for the "P" classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum consumption, all possible modules switched off. 10 ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules switched off. 6 4.10 Flash memory electrical characteristics 4.10.1 Program/erase characteristics Table 24 shows the program and erase characteristics. Table 24. Program and erase specifications Value Symbol Tdwprogram C Parameter CC C Double word (64 bits) program time4 Conditions Code Flash Min Typ1 -- Data Flash T16Kpperase 16 KB block preprogram and erase time Code Flash 32 KB block preprogram and erase time Code Flash -- 128 KB block preprogram and erase time Code Flash -- D Erase Suspend Latency TESRT C Erase Suspend Request Rate 500 s 200 500 5000 ms 300 600 5000 ms 1300 7500 ms 400 -- Data Flash Teslat 50 300 Data Flash T128Kpperase Unit 22 Data Flash T32Kpperase 18 Initial Max3 max2 600 800 -- -- -- 30 30 s Code Flash 20 -- -- -- ms Data Flash 10 -- -- -- 1 Typical program and erase times assume nominal supply values and operation at 25 C. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead. MPC5607B Microcontroller Data Sheet, Rev. 5 56 Freescale Semiconductor Electrical characteristics Table 25. Flash module life Value Symbol C Parameter Conditions Unit Typ Max P/E CC C Number of program/erase cycles per block for 16 KB blocks over the operating temperature range (TJ) -- 100000 -- -- cycles P/E CC C Number of program/erase cycles per block for 32 KB blocks over the operating temperature range (TJ) -- 10000 100000 -- cycles P/E CC C Number of program/erase cycles per block for 128 KB blocks over the operating temperature range (TJ) -- 1000 100000 -- cycles 20 -- -- years 10 -- -- years 5 -- -- years Retention CC C Minimum data retention at 85 Blocks with C average ambient 0-1,000 P/E cycles temperature1 Blocks with 1,001-10,000 P/E cycles Blocks with 10,001-100,000 P/E cycles 1 Min Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range. ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Table 26. Flash read access timing Symbol fREAD 1 C Parameter Conditions1 Max Unit 2 wait states 64 MHz C 1 wait state 40 C 0 wait states 20 CC P Maximum frequency for Flash reading VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified Table 27 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference manual for definitions of these bit fields. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 57 Electrical characteristics Table 27. FLASH_BIU settings vs. frequency of operation Maximum frequency (MHz) APC RWSC WWSC DPFEN IPFEN PFLIM BFEN Up to and including 82 MHz TBD TBD TBD TBD TBD TBD TBD Up to and including 102 MHz TBD TBD TBD TBD TBD TBD TBD Up to and including 132 MHz TBD TBD TBD TBD TBD TBD TBD Default setting after reset TBD TBD TBD TBD TBD TBD TBD 4.10.2 Flash power supply DC characteristics Table 28 shows the power supply DC characteristics on external supply. Table 28. Flash power supply DC electrical characteristics Symbol Parameter Value Conditions1 Unit Min Typ Max 1 2 Code Flash -- -- 33 Data Flash -- -- 33 Program Code Flash /Erase on-going while Data Flash reading Flash registers 2 fCPU = 64 MHz -- -- 52 -- -- 33 Code Flash -- -- 1.1 mA Data Flash -- -- 900 A Code Flash -- -- 150 A Data Flash -- -- 150 ICFREAD CC Sum of the current consumption on VDDHV and VDDBV on read access IDFREAD Flash module read fCPU = 64 MHz2 ICFMOD CC Sum of the current consumption on VDDHV and VDDBV on matrix IDFMOD modification (program/erase) ICFLPW CC Sum of the current consumption on VDDHV and VDDBV during Flash low IDFLPW power mode -- ICFPWD CC Sum of the current consumption on VDDHV and VDDBV during Flash power IDFPWD down mode -- mA mA VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified fCPU 64 MHz can be achieved only at up to 105 C MPC5607B Microcontroller Data Sheet, Rev. 5 58 Freescale Semiconductor Electrical characteristics 4.10.3 Start-up/Switch-off timings Table 29. Start-up time/Switch-off time Symbol C Parameter Value Conditions1 Unit Min Typ Max TFLARSTEXIT CC T Delay for Flash module to exit reset mode -- -- -- 125 TFLALPEXIT CC T Delay for Flash module to exit low-power mode -- -- -- 0.5 TFLAPDEXIT CC T Delay for Flash module to exit power-down mode -- -- -- 30 TFLALPENTRY CC T Delay for Flash module to enter low-power mode -- -- -- 0.5 TFLAPDENTRY CC T Delay for Flash module to enter power-down mode -- -- -- 1.5 1 s VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 4.11 Electromagnetic compatibility (EMC) characteristics Susceptibility tests are performed on a sample basis during product characterization. 4.11.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for the application. * * Software recommendations The software flowchart must include the management of runaway conditions such as: -- Corrupted program counter -- Unexpected reset -- Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. 4.11.2 Electromagnetic interference (EMI) The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI measurements. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 59 Electrical characteristics Table 30. EMI radiated emission measurement1,2 Value Symbol C Parameter Conditions Unit Min -- fCPU 1 2 Max SR -- Scan range -- 0.150 SR -- Operating frequency -- -- 64 -- MHz -- -- 1.28 -- V No PLL frequency modulation -- -- 18 dBV 2% PLL frequency modulation -- -- 14 dBV VDD_LV SR -- LV operating voltages SEMI Typ CC T Peak level VDD = 5 V, TA = 25 C, LQFP144 package Test conforming to IEC 61967-2, fOSC = 8 MHz/fCPU = 64 MHz 1000 MHz EMI testing and I/O port waveforms per IEC 61967-1, -2, -4 For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative. 4.11.3 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 4.11.3.1 Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts(n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. Table 31. ESD absolute maximum ratings1,2 Conditions Class Max value3 Unit VESD(HBM) Electrostatic discharge voltage (Human Body Model) TA = 25 C conforming to AEC-Q100-002 H1C 2000 V VESD(MM) Electrostatic discharge voltage (Machine Model) TA = 25 C conforming to AEC-Q100-003 M2 200 VESD(CDM) Electrostatic discharge voltage (Charged Device Model) TA = 25 C conforming to AEC-Q100-011 C3A 500 Symbol Ratings 750 (corners) 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3 Data based on characterization results, not tested in production 4.11.3.2 Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance: MPC5607B Microcontroller Data Sheet, Rev. 5 60 Freescale Semiconductor Electrical characteristics * * A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard. Table 32. Latch-up results Symbol Parameter LU 4.12 Static latch-up class Conditions Class TA = 125 C conforming to JESD 78 II level A Fast external crystal oscillator (4 to 16 MHz) electrical characteristics The device provides an oscillator/resonator driver. Figure 11 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. Table 33 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations. EXTAL C1 Crystal EXTAL XTAL C2 DEVICE VDD I R EXTAL XTAL Resonator DEVICE XTAL DEVICE Figure 11. Crystal oscillator and resonator connection scheme NOTE XTAL/EXTAL must not be directly used to drive external circuits. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 61 Electrical characteristics Table 33. Crystal description Crystal motional capacitance (Cm) fF Crystal motional inductance (Lm) mH Load on xtalin/xtalout C1 = C2 (pF)1 Shunt capacitance between xtalout and xtalin C02 (pF) Nominal frequency (MHz) NDK crystal reference Crystal equivalent series resistance ESR 4 NX8045GB 300 2.68 591.0 21 2.93 8 NX5032GA 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 1 The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.). S_MTRANS bit (ME_GS register) 1 0 VXTAL 1/fMXOSC VMXOSC 90% VMXOSCOP 10% TMXOSCSU valid internal clock Figure 12. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Symbol fFXOSC C Parameter SR -- Fast external crystal oscillator frequency Value Conditions1 -- Unit Min Typ Max 4.0 -- 16.0 MHz MPC5607B Microcontroller Data Sheet, Rev. 5 62 Freescale Semiconductor Electrical characteristics Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued) Symbol gmFXOSC VFXOSC C Value Conditions1 Parameter Unit Min Typ Max CC C Fast external crystal oscillator transconductance VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 0 2.2 -- 8.2 CC P VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 0 2.0 -- 7.4 CC C VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 1 2.7 -- 9.7 CC C VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 1 2.5 -- 9.2 CC T Oscillation amplitude at EXTAL fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 1.3 -- -- fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 1.3 -- -- -- -- 0.95 VFXOSCOP CC P Oscillation operating point mA/V V V IFXOSC2 CC T Fast external crystal oscillator consumption -- -- 2 3 mA TFXOSCSU CC T Fast external crystal oscillator start-up time fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 -- -- 6 ms fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 -- -- 1.8 1 2 4.13 VIH SR P Input high level CMOS (Schmitt Trigger) Oscillator bypass mode 0.65VDD -- VDD + 0.4 V VIL SR P Input low level CMOS (Schmitt Trigger) Oscillator bypass mode 0.4 -- 0.35VDD V VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals). Slow external crystal oscillator (32 kHz) electrical characteristics The device provides a low power oscillator/resonator driver. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 63 Electrical characteristics OSC32K_EXTAL OSC32K_EXTAL Resonator Crystal C1 RP OSC32K_XTAL OSC32K_XTAL C2 DEVICE DEVICE Figure 13. Crystal oscillator and resonator connection scheme NOTE OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits. l C0 C1 Crystal Rm Cm C2 Lm C1 C2 Figure 14. Equivalent circuit of a quartz crystal Table 35. Crystal motional characteristics1 Value Symbol Parameter Conditions Unit Min Typ Max Lm Motional inductance -- -- 11.796 -- KH Cm Motional capacitance -- -- 2 -- fF -- 18 -- 28 pF k C1/C2 Load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground2 Rm3 Motional resistance AC coupled at C0 = 2.85 pF4 -- -- 65 4 -- -- 50 pF4 -- -- 35 AC coupled at C0 = 9.0 pF4 -- -- 30 AC coupled at C0 = 4.9 pF AC coupled at C0 = 7.0 MPC5607B Microcontroller Data Sheet, Rev. 5 64 Freescale Semiconductor Electrical characteristics 1 The crystal used is Epson Toyocom MC306. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It includes all the parasitics due to board traces, crystal and package. 3 Maximum ESR (Rm) of the crystal is 50 k 4 C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins. 2 OSCON bit (OSC_CTL register) 1 0 VOSC32K_XTAL 1/fLPXOSC32K VLPXOSC32K 90% 10% TLPXOSC32KSU valid internal clock Figure 15. Slow external crystal oscillator (32 kHz) electrical characteristics Table 36. Slow external crystal oscillator (32 kHz) electrical characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max fSXOSC SR -- Slow external crystal oscillator frequency -- 32 32.768 40 kHz VSXOSC CC T Oscillation amplitude -- -- 2.1 -- V ISXOSCBIAS CC T Oscillation bias current -- 2.5 A ISXOSC CC T Slow external crystal oscillator consumption -- -- -- 8 A TSXOSCSU CC T Slow external crystal oscillator start-up time -- -- -- 22 s 1 2 4.14 VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal. FMPLL electrical characteristics The device provides a frequency modulated phase locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 65 Electrical characteristics Table 37. FMPLL electrical characteristics Symbol C Value Conditions1 Parameter Unit Min Typ Max fPLLIN SR -- FMPLL reference clock2 -- 4 -- 64 MHz PLLIN SR -- FMPLL reference clock duty cycle2 -- 40 -- 60 % -- 16 -- 64 MHz -- 256 -- 512 MHz -- 245.76 -- 532.48 fPLLOUT CC P FMPLL output clock frequency fVCO3 CC P VCO frequency without frequency modulation P VCO frequency with frequency modulation fCPU SR -- System clock frequency -- -- -- 644 MHz fFREE CC P Free-running frequency -- 20 -- 150 MHz tLOCK CC P FMPLL lock time 40 100 s tSTJIT CC -- FMPLL short term Stable oscillator (fPLLIN = 16 MHz) jitter5 tLTJIT CC -- FMPLL long term jitter IPLL CC C FMPLL consumption fsys maximum -4 -- 4 % fPLLCLK at 64 MHz, 4000 cycles -- -- 10 ns TA = 25 C -- -- 4 mA VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 3 Frequency modulation is considered 4%. 4 fCPU 64 MHz can be achieved only at up to 105 C. 5 Short term jitter is measured on the clock rising edge at cycle n and n+4. 1 2 4.15 Fast internal RC oscillator (16 MHz) electrical characteristics The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up of the device. Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics Symbol Parameter 2, IFIRCPWD Value Conditions1 CC P Fast internal RC oscillator high TA = 25 C, trimmed frequency SR -- -- fFIRC IFIRCRUN C Unit Min Typ Max -- 16 -- 12 MHz 20 CC T Fast internal RC oscillator high TA = 25 C, trimmed frequency current in running mode -- -- 200 A CC D Fast internal RC oscillator high TA = 25 C frequency current in power down mode -- -- 10 A MPC5607B Microcontroller Data Sheet, Rev. 5 66 Freescale Semiconductor Electrical characteristics Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics (continued) Symbol C Value Conditions1 Parameter IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 C frequency and system clock current in stop mode Unit Min Typ Max sysclk = off -- 500 -- sysclk = 2 MHz -- 600 -- sysclk = 4 MHz -- 700 -- sysclk = 8 MHz -- 900 -- sysclk = 16 MHz -- 1250 -- A TFIRCSU CC C Fast internal RC oscillator start-up time VDD = 5.0 V 10% -- 1.1 2.0 s FIRCPRE CC C Fast internal RC oscillator precision after software trimming of fFIRC TA = 25 C 1 -- 1 % FIRCTRIM CC C Fast internal RC oscillator trimming step TA = 25 C -- 1.6 5 -- FIRCVAR CC C Fast internal RC oscillator variation over temperature and supply with respect to fFIRC at TA = 25 C in high-frequency configuration -- % 5 % VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 1 2 4.16 Slow internal RC oscillator (128 kHz) electrical characteristics The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock for the RTC module. Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max -- 128 -- 100 -- 150 -- -- 5 A CC P Slow internal RC oscillator low frequency SR -- TA = 25 C, trimmed ISIRC2, CC C Slow internal RC oscillator low frequency current TA = 25 C, trimmed TSIRCSU CC P Slow internal RC oscillator start-up TA = 25 C, VDD = 5.0 V 10% time -- 8 12 s SIRCPRE CC C Slow internal RC oscillator precision TA = 25 C after software trimming of fSIRC 2 -- 2 % SIRCTRIM CC C Slow internal RC oscillator trimming step -- 2.7 -- fSIRC -- -- kHz MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 67 Electrical characteristics Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics (continued) Symbol SIRCVAR 1 2 C Parameter Value Conditions1 CC C Slow internal RC oscillator variation High frequency configuration in temperature and supply with respect to fSIRC at TA = 55 C in high frequency configuration Unit Min Typ Max 10 -- 10 % VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 4.17 4.17.1 ADC electrical characteristics Introduction The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit). MPC5607B Microcontroller Data Sheet, Rev. 5 68 Freescale Semiconductor Electrical characteristics Offset Error OSE Gain Error GE 1023 1022 1021 1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2) code out 7 (1) 6 (1) Example of an actual transfer curve 5 (2) The ideal transfer curve (5) (3) Differential non-linearity error (DNL) 4 (4) Integral non-linearity error (INL) (4) (5) Center of a step of the actual transfer curve 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal) Offset Error OSE Figure 16. ADC_0 characteristic and error definitions 4.17.2 Input impedance and ADC accuracy In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 69 Electrical characteristics In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 4: Eqn. 4 R S + R F + R L + R SW + R AD 1 V A --------------------------------------------------------------------------- --- LSB R EQ 2 Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS VA Filter RF Current Limiter RL CF Channel Selection Sampling RSW1 RAD CP1 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 17. Input equivalent circuit (precise channels) MPC5607B Microcontroller Data Sheet, Rev. 5 70 Freescale Semiconductor Electrical characteristics EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS Filter RF VA Current Limiter RL CF RS RF CF RL RSW RAD CP CS CP1 Channel Selection Extended Switch Sampling RSW1 RSW2 RAD CP3 CP2 CS Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance (two contributions RSW1 and RSW2) Sampling Switch Impedance Pin Capacitance (three contributions, CP1, CP2 and CP3) Sampling Capacitance Figure 18. Input equivalent circuit (extended channels) A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 17): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). Voltage Transient on CS VCS VA VA2 V <0.5 LSB 1 2 1 < (RSW + RAD) CS << TS 2 = RL (CS + CP1 + CP2) VA1 TS t Figure 19. Transient behavior during sampling phase In particular two different transient periods can be distinguished: 1. A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 71 Electrical characteristics CP CS 1 = R SW + R AD --------------------CP + CS Eqn. 5 Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: Eqn. 6 1 R SW + R AD C S T S The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 7: Eqn. 7 V A1 C S + C P1 + C P2 = V A C P1 + C P2 2. A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: Eqn. 8 2 R L C S + C P1 + C P2 In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: Eqn. 9 10 2 = 10 R L C S + C P1 + C P2 TS Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge balance assuming now CS already charged at VA1): Eqn. 10 VA2 C S + C P1 + C P2 + C F = V A C F + V A1 C P1 + C P2 + C S The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as antialiasing. MPC5607B Microcontroller Data Sheet, Rev. 5 72 Freescale Semiconductor Electrical characteristics Analog source bandwidth (VA) TC < 2 RFCF (Conversion rate vs. filter pole) Noise fF = f0 (Anti-aliasing filtering condition) 2 f0 < fC (Nyquist) f0 f Anti-aliasing filter (fF = RC filter pole) fF f Sampled signal spectrum (fC = Conversion rate) f0 fC f Figure 20. Spectral representation of input signal Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the antialiasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS: Eqn. 11 VA C P1 + C P2 + C F ----------- = ------------------------------------------------------V A2 C P1 + C P2 + C F + C S From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: ADC_0 (10-bit) Eqn. 12 C F 2048 C S ADC_1 (12-bit) Eqn. 13 C F 8192 C S MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 73 Electrical characteristics 4.17.3 ADC electrical characteristics Table 40. ADC input leakage current Value Symbol C Parameter Conditions Unit Min Typ Max -- 1 -- ILKG CC C Input leakage current TA = 40 C No current injection on adjacent pin C TA = 25 C -- 1 -- C TA = 105 C -- 8 200 P TA = 125 C -- 45 400 nA Table 41. ADC_0 conversion characteristics (10-bit ADC_0) Symbol C Parameter Value Conditions1 Unit Min Typ Max VSS_ADC0 SR -- Voltage on VSS_HV_ADC0 (ADC_0 reference) pin with respect to ground (VSS)2 -- 0.1 -- 0.1 V VDD_ADC0 SR -- Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) -- VDD 0.1 -- VDD + 0.1 V -- VSS_ADC0 0.1 -- VDD_ADC0 + 0.1 V IADC0pwd SR -- ADC_0 consumption in power down mode -- -- -- 50 A IADC0run SR -- ADC_0 consumption in running mode -- -- -- 40 mA -- 6 -- ADC0_SYS SR -- ADC_0 digital clock duty cycle ADCLKSEL = 14 (ipg_clk) 45 -- 55 % -- -- -- 1.5 s fADC = 32 MHz, ADC0_conf_sample_input = 17 0.5 -- fADC = 6 MHz, INPSAMP = 255 -- -- 42 0.625 -- -- s VAINx fADC0 SR -- Analog input voltage3 SR -- ADC_0 analog frequency tADC0_PU SR -- ADC_0 power up delay 5 tADC0_S CC T Sample time tADC0_C CC P Conversion time6 fADC = 32 MHz, ADC_conf_comp = 2 32 + 4% MHz s CS CC D ADC_0 input sampling capacitance -- -- -- 3 pF CP1 CC D ADC_0 input pin capacitance 1 -- -- -- 3 pF CP2 CC D ADC_0 input pin capacitance 2 -- -- -- 1 pF CP3 CC D ADC_0 input pin capacitance 3 -- -- -- 1 pF MPC5607B Microcontroller Data Sheet, Rev. 5 74 Freescale Semiconductor Electrical characteristics Table 41. ADC_0 conversion characteristics (continued)(10-bit ADC_0) Symbol 3 4 5 6 7 Value Conditions1 Unit Min Typ Max CC D Internal resistance of analog source -- -- -- 3 k RSW2 CC D Internal resistance of analog source -- -- -- 2 k RAD CC D Internal resistance of analog source -- -- -- 2 k IINJ SR -- Input current Injection VDD = 3.3 V 10% 5 -- 5 mA VDD = 5.0 V 10% 5 -- 5 Current injection on one ADC_0 input, different from the converted one | INL | CC T Absolute value for integral nonlinearity No overload -- 0.5 1.5 LSB | DNL | CC T Absolute differential nonlinearity No overload -- 0.5 1.0 LSB | OFS | CC T Absolute offset error -- -- 0.5 -- LSB | GNE | CC T Absolute gain error -- -- 0.6 -- LSB LSB TUEX 2 Parameter RSW1 TUEP 1 C CC P Total unadjusted for precise channels, input only T pins Without current injection 2 0.6 2 With current injection 3 -- 3 CC T Total unadjusted error7 for extended channel T Without current injection 3 1 3 With current injection 4 error7 LSB 4 VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. Analog and digital VSS must be common (to be tied together externally). VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t ADC0_S. After the end of the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC0_S depend on programming. This parameter does not include the sample time tADC0_S, but only the time for determining the digital result and the time to load the result's register with the conversion result. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 75 Electrical characteristics Offset Error OSE Gain Error GE 4095 4094 4093 4092 4091 1 LSB ideal = AVDD / 4096 4090 (2) code out 7 (1) 6 (1) Example of an actual transfer curve 5 (5) (2) The ideal transfer curve (3) Differential non-linearity error (DNL) 4 (4) Integral non-linearity error (INL) (4) (5) Center of a step of the actual transfer curve 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 Vin(A) (LSBideal) Offset Error OSE Figure 21. ADC_1 characteristic and error definitions Table 42. ADC_1 conversion characteristics (12-bit ADC_1) Symbol C Parameter Value Conditions1 VSS_ADC1 SR -- Voltage on VSS_HV_ADC1 (ADC_1 reference) pin with respect to ground (VSS)2 -- VDD_ADC1 SR -- Voltage on VDD_HV_ADC1 pin (ADC_1 reference) with respect to ground (VSS) -- Unit Min Typ Max -0.1 -- 0.1 V VDD + 0.1 V VDD - 0.1 -- MPC5607B Microcontroller Data Sheet, Rev. 5 76 Freescale Semiconductor Electrical characteristics Table 42. ADC_1 conversion characteristics (12-bit ADC_1) (continued) Symbol C Parameter Value Conditions1 Unit Min VAINx SR -- Analog input voltage3 -- Typ VSS_ADC1 -- - 0.1 Max VDD_ADC1 + 0.1 V IADC1pwd SR -- ADC_1 consumption in power down mode -- -- -- 50 A IADC1run -- -- -- 6 mA VDD = 3.3 V 3.33 -- 20 + 4% MHz VDD = 5 V 3.33 -- 32 + 4% -- -- -- 1.5 s ns fADC1 SR -- ADC_1 consumption in running mode SR -- ADC_1 analog frequency tADC1_PU SR -- ADC_1 power up delay tADC1_S tADC1_C time4 fADC1 = 20 MHz, ADC1_conf_sample_input = 12 600 -- -- Sample time4 VDD = 5.0 V fADC1= 32 MHz, ADC1_conf_sample_input = 17 500 -- -- Sample time4 VDD = 3.3 V fADC1= 3.33 MHz, ADC1_conf_sample_input = 255 -- -- 76.2 Sample time4 VDD = 5.0 V fADC1= 3.33 MHz, ADC1_conf_sample_input = 255 -- -- 76.2 CC P Conversion time5 VDD = 3 .3 V fADC1 = 20MHz, ADC1_conf_comp = 0 2.4 -- -- s Conversion time5 VDD = 5.0 V fADC 1 = 32 MHz, ADC1_conf_comp = 0 1.5 -- -- s Conversion time5 VDD = 3.3 V fADC 1 = 13.33 MHz, ADC1_conf_comp = 0 -- -- 3.6 s Conversion time5 VDD = 5.0 V fADC1 = 13.33 MHz, ADC1_conf_comp = 0 -- -- 3.6 s 45 -- 55 % CC T Sample VDD = 3.3 V ADC1_SYS SR -- ADC_1 digital clock duty cycle ADCLKSEL = 16 s CS CC D ADC_1 input sampling capacitance -- -- -- 5 pF CP1 CC D ADC_1 input pin capacitance 1 -- -- -- 3 pF CP2 CC D ADC_1 input pin capacitance 2 -- -- -- 1 pF CP3 CC D ADC_1 input pin capacitance 3 -- -- -- 1.5 pF RSW1 CC D Internal resistance of analog source -- -- -- 1 k RSW2 CC D Internal resistance of analog source -- -- -- 2 k RAD CC D Internal resistance of analog source -- -- -- 0.3 k MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 77 Electrical characteristics Table 42. ADC_1 conversion characteristics (12-bit ADC_1) (continued) Symbol IINJ 3 4 5 6 7 SR -- Input current Injection Value Conditions1 Current VDD = 3.3 V 10% injection on VDD = 5.0 V 10% one ADC_1 input, different from the converted one Unit Min Typ Max -5 -- 5 -5 -- 5 mA CC T Absolute Integral No overload non-linearity-Precise channels -- 1 3 LSB INLX CC T Absolute Integral non-linearity-Extended channels No overload -- 1.5 5 LSB DNL CC T Absolute Differential non-linearity No overload -- 0.5 1 LSB OFS CC T Absolute Offset error -- -- 2 -- LSB GNE CC T Absolute Gain error -- -- 2 -- LSB LSB TUEX7 2 Parameter INLP TUEP7 1 C CC P Total Unadjusted Error for precise channels, input only T pins Without current injection -6 -- 6 With current injection -8 -- 8 CC T Total Unadjusted Error for extended channel T Without current injection -10 -- 10 With current injection -12 -- 12 LSB VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified Analog and digital VSS must be common (to be tied together externally). VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0xFFF. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC1_S depend on programming. This parameter does not include the sample time tADC1_S, but only the time for determining the digital result and the time to load the result's register with the conversion result. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. MPC5607B Microcontroller Data Sheet, Rev. 5 78 Freescale Semiconductor Electrical characteristics 4.18 On-chip peripherals 4.18.1 Current consumption Table 43. On-chip peripherals current consumption1 Value Symbol C Parameter Conditions Unit Typ IDD_BV(CAN) IDD_BV(eMIOS) CC T CAN Bitrate = (FlexCAN) 500 Kbps supply current Bitrate = on VDD_BV 125 Kbps Total (static + dynamic) consumption: * FlexCAN in loop-back mode * XTAL at 8 MHz used as CAN engine clock source * Message sending period is 580 s CC T eMIOS supply Static consumption: current on * eMIOS channel OFF VDD_BV * Global prescaler enabled Dynamic consumption: * It does not change varying the frequency (0.003 mA) IDD_BV(SCI) CC T SCI (LINFlex) Total (static + dynamic) consumption: supply current * LIN mode on VDD_BV * Baudrate: 20 Kbps IDD_BV(SPI) CC T SPI (DSPI) Ballast static consumption (only supply current clocked) on VDD_BV Ballast dynamic consumption (continuous communication): * Baudrate: 2 Mbit * Trasmission every 8 s * Frame: 16 bits IDD_BV (ADC_0/ADC_1) IDD_HV_ADC0 8 * fperiph + 85 A 8 * fperiph + 27 29 * fperiph 3 5 * fperiph + 31 1 16 * fperiph CC T ADC_0/ADC_1 VDD = 5.5 V Ballast static consumption supply current (no conversion) on VDD_BV VDD = 5.5 V Ballast dynamic consumption (continuous conversion) 41 * fperiph CC T ADC_0 supply VDD = 5.5 V Analog static consumption current on (no conversion) VDD_HV_ADC0 VDD = 5.5 V Analog dynamic consumption (continuous conversion) 200 A 46 * fperiph 3 mA MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 79 Electrical characteristics Table 43. On-chip peripherals current consumption1 (continued) Value Symbol C Parameter Conditions Unit Typ IDD_HV_ADC1 IDD_HV(FLASH) IDD_BV(PLL) 1 CC T ADC_1 supply VDD = 5.5 V Analog static consumption current on (no conversion) VDD_HV_ADC1 VDD = 5.5 V Analog dynamic consumption (continuous conversion) 300 * fperiph A 4 mA CC T CFlash + VDD = 5.5 V DFlash supply current on VDD_HV -- 12 mA CC T PLL supply current on VDD_BV -- 2.5 mA VDD = 5.5 V Operating conditions: TA = 25 C, fperiph = 8 MHz to 64 MHz MPC5607B Microcontroller Data Sheet, Rev. 5 80 Freescale Semiconductor Freescale Semiconductor 4.18.2 DSPI characteristics Table 44. DSPI characteristics1 DSPI0/DSPI1/DSPI5/DSPI6 No. 1 Symbol tSCK C DSPI2/DSPI4 Parameter Unit MPC5607B Microcontroller Data Sheet, Rev. 5 Min Typ Max Min Typ Max Master mode (MTFE = 0) 125 -- -- 333 -- -- D Slave mode (MTFE = 0) 125 -- -- 333 -- -- D Master mode (MTFE = 1) 83 -- -- 125 -- -- D Slave mode (MTFE = 1) 83 -- -- 125 -- -- -- -- fCPU -- -- fCPU MHz -- -- 153 ns SR D SCK cycle time ns -- fDSPI -- tCSC CC D Internal delay between pad Master mode associated to SCK and pad associated to CSn in master mode for CSn1->0 -- -- 1302 -- tASC CC D Internal delay between pad Master mode associated to SCK and pad associated to CSn in master mode for CSn1->1 -- -- 1303 -- -- 1303 ns SR D DSPI digital controller frequency 2 tCSCext4 SR D CS to SCK delay Slave mode 32 -- -- 32 -- -- ns 3 tASCext5 SR D After SCK delay Slave mode 1/fDSPI + 5 -- -- 1/fDSPI + 5 -- -- ns -- tSCK/2 -- -- tSCK/2 -- ns 4 tSDC CC D SCK duty cycle Master mode SR D Slave mode tSCK/2 -- -- tSCK/2 -- -- tA SR D Slave access time Slave mode -- -- 1/fDSPI + 70 -- -- 1/fDSPI + 130 ns 6 tDI SR D Slave SOUT disable time Slave mode 7 -- -- 7 -- -- ns 9 tSUI SR D Data setup time for inputs Master mode 43 -- -- 145 -- -- ns Slave mode 5 -- -- 5 -- -- Master mode 0 -- -- 0 -- -- Slave mode 26 -- -- 26 -- -- 10 tHI SR D Data hold time for inputs ns 81 Electrical characteristics 5 82 Table 44. DSPI characteristics1 (continued) 11 Symbol tSUO7 C Unit CC D Data valid after SCK edge Master mode Slave mode 12 tHO7 CC D Data hold time for outputs Master mode Slave mode 1 2 MPC5607B Microcontroller Data Sheet, Rev. 5 3 4 5 6 7 DSPI2/DSPI4 Parameter Min Typ Max Min Typ Max -- -- 32 -- -- 50 -- -- 52 -- -- 160 0 -- -- 0 -- -- 8 -- -- 13 -- -- ns ns Operating conditions: Cout = 10 to 50 pF, SlewIN = 3.5 to 15 ns Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK starts before CSn is asserted. DSPI2 has only SLOW SCK available. Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure positive tCSCext. The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive tASCext. This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register. SCK and SOUT are configured as MEDIUM pad. Electrical characteristics DSPI0/DSPI1/DSPI5/DSPI6 No. Freescale Semiconductor Electrical characteristics Figure 22. DSPI classic SPI timing -- master, CPHA = 0 2 3 PCSx 1 4 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 9 SIN 10 First Data Last Data Data 12 SOUT First Data 11 Data Last Data Note: Numbers shown reference Table 43. Figure 23. DSPI classic SPI timing -- master, CPHA = 1 PCSx SCK Output (CPOL = 0) 10 SCK Output (CPOL = 1) 9 SIN Data First Data 12 SOUT First Data Last Data 11 Data Last Data Note: Numbers shown reference Table 43. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 83 Electrical characteristics Figure 24. DSPI classic SPI timing -- slave, CPHA = 0 3 2 SS 1 4 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 First Data SOUT 9 6 Data Last Data Data Last Data 10 First Data SIN 11 12 Note: Numbers shown reference Table 43. Figure 25. DSPI classic SPI timing -- slave, CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 11 5 12 SOUT First Data 9 SIN Data Last Data Data Last Data 6 10 First Data Note: Numbers shown reference Table 43. MPC5607B Microcontroller Data Sheet, Rev. 5 84 Freescale Semiconductor Electrical characteristics Figure 26. DSPI modified transfer format timing -- master, CPHA = 0 3 PCSx 4 1 2 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 9 SIN 10 First Data Last Data Data 12 SOUT 11 First Data Last Data Data Note: Numbers shown reference Table 43. Figure 27. DSPI modified transfer format timing -- master, CPHA = 1 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) 10 9 SIN First Data Data 12 SOUT First Data Data Last Data 11 Last Data Note: Numbers shown reference Table 43. MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 85 Electrical characteristics Figure 28. DSPI modified transfer format timing -- slave, CPHA = 0 3 2 SS 1 SCK Input (CPOL = 0) 4 4 SCK Input (CPOL = 1) First Data SOUT Data 6 Last Data 10 9 Data First Data SIN 12 11 5 Last Data Note: Numbers shown reference Table 43. Figure 29. DSPI modified transfer format timing -- slave, CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 11 5 12 First Data SOUT 9 SIN Data Last Data Data Last Data 6 10 First Data Note: Numbers shown reference Table 43. MPC5607B Microcontroller Data Sheet, Rev. 5 86 Freescale Semiconductor Electrical characteristics 8 7 PCSS PCSx Note: Numbers shown reference Table 43. Figure 30. DSPI PCS strobe (PCSS) timing 4.18.3 Nexus characteristics Table 45. Nexus characteristics Value No. Symbol C Parameter Unit Min Typ Max 1 tTCYC CC D TCK cycle time 64 -- -- ns 2 tMCYC CC D MCKO cycle time 32 -- -- ns 3 tMDOV CC D MCKO low to MDO data valid -- -- 8 ns 4 tMSEOV CC D MCKO low to MSEO_b data valid -- -- 8 ns 5 tEVTOV CC D MCKO low to EVTO data valid -- -- 8 ns 6 tNTDIS CC D TDI data setup time 15 -- -- ns tNTMSS CC D TMS data setup time 15 -- -- ns tNTDIH CC D TDI data hold time 5 -- -- ns tNTMSH CC D TMS data hold time 5 -- -- ns 7 8 tTDOV CC D TCK low to TDO data valid 35 -- -- ns 9 tTDOI CC D TCK low to TDO data invalid 6 -- -- ns MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 87 Electrical characteristics TCK 10 11 TMS, TDI 12 TDO Note: Numbers shown reference Table 45. Figure 31. Nexus TDI, TMS, TDO timing 4.18.4 JTAG characteristics Table 46. JTAG characteristics Value No. Symbol C Parameter Unit Min Typ Max 1 tJCYC CC D TCK cycle time 64 -- -- ns 2 tTDIS CC D TDI setup time 15 -- -- ns 3 tTDIH CC D TDI hold time 5 -- -- ns 4 tTMSS CC D TMS setup time 15 -- -- ns 5 tTMSH CC D TMS hold time 5 -- -- ns 6 tTDOV CC D TCK low to TDO valid -- -- 33 ns 7 tTDOI CC D TCK low to TDO invalid 6 -- -- ns MPC5607B Microcontroller Data Sheet, Rev. 5 88 Freescale Semiconductor Electrical characteristics TCK 2/4 DATA INPUTS 3/5 INPUT DATA VALID 6 DATA OUTPUTS OUTPUT DATA VALID 7 DATA OUTPUTS Note: Numbers shown reference Table 46. Figure 32. Timing diagram -- JTAG boundary scan MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 89 Package characteristics 5 Package characteristics 5.1 Package mechanical data 5.1.1 176 LQFP Figure 33. 176 LQFP package mechanical drawing (Part 1 of 3) MPC5607B Microcontroller Data Sheet, Rev. 5 90 Freescale Semiconductor Package characteristics Figure 34. 176 LQFP package mechanical drawing (Part 2 of 3) MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 91 Package characteristics Figure 35. 176 LQFP package mechanical drawing (Part 3 of 3) MPC5607B Microcontroller Data Sheet, Rev. 5 92 Freescale Semiconductor Package characteristics 5.1.2 144 LQFP Figure 36. 144 LQFP package mechanical drawing (Part 1 of 2) MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 93 Package characteristics Figure 37. 144 LQFP package mechanical drawing (Part 2 of 2) MPC5607B Microcontroller Data Sheet, Rev. 5 94 Freescale Semiconductor Package characteristics 5.1.3 100 LQFP Figure 38. 100 LQFP package mechanical drawing (Part 1 of 3) MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 95 Package characteristics Figure 39. 100 LQFP package mechanical drawing (Part 2 of 3) MPC5607B Microcontroller Data Sheet, Rev. 5 96 Freescale Semiconductor Package characteristics Figure 40. 100 LQFP package mechanical drawing (Part 3 of 3) MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 97 Package characteristics 5.1.4 208 MAPBGA Figure 41. 208 MAPBGA package mechanical drawing (Part 1 of 2) MPC5607B Microcontroller Data Sheet, Rev. 5 98 Freescale Semiconductor Package characteristics Figure 42. 208 MAPBGA package mechanical drawing (Part 2 of 2) MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 99 Ordering information 6 Ordering information Figure 43. Commercial product code structure Example code: M PC 56 0 7 B F1A M LL 6 R Qualification Status Power Architecture Core Automotive Platform Core Version Flash Size (core dependent) Product Fab and Mask Indicator Temperature spec. Package Code Frequency R = Tape & Reel (blank if Tray) 1 Qualification Status M = general market qualified S = Automotive qualified P = Engineering samples Flash Size (for z0 core) 5 = 768 KB 6 = 1024 KB 7 = 1.5 MB Temperature spec. C = -40 to 85 C V = -40 to 105 C M = -40 to 125 C Automotive Platform 56 = PPC in 90nm Product B = Body Core Version 0 = e200z0 Fab and Mask Indicator F = ATMC Fab 0 = Version of the maskset A = Mask set indicator (Blank = 1st production maskset, A = 2nd, B = 3rd, etc) Package Code LL = 100 LQFP LQ = 144 LQFP LU = 176 LQFP MG = 208 MAPBGA1 Frequency 4 = Up to 48 MHz 6 = Up to 64 MHz 208 MAPBGA is available only as development package for Nexus2+. MPC5607B Microcontroller Data Sheet, Rev. 5 100 Freescale Semiconductor Abbreviations Appendix A Abbreviations Table 47 lists abbreviations used but not defined elsewhere in this document. Table 47. Abbreviations Abbreviation Meaning CMOS Complementary metal oxide semiconductor CPHA Clock phase CPOL Clock polarity CS Peripheral chip select EVTO Event out MCKO Message clock out MDO Message data out MSEO Message start/end out MTFE Modified timing format enable SCK Serial communications clock SOUT Serial data out TBD To be defined TCK Test clock input TDI Test data input TDO Test data output TMS Test mode select MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 101 Revision history 7 Revision history Table 48 summarizes revisions to this document. Table 48. Revision history Revision Date Substantive changes 1 12-Jan-2009 Initial release 2 09 Nov-2009 Updated Features Replaced 27 IRQs in place of 23 ADC features External Ballast resistor support conditions Updated device summary-added 208 BGA details Updated block diagram to include WKUP Updated block diagram to include 5 ch ADC 12 -bit Updated Block summary table Updated LQFP 144, 176 and 100 pinouts. Applied new naming convention for ADC signals as ADCx_P[x] and ADCx_S[x] Section 1, "General description Updated device comparison table Updated block diagram-aligned with 512k Updated block summary-aligned with 512k Section 2, "Package pinouts Updated 100,144,176,208 packages according to cut2.0 changes Added Section 3.5.1, "External ballast resistor recommendations Added NVUSRO [WATCHDOG_EN] field description Updated Absolute maximum ratings Updated LQFP thermal characteristics Updated I/O supply segments Updated Voltage regulator capacitance connection Updated Low voltage monitor electrical characteristics Updated Low voltage power domain electrical characteristics Updated DC electrical characteristics Updated Program/Erase specifications Updated Conversion characteristics (10 bit ADC) Updated FMPLL electrical characteristics Updated Fast RC oscillator electrical characteristics-aligned with MPC5604B Updated On-chip peripherals current consumption Updated ADC characteristics and error definitions diagram Updated ADC conversion characteristics (10 bit and 12 bit) Added ADC characteristics and error definitions diagram for 12 bit ADC 3 25 Jan-2010 Updated Features Updated block diagram to connect peripherals to pad I/O Updated block summary to include ADC 12-bit Updated 144, 176 and 100 pinouts to adjust format issues Table 26 Flash module life-retention value changed from 1-5 to 5 yrs Minor editing changes MPC5607B Microcontroller Data Sheet, Rev. 5 102 Freescale Semiconductor Revision history Table 48. Revision history (continued) Revision 4 Date Substantive changes 24 Aug 2010 Editorial changes and improvements. Updated "Features" section Table 1: updated footnote concerning 208 MAPBGA In the block diagram: * Added "5ch 12-bit ADC" block. * Updated Legend. * Added "Interrupt request with wakeup functionality" as an input to the WKPU block. Figure 2: removed alternate functions Figure 3: removed alternate functions Figure 4: removed alternate functions Table 3: added contents concerning the following blocks: CMU, eDMA, ECSM, MC_ME, MC_PCU, NMI, SSCM, SWT and WKPU Added Section 3.2, "Pin muxing Section 4, "Electrical characteristics: removed "Caution" note Section 4.2, "NVUSRO register: removed "NVUSRO[WATCHDOG_EN] field description" section Table 7: VIN: removed min value in "relative to VDD" row Table 8 * TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part: added new rows * TVDD: contents merged into one row * VDD_BV: changed min value in "relative to VDD" row Section 4.5, "Thermal characteristics * Section 4.5.1, "External ballast resistor recommendations: added new paragraph about power supply * Table 10: added RJB and RJC rows * Removed "208 MAPBGA thermal characteristics" table Table 11: rewrote parameter description of WFI and WNFI Section 4.6.5, "I/O pad current specification * Removed IDYNSEG information * Updated "I/O supply segments" table Table 18: removed IDYNSEG row Added Table 19 Table 21 * Updated all values * Removed IVREGREF and IVREDLVD12 rows * Added the footnote "The duration of the in-rush current depends on the capacitance placed on LV pins. BV decaps must be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc." to the IDD_BV specification. Table 22 * Updated VPORH min/max value * Updated VLVDLVCORL min value Updated Table 23 Table 24 * Tdwprogram: added initial max value * Inserted Teslat row Table 25: removed the "To be confirmed" footnote In the "Crystal oscillator and resonator connection scheme" figure, removed RP. Table 36 * Removed gmSXOSC row * ISXOSCBIAS: added min/typ/max value MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 103 Revision history Table 48. Revision history (continued) Revision 4 (cont.) 5 Date Substantive changes 24 Aug 2010 Table 37: (cont.) * Added fVCO row * Added tSTJIT row Table 38 * IFIRCPWD: removed row for TA = 55 C * Updated TFIRCSU row Table 41: Added two rows: IADC0pwd and IADC0run Table 42 * Added two rows: IADC1pwd and IADC1run * Updated values of fADC_1 and tADC1_PU * Updated tADC1_C row Updated Table 43 Updated Table 44 Updated Figure 43 Section 6, "Ordering information: deleted "Orderable part number summary" table 27 Aug 2010 Removed "Preliminary--Subject to Change Without Notice" marking. This data sheet contains specifications based on characterization data. MPC5607B Microcontroller Data Sheet, Rev. 5 104 Freescale Semiconductor THIS PAGE INTENTIONALLY BLANK MPC5607B Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor 105 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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