MPC5607BVLL4R - Freescale Semiconductor, Inc.

Freescale Semiconductor

Data Sheet: Technical Data Document Number: MPC5607B

Rev. 5, 08/2010

MPC5607B

100 LQFP

14 mm x 14 mm 144 LQFP

20 mm x 20 mm

176 LQFP

24 mm x 24 mm 208 MAPBGA

17 mm x 17 mm

• Single issue, 32-bit CPU core complex (e200z0h)

– Compliant with the Power Architecture® technology

embedded category

– Enhanced instruction set allowing variable length

encoding (VLE) for code size footprint reduction. With

the optional encoding of mixed 16-bit and 32-bit

instructions, it is possible to achieve significant code

size footprint reduction.

• Up to 1.5 MB on-chip code flash memory supported with

the flash memory controller

• 64 (4 × 16) KB on-chip data flash memory with EC C

• Up to 96 KB on-chip SRAM

• Memory protection unit (MPU ) with 8 region descriptors

and 32-byte region granularity on certain family members

(Refer to Table 1 for details.)

• Interrupt controller (INTC) capable of handling 204

selectable-priority interrupt sources

• Frequency modulated phase-locked loop (FMPLL)

• Crossbar switch architecture for concurrent access to

peripherals, Flash, or RAM from multiple bus masters

• 16-channel eDMA controller with multiple transfer request

sources using DMA multiplexer

• Boot assist module (BAM) supports internal Flash

programming via a serial link (CAN or SCI)

• Timer supports I/O channel s providing a range of 16-bit

input capture, output compare, and pulse width modulation

functions (eMIOS)

• 2 analog-to-digital converters (ADC): one 10-bi t and one

12-bit

• Cross Trigger Unit to enable synchronizatio n of ADC

conversions with a timer event from the eMIOS or PIT

• Up to 6 serial peripheral interface (DSPI) modules

• Up to 10 serial communication interface (LINFlex)

modules

• Up to 6 enhanced full CAN (FlexCAN) modules with

configurable buffers

• 1 inter-integrated circuit (I2C) interface module

• Up to 149 configurable general pu rpose pins supporting

input and output operations (package dependent)

• Real-Time Counter (RTC)

– Clock source from internal 128 kHz or 16 MHz

oscillator supporting autonomous wakeup with 1 ms

resolution with maximum timeout of 2 seconds

– Optional support for RT C with clock source from

external 32 kHz crystal oscillator, supporting wakeup

with 1 sec resolution and maximum timeout of 1 hour

• Up to 8 periodic interrupt timers (PIT) with 32-bit counter

resolution

• Nexus development interface (NDI) per IEEE-ISTO

5001-2003 Class Two Plus

• Device/board boundary scan testing supported per Joint

Test Action Group (JTAG) of IEEE (IEEE 1149.1)

• On-chip voltage regulator (VREG) for regulation of input

supply for all internal levels

MPC5607B Microcontroller

Data Sheet

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor2

Table of Contents

1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7

3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .31

4.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.2.1 NVUSRO[PAD3V5V] field description . . . . . . . .31

4.2.2 NVUSRO[OSCILLAT OR_MARGIN] field description

4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .32

4.4 Recommended operating conditions . . . . . . . . . . . . . .33

4.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .36

4.5.1 External ballast resistor recommendations . . . .36

4.5.2 Package thermal characteristics . . . . . . . . . . . .36

4.5.3 Power considerations. . . . . . . . . . . . . . . . . . . . .37

4.6 I/O pad electrical characteristics. . . . . . . . . . . . . . . . . .38

4.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.6.2 I/O input DC characteristics. . . . . . . . . . . . . . . .38

4.6.3 I/O output DC characteristics. . . . . . . . . . . . . . .39

4.6.4 Output pin transition times. . . . . . . . . . . . . . . . .42

4.6.5 I/O pad current specification . . . . . . . . . . . . . . .42

4.7 RESET electrical characteristics. . . . . . . . . . . . . . . . . .49

4.8 Power management electrical characteristics. . . . . . . .51

4.8.1 Voltage regulator electrical characteristics . . . .51

4.8.2 Voltage monitor electrical characteristics. . . . . .53

4.9 Low voltage domain power consumption . . . . . . . . . . .55

4.10 Flash memory electrical characteristics . . . . . . . . . . . .56

4.10.1 Program/erase characteristics. . . . . . . . . . . . . .56

4.10.2 Flash power supply DC characteristics . . . . . . .58

4.10.3 Start-up/Switch-off timings. . . . . . . . . . . . . . . . 59

4.11 Electromagnetic compatibility (EMC) characteristics. . 59

4.11.1 Designing hardened software to avoid noise

problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.11.2 Electromagnetic interference (EMI) . . . . . . . . . 59

4.11.3 Absolute maximum ratings (electrical sensitivity)60

4.12 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.13 Slow external crystal oscillator (32 kHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 65

4.15 Fast internal RC oscillator (16 MHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.16 Slow internal RC oscillator (128 kHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 68

4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.17.2 Input impedance and ADC accuracy . . . . . . . . 69

4.17.3 ADC electrical characteristics . . . . . . . . . . . . . 74

4.18 On-chip peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 79

4.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 81

4.18.3 Nexus characteristics. . . . . . . . . . . . . . . . . . . . 87

4.18.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 88

5 Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 90

5.1.1 176 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.1.2 144 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.1.3 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.1.4 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . . 98

6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Introduction

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 3

1 Introduction

1.1 Document overview

This document describes the features of the family and options available within the family members, and highlights important

electrical and physical characteristics of the device.

1.2 Description

This family of 32-bit system-on-chip (SoC) microcontrollers is the latest achievement in integrated automotive application

controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body

electronics applications within the vehicle.

The advanced and cost-efficient e200z0 host processor core of this automotive controller family complies with the Power

Architecture technology and only implements the VLE (variable-length encoding) APU (Auxiliary Processor Unit), providing

improved code density . It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power

consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported

with software drivers, operating systems and configuration code to assist with users implementations.

Table 1. MPC5607B family comparison1

Feature MPC5605B MPC5606B MPC5607B

CPU e200z0h

Execution speed2Up to 64 MHz

Code Flash 768 KB 1 MB 1.5 MB

Data Flash 64 (4 x 16) KB

SRAM 64 KB 80 KB 96 KB

MPU 8-entry

eDMA 16 ch

10-bit ADC Ye s

dedicated37ch 15ch 29ch 15ch 29ch

shared with 12-bit ADC 19 ch

12-bit ADC Ye s

dedicated45 ch

shared with 10-bit ADC 19 ch

Total timer I/O5

eMIOS 37 ch,

16-bit 64 ch,

16-bit

Counter / OPWM / ICOC610 ch

O(I)PWM / OPWFMB /

OPWMCB / ICOC77ch

O(I)PWM / ICOC87ch 14ch

OPWM / ICOC913 ch 33 ch

SCI (LINFlex) 46868 10

SPI (DSPI) 3565 6

MPC5607B Microcontroller Data Sheet, Rev. 5

Introduction

Freescale Semiconductor4

CAN (Fle xCAN) 6

I2C1

32 kHz oscillator Yes

GPIO10 77 121 149 121 149 149

Debug JTAG N2+

Package 100

LQFP 144

LQFP 176

LQFP 144

LQFP 176

LQFP 208 MAP

BGA11

1Feature set dependent on selected peripheral multiplexing; table shows example.

2Based on 105 C ambient operating temperature.

3Not shared with 12-bit ADC, but possibly shared with other alternate functions.

4Not shared with 10-bit ADC, but possibly shared with other alternate functions.

5Refer to eMIOS section of device reference manual for information on the channel configuration and functions.

6Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output

Compare.

7Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output

Compare.

8Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, P eriod and

Pulse width measurement.

9Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.

10 Maximum I/O count based on multiplexing with peripherals.

11 208 MAPBGA available only as development package for Nexus2 +.

Table 1. MPC5607B family comparison1 (continued)

Feature MPC5605B MPC5606B MPC5607B

Block diagram

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 5

2 Block diagram

Figure 1shows a top-level block di agram of the MPC5607B.

Figure 1. MPC5607B block diagram

6 x

DSPI

FMPLL

Nexus 2+

Nexus

SRAM

SIUL

Reset Control

96 KB

External

IMUX

GPIO &

JTAG

Pad Control

JTAG Port

Nexus Port e200z0h

Interrupt requests

64-bit 2 x 3 Crossbar Switch

6 x

FlexCAN

Peripheral Bridge

Interrupt

Request

Interrupt

Request

I/O

Clocks

Instructions

Data

Voltage

Regulator

NMI

SWT PIT

STM

NMI

SIUL

. . .

INTC

. . .

10 x

LINFlex

64 ch

29 ch 10-bit

MPU

CMU

SRAM Flash

Code Flash

1.5 MB Data Flash

64 KB

MC_PCUMC_MEMC_CGMMC_RGM BAM

CTU

RTC SSCM

(Master)

(Slave)

Controller

Legend:

ADC Analog-to-Digital Converter

BAM Boot Assist Module

CMU Clock Monito r Uni t

CTU Cross Triggering Unit

DSPI Deserial Serial Peripheral Interface

ECSM Error Correction Status Module

eDMA Enhanced Direct Memory Access

eMIOS Enhanced Modular Input Output System

Flash Flash memory

Flex CAN Controller Area Network

FMPLL Frequency-Modulated Phase-Locked Loop

I2C Inter-Integrated Circuit bus

IMUX Internal Multiplexer

INTC Interrupt Controller

JTAG JTAG controller

LINFlex Serial Communication Interface (LIN support)

MC_CGM Clock Generation Module

MC_ME Mode Entry Module

MC_PCU Power Control Unit

MC_RGM Reset Generation Module

MPU Memory Protection Unit

NMI Non-Maskable Interrupt

PIT Periodic Interrupt Timer

RTC Real-Time Clock

SIUL System Integration Unit Lite

SRAM Static Random-Access Memory

SSCM Syst em Status Configuration Module

STM System Timer Module

SWT Software Watchdog Timer

WKPU Wakeup Unit

XBAR Crossbar switch

MPU

ECSM

from peripheral

Registers

blocks

ADC eMIOS

19 ch 10-bit/12-bit

ADC

(Master)

. . .

WKPU

5 ch 12-bit

ADC

eDMA

Interrupt

request with

wakeup

functionality

MPC5607B Microcontroller Data Sheet, Rev. 5

Block diagram

Freescale Semiconductor6

Table 2 summarizes the functions of the blocks present on the MPC5607B.

Table 2. MPC5607B series block summary

Block Function

Analog-to-digital converter (ADC) Converts analog voltages to digital values

Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according

to the boot mode of the device

Clock generation module

(MC_CGM) Provides logic and control required for the generation of system and peripheral

clocks

Clock monitor unit (CMU) Monitors clock source (internal and external) integrity

Cross triggering unit (CTU) Enables synchronization of ADC conv ersions with a timer ev ent from the eMIOS

or from the PIT

Crossbar switch (XBAR) Supports simultaneous connections between tw o master ports and three slave

ports. Th e cro ssb ar su pp o rts a 32-bit address bus width and a 64-bi t dat a bus

width.

Deserial serial peripheral interface

(DSPI) Provides a synchronous serial interface f or comm unication with e xternal devices

Enhanced Direct Memory Access

(eDMA) P erforms complex data transf ers with minimal intervention from a host processor

via “n” programmab le channels

Enhanced modular input output

system (eMIOS) Provides the functionality to generate or measure events

Error Correction Status Module

(ECSM) Provides a myriad of miscellaneous control functions for the device including

program-visible inf ormation about configuration and revision levels, a reset status

inf o rmation on memory errors reported by error-correcting codes

Flash memory Provides non-volatile storage for program code, constants and variables

FlexCAN (controller area networ k ) Supports the standard CAN communications protocol

Frequency-modulated

phase-locked loop (FMPLL) Generates high-speed system clocks and supports programmable frequency

modulation

Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of

data exchange between devices

Inter na l multiplexer (IMUX) SIU

subblock Allows flexible mapping of peripheral interface on the different pins of the device

Interrupt controller (IN TC) Provides priority-based preemptive scheduling of interr upt requests

JTAG controller Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

LINFlex controller Manages a high number of LIN (Local Interconnect Network protocol) messages

efficiently wi t h a mini mum of CPU load

Memory protection unit (MPU) Provides hardware access control for all memory references generated in a

device

Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and

modetransition sequences in all functional states; also manages the pow er

control unit, reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 7

3 Package pinouts and signal descriptions

3.1 Package pinouts

The available LQFP pinouts and the ballmap are provided in the following figures. For pin signal descript ions, please see

Table 3.

Figure 2 shows the MPC5607B in the 176 LQFP package.

Non-Maskable Interrupt (NMI) Handles external events that must produce an immed iate response, such as

power do wn detection

Periodic interrupt timer (PIT) Produces per iodic interrupts and triggers

Power control unit (MC_PCU) Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

Real-time counter (RTC) A free running counter used for time keeping applications, the RTC can be

configured to generate an interrup t at a predefined interval independent of the

mode of operation (run mode or low-pow e r mode)

Reset generation module

(MC_RGM) Centralizes reset sources and manages the device reset sequence of the device

Static random-access memory

(SRAM) Provides storage for program code, constants, and variables

System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits

of bidirectional, general-purpose input and output signals and supports up to 32

e xternal interrupts with trigger event configuration

System status and configuration

module (SSCM) Provides system configuration and status data (such as memory size and status,

device mode and security status), device identification data, debug status port

enable and selection, and bus and peripheral abort enable/disable

System timer module (STM) Provides a set of output compare events to support AUTOSAR (AUTomotive

Open System ARchitecture) and operating system tasks

System watchdog timer (SWT) Provides protection from runaway code

WKPU (wakeup unit) The wakeup unit supports up to 18 e xternal sources that can generate interrupts

or wakeup events, of which 1 can cause non-maskable interrupt requests or

wakeup events.

Table 2. MPC5607B series block summary (continued)

Block Function

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor8

Figure 2. 176 LQFP pin configuration (top view)

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

PA[11]

PA[10]

PA[9]

PA[8]

PA[7]

PE[13]

PF[14]

PF[15]

VDD_HV

VSS_HV

PG[0]

PG[1]

PH[3]

PH[2]

PH[1]

PH[0]

PG[12]

PG[13]

PA[3]

PI[13]

PI[12]

PI[11]

PI[10]

PI[9]

PI[8]

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

PD[12]

VDD_HV_ADC1

VSS_HV_ADC1

PB[11]

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC0

VSS_HV_ADC0

PB[3]

PC[9]

PC[14]

EPC[15]

PJ[4]

VDD_HV

VSS_HV

PH[15]

PH[13]

PH[14]

PI[6]

PI[7]

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PG[9]

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

PB[1]

PF[9]

PF[8]

PF[12]

PC[6]

PC[7]

PF[10]

PF[11]

PA[15]

PF[13]

PA[14]

PA[4]

PA[13]

PA[12]

VDD_LV

VSS_LV

XTAL

VSS_HV

EXTAL

VDD_HV

PB[9]

PB[8]

PB[10]

PF[0]

PF[1]

PF[2]

PF[3]

PF[4]

PF[5]

PF[6]

PF[7]

PJ[3]

PJ[2]

PJ[1]

PJ[0]

PI[15]

PI[14]

PD[0]

PD[1]

PD[2]

PD[3]

PD[4]

PD[5]

PD[6]

PD[7]

VDD_HV

VSS_HV

PD[8]

PB[4]

PB[2]

PC[8]

PC[13]

PC[12]

PI[0]

PI[1]

PI[2]

PI[3]

PE[7]

PE[6]

PH[8]

PH[7]

PH[6]

PH[5]

PH[4]

PE[5]

PE[4]

PC[4]

PC[5]

PE[3]

PE[2]

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA[6]

PA[5]

PC[2]

PC[3]

PI[4]

PI[5]

PH[12]

PH[11]

PG[11]

PG[10]

PE[15]

PE[14]

PG[15]

PG[14]

PE[12]

176 LQFP

Top view

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 9

Figure 3 shows the MPC5607B in the 144 LQFP package.

Figure 3. 144 LQFP pin configuration (top view)

108

107

106

105

104

103

102

101

100

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

PB[3]

PC[9]

PC[14]

PC[15]

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PG[9]

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

PB[1]

PF[9]

PF[8]

PF[12]

PC[6]

PA[11]

PA[10]

PA[9]

PA[8]

PA[7]

PE[13]

PF[14]

PF[15]

VDD_HV

VSS_HV

PG[0]

PG[1]

PH[3]

PH[2]

PH[1]

PH[0]

PG[12]

PG[13]

PA[3]

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

VDD_HV_ADC1

VSS_HV_ADC1

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC0

VSS_HV_ADC0

PB[3]

PC[9]

PC[14]

PC[15]

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PG[9]

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

PB[1]

PF[9]

PF[8]

PF[12]

PC[6]

PB[2]

PC[8]

PC[13]

PC[12]

PE[7]

PE[6]

PH[8]

PH[7]

PH[6]

PH[5]

PH[4]

PE[5]

PE[4]

PC[4]

PC[5]

PE[3]

PE[2]

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA[6]

PA[5]

PC[2]

PC[3]

PG[11]

PG[10]

PE[15]

PE[14]

PG[15]

PG[14]

PE[12]

144 LQFP

Top view

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor10

Figure 4 shows the MPC5607B in the 100 LQFP package.

Figure 4. 100 LQFP pin configuration (top view)

Figure 5 shows the MPC5607B in the 208 MAPBGA package.

100

PB[3]

PC[9]

PC[14]

PC[15]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[11]

PC[10]

PB[0]

PB[1]

PC[6]

PA[11]

PA[10]

PA[9]

PA[8]

PA[7]

VDD_HV

VSS_HV

PA[3]

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

VDD_HV_ADC1

VSS_HV_ADC1

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC0

VSS_HV_ADC0

PC[7]

PA[15]

PA[14]

PA[4]

PA[13]

PA[12]

VDD_LV

VSS_LV

XTAL

VSS_HV

EXTAL

VDD_HV

PB[9]

PB[8]

PB[10]

PD[0]

PD[1]

PD[2]

PD[3]

PD[4]

PD[5]

PD[6]

PD[7]

PD[8]

PB[4]

PB[2]

PC[8]

PC[13]

PC[12]

PE[7]

PE[6]

PE[5]

PE[4]

PC[4]

PC[5]

PE[3]

PE[2]

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA[6]

PA[5]

PC[2]

PC[3]

PE[12]

100 LQFP

Top view

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 11

Figure 5. 208 MAPBGA configuration

1 2345678910111213141516

APC[8] PC[13] PH[15] PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[15] PH[11] NC NC A

BPC[9] PB[2] PH[13] PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] PI[2] PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B

CPC[14] VDD_HV PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] PI[3] PA[5] PI[5] PE[14] PE[12] PA[9] PA[8] C

DPH[14] PI[6] PC[15] PI[7] PH[6] PE[4] PE[2] VDD_LV VDD_HV NC PA[6] PH[12] PG[10] PF[14] PE[13] PA[7] D

EPG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_HV E

FPE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F

GPE[9] PE[8] PE[10] PA[0] VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV PI[12] PI[13] MSEO G

HVSS_HV PE[11] VDD_HV NC VSS_HV VSS_HV VSS_HV VSS_HV MDO3 MDO2 MDO0 MDO1 H

JRESET VSS_LV NC NC VSS_HV VSS_HV VSS_HV VSS_HV PI[8] PI[9] PI[10] PI[11] J

KEVTI NC VDD_BV VDD_LV VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV

_ADC1 PG[12] PA[3] PG[13] K

LPG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L

MPG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M

NPB[1] PF[9] PB[0] VDD_HV PJ[0] PA[4] VSS_LV EXTAL VDD_HV PF[0] PF[4] VSS_HV

_ADC1 PB[11] PD[10] PD[9] PD[11] N

PPF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[14] VDD_LV XTAL PB[10] PF[1] PF[5] PD[0] PD[3] VDD_HV

_ADC0 PB[6] PB[7] P

RPF[12] PC[6] PF[10] PF[11] VDD_HV PA[15] PA[13] PI[14] XTAL32 PF[3] PF[7] PD[2] PD[4] PD[7] VSS_HV

_ADC0 PB[5] R

TNC NC NC MCKO NC PF[13] PA[12] PI[15] EXTAL

32 PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T

1 2345678910111213141516

NOTE: The 208 MAPBGA is available only as development package for Nexus 2+. NC = Not connected

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor12

3.2 Pin muxing

Table 3 defines the pin list and muxing for thi s device.

Each entry of Table 3 shows all the possible configurations for each pin, via the alternate functions. The default function

assigned to each pin after reset is indicated by AF0.

Table 3. Functional port pin descriptions

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

Port A

PA[0] PCR[0] AF0

AF1

AF2

AF3

—

GPIO[0]

E0UC[0]

CLKOUT

E0UC[13]

WKUP[19]4

SIUL

eMIOS_0

MC_CGM

eMIOS_0

WKUP

I/O

MTristate121624G4

PA[1] PCR[1] AF0

AF1

AF2

AF3

—

GPIO[1]

E0UC[1]

NMI5

—

WKUP[2]4

SIUL

eMIOS_0

WKUP

—

WKUP

I/O

—

S Tristate 7 11 19 F3

PA[2] PCR[2] AF0

AF1

AF2

AF3

—

GPIO[2]

E0UC[2]

—

MA[2]

WKUP[3]4

SIUL

eMIOS_0

—

ADC_0

WKUP

I/O

—

S Tristate 5 9 17 F2

PA[3] PCR[3] AF0

AF1

AF2

AF3

—

GPIO[3]

E0UC[3]

LIN5TX

CS4_1

EIRQ[0]

ADC1_S[0]

SIUL

eMIOS_0

LINFlex_5

DSPI_1

SIUL

ADC_1

I/O

J Tristate 68 90 114 K15

PA[4] PCR[4] AF0

AF1

AF2

AF3

—

GPIO[4]

E0UC[4]

—

CS0_1

LIN5RX

WKUP[9]4

SIUL

eMIOS_0

—

DSPI_1

LINFlex_5

WKUP

I/O

—

I/O

STristate294351N6

PA[5] PCR[5] AF0

AF1

AF2

AF3

GPIO[5]

E0UC[5]

LIN4TX

—

SIUL

eMIOS_0

LINFlex_4

—

I/O

—

M Tristate 79 118 146 C11

PA[6] PCR[6] AF0

AF1

AF2

AF3

—

GPIO[6]

E0UC[6]

—

CS1_1

EIRQ[1]

LIN4RX

SIUL

eMIOS_0

—

DSPI_1

SIUL

LINFlex_4

I/O

—

S Tristate 80 119 147 D11

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 13

PA[7] PCR[7] AF0

AF1

AF2

AF3

—

GPIO[7]

E0UC[7]

LIN3TX

—

EIRQ[2]

ADC1_S[1]

SIUL

eMIOS_0

LINFlex_3

—

SIUL

ADC_1

I/O

—

J Tristate 71 104 128 D16

PA[8] PCR[8] AF0

AF1

AF2

AF3

—

N/A6

—

GPIO[8]

E0UC[8]

E0UC[14]

—

EIRQ[3]

ABS[0]

LIN3RX

SIUL

eMIOS_0

—

SIUL

BAM

LINFlex_3

I/O

—

S Input,

weak

pull-up

72 105 129 C16

PA[9] PCR[9] AF0

AF1

AF2

AF3

N/A6

GPIO[9]

E0UC[9]

—

CS2_1

FAB

SIUL

eMIOS_0

—

DSPI_1

BAM

I/O

—

SPull-

down 73 106 130 C15

PA[10] PCR[10] AF0

AF1

AF2

AF3

—

GPIO[10]

E0UC[10]

SDA

LIN2TX

ADC1_S[2]

SIUL

eMIOS_0

I2C_0

LINFlex_2

ADC_1

I/O

J Tristate 74 107 131 B16

PA[11] PCR[11] AF0

AF1

AF2

AF3

—

GPIO[11]

E0UC[11]

SCL

—

EIRQ[16]

LIN2RX

ADC1_S[3]

SIUL

eMIOS_0

I2C_0

—

SIUL

LINFlex_2

ADC_1

I/O

—

J Tristate 75 108 132 B15

PA[12] PCR[12] AF0

AF1

AF2

AF3

—

GPIO[12]

—

E0UC[28]

CS3_1

EIRQ[17]

SIN_0

SIUL

—

eMIOS_0

DSPI_1

SIUL

DSPI_0

I/O

—

I/O

STristate314553T7

PA[13] PCR[13] AF0

AF1

AF2

AF3

GPIO[13]

SOUT_0

E0UC[29]

—

SIUL

DSPI_0

eMIOS_0

—

I/O

—

MTristate304452R7

PA[14] PCR[14] AF0

AF1

AF2

AF3

—

GPIO[14]

SCK_0

CS0_0

E0UC[0]

EIRQ[4]

SIUL

DSPI_0

eMIOS_0

SIUL

I/O

MTristate284250P6

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor14

PA[15] PCR[15] AF0

AF1

AF2

AF3

—

GPIO[15]

CS0_0

SCK_0

E0UC[1]

WKUP[10]4

SIUL

DSPI_0

eMIOS_0

WKUP

I/O

MTristate274048R6

Port B

PB[0] PCR[16] AF0

AF1

AF2

AF3

GPIO[16]

CAN0TX

E0UC[30]

LIN0TX

SIUL

FlexCAN_0

eMIOS_0

LINFlex_0

I/O

MTristate233139N3

PB[1] PCR[17] AF0

AF1

AF2

AF3

—

GPIO[17]

—

E0UC[31]

—

WKUP[4]4

CAN0RX

LIN0RX

SIUL

—

eMIOS_0

—

WKUP

FlexCAN_0

LINFlex_0

I/O

—

I/O

—

STristate243240N1

PB[2] PCR[18] AF0

AF1

AF2

AF3

GPIO[18]

LIN0TX

SDA

E0UC[30]

SIUL

LINFlex_0

I2C_0

eMIOS_0

I/O

M Tristate 100 144 176 B2

PB[3] PCR[19] AF0

AF1

AF2

AF3

—

GPIO[19]

E0UC[31]

SCL

—

WKUP[11]4

LIN0RX

SIUL

eMIOS_0

I2C_0

—

WKUP

LINFlex_0

I/O

—

STristate111C3

PB[4] PCR[20] AF0

AF1

AF2

AF3

—

ADC0_P[0]

ADC1_P[0]

GPIO[20]

—

ADC_0

ADC_1

SIUL

—

ITristate507288T16

PB[5] PCR[21] AF0

AF1

AF2

AF3

—

ADC0_P[1]

ADC1_P[1]

GPIO[21]

—

ADC_0

ADC_1

SIUL

—

ITristate537591R16

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 15

PB[6] PCR[22] AF0

AF1

AF2

AF3

—

ADC0_P[2]

ADC1_P[2]

GPIO[22]

—

ADC_0

ADC_1

SIUL

—

ITristate547692P15

PB[7] PCR[23] AF0

AF1

AF2

AF3

—

ADC0_P[3]

ADC1_P[3]

GPIO[23]

—

ADC_0

ADC_1

SIUL

—

ITristate557793P16

PB[8] PCR[24] AF0

AF1

AF2

AF3

—

GPIO[24]

—

OSC32K_XTAL7

WKUP[25]

ADC0_S[0]

ADC1_S[4]

SIUL

—

OSC32K

WKUP

ADC_0

ADC_1

—

I — 39 53 61 R9

PB[9] PCR[25] AF0

AF1

AF2

AF3

—

GPIO[25]

—

OSC32K_EXTAL7

WKUP[26]

ADC0_S[1]

ADC1_S[5]

SIUL

—

OSC32K

WKUP

ADC_0

ADC_1

—

I — 38 52 60 T9

PB[10] PCR[26] AF0

AF1

AF2

AF3

—

GPIO[26]

—

WKUP[8]4

ADC0_S[2]

ADC1_S[6]

SIUL

—

WKUP

ADC_0

ADC_1

I/O

—

JTristate405462P9

PB[11] PCR[27] AF0

AF1

AF2

AF3

—

GPIO[27]

E0UC[3]

—

CS0_0

ADC0_S[3]

SIUL

eMIOS_0

—

DSPI_0

ADC_0

I/O

—

I/O

JTristate — — 97 N13

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor16

PB[12] PCR[28] AF0

AF1

AF2

AF3

—

GPIO[28]

E0UC[4]

—

CS1_0

ADC0_X[0]

SIUL

eMIOS_0

—

DSPI_0

ADC_0

I/O

—

J Tristate 61 83 101 M16

PB[13] PCR[29] AF0

AF1

AF2

AF3

—

GPIO[29]

E0UC[5]

—

CS2_0

ADC0_X[1]

SIUL

eMIOS_0

—

DSPI_0

ADC_0

I/O

—

J Tristate 63 85 103 M13

PB[14] PCR[30] AF0

AF1

AF2

AF3

—

GPIO[30]

E0UC[6]

—

CS3_0

ADC0_X[2]

SIUL

eMIOS_0

—

DSPI_0

ADC_0

I/O

—

J Tristate 65 87 105 L16

PB[15] PCR[31] AF0

AF1

AF2

AF3

—

GPIO[31]

E0UC[7]

—

CS4_0

ADC0_X[3]

SIUL

eMIOS_0

—

DSPI_0

ADC_0

I/O

—

J Tristate 67 89 107 L13

Port C

PC[0]8PCR[32] AF0

AF1

AF2

AF3

GPIO[32]

—

TDI

—

SIUL

—

JTAGC

—

I/O

—

M Input,

weak

pull-up

87 126 154 A8

PC[1]8PCR[33] AF0

AF1

AF2

AF3

GPIO[33]

—

TDO

—

SIUL

—

JTAGC

—

I/O

—

F9Tristate 82 121 149 C9

PC[2] PCR[34] AF0

AF1

AF2

AF3

—

GPIO[34]

SCK_1

CAN4TX

DEBUG[0]

EIRQ[5]

SIUL

DSPI_1

FlexCAN_4

SSCM

SIUL

I/O

M Tristate 78 117 145 A11

PC[3] PCR[35] AF0

AF1

AF2

AF3

—

GPIO[35]

CS0_1

MA[0]

DEBUG[1]

EIRQ[6]

CAN1RX

CAN4RX

SIUL

DSPI_1

ADC_0

SSCM

SIUL

FlexCAN_1

FlexCAN_4

I/O

S Tristate 77 116 144 B11

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 17

PC[4] PCR[36] AF0

AF1

AF2

AF3

—

GPIO[36]

E1UC[31]

—

DEBUG[2]

EIRQ[18]

SIN_1

CAN3RX

SIUL

eMIOS_1

—

SSCM

SIUL

DSPI_1

FlexCAN_3

I/O

—

M Tristate 92 131 159 B7

PC[5] PCR[37] AF0

AF1

AF2

AF3

—

GPIO[37]

SOUT_1

CAN3TX

DEBUG[3]

EIRQ[7]

SIUL

DSPI_1

FlexCAN_3

SSCM

SIUL

I/O

M Tristate 91 130 158 A7

PC[6] PCR[38] AF0

AF1

AF2

AF3

GPIO[38]

LIN1TX

E1UC[28]

DEBUG[4]

SIUL

LINFlex_1

eMIOS_1

SSCM

I/O

STristate253644R2

PC[7] PCR[39] AF0

AF1

AF2

AF3

—

GPIO[39]

—

E1UC[29]

DEBUG[5]

LIN1RX

WKUP[12]4

SIUL

—

eMIOS_1

SSCM

LINFlex_1

WKUP

I/O

—

I/O

STristate263745P3

PC[8] PCR[40] AF0

AF1

AF2

AF3

GPIO[40]

LIN2TX

E0UC[3]

DEBUG[6]

SIUL

LINFlex_2

eMIOS_0

SSCM

I/O

S Tristate 99 143 175 A1

PC[9] PCR[41] AF0

AF1

AF2

AF3

—

GPIO[41]

—

E0UC[7]

DEBUG[7]

WKUP[13]4

LIN2RX

SIUL

—

eMIOS_0

SSCM

WKUP

LINFlex_2

I/O

—

I/O

STristate222B1

PC[10] PCR[42] AF0

AF1

AF2

AF3

GPIO[42]

CAN1TX

CAN4TX

MA[1]

SIUL

FlexCAN_1

FlexCAN_4

ADC_0

I/O

MTristate222836M3

PC[11] PCR[43] AF0

AF1

AF2

AF3

—

GPIO[43]

—

MA[2]

WKUP[5]4

CAN1RX

CAN4RX

SIUL

—

ADC_0

WKUP

FlexCAN_1

FlexCAN_4

I/O

—

STristate212735M4

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor18

PC[12] PCR[44] AF0

AF1

AF2

AF3

—

GPIO[44]

E0UC[12]

—

EIRQ[19]

SIN_2

SIUL

eMIOS_0

—

SIUL

DSPI_2

I/O

—

M Tristate 97 141 173 B4

PC[13] PCR[45] AF0

AF1

AF2

AF3

GPIO[45]

E0UC[13]

SOUT_2

—

SIUL

eMIOS_0

DSPI_2

—

I/O

—

S Tristate 98 142 174 A2

PC[14] PCR[46] AF0

AF1

AF2

AF3

—

GPIO[46]

E0UC[14]

SCK_2

—

EIRQ[8]

SIUL

eMIOS_0

DSPI_2

—

SIUL

I/O

—

STristate333C1

PC[15] PCR[47] AF0

AF1

AF2

AF3

—

GPIO[47]

E0UC[15]

CS0_2

—

EIRQ[20]

SIUL

eMIOS_0

DSPI_2

—

SIUL

I/O

—

MTristate444D3

Port D

PD[0] PCR[48] AF0

AF1

AF2

AF3

—

GPIO[48]

—

WKUP[27]

ADC0_P[4]

ADC1_P[4]

SIUL

—

WKUP

ADC_0

ADC_1

—

ITristate416377P12

PD[1] PCR[49] AF0

AF1

AF2

AF3

—

GPIO[49]

—

WKUP[28]

ADC0_P[5]

ADC1_P[5]

SIUL

—

WKUP

ADC_0

ADC_1

—

ITristate426478T12

PD[2] PCR[50] AF0

AF1

AF2

AF3

—

GPIO[50]

—

ADC0_P[6]

ADC1_P[6]

SIUL

—

ADC_0

ADC_1

—

ITristate436579R12

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 19

PD[3] PCR[51] AF0

AF1

AF2

AF3

—

GPIO[51]

—

ADC0_P[7]

ADC1_P[7]

SIUL

—

ADC_0

ADC_1

—

ITristate446680P13

PD[4] PCR[52] AF0

AF1

AF2

AF3

—

GPIO[52]

—

ADC0_P[8]

ADC1_P[8]

SIUL

—

ADC_0

ADC_1

—

ITristate456781R13

PD[5] PCR[53] AF0

AF1

AF2

AF3

—

GPIO[53]

—

ADC0_P[9]

ADC1_P[9]

SIUL

—

ADC_0

ADC_1

—

ITristate466882T13

PD[6] PCR[54] AF0

AF1

AF2

AF3

—

GPIO[54]

—

ADC0_P[10]

ADC1_P[10]

SIUL

—

ADC_0

ADC_1

—

ITristate476983T14

PD[7] PCR[55] AF0

AF1

AF2

AF3

—

GPIO[55]

—

ADC0_P[11]

ADC1_P[11]

SIUL

—

ADC_0

ADC_1

—

ITristate487084R14

PD[8] PCR[56] AF0

AF1

AF2

AF3

—

GPIO[56]

—

ADC0_P[12]

ADC1_P[12]

SIUL

—

ADC_0

ADC_1

—

ITristate497187T15

PD[9] PCR[57] AF0

AF1

AF2

AF3

—

GPIO[57]

—

ADC0_P[13]

ADC1_P[13]

SIUL

—

ADC_0

ADC_1

—

ITristate567894N15

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor20

PD[10] PCR[58] AF0

AF1

AF2

AF3

—

GPIO[58]

—

ADC0_P[14]

ADC1_P[14]

SIUL

—

ADC_0

ADC_1

—

ITristate577995N14

PD[11] PCR[59] AF0

AF1

AF2

AF3

—

GPIO[59]

—

ADC0_P[15]

ADC1_P[15]

SIUL

—

ADC_0

ADC_1

—

ITristate588096N16

PD[12] PCR[60] AF0

AF1

AF2

AF3

—

GPIO[60]

CS5_0

E0UC[24]

—

ADC0_S[4]

SIUL

DSPI_0

eMIOS_0

—

ADC_0

I/O

—

J Tristate — — 100 M15

PD[13] PCR[61] AF0

AF1

AF2

AF3

—

GPIO[61]

CS0_1

E0UC[25]

—

ADC0_S[5]

SIUL

DSPI_1

eMIOS_0

—

ADC_0

I/O

—

J Tristate 62 84 102 M14

PD[14] PCR[62] AF0

AF1

AF2

AF3

—

GPIO[62]

CS1_1

E0UC[26]

—

ADC0_S[6]

SIUL

DSPI_1

eMIOS_0

—

ADC_0

I/O

—

J Tristate 64 86 104 L15

PD[15] PCR[63] AF0

AF1

AF2

AF3

—

GPIO[63]

CS2_1

E0UC[27]

—

ADC0_S[7]

SIUL

DSPI_1

eMIOS_0

—

ADC_0

I/O

—

J Tristate 66 88 106 L14

Port E

PE[0] PCR[64] AF0

AF1

AF2

AF3

—

GPIO[64]

E0UC[16]

—

WKUP[6]4

CAN5RX

SIUL

eMIOS_0

—

WKUP

FlexCAN_5

I/O

—

S Tristate 6 10 18 F1

PE[1] PCR[65] AF0

AF1

AF2

AF3

GPIO[65]

E0UC[17]

CAN5TX

—

SIUL

eMIOS_0

FlexCAN_5

—

I/O

—

M Tristate 8 12 20 F4

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 21

PE[2] PCR[66] AF0

AF1

AF2

AF3

—

GPIO[66]

E0UC[18]

—

EIRQ[21]

SIN_1

SIUL

eMIOS_0

—

SIUL

DSPI_1

I/O

—

M Tristate 89 128 156 D7

PE[3] PCR[67] AF0

AF1

AF2

AF3

GPIO[67]

E0UC[19]

SOUT_1

—

SIUL

eMIOS_0

DSPI_1

—

I/O

—

M Tristate 90 129 157 C7

PE[4] PCR[68] AF0

AF1

AF2

AF3

—

GPIO[68]

E0UC[20]

SCK_1

—

EIRQ[9]

SIUL

eMIOS_0

DSPI_1

—

SIUL

I/O

—

M Tristate 93 132 160 D6

PE[5] PCR[69] AF0

AF1

AF2

AF3

GPIO[69]

E0UC[21]

CS0_1

MA[2]

SIUL

eMIOS_0

DSPI_1

ADC_0

I/O

M Tristate 94 133 161 C6

PE[6] PCR[70] AF0

AF1

AF2

AF3

—

GPIO[70]

E0UC[22]

CS3_0

MA[1]

EIRQ[22]

SIUL

eMIOS_0

DSPI_0

ADC_0

SIUL

I/O

M Tristate 95 139 167 B5

PE[7] PCR[71] AF0

AF1

AF2

AF3

—

GPIO[71]

E0UC[23]

CS2_0

MA[0]

EIRQ[23]

SIUL

eMIOS_0

DSPI_0

ADC_0

SIUL

I/O

M Tristate 96 140 168 C4

PE[8] PCR[72] AF0

AF1

AF2

AF3

GPIO[72]

CAN2TX

E0UC[22]

CAN3TX

SIUL

FlexCAN_2

eMIOS_0

FlexCAN_3

I/O

M Tristate 9 13 21 G2

PE[9] PCR[73] AF0

AF1

AF2

AF3

—

GPIO[73]

—

E0UC[23]

—

WKUP[7]4

CAN2RX

CAN3RX

SIUL

—

eMIOS_0

—

WKUP

FlexCAN_2

FlexCAN_3

I/O

—

I/O

—

STristate101422G1

PE[10] PCR[74] AF0

AF1

AF2

AF3

—

GPIO[74]

LIN3TX

CS3_1

E1UC[30]

EIRQ[10]

SIUL

LINFlex_3

DSPI_1

eMIOS_1

SIUL

I/O

STristate111523G3

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor22

PE[11] PCR[75] AF0

AF1

AF2

AF3

—

GPIO[75]

E0UC[24]

CS4_1

—

LIN3RX

WKUP[14]4

SIUL

eMIOS_0

DSPI_1

—

LINFlex_3

WKUP

I/O

—

STristate131725H2

PE[12] PCR[76] AF0

AF1

AF2

AF3

—

GPIO[76]

—

E1UC[19]10

—

EIRQ[11]

SIN_2

ADC1_S[7]

SIUL

—

eMIOS_1

—

SIUL

DSPI_2

ADC_1

I/O

—

I/O

—

J Tristate 76 109 133 C14

PE[13] PCR[77] AF0

AF1

AF2

AF3

GPIO[77]

SOUT_2

E1UC[20]

—

SIUL

DSPI_2

eMIOS_1

—

I/O

—

S Tristate — 103 127 D15

PE[14] PCR[78] AF0

AF1

AF2

AF3

—

GPIO[78]

SCK_2

E1UC[21]

—

EIRQ[12]

SIUL

DSPI_2

eMIOS_1

—

SIUL

I/O

—

S Tristate — 112 136 C13

PE[15] PCR[79] AF0

AF1

AF2

AF3

GPIO[79]

CS0_2

E1UC[22]

—

SIUL

DSPI_2

eMIOS_1

—

I/O

—

M Tristate — 113 137 A13

Port F

PF[0] PCR[80] AF0

AF1

AF2

AF3

—

GPIO[80]

E0UC[10]

CS3_1

—

ADC0_S[8]

SIUL

eMIOS_0

DSPI_1

—

ADC_0

I/O

—

J Tristate — 55 63 N10

PF[1] PCR[81] AF0

AF1

AF2

AF3

—

GPIO[81]

E0UC[11]

CS4_1

—

ADC0_S[9]

SIUL

eMIOS_0

DSPI_1

—

ADC_0

I/O

—

J Tristate — 56 64 P10

PF[2] PCR[82] AF0

AF1

AF2

AF3

—

GPIO[82]

E0UC[12]

CS0_2

—

ADC0_S[10]

SIUL

eMIOS_0

DSPI_2

—

ADC_0

I/O

—

J Tristate — 57 65 T10

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 23

PF[3] PCR[83] AF0

AF1

AF2

AF3

—

GPIO[83]

E0UC[13]

CS1_2

—

ADC0_S[11]

SIUL

eMIOS_0

DSPI_2

—

ADC_0

I/O

—

J Tristate — 58 66 R10

PF[4] PCR[84] AF0

AF1

AF2

AF3

—

GPIO[84]

E0UC[14]

CS2_2

—

ADC0_S[12]

SIUL

eMIOS_0

DSPI_2

—

ADC_0

I/O

—

J Tristate — 59 67 N11

PF[5] PCR[85] AF0

AF1

AF2

AF3

—

GPIO[85]

E0UC[22]

CS3_2

—

ADC0_S[13]

SIUL

eMIOS_0

DSPI_2

—

ADC_0

I/O

—

J Tristate — 60 68 P11

PF[6] PCR[86] AF0

AF1

AF2

AF3

—

GPIO[86]

E0UC[23]

CS1_1

—

ADC0_S[14]

SIUL

eMIOS_0

DSPI_1

—

ADC_0

I/O

—

J Tristate — 61 69 T11

PF[7] PCR[87] AF0

AF1

AF2

AF3

—

GPIO[87]

—

CS2_1

—

ADC0_S[15]

SIUL

—

DSPI_1

—

ADC_0

I/O

—

JTristate — 62 70 R11

PF[8] PCR[88] AF0

AF1

AF2

AF3

GPIO[88]

CAN3TX

CS4_0

CAN2TX

SIUL

FlexCAN_3

DSPI_0

FlexCAN_2

I/O

M Tristate — 34 42 P1

PF[9] PCR[89] AF0

AF1

AF2

AF3

—

GPIO[89]

E1UC[1]

CS5_0

—

WKUP[22]4

CAN2RX

CAN3RX

SIUL

eMIOS_1

DSPI_0

—

WKUP

FlexCAN_2

FlexCAN_3

I/O

—

S Tristate — 33 41 N2

PF[10] PCR[90] AF0

AF1

AF2

AF3

GPIO[90]

CS1_0

LIN4TX

E1UC[2]

SIUL

DSPI_0

LINFlex_4

eMIOS_1

I/O

M Tristate — 38 46 R3

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor24

PF[11] PCR[91] AF0

AF1

AF2

AF3

—

GPIO[91]

CS2_0

E1UC[3]

—

WKUP[15]4

LIN4RX

SIUL

DSPI_0

eMIOS_1

—

WKUP

LINFlex_4

I/O

—

S Tristate — 39 47 R4

PF[12] PCR[92] AF0

AF1

AF2

AF3

GPIO[92]

E1UC[25]

LIN5TX

—

SIUL

eMIOS_1

LINFlex_5

—

I/O

—

M Tristate — 35 43 R1

PF[13] PCR[93] AF0

AF1

AF2

AF3

—

GPIO[93]

E1UC[26]

—

WKUP[16]4

LIN5RX

SIUL

eMIOS_1

—

WKUP

LINFlex_5

I/O

—

S Tristate — 41 49 T6

PF[14] PCR[94] AF0

AF1

AF2

AF3

GPIO[94]

CAN4TX

E1UC[27]

CAN1TX

SIUL

FlexCAN_4

eMIOS_1

FlexCAN_1

I/O

M Tristate — 102 126 D14

PF[15] PCR[95] AF0

AF1

AF2

AF3

—

GPIO[95]

E1UC[4]

—

EIRQ[13]

CAN1RX

CAN4RX

SIUL

eMIOS_1

—

SIUL

FlexCAN_1

FlexCAN_4

I/O

—

S Tristate — 101 125 E15

Port G

PG[0] PCR[96] AF0

AF1

AF2

AF3

GPIO[96]

CAN5TX

E1UC[23]

—

SIUL

FlexCAN_5

eMIOS_1

—

I/O

—

M Tristate — 98 122 E14

PG[1] PCR[97] AF0

AF1

AF2

AF3

—

GPIO[97]

—

E1UC[24]

—

EIRQ[14]

CAN5RX

SIUL

—

eMIOS_1

—

SIUL

FlexCAN_5

I/O

—

I/O

—

S Tristate — 97 121 E13

PG[2] PCR[98] AF0

AF1

AF2

AF3

GPIO[98]

E1UC[11]

SOUT_3

—

SIUL

eMIOS_1

DSPI_3

—

I/O

—

M Tristate — 8 16 E4

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 25

PG[3] PCR[99] AF0

AF1

AF2

AF3

—

GPIO[99]

E1UC[12]

CS0_3

—

WKUP[17]4

SIUL

eMIOS_1

DSPI_3

—

WKUP

I/O

—

S Tristate — 7 15 E3

PG[4] PCR[100] AF0

AF1

AF2

AF3

GPIO[100]

E1UC[13]

SCK_3

—

SIUL

eMIOS_1

DSPI_3

—

I/O

—

M Tristate — 6 14 E1

PG[5] PCR[101] AF0

AF1

AF2

AF3

—

GPIO[101]

E1UC[14]

—

WKUP[18]4

SIN_3

SIUL

eMIOS_1

—

WKUP

DSPI_3

I/O

—

S Tristate — 5 13 E2

PG[6] PCR[102] AF0

AF1

AF2

AF3

GPIO[102]

E1UC[15]

LIN6TX

—

SIUL

eMIOS_1

LINFlex_6

—

I/O

—

M Tristate — 30 38 M2

PG[7] PCR[103] AF0

AF1

AF2

AF3

—

GPIO[103]

E1UC[16]

E1UC[30]

—

WKUP[20]4

LIN6RX

SIUL

eMIOS_1

—

WKUP

LINFlex_6

I/O

—

S Tristate — 29 37 M1

PG[8] PCR[104] AF0

AF1

AF2

AF3

—

GPIO[104]

E1UC[17]

LIN7TX

CS0_2

EIRQ[15]

SIUL

eMIOS_1

LINFlex_7

DSPI_2

SIUL

I/O

S Tristate — 26 34 L2

PG[9] PCR[105] AF0

AF1

AF2

AF3

—

GPIO[105]

E1UC[18]

—

SCK_2

WKUP[21]4

LIN7RX

SIUL

eMIOS_1

—

DSPI_2

WKUP

LINFlex_7

I/O

—

I/O

S Tristate — 25 33 L1

PG[10] PCR[106] AF0

AF1

AF2

AF3

—

GPIO[106]

E0UC[24]

E1UC[31]

—

SIN_4

SIUL

eMIOS_0

eMIOS_1

—

DSPI_4

I/O

—

S Tristate — 114 138 D13

PG[11] PCR[107] AF0

AF1

AF2

AF3

GPIO[107]

E0UC[25]

CS0_4

—

SIUL

eMIOS_0

DSPI_4

—

I/O

—

M Tristate — 115 139 B12

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor26

PG[12] PCR[108] AF0

AF1

AF2

AF3

GPIO[108]

E0UC[26]

SOUT_4

—

SIUL

eMIOS_0

DSPI_4

—

I/O

—

M Tristate — 92 116 K14

PG[13] PCR[109] AF0

AF1

AF2

AF3

GPIO[109]

E0UC[27]

SCK_4

—

SIUL

eMIOS_0

DSPI_4

—

I/O

—

M Tristate — 91 115 K16

PG[14] PCR[110] AF0

AF1

AF2

AF3

GPIO[110]

E1UC[0]

LIN8TX

—

SIUL

eMIOS_1

LINFlex_8

—

I/O

—

S Tristate — 110 134 B14

PG[15] PCR[111] AF0

AF1

AF2

AF3

—

GPIO[111]

E1UC[1]

—

LIN8RX

SIUL

eMIOS_1

—

LINFlex_8

I/O

—

M Tristate — 111 135 B13

Port H

PH[0] PCR[112] AF0

AF1

AF2

AF3

—

GPIO[112]

E1UC[2]

—

SIN_1

SIUL

eMIOS_1

—

DSPI_1

I/O

—

M Tristate — 93 117 F13

PH[1] PCR[113] AF0

AF1

AF2

AF3

GPIO[113]

E1UC[3]

SOUT_1

—

SIUL

eMIOS_1

DSPI_1

—

I/O

—

M Tristate — 94 118 F14

PH[2] PCR[114] AF0

AF1

AF2

AF3

GPIO[114]

E1UC[4]

SCK_1

—

SIUL

eMIOS_1

DSPI_1

—

I/O

—

M Tristate — 95 119 F16

PH[3] PCR[115] AF0

AF1

AF2

AF3

GPIO[115]

E1UC[5]

CS0_1

—

SIUL

eMIOS_1

DSPI_1

—

I/O

—

M Tristate — 96 120 F15

PH[4] PCR[116] AF0

AF1

AF2

AF3

GPIO[116]

E1UC[6]

—

SIUL

eMIOS_1

—

I/O

—

M Tristate — 134 162 A6

PH[5] PCR[117] AF0

AF1

AF2

AF3

GPIO[117]

E1UC[7]

—

SIUL

eMIOS_1

—

I/O

—

S Tristate — 135 163 B6

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 27

PH[6] PCR[118] AF0

AF1

AF2

AF3

GPIO[118]

E1UC[8]

—

MA[2]

SIUL

eMIOS_1

—

ADC_0

I/O

—

M Tristate — 136 164 D5

PH[7] PCR[119] AF0

AF1

AF2

AF3

GPIO[119]

E1UC[9]

CS3_2

MA[1]

SIUL

eMIOS_1

DSPI_2

ADC_0

I/O

M Tristate — 137 165 C5

PH[8] PCR[120] AF0

AF1

AF2

AF3

GPIO[120]

E1UC[10]

CS2_2

MA[0]

SIUL

eMIOS_1

DSPI_2

ADC_0

I/O

M Tristate — 138 166 A5

PH[9]8PCR[121] AF0

AF1

AF2

AF3

GPIO[121]

—

TCK

—

SIUL

—

JTAGC

—

I/O

—

S Input,

weak

pull-up

88 127 155 B8

PH[10]8PCR[122] AF0

AF1

AF2

AF3

GPIO[122]

—

TMS

—

SIUL

—

JTAGC

—

I/O

—

M Input,

weak

pull-up

81 120 148 B9

PH[11] PCR[123] AF0

AF1

AF2

AF3

GPIO[123]

SOUT_3

CS0_4

E1UC[5]

SIUL

DSPI_3

DSPI_4

eMIOS_1

I/O

—

M Tristate — — 140 A14

PH[12] PCR[124] AF0

AF1

AF2

AF3

GPIO[124]

SCK_3

CS1_4

E1UC[25]

SIUL

DSPI_3

DSPI_4

eMIOS_1

I/O

—

M Tristate — — 141 D12

PH[13] PCR[125] AF0

AF1

AF2

AF3

GPIO[125]

SOUT_4

CS0_3

E1UC[26]

SIUL

DSPI_4

DSPI_3

eMIOS_1

I/O

—

MTristate — — 9 B3

PH[14] PCR[126] AF0

AF1

AF2

AF3

GPIO[126]

SCK_4

CS1_3

E1UC[27]

SIUL

DSPI_4

DSPI_3

eMIOS_1

I/O

—

M Tristate — — 10 D1

PH[15] PCR[127] AF0

AF1

AF2

AF3

GPIO[127]

SOUT_5

—

E1UC[17]

SIUL

DSPI_5

—

eMIOS_1

I/O

—

MTristate — — 8 A3

Port I

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor28

PI[0] PCR[128] AF0

AF1

AF2

AF3

GPIO[128]

E0UC[28]

LIN8TX

—

SIUL

eMIOS_0

LINFlex_8

—

I/O

—

S Tristate — — 172 A9

PI[1] PCR[129] AF0

AF1

AF2

AF3

—

GPIO[129]

E0UC[29]

—

WKUP[24]4

LIN8RX

SIUL

eMIOS_0

—

WKUP

LINFlex_8

I/O

—

S Tristate — — 171 A10

PI[2] PCR[130] AF0

AF1

AF2

AF3

GPIO[130]

E0UC[30]

LIN9TX

—

SIUL

eMIOS_0

LINFlex_9

—

I/O

—

S Tristate — — 170 B10

PI[3] PCR[131] AF0

AF1

AF2

AF3

—

GPIO[131]

E0UC[31]

—

WKUP[23]4

LIN9RX

SIUL

eMIOS_0

—

WKUP

LINFlex_9

I/O

—

S Tristate — — 169 C10

PI[4] PCR[132] AF0

AF1

AF2

AF3

GPIO[132]

E1UC[28]

SOUT_4

—

SIUL

eMIOS_1

DSPI_4

—

I/O

—

S Tristate — — 143 A12

PI[5] PCR[133] AF0

AF1

AF2

AF3

GPIO[133]

E1UC[29]

SCK_4

—

SIUL

eMIOS_1

DSPI_4

—

I/O

—

S Tristate — — 142 C12

PI[6] PCR[134] AF0

AF1

AF2

AF3

GPIO[134]

E1UC[30]

CS0_4

—

SIUL

eMIOS_1

DSPI_4

—

I/O

—

S Tristate — — 11 D2

PI[7] PCR[135] AF0

AF1

AF2

AF3

GPIO[135]

E1UC[31]

CS1_4

—

SIUL

eMIOS_1

DSPI_4

—

I/O

—

S Tristate — — 12 D3

PI[8] PCR[136] AF0

AF1

AF2

AF3

—

GPIO[136]

—

ADC0_S[16]

SIUL

—

ADC_0

I/O

—

J Tristate — — 108 J13

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

Package pinouts and signal descriptions

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 29

PI[9] PCR[137] AF0

AF1

AF2

AF3

—

GPIO[137]

—

ADC0_S[17]

SIUL

—

ADC_0

I/O

—

J Tristate — — 109 J14

PI[10] PCR[138] AF0

AF1

AF2

AF3

—

GPIO[138]

—

ADC0_S[18]

SIUL

—

ADC_0

I/O

—

J Tristate — — 110 J15

PI[11] PCR[139] AF0

AF1

AF2

AF3

—

GPIO[139]

—

ADC0_S[19]

SIN_3

SIUL

—

ADC_0

DSPI_3

I/O

—

J Tristate — — 111 J16

PI[12] PCR[140] AF0

AF1

AF2

AF3

—

GPIO[140]

CS0_3

—

ADC0_S[20]

SIUL

DSPI_3

—

ADC_0

I/O

—

J Tristate — — 112 G14

PI[13] PCR[141] AF0

AF1

AF2

AF3

—

GPIO[141]

CS1_3

—

ADC0_S[21]

SIUL

DSPI_3

—

ADC_0

I/O

—

J Tristate — — 113 G15

PI[14] PCR[142] AF0

AF1

AF2

AF3

—

GPIO[142]

—

ADC0_S[22]

SIN_4

SIUL

—

ADC_0

DSPI_4

I/O

—

J Tristate — — 76 R8

PI[15] PCR[143] AF0

AF1

AF2

AF3

—

GPIO[143]

CS0_4

—

ADC0_S[23]

SIUL

DSPI_4

—

ADC_0

I/O

—

J Tristate — — 75 T8

Port J

PJ[0] PCR[144] AF0

AF1

AF2

AF3

—

GPIO[144]

CS1_4

—

ADC0_S[24]

SIUL

DSPI_4

—

ADC_0

I/O

—

J Tristate — — 74 N5

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

MPC5607B Microcontroller Data Sheet, Rev. 5

Package pinouts and signal descri pti on s

Freescale Semiconductor30

PJ[1] PCR[145] AF0

AF1

AF2

AF3

—

GPIO[145]

—

ADC0_S[25]

SIN_5

SIUL

—

——

ADC_0

DSPI_5

I/O

—

J Tristate — — 73 P5

PJ[2] PCR[146] AF0

AF1

AF2

AF3

—

GPIO[146]

CS0_5

—

ADC0_S[26]

SIUL

DSPI_5

—

ADC_0

I/O

—

J Tristate — — 72 P4

PJ[3] PCR[147] AF0

AF1

AF2

AF3

—

GPIO[147]

CS1_5

—

ADC0_S[27]

SIUL

DSPI_5

—

ADC_0

I/O

—

J Tristate — — 71 P2

PJ[4] PCR[148] AF0

AF1

AF2

AF3

GPIO[148]

SCK_5

E1UC[18]

—

SIUL

DSPI_5

eMIOS_1

—

I/O

—

MTristate — — 5 A4

1Alter nate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.

PCR.PA = 00  AF0; PCR.PA = 01  AF1; PCR.PA = 10  AF2; PCR.PA = 11 AF3. This is intended to select the

output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values

selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only functi on is reported as “—”.

2The RESET configuration applies during and after reset.

3208 MAPBGA available only as development package for Nexus2+

4All WKUP pins also support external interrupt capability. See the WKPU chapter of th e MPC5607B Microcontroller

Reference Manual for further details.

5NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.

6“Not applicable” because these functions are available only while the device is booting. See the BAM chapter of the

MPC5607B Microcontroller Reference Manual for details.

7Value of PCR.IBE bit must be 0

8Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.

PC[0:1] are av a i la ble as JTA G pi n s ( TD I an d TDO resp e cti vely).

PH[9:10] are available as JTAG pins (TCK and TMS respectively).

It is up to the user to configure these pins as GPIO when needed.

9PC[1] is a fast/medium pad but is in medium configuration by def ault. This pad is in Alternate Function 2 mode after reset

which has TDO functionality. The reset v alue of PCR.OBE is ‘1’, but this setting has no impact as long as this pad stays

in AF2 mode. After configuring this pad as GPIO (PCR.PA = 0), output buff er is enabled as reset value of PCR.OBE = 1.

10 Not available in 100 LQFP package

Table 3. Functional port pin descriptions (continued)

Port

pin PCR

function1Function

Peripheral

I/O

direction

Pad type

RESET

config.2

Pin No.

LQFP

100

LQFP

144

LQFP

176

LQFP

208

MAP

BGA3

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 31

4 Electrical characteristics

This section contains electrical characteristics of the device as well as temperature and power considerations.

This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take

precautions to avoid application of any vo ltage higher than the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by

the internal pull-up and pull-d own, whi ch is prov ided by the product for most general purpose pins.

The parameters listed in the following tables represent the characteristics of the device and its demands on the system.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller

Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol

“SR” for System Requirement is included in the Symbol column.

4.1 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better

understanding, the classifications listed in Table 4 are used and the parameters are tagge d accordingly in the tables where

appropriate.

NOTE

The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

4.2 NVUSRO register

Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are

controlled via bit values in the Non-Volatile User Opt ion s Register (NVUSRO) register.

For a detailed descri pt ion of the NVUSRO register, please refer to the MPC560 7B Microcontroller Reference Manual.

4.2.1 NVUSR O[PAD3V5V] field description

Table 5 shows how NVUSRO[PAD3V5V] controls the device configuration.

Table 4. Parameter classifications

Classification tag Tag description

P Those parameters are guaranteed during prod uction testing on each individual device.

C Those parameters are achieved by the design characterization by measuring a statistically

relevant sample size across process variations.

T Those parameters are achiev ed b y design characterization on a small sample size from typical

de vices under typical conditions unless otherwise noted. All values shown in the typical column

are within this category.

D Those parameters are derived mainly from simulations.

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor32

The DC electrical characteristics are dependent on the PAD3V5V bit value.

4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description

Table 6 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.

The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.

4.3 Absolute maximum ratings

Table 5. PAD3V5V field description1

1See the device reference manual fo r more information on the NVUSRO register.

Value2

2'1' is delivery value. It is part of shadow Flash, thus programmable by customer.

Description

0 High voltage supply is 5.0 V

1 High voltage supply is 3.3 V

Table 6. OSCILLATOR_MARGIN field description1

1See the device reference manual fo r more information on the NVUSRO register.

Value2

2'1' is delivery value. It is part of shadow Flash, thus programmable by customer.

Description

0 Low consumption configuration (4 MHz/8 MHz)

1 High margin configuration (4 MHz/16 MHz)

Table 7. Absolute maximum ratings

Symbol Parameter Conditions Value Unit

Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

VDD SR Voltage on VDD_HV pins with respect to

ground (VSS)—–0.36.0V

VSS_LV SR V oltage on VSS_LV (low v oltage digital supply)

pins with respect to ground (VSS)—V

SS –0.1 V

SS +0.1 V

VDD_BV SR V oltage on VDD_BV pin (regulator supply) with

respect to ground (VSS)—–0.36.0V

Relative to VDD –0.3 VDD +0.3

VSS_ADC SR Vo ltage on VSS_HV_ADC0, VSS_HV_ADC1

(ADC reference) pin with respect to ground

(VSS)

—V

SS –0.1 V

SS +0.1 V

VDD_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1

(ADC reference) with respect to ground (VSS)—–0.36.0V

Relative to VDD VDD 0.3 VDD +0.3

VIN SR Voltage on any GPIO pin with respect to

ground (VSS)—–0.36.0V

Relative to VDD —V

DD +0.3

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 33

NOTE

Stresses exceeding the recommended absolute maximum ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification are not implied. Exposure to absolute maximum rating conditions fo r

extended periods may affect device reliability. During overload conditions (VIN >V

DD or

VIN <V

SS), the voltage on pins with respect to ground (VSS) must not exceed the

recommended values.

4.4 Recommended operating conditions

IINJPAD SR Injected input current on any pin during

overload condition — –10 10 mA

IINJSUM SR Absolute sum of all injected input currents

during overload condition — –50 50

IAVGSEG SR Sum of all the static I/O current within a supply

segment VDD = 5.0 V ± 10%,

PAD3V5V = 0 —70mA

VDD = 3.3 V ± 10%,

PAD3V5V = 1 —64

TSTORAGE SR Storage temperature — –55 150 °C

Table 8. Recommended operating conditions (3.3 V)

Symbol Parameter Conditions Value Unit

Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

VDD1SR Voltage on VDD_HV pins with respect

to ground (VSS)—3.03.6V

VSS_LV2SR V oltage on VSS_LV (low voltage digital

supply) pins with respect to ground

(VSS)

—V

SS 0.1 VSS +0.1 V

VDD_BV3SR Voltage on VDD_BV pin (regulator

supply) with respect to ground (VSS)—3.03.6V

Relative to VDD VDD 0.1 VDD +0.1

VSS_ADC SR Voltage on VSS_HV_ADC0,

VSS_HV_ADC1 (ADC reference) pin

with respect to ground (VSS)

—V

SS 0.1 VSS +0.1 V

VDD_ADC4SR Voltage on VSS_HV_ADC0,

VSS_HV_ADC1 (ADC ref erence) with

respect to ground (VSS)

—3.0

53.6 V

Relative to VDD VDD 0.1 VDD +0.1

VIN SR Voltage on any GPIO pin with respect

to ground (VSS)—V

SS 0.1 — V

Relative to VDD —V

DD +0.1

Table 7. Absolute maximum ratings (continued)

Symbol Parameter Conditions Value Unit

Min Max

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor34

IINJPAD SR Injected input current on any pin during

overload condition —55mA

IINJSUM SR Absolute sum of all injected input

currents during overload condition —50 50

TVDD SR VDD slope to ensure correct power up6— — 0.25 V/µs

TA C-Grade

Part

SR Ambient temperature under bias fCPU < 64 MHz740 85 °C

TJ C-Grade

Part

SR Junction temperature under bias — 40 110

TA V-Grade

Part

SR Ambient temperature under bias fCPU < 64 MHz740 105

TJ V-Grade

Part

SR Junction temperature under bias — 40 130

TA M-Grade

Part

SR Ambient temperature under bias fCPU < 64 MHz740 125

TJ M-Grade

Part

SR Junction temperature under bias — 40 150

1100 nF capacitance needs to be provided between each VDD/VSS pair.

2330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.

3470 nF capacitance need s to be provided between VDD_BV and the nearest VSS_LV (higher value ma y be needed

depending on external regulator characteristics). Supply ramp slope on VDD_BV should always be faster or equal

to slope of VDD_HV. Otherwise, device may enter regulator bypass mode if slope on VDD_BV is slower.

4100 nF capacitance need s to be provided between VDD_ADC/VSS_ADC pair.

5Full electrical specification cannot be guaranteed when v oltage drops below 3.0 V. In particular , ADC electrical

characteristics and I/Os DC electrical specification ma y not be guaranteed. When voltage drops below VLVDHVL,

device is reset.

6Guaranteed by device validation

7This frequency includes the 4% frequency modulation guardband.

Table 9. Recommended operating conditions (5.0 V)

Symbol Parameter Conditions Value Unit

Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

VDD1SR Voltage on VDD_HV pins with respect to ground

(VSS)—4.55.5V

Voltage drop23.0 5.5

VSS_LV3SR V oltage on VSS_L V (low voltage digital supply) pins

with respect to ground (VSS)—V

SS 0.1 VSS +0.1 V

Table 8. Recommended operating conditio ns (3.3 V) (continued)

Symbol Parameter Conditions Value Unit

Min Max

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 35

VDD_BV4SR Voltage on VDD_BV pin (regulator supply) with

respect to ground (VSS)—4.55.5V

Voltage drop23.0 5.5

Relative to VDD 3.0 VDD +0.1

VSS_ADC SR V oltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC

reference) pin with respect to ground (VSS)—V

SS 0.1 VSS +0.1 V

VDD_ADC5SR V oltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC

reference) with respect to ground (VSS)—4.55.5V

Voltage drop23.0 5.5

Relative to VDD VDD 0.1 VDD +0.1

VIN SR Vo ltage on any GPIO pin with respect to ground

(VSS)—V

SS 0.1 — V

Relative to VDD —V

DD +0.1

IINJPAD SR Injected input current on any pin dur ing overload

condition —55mA

IINJSUM SR Absolute sum of all injected input currents during

overload condition —50 50

TVDD SR VDD slope to ensure correct power up6— — 0.25 V/µs

TA C-Grade

Part

SR Ambient temperature under bias fCPU < 64 MHz740 85 °C

TJ C-Grade

Part

SR Junction temperature under bias — 40 110

TA V-Grade

Part

SR Ambient temperature under bias fCPU < 64 MHz740 105

TJ V-Grade

Part

SR Junction temperature under bias — 40 130

TA M-Grade

Part

SR Ambient temperature under bias fCPU < 64 MHz740 125

TJ M-Grade

Part

SR Junction temperature under bias — 40 150

1100 nF capacitance needs to be provided between each VDD/VSS pair.

2Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain

analog electrica l characteristics will not be guaranteed to stay within the stated limits.

3330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.

4470 nF capacitance need s to be provided between VDD_BV and the nearest VSS_LV (higher value ma y be needed

depending on external regulator characteristics). While the supply voltage ramps up, the slope on VDD_BV should

be less than 0.9V DD_HV in order to ensure the device does not ente r regulator bypass mode.

5100 nF capacitance need s to be provided between VDD_ADC/VSS_ADC pair.

6Guaranteed by device validation. Please refer to Section 4.5.1, “External ballast resistor recommendations for

minimum VDD slope to be guaranteed to ensure correct power up in case of exter nal resistor usage.

7This frequency includes the 4% frequency modulation guardband.

Table 9. Recommended operating conditio ns (5.0 V) (continued)

Symbol Parameter Conditions Value Unit

Min Max

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor36

NOTE

RAM data retention is guaranteed with VDD_LV not below 1.08 V.

4.5 Thermal characteristics

4.5.1 External ballast resistor recommendations

External ballast resistor on VDD_BV pin helps in reducing the overall power dissipation inside the device. This resist or is

required only when maximum power consumption exceeds the limit imposed by package thermal characteristics.

As stated in Table 10 LQFP thermal characteristics, considering a thermal resistance of 144 LQFP as 48.3 °C/W, at ambient

temperature TA = 125 °C, the junction temperature Tj will cross 150 °C if the total power dissipation is greater than

(150 – 125)/48.3 = 51 7 mW. Therefore, the total device current IDDMAX at 125 °C/5.5 V must not exceed 94.1 mA (i.e.,

PD/VDD). Assuming an average IDD(VDD_HV) of 15–20 mA consumption typically during device RUN mode, the LV domain

consumption IDD(VDD_BV) is thus limited to IDDMAX –I

DD(VDD_HV), i.e., 80 mA.

Therefore, respecting the maximum power allowed as explained in Section 4.5.2, “Package thermal characteristics, it is

recommended to use this resistor only in the 125 °C/5.5 V operating corner as per the following guidelines:

•If I

DD(VDD_BV) < 80 mA, then no resistor is required.

•If 80 mA < I

DD(VDD_BV) < 90 mA, then 4  resistor can be used.

•If I

DD(VDD_BV) > 90 mA, then 8  resistor can be used.

Using resistance in the range of 4–8 , the gain will be around 10–20% of total consumption on VDD_BV. For example, if 8 

resistor is used, then power consumption when IDD(VDD_BV) is 110 mA is equivalent to pow er consum ption when

IDD(VDD_BV) is 90 mA (approximately) when resistor not used.

In order to ensure correct power up, the minimum VDD_BV to be guaranteed is 30 ms/V. If the supply ramp is slower than this

value, then LVDHV3B m onitoring ballast supply VDD_BV pin gets trig gered leading to device reset. Until the supply reaches

certain threshold, this low voltage monitor generates destructive reset event in the system. This threshold depends on the

maximum IDD(VDD_BV) possible across the external resistor.

4.5.2 Package thermal characteristics

Table 10. LQFP thermal characteristics1

Symbol C Parameter Conditions2Pin count Value Unit

Min Typ Max

RJA CC D Thermal resistance,

junction-to-ambient natural

convection3

Single-layer board — 1s 100 — — 64 °C/W

144 — — 64

176 — — 64

Four-layer board — 2s2p 100 — — 49.7

144 — — 48.3

176 — — 47.3

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 37

4.5.3 Power considerations

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:

TJ = TA + (PD x RJA)Eqn. 1

Where:

TA is the ambient temperature in °C.

RJA is the package junction-to-ambient thermal resistance, in °C/W.

PD is the sum of PINT and PI/O (PD = PINT + PI/O).

PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power.

PI/O represents the power dissipation on input and output pins; user determ ined.

Most of the time for the applications, PI/O< PINT and may be neglected. On the other hand, PI/O may be significant, if the device

is configured to continuously drive external modules and/or memories.

An approximate relationship between PD and TJ (if PI/O is neglected) is given by:

RJB CC Thermal resistance,

junction-to-board4Single-la yer board — 1s 100 — — 36 °C/W

144 — — 38

176 — — 38

Four-layer board — 2s2p 100 — — 33.6

144 — — 33.4

176 — — 33.4

RJC CC Thermal resistance,

junction-to-case5Single-layer board — 1s 100 — — 23 °C/W

144 — — 23

176 — — 23

Four-layer board — 2s2p 100 — — 19.8

144 — — 19.2

176 — — 18.8

1Thermal characteristics are targets based on simulation.

2VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C.

3Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board

meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA

and RthJMA.

4Junction-to-board thermal resistance de termined per JEDEC JESD51-8. Thermal test board meets JEDEC

specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB.

5Junction-to-case at the top of the package determin ed using MIL-STD 883 Method 1012.1. The cold plate

temperature is used for the case temperature. Reported value includes the thermal resistance of the interface

layer. When Greek letters are not available, the symbols are typed as RthJC.

Table 10. LQFP thermal characteristics1 (continued)

Symbol C Parameter Conditions2Pin count Value Unit

Min Typ Max

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor38

PD = K / (TJ + 273 °C) Eqn. 2

Therefore, solving equations 1 and 2:

K = PD x (TA + 273 °C) + RJA x PD2Eqn. 3

Where:

K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium)

for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2

iteratively for any value of TA.

4.6 I/O pad electrical characteristics

4.6.1 I/O pad types

The device provides four main I/O pad types depending on the associated alternate functions:

• Slow pads - are the most common pads, providing a good compromise between transition time and low

electromagnetic emission.

• Medium pads - provide transition fast enough for the serial communication channels with controlled current to reduce

electromagnetic emission.

• Fast pads - provide maximum speed. These are used for improved Nexus debugging capability.

• Input only pads - are associated with ADC channels and 32 kHz low power external crystal oscillator providing low

input leakage.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.

4.6.2 I/O input DC characteristics

Table 11 provides input DC electrical characteristics as described in Figure 6.

Figure 6. I/O input DC electrical cha racteristics definition

VIL

VIN

VIH

PDIx = ‘1

VDD

VHYS

(GPDI register of SIUL)

PDIx = ‘0’

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 39

4.6.3 I/O output DC characteristics

The following tables provide DC characteristics for bidirectional pads:

•Table 12 provides weak pull figures. Both pull- up and pull-down resistances are supported.

•Table 13 provides output driver characteristics for I/O pads when in SLOW configuration.

•Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration.

•Table 15 provides output driver characteristics for I/O pads when in FAST configuration.

Table 11. I/O input DC electrical characteristics

Symbol C Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value Unit

Min Typ Max

VIH SR P Input high level CMOS (Schmitt

Trigger) — 0.65VDD —V

DD +0.4 V

VIL SR P Input low level CMOS (Schmitt

Trigger) —0.4 — 0.35VDD

VHYS CC C Input hysteresis CMOS (Schmitt

Trigger) —0.1V

DD ——

ILKG CC P Digital input leakage No injection

on adjacent

TA=40 °C — 2 — nA

A= 25 °C — 2 —

A= 105 °C — 12 500

A= 125 °C — 70 1000

WFI2

2In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating te mperature and

voltage.

SR P Wakeup input filtered pulse — — — 40 ns

WNFI2SR P Wakeup input not filtered pulse — 1000 — — ns

Table 12. I/O pull-up/pull-down DC electrical characteristics

Symbol C Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

Value Unit

Min Typ Max

|IWPU| CC P Weak pull-up current

absolute value VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V = 0 10 — 150 µA

C PAD3V5V = 12

2The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO ) are configured in input or in high impedance state.

10 — 250

IN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150

|IWPD| CC P Weak pull-down current

absolute value VIN = VIH, VDD = 5.0 V ± 10% PAD3V5V = 0 10 — 150 µA

C PAD3V5V = 1 10 — 250

IN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor40

Table 13. SLOW configuration output buffer ele ctrical characteristics

Symbol C Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value Unit

Min Typ Max

VOH CC P Output high lev el

SLO W configuration Push Pull IOH = 2mA,

VDD = 5.0 V ± 10%,

PAD3V5V = 0

(recommended)

0.8VDD ——V

OH = 2mA,

VDD = 5.0 V ± 10%,

PAD3V5V = 12

2The configuration PAD3V5 = 1 when VDD = 5 V is only a transi ent configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

0.8VDD ——

OH = 1mA,

VDD = 3.3 V ± 10%,

PAD3V5V = 1

(recommended)

VDD 0.8 — —

VOL CC P Output low level

SLO W configuration Push Pull IOL = 2 mA,

VDD = 5.0 V ± 10%,

PAD3V5V = 0

(recommended)

— — 0.1VDD V

OL = 2 mA,

VDD = 5.0 V ± 10%,

PAD3V5V = 12

— — 0.1VDD

OL = 1 mA,

VDD = 3.3 V ± 10%,

PAD3V5V = 1

(recommended)

——0.5

Table 14. MEDIUM configuration output buffer electrical characteristics

Symbol C Parameter Conditions1Value Unit

Min Typ Max

VOH CC C Output high level

MEDIUM configuration Push Pull IOH = 3.8 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD —— V

OH = 2mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

0.8VDD ——

OH = 1mA,

VDD = 5.0 V ± 10%, PAD3V5V = 120.8VDD ——

OH = 1mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

VDD 0.8 — —

OH = 100 µA,

VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD ——

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 41

VOL CC C Output low level

MEDIUM configuration Push Pull IOL = 3.8 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.2VDD V

OL = 2 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

— — 0.1VDD

OL = 1 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 12— — 0.1VDD

OL = 1 mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

——0.5

OH = 100 µA,

VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2The configuration PAD3V5 = 1 when VDD = 5 V is only a transi ent configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 15. FAST configuration output buffer electrical characteristics

Symbol C Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value Unit

Min Typ Max

VOH CC P Output high level

FAST configuration Push Pull IOH = 14 mA,

VDD = 5.0 V ± 10%,

PAD3V5V = 0

(recommended)

0.8VDD ——V

OH = 7mA,

VDD = 5.0 V ± 10%,

PAD3V5V = 12

0.8VDD ——

OH = 11 mA,

VDD = 3.3 V ± 10%,

PAD3V5V = 1

(recommended)

VDD 0.8 — —

VOL CC P Output low level

FAST configuration Push Pull IOL = 14 mA,

VDD = 5.0 V ± 10%,

PAD3V5V = 0

(recommended)

— — 0.1VDD V

OL = 7 mA,

VDD = 5.0 V ± 10%,

PAD3V5V = 12

— — 0.1VDD

OL = 11 mA,

VDD = 3.3 V ± 10%,

PAD3V5V = 1

(recommended)

——0.5

Table 14. MEDIUM configuration output buffer electrical chara cteristics (continued)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor42

4.6.4 Output pin transition times

4.6.5 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as

described in Table 17.

Table 18 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG

maximum value.

2The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 16. Output pin transition times

Symbol C Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value Unit

Min Typ Max

Ttr CC D Output transition time output pin2

SLO W configuration

2CL includes device and package capacitances (CPKG < 5 pF).

CL = 25 pF VDD = 5.0 V ± 10%,

PAD3V5V = 0 — — 50 ns

L = 50 pF — — 100

L = 100 pF — — 125

L = 25 pF VDD = 3.3 V ± 10%,

PAD3V5V = 1 ——50

L = 50 pF — — 100

L = 100 pF — — 125

Ttr CC D Output transition time output pin2

MEDIUM configuration CL = 25 pF VDD = 5.0 V ± 10%,

PAD3V5V = 0

SIUL.PCRx.SRC = 1

— — 10 ns

L = 50 pF — — 20

L = 100 pF — — 40

L = 25 pF VDD = 3.3 V ± 10%,

PAD3V5V = 1

SIUL.PCRx.SRC = 1

——12

L = 50 pF — — 25

L = 100 pF — — 40

Ttr CC D Output transition time output pin2

FAST configuration CL = 25 pF VDD = 5.0 V ± 10%,

PAD3V5V = 0 —— 4 ns

CL = 50 pF — — 6

CL = 100 pF — — 12

CL = 25 pF VDD = 3.3 V ± 10%,

PAD3V5V = 1 —— 4

CL = 50 pF — — 7

CL = 100 pF — — 12

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 43

Table 17. I/O supply segments

Package Supply segment

12345678

208

MAPBGA1

1208 MAPBGA available only as development package for Nexus2+

Equivalent to 176 LQFP segment pad distribution MCKO MDOn

/MSEO

176 LQFP pin7 –

pin27 pin28 –

pin57 pin59 –

pin85 pin86 –

pin123 pin124 –

pin150 pin151 –

pin6 — —

144 LQFP pin20 –

pin49 pin51 –

pin99 pin100 –

pin122 pin 123 –

pin19 — — — —

100 LQFP pin16 –

pin35 pin37 –

pin69 pin70 –

pin83 pin84 –

pin15 — — — —

Table 18. I/O consumption

Symbol C Parameter Conditions1Value Unit

Min Typ Max

ISWTSLW,2 CC D Dynamic I/O current fo r

SLOW configuration CL = 25 pF VDD = 5.0 V ± 10%,

PAD3V5V = 0 ——20mA

VDD = 3.3 V ± 10%,

PAD3V5V = 1 ——16

ISWTMED2CC D Dynamic I/O current for

MEDIUM configuration CL = 25 pF VDD = 5.0 V ± 10%,

PAD3V5V = 0 ——29mA

VDD = 3.3 V ± 10%,

PAD3V5V = 1 ——17

ISWTFST2CC D Dynamic I/O current for

FAST configuratio n CL = 25 pF VDD = 5.0 V ± 10%,

PAD3V5V = 0 ——110mA

VDD = 3.3 V ± 10%,

PAD3V5V = 1 ——50

IRMSSLW CC D Root medium square I/O

current for SLOW

configuration

CL = 25 pF, 2 MHz VDD = 5.0 V ± 10%,

PAD3V5V = 0 ——2.3mA

CL = 25 pF, 4 MHz — — 3.2

CL = 100 pF, 2 MHz — — 6.6

CL = 25 pF, 2 MHz VDD = 3.3 V ± 10%,

PAD3V5V = 1 ——1.6

CL = 25 pF, 4 MHz — — 2.3

CL = 100 pF, 2 MHz — — 4.7

IRMSMED CC D Root medium square I/O

current for MEDIUM

configuration

CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%,

PAD3V5V = 0 ——6.6mA

CL = 25 pF, 40 MHz — — 13.4

CL = 100 pF, 13 MHz — — 18.3

CL = 25 pF, 13 MHz VDD = 3.3 V ± 10%,

PAD3V5V = 1 —— 5

CL = 25 pF, 40 MHz — — 8.5

CL = 100 pF, 13 MHz — — 11

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor44

Table 19 provides the weight of concurrent switching I/Os.

In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain

below the 100%.

IRMSFST CC D Root medium square I/O

current for FAST

configuration

CL = 25 pF, 40 MHz VDD = 5.0 V ± 10%,

PAD3V5V = 0 ——22mA

CL = 25 pF, 64 MHz — — 33

CL = 100 pF, 40 MHz — — 56

CL = 25 pF, 40 MHz VDD = 3.3 V ± 10%,

PAD3V5V = 1 ——14

CL = 25 pF, 64 MHz — — 20

CL = 100 pF, 40 MHz — — 35

IAVGSEG SR D Sum of all the static I/O

current within a supply

segment

VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70 mA

VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified

2Stated maximum values represent peak co nsumption that lasts only a few ns during I/O transition.

Table 19. I/O weight1

PAD

176 LQFP 144/100 LQFP

Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1 Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1

PB[3] 5% — 6% — 13% — 15% —

PC[9] 4% — 5% — 13% — 15% —

PC[14] 4% — 4% — 13% — 15% —

PC[15] 3% 4% 4% 4% 12% 18% 15% 16%

PJ[4] 3% 4% 3% 3% 12% 18% 15% 16%

PH[15] 2% 3% 3% 3% 11% 16% 13% 14%

PH[13] 3% 4% 3% 4% 11% 15% 13% 14%

PH[14] 3% 4% 4% 4% 11% 15% 13% 13%

PI[6] 4% — 4% — 10% — 12% —

PI[7] 4% — 4% — 10% — 12% —

PG[5] 4% — 5% — 10% — 12% —

PG[4] 4% 6% 5% 5% 9% 13% 11% 12%

PG[3]4%— 5% — 9%—11% —

PG[2] 4% 6% 5% 5% 9% 12% 10% 11%

PA[2]4%— 5% — 8%—10% —

PE[0] 4% — 5% — 8% — 9% —

Table 18. I/O consumption (continued)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 45

PA[1]4%— 5% — 8%— 9% —

PE[1] 4% 6% 5% 6% 7% 10% 9% 9%

PE[8] 4% 6% 5% 6% 7% 10% 8% 9%

PE[9] 4% — 5% — 6% — 8% —

PE[10] 4% — 5% — 6% — 7% —

PA[0]4%6%5% 5%6%8%7% 7%

PE[11] 4% — 5% — 5% — 6% —

PG[9] 9% — 10% — 9% — 10% —

PG[8] 9% — 11% — 9% — 11% —

PC[11] 9% — 11% — 9% — 11% —

PC[10] 9% 13% 11% 12% 9% 13% 11% 12%

PG[7] 9% — 11% — 9% — 11% —

PG[6] 10% 14% 11% 12% 10% 14% 11% 12%

PB[0] 10% 14% 12% 12% 10% 14% 12% 12%

PB[1] 10% — 12% — 10% — 12% —

PF[9] 10% — 12% — 10% — 12% —

PF[8] 10% 14% 12% 13% 10% 14% 12% 13%

PF[12] 10% 15% 12% 13% 10% 15% 12% 13%

PC[6] 10% — 12% — 10% — 12% —

PC[7] 10% — 12% — 10% — 12% —

PF[10] 10% 14% 11% 12% 10% 14% 11% 12%

PF[11] 9% — 11% — 9% — 11% —

PA[15] 8% 12% 10% 10% 8% 12% 10% 10%

PF[13] 8% — 10% — 8% — 10% —

PA[14] 8% 11% 9% 10% 8% 11% 9% 10%

PA[4]7%— 9% — 7%— 9% —

PA[13] 7% 10% 8% 9% 7% 10% 8% 9%

PA[12] 7% — 8% — 7% — 8% —

PB[9] 1% — 1% — 1% — 1% —

PB[8] 1% — 1% — 1% — 1% —

PB[10] 5% — 6% — 6% — 7% —

PF[0]5%— 6% — 6%— 8% —

PF[1]5%— 6% — 7%— 8% —

Table 19. I/O weight1 (conti nued)

PAD

176 LQFP 144/100 LQFP

Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1 Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor46

PF[2]6%— 7% — 7%— 9% —

PF[3]6%— 7% — 8%— 9% —

PF[4]6%— 7% — 8%—10% —

PF[5]6%— 7% — 9%—10% —

PF[6]6%— 7% — 9%—11% —

PF[7]6%— 7% — 9%—11% —

PJ[3] 6% — 7% — 10% — 12% —

PJ[2] 6% — 7% — 10% — 12% —

PJ[1] 6% — 7% — 11% — 13% —

PJ[0] 6% — 7% — 11% — 13% —

PI[15] 6% — 7% — 12% — 14% —

PI[14] 6% — 7% — 12% — 14% —

PD[0]1%— 1% — 1%— 1% —

PD[1]1%— 1% — 1%— 1% —

PD[2]1%— 1% — 1%— 1% —

PD[3]1%— 1% — 1%— 1% —

PD[4]1%— 1% — 1%— 1% —

PD[5]1%— 1% — 1%— 1% —

PD[6]1%— 1% — 1%— 2% —

PD[7]1%— 1% — 1%— 2% —

PD[8]1%— 1% — 1%— 2% —

PB[4] 1% — 1% — 1% — 2% —

PB[5] 1% — 1% — 1% — 2% —

PB[6] 1% — 1% — 1% — 2% —

PB[7] 1% — 1% — 1% — 2% —

PD[9]1%— 1% — 1%— 2% —

PD[10] 1% — 1% — 1% — 2% —

PD[11] 1% — 1% — 1% — 2% —

PB[11] 1% — 1% — 1% — 2% —

PD[12] 11% — 13% — 15% — 18% —

PB[12] 11% — 13% — 15% — 17% —

PD[13] 11% — 13% — 14% — 17% —

PB[13] 11% — 13% — 14% — 17% —

Table 19. I/O weight1 (conti nued)

PAD

176 LQFP 144/100 LQFP

Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1 Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 47

PD[14] 11% — 13% — 14% — 17% —

PB[14] 11% — 13% — 14% — 16% —

PD[15] 11% — 13% — 13% — 16% —

PB[15] 11% — 13% — 13% — 15% —

PI[8] 10% — 12% — 12% — 15% —

PI[9] 10% — 12% — 12% — 15% —

PI[10] 10% — 12% — 12% — 14% —

PI[11] 10% — 12% — 12% — 14% —

PI[12] 10% — 12% — 11% — 13% —

PI[13] 10% — 11% — 11% — 13% —

PA[3] 9% — 11% — 11% — 13% —

PG[13] 9% 13% 11% 11% 10% 14% 12% 13%

PG[12] 9% 13% 10% 11% 10% 14% 12% 12%

PH[0]6%8%7% 7%6%9%7% 8%

PH[1]6%8%7% 7%6%8%7% 7%

PH[2]5%7%6% 6%5%7%6% 7%

PH[3]5%7%5% 6%5%7%6% 6%

PG[1]4%— 5% — 4%— 5% —

PG[0]4%5%4% 5%4%5%4% 5%

PF[15] 4% — 4% — 4% — 4% —

PF[14] 4% 6% 5% 5% 4% 6% 5% 5%

PE[13] 4% — 5% — 4% — 5% —

PA[7]5%— 6% — 5%— 6% —

PA[8]5%— 6% — 5%— 6% —

PA[9]6%— 7% — 6%— 7% —

PA[10] 6% — 8% — 6% — 8% —

PA[11] 8% — 9% — 8% — 9% —

PE[12] 8% — 9% — 8% — 9% —

PG[14] 8% — 9% — 8% — 9% —

PG[15] 8% 11% 9% 10% 8% 11% 9% 10%

PE[14] 8% — 9% — 8% — 9% —

PE[15] 8% 11% 9% 10% 8% 11% 9% 10%

PG[10] 8% — 9% — 8% — 9% —

Table 19. I/O weight1 (conti nued)

PAD

176 LQFP 144/100 LQFP

Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1 Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor48

PG[11] 7% 11% 9% 9% 7% 11% 9% 9%

PH[11] 7% 10% 9% 9% 7% 10% 9% 9%

PH[12] 7% 10% 8% 9% 7% 10% 8% 9%

PI[5]7%— 8% — 7%— 8% —

PI[4]7%— 8% — 7%— 8% —

PC[3]6%— 8% — 6%— 8% —

PC[2]6%8%7% 7%6%8%7% 7%

PA[5]6%8%7% 7%6%8%7% 7%

PA[6]5%— 6% — 5%— 6% —

PH[10] 5% 7% 6% 6% 5% 7% 6% 6%

PC[1] 5% 19% 5% 13% 5% 19% 5% 13%

PC[0] 6% 9% 7% 8% 7% 10% 8% 8%

PH[9]7%— 8% — 7%— 9% —

PE[2] 7% 10% 8% 9% 8% 11% 9% 10%

PE[3] 7% 10% 9% 9% 8% 12% 10% 10%

PC[5] 7% 11% 9% 9% 8% 12% 10% 11%

PC[4] 8% 11% 9% 10% 9% 13% 10% 11%

PE[4] 8% 11% 9% 10% 9% 13% 11% 12%

PE[5] 8% 11% 10% 10% 9% 14% 11% 12%

PH[4] 8% 12% 10% 10% 10% 14% 12% 12%

PH[5] 8% — 10% — 10% — 12% —

PH[6] 8% 12% 10% 11% 10% 15% 12% 13%

PH[7] 9% 12% 10% 11% 11% 15% 13% 13%

PH[8] 9% 12% 10% 11% 11% 16% 13% 14%

PE[6] 9% 12% 10% 11% 11% 16% 13% 14%

PE[7] 9% 12% 10% 11% 11% 16% 14% 14%

PI[3] 9% — 10% — 12% — 14% —

PI[2] 9% — 10% — 12% — 14% —

PI[1] 9% — 10% — 12% — 15% —

PI[0] 9% — 10% — 12% — 15% —

Table 19. I/O weight1 (conti nued)

PAD

176 LQFP 144/100 LQFP

Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1 Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 49

4.7 RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin.

Figure 7. Start-up reset requirements

PC[12] 8% 12% 10% 11% 12% 18% 15% 16%

PC[13] 8% — 10% — 13% — 15% —

PC[8] 8% — 10% — 13% — 15% —

PB[2] 8% 11% 9% 10% 13% 18% 15% 16%

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Table 19. I/O weight1 (conti nued)

PAD

176 LQFP 144/100 LQFP

Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1 Weight 5V

SRE = 0 Weight 5V

SRE = 1 Weight 3.3V

SRE = 0 Weight 3.3V

SRE = 1

VIL

VDD

device reset forced by RESET

VDDMIN

RESET

VIH

device start-up phase

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor50

Figure 8. Noise filtering on reset signal

Table 20. Reset electrical characteristics

Symbol C Parameter Conditions1Value Unit

Min Typ Max

VIH SR P Input High Level CMOS

(Schmitt Trigger) —0.65V

DD —V

DD +0.4 V

VIL SR P Input low Level CMOS

(Schmitt Trigger) —0.4 — 0.35VDD V

VHYS CC C Input hysteresis CMOS

(Schmitt Trigger) —0.1V

DD —— V

VOL CC P Output low level Push Pull, IOL = 2 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

— — 0.1VDD V

Push Pull, IOL = 1 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 12— — 0.1VDD

Push Pull, IOL = 1 mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

——0.5

VRESET

VIL

VIH

VDD

filtered by

hysteresis filtered by

lowpass filter

WFRST WNFRST

hw_rst

‘1’

‘0’

filtered by

lowpass filter

WFRST

unknown reset

state device under hardware reset

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 51

4.8 Power management electrical characteristics

4.8.1 Voltage regulator electrical characteristics

The device implements an internal volt age regulator to generate the low volt age core supply VDD_LV from the high voltage

ballast supply VDD_BV. The regulator itself is supplied by the comm on I/O suppl y V DD. The followi ng supp lies are involved:

• HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD

power pin.

• BV : High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV

power pin. Voltage values should be aligned with VDD.

• LV: Low voltage internal power suppl y for core, FMPLL and Flash digital logic. This is generated by the intern al

voltage regulator but provided outside to connect stability capacitor . It is further split into four main domains to ensure

noise isolation between critical LV m odul es within the device:

— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.

— LV_CFLA: Low voltage supply for code Flash module. It is supplied with dedicated ballast and shorted to

LV_COR through dou ble bonding.

Ttr CC D Output transition time output

pin3 MEDIUM configuration CL = 25 pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 10 ns

CL = 50 pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0 —— 20

CL = 100 pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0 —— 40

CL = 25 pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 12

CL = 50 pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 25

CL = 100 pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 40

WFRST SR P RESET input filtered pulse — — — 40 ns

WNFRST SR P RESET input not filtered pulse — 1000 — — ns

|IWPU| CC P Weak pull-up current absolute

value VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150 µA

VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150

VDD = 5.0 V ± 10%, PAD3V5V = 1410 — 250

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of

the device reference manual).

3CL includes device and package capacitance (CPKG <5pF).

4The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up . All pads but RESET

and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 20. Reset electrical characteristics (continued)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor52

— LV_DFLA: Low voltage supply for data Flash module. It is suppl ied wit h dedicat ed ballast and shorted to

LV_COR through dou ble bonding.

— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.

Figure 9. Voltage regulator capacitance connect ion

The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable

low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.

Care should also be taken to limit the serial inductance of the board to less than 5 nH.

Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see

Section 4.4, “Recommended operating conditions).

Table 21. Voltage regulator electri cal characteristics

Symbol C Parameter Conditions1Value Unit

Min Typ Max

CREGn SR — Internal voltage regulator external

capacitance — 200 — 500 nF

RREG SR — Stability capacitor equivalent serial

resistance ———0.2

CDEC1 SR — Decoupling capacitance2 ballast VDD_BV/VSS_LV pair:

VDD_BV = 4.5 V to

5.5 V

10034704—nF

VDD_BV/VSS_LV pair:

VDD_BV = 3V to 3.6V 400 —

CREG1 (LV_COR/LV_DFLA)

DEVICE

VSS_LV

VDD_BV

VDD_LV

CDEC1 (Ballast decoupling)

VSS_LV VDD_LV VDD

VSS_LV VDD_LV

CREG2 (LV_COR/LV_CFLA)

CREG3 (LV_COR/LV_PLL) CDEC2 (supply/IO decoupling)

DEVICE

VDD_BV

VDD_LVn

VREF

VDD

Voltage Regulator

VSS

VSS_LVn

GND

GND GND

GND

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 53

4.8.2 Voltage monitor electrical characteristics

The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four low voltage detectors

to monitor the VDD and the VDD_LV voltage while device is supplied:

CDEC2 SR — Decoupling capacitance regulator

supply VDD/VSS pair 10 100 — nF

VMREG CC PMain regulator output voltage Before exting from

reset —1.32 — V

After trimming 1.15 1.28 1.32

IMREG SR —Main regulator current provided to

VDD_LV domain ———150 mA

IMREGINT CC DMain regulator module current

consumption IMREG = 200 mA — — 2mA

IMREG = 0 mA — — 1

VLPREG CC PLo w power regu l a to r out p ut voltage After trimming 1.15 1.23 1.32 V

ILPREG SR —Low power regulator current provided

to VDD_LV domain ———15 mA

ILPREGINT CC DLow power regulator module current

consumption ILPREG = 15 mA;

TA = 55 °C ——

600 µA

— ILPREG = 0 mA;

TA = 55 °C —5—

VULPREG CC PUltra low power regulator output

voltage After trimming 1.15 1.23 1.32 V

IULPREG SR —Ultra low power regulator current

provided to VDD_LV domain ———5mA

IULPREGINT CC DUltra low power regulator module

current consumption IULPREG = 5 mA;

TA = 55 °C ——100 µA

IULPREG = 0 mA;

TA = 55 °C —2—

IDD_BV CC DIn-rush curren t on VDD_BV during

power-up5———4006mA

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.

A typical value is in the range of 470 nF.

3This value is acceptable to guarantee operation from 4.5 V to 5.5 V

4External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV

in operating range.

5In-rush current is seen only for short time during power-up and on standb y exit (max 20µs, depending on external

capacitances to be load).

6The duration of the in-rush current depen ds on the capacitance placed on LV pins. BV decaps must be sized

accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.

Table 21. Voltage regulator electrical characteristics (continued)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor54

• POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state

• LVDHV3 monitors VDD to ensure device reset below minimum function al supply

• LVDHV3B monitors VDD_BV to ensure device reset below minim um functi onal supply

• LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range

• LVDLVCOR monitors power domain No. 1

• LVDLVBKP monitors power domain No. 0

NOTE

When enabled, power domain No. 2 is monitored through LVDLVBKP.

Figure 10. Low voltage monitor vs reset

Table 22. Low voltage monitor electrical characteristics

Symbol C Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value Unit

Min Typ Max

VPORUP SR P Supply for functional POR module TA = 25 °C,

after trimming 1.0 — 5.5 V

VPORH CC P Power-on reset threshold 1.5 — 2.6

VLVDHV3H CC T LVDHV3 low voltage detector high threshold — — 2.95

VLVDHV3L CC P LVDHV3 low voltage detector low threshold 2.7 — 2.9

VLVDHV3BH CC P LVDHV3B low voltage detector high threshold — — 2.95

VLVDHV3BL CC P LVDHV3BL low voltage detector low threshold 2.7 — 2.9

VLVDHV5H CC T LVDHV5 low voltage detector high threshold — — 4 .5

VLVDHV5L CC P LVDHV5 low voltage detector low threshold 3.8 — 4.4

VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold 1.08 — —

VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold 1.08 — 1.14

VDD

VLVDHVxH

RESET

VLVDHVxL

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 55

4.9 Low voltage domain power consumption

Table 23 provides DC electrical characteristics for significant application modes. These values are indicative values; actual

consumption depends on the application.

Table 23. Low voltage power domain electrical characteristics1

1Except for IDDMAX, all consumptions in this table apply to VDD_BV only and do not include VDD_HV.

Symbol C Parameter Conditions2

2VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value Unit

Min Typ Max

IDDMAX3

3Running consumption is given on voltage regu lator supply (VDDREG). IDDMAX is composed of three components:

IDDMAX = IDD(VDD_BV) + IDD(VDD_HV) + IDD(VDD_HV_ADC). It does not include a fourth component linked to I/Os

toggling which is highly dependent on the application. The given value is thought to be a wo rst case value with

all peripherals running, and code fetched from code flash while modify operation on-going on data flash. Note that

this value can be significantly reduced by the application: switch off not used peripherals (default), reduce peripheral

frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible.

CC D RUN mode maximum average

current — — 115 1404

4Higher current may be sunk by de vice during power-up and standby e xit. Please refer to in-rush current in Table 21.

IDDRUN5CC T RUN mode typical average

current6fCPU = 8 MHz — 12 — mA

CPU = 16 MHz — 27 —

CPU = 32 MHz — 43 —

CPU = 48 MHz — 56 —

CPU = 64 MHz — 70 —

IDDHALT CC C HALT mode current7Slow internal RC

oscillator (128 kHz)

running

TA= 25 °C — 10 18 mA

A= 125 °C — 17 28

IDDSTOP CC P ST OP mode curr ent8Slow internal RC

oscillator (128 kHz)

running

TA= 25 °C — 350 900 µA

A=55°C — 750 —

A=85°C — 2 — mA

A= 105 °C — 4 —

A= 125 °C — 7 14

IDDSTDBY2 CC P STANDBY2 mode current9Slow interna l RC

oscillator (128 kHz)

running

TA= 25 °C — 30 100 µA

A=55°C — 75 —

A=85°C — 180 —

A= 105 °C — 315 —

A= 125 °C — 560 1700

IDDSTDBY1 CC T STANDBY1 mode current10 Slow internal RC

oscillator (128 kHz)

running

TA= 25 °C — 20 60 µA

A=55°C — 45 —

A=85°C — 100 —

A= 105 °C — 165 —

A= 125 °C — 280 900

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor56

4.10 Flash memory electrical characteristics

4.10.1 Program/erase characteristics

Table 24 shows the program and erase characteristics.

5RUN current measured with typical application with accesses on both Flash and RAM.

6Only for the “P” classification: Data and Code Flash in Normal P ower . Code f etched from RAM: Serial IPs CAN and

LIN in loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and

running at max frequency, periodic SW/WDG timer reset enabled.

7Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz on. 10 MHz XTAL clock.

FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clocks gated. LINFle x:

instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 to 9 cloc ks gated. eMIOS: instance:

0 ON (16 channels on PA[0]–PA [11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI:

instance: 0 (clocked b ut no communication), instance: 1 to 5 cloc ks gated. R TC/ API ON. PIT ON. STM ON. A DC1

OFF. ADC0 ON but no conversion except two analog watchdogs.

8Only for the “P” classification: No clock, FIRC 16 MHz off, SIRC 128 kHz on, PLL off, HPvreg off,

ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.

9Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum

consumption, all possible modules s witched off.

10 ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules

switched off.

Table 24. Program and erase specifications

Symbol C Parameter Conditions

Value

Unit

Min Typ1

1Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to

change pending device characterization.

Initial

max2

2Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

Max3

3The maximum program and erase times occur after the specified number of program/erase cycles. These maximum

values are characterized but not guaranteed.

Tdwprogram CC C Double word (64 bits) program time4

4Actual hardware programming times. This does not include software overhead.

Code Flash — 18 50 500 µs

Data Flash 22

T16Kpperase 16 KB block preprogram and erase time Code Flash — 200 500 5000 ms

Data Flash 300

T32Kpperase 32 KB block preprogram and erase time Code Flash — 300 600 5000 ms

Data Flash 400

T128Kpperase 128 KB block preprogram and erase time Code Flash — 600 1300 7500 ms

Data Flash 800

Teslat D Erase Suspend Latency — — — 30 30 µs

TESRT C Erase Suspend Request Rate Code Flash 20 — — — ms

Data Flash 10 — — —

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 57

ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units

will experience single bit corrections throughout the life of the product with no imp act to product reliability.

Table 27 shows the FLASH_BIU settings versus frequency of operation. Re fer to the device reference manual for definitions

of these bit fields.

Table 25. Flash module life

Symbol C Parameter Conditions Value Unit

Min Typ Max

P/E CC C Number of program/erase

cycles per block for 16 KB

blocks over the operating

temperature range (TJ)

— 100000 — — cycles

P/E CC C Number of program/erase

cycles per block for 32 KB

blocks over the operating

temperature range (TJ)

— 10000 100000 — cycles

P/E CC C Number of program/erase

cycles per block for 128 KB

blocks over the operating

temperature range (TJ)

— 1000 100000 — cycles

Retention CC C Minimum data retention at 85

°C av erage ambient

temperature1

1Ambient temperature averaged over duration of application, not to exceed recommended product operating

temperature range.

Blocks with

0–1,000 P/E cycles 20 — — years

Blocks wit h

1,001–10,000 P/E

cycles

10 — — years

Blocks wit h

10,001–100,000 P/E

cycles

5——years

Table 26. Flash read access t iming

Symbol C Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Max Unit

fREAD CC P Maximum frequency for Flash reading 2 wait states 64 MHz

C 1 wait state 40

C 0 wait states 20

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor58

4.10.2 Flash power supply DC characteristics

Table 28 shows the power supply DC characteristics on external supply.

Table 27. FLASH_BIU settings vs. frequency of operation

Maximum frequency

(MHz) APC RWSC WWSC DPFEN IPFEN PFLIM BFEN

Up to and including

82 MHz TBD TBD TBD TBD TBD TBD TBD

Up to and including

102 MHz TBD TBD TBD TBD TBD TBD TBD

Up to and including

132 MHz TBD TBD TBD TBD TBD TBD TBD

Def ault setting after

reset TBD TBD TBD TBD TBD TBD TBD

Table 28. Flash power supply DC electrical characteristics

Symbol Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified

Value Unit

Min Typ Max

ICFREAD CC Sum of the current consumption on

VDDHV and VDDBV on read access Flash module read

fCPU = 64 MHz2

2fCPU 64 MHz can be achieved only at up to 105 °C

Code Flash — — 33 mA

IDFREAD Data Flash — — 33

ICFMOD CC Sum of the current consumption on

VDDHV and VDDBV on matrix

modification (program/erase)

Program

/Erase on-going while

reading Flash registers

fCPU = 64 MHz2

Code Flash — — 52 mA

IDFMOD Data Flash — — 33

ICFLPW CC Sum of the current consumption on

VDDHV and VDDBV during Flash low

powe r mode

— Code Flash — — 1.1 mA

IDFLPW Data Fla s h — — 900 µA

ICFPWD CC Sum of the current consumption on

VDDHV and VDDBV during Flash power

down mode

— Code Flash — — 150 µA

IDFPWD Data Flash — — 150

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 59

4.10.3 Start-up/Switch-off timings

4.11 Electromagnetic compatibility (EMC) characteristics

Susceptibility tests are performed on a sample basis during product characterization.

4.11.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified

MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in

particular.

Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC

level requested for the application.

• Software recommendations The software flowchart must include the management of runaway conditions such as:

— Corrupted program counter

— Unexpected reset

— Critical data corruption (control registers...)

• Prequalification trials Most of th e common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the

software can be hardened to prevent unrecoverable errors occurring.

4.11.2 Electromagnetic interference (EMI)

The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1

standard, which specifies the general conditions for EMI measurements.

Table 29. Star t- u p time/Switch-off time

Symbol C Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value Unit

Min Typ Max

TFLARSTEXIT CC T Delay for Flash module to exit reset mode — — — 125 µs

TFLALPEXIT CC T Delay for Flash module to exit low-power mode — — — 0.5

TFLAPDEXIT CC T Delay for Flash module to exit power-down

mode ———30

TFLALPENTRY CC T Delay for Flash module to enter low-power

mode ———0.5

TFLAPDENTRY CC T Delay for Flash module to enter power-down

mode ———1.5

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor60

4.11.3 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine

its performance in terms of electrical sensitivity.

4.11.3.1 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according

to each pin combination. The sample size depends on the number of supply pins in the device (3 parts(n + 1) supply pin). This

test conforms to the AEC-Q100-002/-003/-011 standard.

4.11.3.2 Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performa nce:

Table 30. EMI radiated emission measurement1,2

1EMI testing and I/O port waveforms per IEC 61967-1, -2, -4

2F or information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your

local marketing representative.

Symbol C Parameter Conditions Value Unit

Min Typ Max

— SR — Scan range — 0.150 1000 MHz

fCPU SR — Operating frequency — — 64 — MHz

VDD_LV SR — LV operating voltages — — 1.28 — V

SEMI CC T Peak level VDD = 5V, T

A=25°C,

LQFP144 package

Test co nf orming to IEC

61967-2,

fOSC = 8 MHz/fCPU =

64 MHz

No PLL frequency

modulation — — 18 dBµV

± 2% PLL frequency

modulation — — 14 dBµV

Ta ble 31. ESD absolute maxi mum ratings1,2

1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated

Circuits.

2A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification requirements. Complete DC parametric and functional testing shall be performed per applicable

device specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

Symbol Ratings Conditions Class Max value3

3Data based on characteri zation results, not tested in production

Unit

VESD(HBM) Electrostatic discharge voltage

(Human Body Model) TA = 25 °C

conforming to AEC-Q100-002 H1C 2000 V

VESD(MM) Electrostatic di scharge voltage

(Machine Model) TA = 25 °C

conforming to AEC-Q100-003 M2 200

VESD(CDM) Electrostatic di scharge voltage

(Charged Device Model) TA = 25 °C

conforming to AEC-Q100-011 C3A 500

750 (corners)

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 61

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with the EIA/JESD 78 IC latch-up standard.

4.12 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics

The device provides an oscillator/resonator driver. Figure 11 describes a simple model of th e internal oscillator driver and

provides an example of a connection for an oscillator or a resonator.

Table 33 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulatio ns.

Figure 11. Crystal oscillator an d resonator connection scheme

NOTE

XTAL/EXTAL must not be directly used to drive external circuits.

Table 32. Latch-up results

Symbol Parameter Conditions Class

LU Static latch-up class TA = 125 °C

conforming to JESD 78 II level A

Crystal

XTAL

EXTAL

Resonator

XTAL

EXTAL

DEVICE

DEVICE XTAL

EXTAL

VDD

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor62

Figure 12. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

Table 33. Crystal description

Nominal

frequency

(MHz)

NDK crystal

reference

Crystal

equivalent

series

resistance

ESR 

Crystal

motional

capacitance

(Cm) fF

Crystal

motional

inductance

(Lm) mH

Load on

xtalin/xtalout

C1 = C2

(pF)1

1The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing

includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.

Shunt

capacitance

between

xtalout

and xtalin

C02 (pF)

2The value of C0 specified here includes 2 pF addition al capacitance for parasitics (to be seen with bond-pad s,

package, etc.).

4 NX8045GB 300 2.68 591.0 21 2.93

8 NX5032GA 300 2.46 160.7 17 3.01

10 150 2.93 86.6 15 2.91

12 120 3.11 56.5 15 2.93

16 120 3.90 25.3 10 3.00

Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

Symbol C Parameter Conditions1Value Unit

Min Typ Max

fFXOSC SR — Fast external crystal

oscillator frequency —4.0—16.0MHz

VMXOSCOP

TMXOSCSU

VXTAL

VMXOSC

valid internal clock

90%

10%

1/fMXOSC

S_MTRANS bit (ME_GS register)

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 63

4.13 Slow e xternal crystal oscillator (32 kHz) electrical characteristics

The device provides a low power oscillator/resonator driver.

gmFXOSC CC C Fast external crystal

oscillator

transconductance

VDD = 3.3 V ± 10%,

PAD3V5V = 1

OSCILLATOR_MARGIN = 0

2.2 — 8.2 mA/V

CC P VDD = 5.0 V ± 10%,

PAD3V5V = 0

OSCILLATOR_MARGIN = 0

2.0 — 7.4

CC C VDD = 3.3 V ± 10%,

PAD3V5V = 1

OSCILLATOR_MARGIN = 1

2.7 — 9.7

CC C VDD = 5.0 V ± 10%,

PAD3V5V = 0

OSCILLATOR_MARGIN = 1

2.5 — 9.2

VFXOSC CC T Oscillation amplitude at

EXTAL fOSC =4MHz,

OSCILLATOR_MARGIN = 0 1.3 — — V

fOSC =16MHz,

OSCILLATOR_MARGIN = 1 1.3 — —

VFXOSCOP CC P Oscillation operating point — — 0.95 V

IFXOSC2CC T Fast exter nal crystal

oscillator consumption ——23mA

TFXOSCSU CC T Fast external crystal

oscillator start-up time fOSC = 4 MHz,

OSCILLATOR_MARGIN = 0 —— 6ms

fOSC = 16 MHz,

OSCILLATOR_MARGIN = 1 ——1.8

VIH SR P Input high level CMOS

(Schmitt Trigger) Oscillator bypass mode 0.65VDD —V

DD +0.4 V

VIL SR P Input low level CMOS

(Schmitt Trigger) Oscillator bypass mode 0.4 — 0.35VDD V

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2Stated values take into account only analog module consumption but not the digital contributor (clock tree and

enabled peripherals).

Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor64

Figure 13. Crystal oscillator an d resonator connection scheme

NOTE

OSC32K_XTAL/OSC32K_EXTAL must not be dir ectly used to drive external circuits.

Figure 14. Equivalent circuit of a quartz crystal

Table 35. Crystal motional characteristics1

Symbol Parameter Conditions Value Unit

Min Typ Max

LmMotional inductance — — 11.796 — KH

CmMotional capacitance — — 2 — fF

C1/C2 Load capacitance at OSC32K_XTAL and

OSC32K_EXTAL with respect to ground2—18—28pF

Rm3Motional resistance AC coupled at C0 = 2.85 pF4——65k

AC coupled at C0 = 4.9 pF4——50

AC coupled at C0 = 7.0 pF4——35

AC coupled at C0 = 9.0 pF4——30

OSC32K_XTAL

OSC32K_EXTAL

DEVICE

Crystal

OSC32K_XTAL

OSC32K_EXTAL

Resonator

DEVICE

C2C1 C2

Crystal

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 65

Figure 15. Slow e xternal crystal oscillator (32 kHz) electrical characteristics

4.14 FMPLL electrical characteristics

The device provides a frequency modulated phase locked loop (FMPLL) module to generate a fast system clock from the main

oscillator driver.

1The cr ystal used is Epson Toyocom MC306.

2This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to

ground. It includes all the parasitics due to board traces, crystal and package.

3Maximum ESR (Rm) of the crystal is 50 k

4C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.

Table 36. Slow external crystal oscillator (32 kHz) electrical characteri stics

Symbol C Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value Unit

Min Typ Max

fSXOSC SR — Slow external crystal oscillator

frequency — 32 32.768 40 kHz

VSXOSC CC T Oscillation amplitude — — 2.1 — V

ISXOSCBIAS CC T Oscillation bias current — 2.5 µA

ISXOSC CC T Slow external crystal oscillator

consumption ———8µA

TSXOSCSU CC T Slow e xternal crystal oscillator

start-up time ———2

2Start-up time has been measured with EPSON T O Y OCOM MC306 crystal. V ariation ma y be seen with other crystal.

OSCON bit (OSC_CTL register)

TLPXOSC32KSU

VOSC32K_XTAL

VLPXOSC32K

valid internal clock

90%

10%

1/fLPXOSC32K

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor66

4.15 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up of the device.

Table 37. FMPLL electrical characteristics

Symbol C Parameter Conditions1

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value Unit

Min Typ Max

fPLLIN SR — FMPLL ref erence clock2

2PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in

functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN.

—4—64MHz

PLLIN SR — FMPLL reference clock duty

cycle2—40—60%

fPLLOUT CC P FMPLL output clock frequency — 16 — 64 MHz

fVCO3

3Frequency modulation is considered ± 4%.

CC P VCO frequency without

frequency modu l a ti on — 256 — 512 MHz

P VCO frequency with frequency

modulation — 245.76 — 532.48

fCPU SR — System clock frequency — — — 644

4fCPU 64 MHz can be achieved only at up to 105 °C .

MHz

fFREE CC P Free-running frequency — 20 — 150 MHz

tLOCK CC P FMPLL lock time Stable oscillator (fPLLIN = 16 MHz) 40 100 µs

tSTJIT CC — FMPLL short term jitter5

5Short term jitter is measured on the clock rising edge at cycle n and n+4.

fsys maximum –4 — 4 %

tLTJIT CC — FMPLL long term jitter fPLLCLK at 64 MHz, 4000 cycles — — 10 ns

IPLL CC C FMPLL consumption TA = 25 °C — — 4 mA

Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics

Symbol C Parameter Conditions1Value Unit

Min Typ Max

fFIRC CC P Fast internal RC oscillator high

frequency TA = 25 °C, trimmed — 16 — MHz

SR — — 12 20

IFIRCRUN2, CC T Fast internal RC oscillator high

frequency current in run ning

mode

TA = 25 °C, trimmed — — 200 µA

IFIRCPWD CC D Fast internal RC oscillator high

frequency current in power

down mode

TA = 25 °C — — 10 µA

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 67

4.16 Slow internal RC oscillator (128 kHz) electrical characteristics

The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock for the RTC module.

IFIRCSTOP CC T Fast in ternal RC oscillator high

frequency and system cloc k

current in stop mode

TA = 25 °C sysclk = off — 500 — µA

sysclk = 2 MHz — 600 —

sysclk = 4 MHz — 700 —

sysclk = 8 MHz — 900 —

sysclk = 16 MHz — 1250 —

TFIRCSU CC C Fast internal RC oscillato r

start-up time VDD = 5.0 V ± 10% — 1.1 2.0 µs

FIRCPRE CC C Fast internal RC oscillator

precision after software

trimmin g of fFIRC

TA = 25 °C 1— 1%

FIRCTRIM CC C Fast internal RC oscillator

trimming step TA = 25 °C — 1.6 %

FIRCVAR CC C Fast internal RC oscillator

variation over temperature and

supply with respect to fFIRC at

TA= 25 °C in high-frequency

configuration

—5— 5%

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2This does not include consumption link ed to clock tree toggling and peripherals consumption when RC oscillator is

ON.

Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics

Symbol C Parameter Conditions1Value Unit

Min Typ Max

fSIRC CC P S low internal RC oscillator low

frequency TA = 25 °C , trimme d — 128 — kHz

SR — — 100 — 150

ISIRC2, CC C Slow internal RC oscillator low

frequency current TA = 25 °C, trimme d — — 5 µA

TSIRCSU CC P S low internal RC oscillator start-up

time TA = 25 °C , VDD = 5.0 V ± 10% — 8 12 µs

SIRCPRE CC C Slow internal RC oscillator precision

after software trimming of fSIRC

TA = 25 °C 2— 2%

SIRCTRIM CC C Slow internal RC oscillator trimming

step ——2.7—

Table 38. Fast internal RC oscillator (16 MHz) el ectrical characteristics (cont inued)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor68

4.17 ADC electrical characteristics

4.17.1 Introduction

The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit).

SIRCVAR CC C Slow internal RC oscillator v ariation

in temperature and supply with

respect to fSIRC at TA= 55 °C in high

frequency configuration

High frequency configuration 10 — 10 %

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2This does not include consumption link ed to clock tree toggling and peripherals consumption when RC oscillator is

ON.

Table 39. Slow internal RC oscill ator (128 kHz) electrical characteristics (continued)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 69

Figure 16. ADC_0 characteristic and error definitions

4.17.2 Input im pedance and ADC accuracy

In the following analysis, th e input circuit corresponding to the precise channels is considered.

T o preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor

with good high frequency characteristics at the input pin of the devi ce can be effective: the capacitor should be as large as

possible, ideally infinite. This capacitor cont ributes to attenuating the noise present on the input pin; furthermore, it sources

charge during the sampling phase, when the analog signal source is a high-impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC

filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to

be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal

(bandwidth) and the equivalen t input impedance of the ADC itself.

(2)

(1)

(3)

(4)

(5)

Offset Error OSE

Gain Error GE

1 LSB (ideal)

Vin(A) (LSBideal)

(1) Example of an actual tr ansfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

code out

1023

1022

1021

1020

1019

1018

1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023

1 LSB ideal = VDD_ADC / 1024

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor70

In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being

substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path

to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ

= 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage

partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit

must be designed to respect the Equation 4:

Eqn. 4

Equation 4 generates a constraint for external network design, in particular on re si st ive path. Internal switch resistances (RSW

and RAD) can be neglected with respect to external resistances.

Figure 17. Input equivalent circuit (precise channels)

RSRFRLRSW RAD

+++ +

REQ

---------------------------------------------------------------------------

1

---LSB

SW1

Sampling

Source Filter Current Limiter

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

RS Source Impedance

RF Filter Resistance

CF Filter Capacitance

RL Current Limiter Resistance

RSW1 Channel Selection Switch Impedance

RAD Sampling Switch Impedance

CP Pin Capacitance (two contributions, CP1 and CP2)

CS Sampling Capacitance

Channel

Selection

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 71

Figure 18. Input equivalent circuit (extended channels)

A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are

initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 17): A charge sharing phenomenon

is installed when the sampling phase is started (A/D switch close).

Figure 19. Transient behavior during sampling phase

In particular two different transient periods can be distinguished:

1. A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS

is supposed initially completely discharged): considering a worst case (since the time constant in reality would be

faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in s eries,

and the time constant is

SW1

Sampling

Source Filter Current Limiter

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

RS Source Impedance

RF Filter Resistance

CF Filter Capacitance

RL Current Limiter Resistance

RSW Channel Selection Switch Impedance (two contributions RSW1 and RSW2)

RAD Sampling Switch Impedance

CP Pin Capacitance (three contributions, CP1, CP2 and CP3)

CS Sampling Capacitance

Channel

Selection

Extended

SW2

Switch

VA1

VA2

VCS Voltage Transient on CS

V <0.5 LSB

1 < (RSW + RAD) CS << TS



= R

+ C

)

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor72

Eqn. 5

Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is

faster , but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS

is always much longer than the internal time constant:

Eqn. 6

The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance

according to Equation 7:

Eqn. 7

2. A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance

RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality

would be faster), the time constant is:

Eqn. 8

In this case, the time constant depends on the external circuit: in particular imposing that th e transient is completed

well before the end of sampling time TS, a constraints on RL sizing is obtained:

Eqn. 9

Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source

impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2

(at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge

balance assuming now CS already charged at VA1):

Eqn. 10

The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to

provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of

the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as antialiasing.

1RSW RAD

+=CPCS



CPCS

---------------------



1RSW RAD

+CSTS

«

VA1 CSCP1 CP2

++VACP1 CP2

+=

2RL

CSCP1 CP2

++

10 2

10 RLCSCP1 CP2

++=T



VA2 CSCP1 CP2 CF

+++VACF

VA1

P1 CP2

+=

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 73

Figure 20. Spectral representation of input signal

Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the antialiasing filter , fF), according

to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constan t time o f the filter is greater than or

at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which

is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific

channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time

TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is

closed.

The considerations above lead to impose new cons traints on the external circuit, to reduce the accuracy error due to the voltage

drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled

voltage on CS:

Eqn. 11

From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of

half a count, a constraint is evident on CF value:

ADC_0 (10-bit) Eqn. 12

ADC_1 (12-bit) Eqn. 13

f0f

Analog source bandwidth (VA)

f0f

Sampled signal spectrum (fC = Conversion rate)

Anti-aliasing filter (fF = RC filter pole)

2 f0<fC (Nyquist)

fF = f0 (Anti-aliasing filtering condition)

TC<2 RFCF (Conversion rate vs. filter pole)

Noise

VA2

------------CP1 CP2

CP1 CP2

FCS

--------------------------------------------------------=

CF2048 CS



CF8192 CS



MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor74

4.17.3 ADC electrical characteristics

Table 40. ADC input leakage current

Symbol C Parameter Conditions Value Unit

Min Typ Max

ILKG CC C Input leakage current TA=40 °C No current injection on adjacent pin — 1 — nA

A= 25 °C — 1 —

A= 105 °C — 8 200

A= 125 °C — 45 400

Table 41. ADC_0 conversion characteristics (10-bit ADC_0)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

VSS_ADC0 SR — Voltage on VSS_HV_ADC0

(ADC_0 reference) pin with

respect to ground (VSS)2

—0.1 — 0.1 V

VDD_ADC0 SR — Voltage on VDD_HV_ADC pin

(ADC reference) with respect

to ground (VSS)

—V

DD 0.1 — VDD +0.1 V

VAINx SR — Analog input voltage3—V

SS_ADC0

0.1 —V

DD_ADC0

+0.1 V

IADC0pwd SR — ADC_0 consumption in power

down mode ———50µA

IADC0run SR — ADC_0 consumption in

running mode ———40mA

fADC0 SR —ADC_0 analog frequency —6—32 + 4% MHz

ADC0_SYS SR —ADC_0 digital clock duty cycle

(ipg_clk) ADCLKSEL = 1445 — 55 %

tADC0_PU SR —ADC_0 power up del ay ———1.5 µs

tADC0_S CC T Sample time5fADC = 32 MHz,

ADC0_conf_sample_input = 17 0.5 — µs

fADC = 6 MHz,

INPSAMP = 255 ——42

tADC0_C CC P Conversion time6fADC = 32 MHz,

ADC_conf_comp = 2 0.625 — — µs

CSCC DADC_0 input sampling

capacitance ———3pF

CP1 CC DADC_0 input pin capacitance 1 — — — 3pF

CP2 CC DADC_0 input pin capacitance 2 ———1pF

CP3 CC DADC_0 input pin capacitance 3 — — — 1pF

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 75

RSW1 CC DInternal resistance of analog

source ———3 k

RSW2 CC DInternal resistance of analog

source — — — 2 k

RAD CC DInternal resistance of analog

source ———2 k

IINJ SR —Input current Injection Current injection

on one ADC_0

input, different

from the

converted one

VDD =

3.3 V ± 10% 5—5mA

VDD =

5.0 V ± 10% 5 — 5

| INL | CC TAbsolute va lue for integral

nonlinearity No overload — 0.5 1.5 LSB

| DNL | CC TAbsolute differential

nonlinearity No overload —0.5 1.0 LSB

| OFS | CC TAbsolute offset error — — 0.5 — LSB

| GNE | CC TAbsolute gain error ——0.6 —LSB

TUEP CC PTotal unadjusted error7 fo r

precise channels, input only

pins

Without current injection 20.6 2LSB

TWith current injection 3 — 3

TUEX CC TTotal unadjusted error7 fo r

extended channel Without current injection 3 1 3 LSB

TWith current injection 4 4

1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

2Analog and digita l VSS must be common (to be tied together externally).

3VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0x3FF.

4Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured

by internal divider by 2.

5During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the

end of the sample time tADC0_S, changes of the analog input v oltage have no eff ect on the conversion result. V alues

for the sample clock tADC0_S depend on programming.

6This parameter does not include the sample time tADC0_S, but only the time f or determining the digital result and the

time to load the result’s register with the conversion result.

7Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

Table 41. ADC_0 conversion characteristics (continued)(10-bit ADC_0)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor76

Figure 21. ADC_1 characteristic and error definitions

Table 42. ADC_1 conversion characteristics (12-bit ADC_1)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

VSS_ADC1 SR — Voltage on VSS_HV_ADC1

(ADC_1 reference) pin with

respect to ground (VSS)2

—–0.1—0.1V

VDD_ADC1 SR — V oltage on VDD_HV_ADC1 pin

(ADC_1 ref e rence) with

respect to ground (VSS)

—V

DD –0.1 — V

DD +0.1 V

(2)

(1)

(3)

(4)

(5)

Offset Erro r OS E

Offset Error OSE

Gain Error GE

1 LSB (ideal)

Vin(A) (L SBideal)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Diff erential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

code out

4095

4094

4093

4092

4091

4090

1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095

1 LSB ideal = AVDD / 4096

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 77

VAINx SR — Analog input voltage3—V

SS_ADC1

–0.1 —V

DD_ADC1

+0.1 V

IADC1pwd SR — ADC_1 consumption in power

down mode ———50µA

IADC1run SR — ADC_1 consumption in running

mode ———6mA

fADC1 SR —ADC_1 analog frequency VDD = 3.3 V 3.33 — 20 + 4% MHz

VDD = 5 V 3.33 — 32 + 4%

tADC1_PU SR —ADC_1 power up de l ay ———1.5 µs

tADC1_S CC T Sample time4

VDD = 3.3 V fADC1 = 20 MHz,

ADC1_conf_sample_input = 12 600 — — ns

Sample time4

VDD = 5.0 V fADC1= 32 MHz,

ADC1_conf_sample_input = 17 500 — —

Sample time4

VDD = 3.3 V fADC1= 3.33 MHz,

ADC1_conf_sample_input = 255 — — 76.2 µs

Sample time4

VDD = 5.0 V fADC1= 3.33 MHz,

ADC1_conf_sample_input = 255 ——76.2

tADC1_C CC P Conv ersion time5

VDD = 3 .3 V fADC1 = 20MHz,

ADC1_conf_comp = 0 2.4 — — µs

Conversion time5

VDD = 5.0 V fADC 1 = 32 MHz,

ADC1_conf_comp = 0 1.5 — — µs

Conversion time5

VDD = 3.3 V fADC 1 = 13.33 MHz,

ADC1_conf_comp = 0 ——3.6µs

Conversion time5

VDD = 5.0 V fADC1 = 13.33 MHz,

ADC1_conf_comp = 0 ——3.6µs

ADC1_SYS SR —ADC_1 digital clock duty cycle ADCLKSEL = 1645 —55 %

CSCC DADC_1 input sampling

capacitance — — —5pF

CP1 CC DADC_1 input pin capacitance 1 — — —3pF

CP2 CC DADC_1 input pin capacitance 2 — — —1pF

CP3 CC DADC_1 input pin capacitance 3 — — —1.5pF

RSW1 CC DInternal resistance of analog

source ———1k

RSW2 CC DInternal resistance of analog

source ———2k

RAD CC DInternal resistance of analog

source ———0.3k

Table 42. ADC_1 conversio n characteristi cs (12-bit ADC_1) (continued)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor78

IINJ SR —Input current Injection Current

injection on

one ADC_1

input, different

from the

converted one

VDD = 3.3 V ± 10% –5 — 5 mA

VDD = 5.0 V ± 10% –5 — 5

INLP CC TAbsolute Integral

non-linearity-Precise channels No overload — 1 3 LSB

INLX CC TAbsolute Integral

non-linearity-Extended

channels

No overload — 1.5 5 LSB

DNL CC TAbsolute Differential

non-linearity No overload — 0.5 1 LSB

OFS CC TAbsolute Offset error ——2—LSB

GNE CC TAbsolute Gain error ——2—LSB

TUEP7CC PTotal Unadjusted Error for

precise channels, input only

pins

Without current injection –6 — 6 LSB

TWith current injection –8 — 8

TUEX7CC TTotal Unadjusted Error for

extended channel Without current injection –10 —10 LSB

TWith current injection –12 —12

1VDD = 3.3 V ± 10% / 5.0 V ± 10% , TA = –40 to 125 °C, unless otherwise specified

2Analog and digital VSS must be common (to be tied together externally).

3VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0xFFF.

4During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final v oltage le v el within tADC1_S. After th e end

of the sample time tADC1_S, changes of the analog input voltage hav e no eff ect on the con version result. Values for the

sample clock tADC1_S depend on programming.

5This parameter does not include the sample time tADC1_S, but only the time for determining the digital resu lt and the

time to load the result’s register with the conversion result.

6Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by

internal divider by 2.

7Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

Table 42. ADC_1 conversio n characteristi cs (12-bit ADC_1) (continued)

Symbol C Parameter Conditions1Value Unit

Min Typ Max

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 79

4.18 On-chip peripherals

4.18.1 Current consumption

Table 43. On-chip peripherals current consumption1

Symbol C Parameter Conditions Value Unit

Typ

IDD_BV(CAN) CC T CAN

(Fle xCAN)

supply current

on VDD_BV

Bitrate =

500 Kbps Total (static + dynamic)

consumption:

• F lexCAN in loop-back

mode

• XTAL at 8 MHz used as

CAN engine clock

source

• Message sending

period is 580 µs

8 * fperiph + 85 µA

Bitrate =

125 Kbps 8 * fperiph + 27

IDD_BV(eMIOS) CC T eMIOS supply

current on

VDD_BV

Static consumption:

• eMIOS chan nel OFF

• Global prescaler enabled

29 * fperiph

Dynamic consumption:

• It does not change varying the

frequency (0.003 mA)

IDD_BV(SCI) CC T SCI (LINFlex)

supply current

on VDD_BV

Total (static + dynamic) consumption:

• LIN mode

• Baudrate: 20 Kbps

5 * fperiph + 31

IDD_BV(SPI) CC T SPI (DSPI)

supply current

on VDD_BV

Ballast static consumption (only

clocked) 1

Ballast dynamic consumption

(continuous communication):

• B audrate: 2 Mbit

• Trasmission every 8 µs

• Frame: 16 bits

16 * fperiph

IDD_BV

(ADC_0/ADC_1)

CC T ADC_0/ADC_1

supply current

on VDD_BV

VDD = 5.5 V Ballast static consumption

(no conversion) 41 * fperiph µA

VDD = 5.5 V Ballast dynamic

consumption (continuous

conversion)

46 * fperiph

IDD_HV_ADC0 CC T ADC_0 supply

current on

VDD_HV_ADC0

VDD = 5.5 V Analog static consumption

(no conversion) 200

VDD = 5.5 V Analog dynamic

consumption (continuous

conversion)

3mA

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor80

IDD_HV_ADC1 CC T ADC_1 supply

current on

VDD_HV_ADC1

VDD = 5.5 V Analog static consumption

(no conversion) 300 * fperiph µA

VDD = 5.5 V Analog dynamic

consumption (continuous

conversion)

4mA

IDD_HV(FLASH) CC T CFlash +

DFlash supply

current on

VDD_HV

VDD = 5.5 V — 12 mA

IDD_BV(PLL) CC T P LL supply

current on

VDD_BV

VDD = 5.5 V — 2.5 mA

1Operating conditions: TA = 25 °C , f periph = 8 MHz to 64 MHz

Table 43. On-chip peripherals current consumption1 (continued)

Symbol C Parameter Conditions Value Unit

Typ

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 81

4.18.2 DSPI characteristics

Table 44. DSPI characteristics1

No. Symbol C Parameter DSPI0/DSPI1/DSPI5/DSPI6 DSPI2/DSPI4 Unit

Min Typ Max Min Typ Max

SCK SR D SCK cycle time Master mode

(MTFE = 0) 125 — — 333 — — ns

DSlave mode

(MTFE = 0) 125 — — 333 — —

D Master mode

(MTFE = 1) 83 — — 125 — —

DSlave mode

(MTFE = 1) 83 — — 125 — —

—f

DSPI SR D DSPI digital controller frequency — — fCPU ——f

CPU MHz

—tCSC CC D Internal delay between pad

associated to SCK and pad

associated to CSn in

master mode for CSn1->0

Master mode — — 1302—— 15

3ns

—tASC CC D Internal delay between pad

associated to SCK and pad

associated to CSn in

master mode for CSn1->1

Master mode — — 1303— — 1303ns

CSCext4SR D CS to SCK delay Slave mode 32 — — 32 — — ns

ASCext5SR D After SCK delay Slave mode 1/fDSPI + 5 — — 1/fDSPI + 5 — — ns

SDC CC D SCK duty cycle Master mode — tSCK/2 — — tSCK/2 — ns

SR D Slave mode tSCK/2 — — tSCK/2 — —

ASR D Slave access time Slave mode — — 1/fDSPI + 70 — — 1/fDSPI + 130 n s

DI SR D Slave SOUT disable time Slave mode 7 — — 7 — — ns

SUI SR D Data setup time for inputs Master mode 43 — — 145 — — ns

Slave mode 5 — — 5 — —

10 tHI SR D Data hold time fo r inputs Master mode 0 — — 0 — — ns

Slave mode 26—— 2

6——

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristic s

Freescale Semiconductor82

11 tSUO7CC D Data valid after SCK edge Master mode — — 32 — — 50 ns

Slave mode — — 52 — — 160

12 tHO7CC D Data hold time for outputs Master mode 0 — — 0 — — ns

Slave mode 8 — — 13 — —

1Operating conditions: Cout = 10 to 50 pF, SlewIN = 3.5 to 15 ns

2Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK

starts before CSn is asserted. DSPI2 has only SLOW SCK available.

3Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLO W. A positive v alue means that CSn is

deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.

4The tCSC dela y value is configurable through a register . When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay

between internal CS and intern al SCK must be higher than tCSC to ensu re positive tCSCext.

5The tASC delay v alue is configurab le through a register . When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between

internal CS and internal SCK must be highe r than tASC to ensure positive tASCext.

6This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.

7SCK and SOUT are configured as MEDIUM pad.

Table 44. DSPI characteristics1 (continued)

No. Symbol C Parameter DSPI0/DSPI1/DSPI5/DSPI6 DSPI2/DSPI4 Unit

Min Typ Max Min Typ Max

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 83

Figure 22. DSPI classic SPI timing — master, CPHA = 0

Figure 23. DSPI classic SPI timing — master, CPHA = 1

Data Last Data

First Data

First Data Data Last Data

SIN

SOUT

PCSx

SCK Output

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Table 43.

Data Last Data

First Data

SIN

SOUT

12 11

Last Data

Data

First Data

SCK Output

PCSx

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Table 43.

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor84

Figure 24. DSPI classic SPI timing — slave, CPHA = 0

Figure 25. DSPI classic SPI timing — slave, CPHA = 1

Last Data

First Data

Data

SIN

SOUT

5 6

SCK Input

First Data Last Data

SCK Input

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Table 43.

5 6

Last Data

SIN

SOUT

First Data

Data

SCK Input

(CPOL = 0)

(CPOL = 1)

Note: Numbers sho wn reference Table 43.

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 85

Figure 26. DSPI modified transfer format timing — master, CPHA = 0

Figure 27. DSPI modified transfer format timing — master, CPHA = 1

PCSx

12 11

SCK Output

SIN

SOUT

First Data Data Last Data

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Table 43.

PCSx

12 11

SCK Output

SIN

SOUT

First Data Data Last Data

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Table 43.

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor86

Figure 28. DSPI modified transfer format timing — slave, CPHA = 0

Figure 29. DSPI modified transfer format timing — slave, CPHA = 1

Last Data

First Data

Data

SIN

SOUT

5 6

SCK Input

First Data Last Data

SCK Input

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Table 43.

5 6

Last Data

SIN

SOUT

First Data

Data

SCK Input

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Table 43.

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 87

Figure 30. DSPI PCS strobe (PCSS) timing

4.18.3 Nexus characteristics

Table 45. Nexus characteristics

No. Symbol C Parameter Value Unit

Min Typ Max

TCYC CC D TCK cycle time 64 — — ns

MCYC CC D MCKO cycle time 32 — — ns

MDOV CC D MCKO low to MDO data valid — — 8 ns

MSEOV CC D MCKO low to MSEO_b data v alid — — 8 ns

EVTOV CC D MCKO low to EVTO data valid — — 8 ns

NTDIS CC D TDI data setup time 15 — — ns

tNTMSS CC D TMS data setup time 15 — — ns

NTDIH CC D TDI data hold time 5 — — ns

tNTMSH CC D TMS data hold time 5 — — ns

TDOV CC D TCK low to TDO data valid 35 — — ns

TDOI CC D TCK low to TDO data invalid 6 — — ns

PCSx

PCSS

Note: Numbers shown reference Table 43.

MPC5607B Microcontroller Data Sheet, Rev. 5

Electrical characteristics

Freescale Semiconductor88

Figure 31. Nexus TDI, TMS, TDO timing

4.18.4 JTAG characteristics

Table 46. JTAG characteristics

No. Symbol C Parameter Value Unit

Min Typ Max

JCYC CC D TCK cycle time 64 — — ns

TDIS CC D TDI setup time 15 — — ns

TDIH CC D TDI hold time 5 — — ns

TMSS CC D TMS setup time 15 — — ns

TMSH CC D TMS hold time 5 — — ns

TDOV CC D TCK low to TDO valid — — 33 ns

TDOI CC D TCK low to TDO invalid 6 — — ns

TCK

TMS, TDI

TDO

Note: Numbers shown reference Table 45.

Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 89

Figure 32. Timing diagram — JTAG boundary scan

INPUT DATA VALID

OUTPUT DATA VALID

DATA INPUTS

DATA OUTPUTS

TCK

Note: Numbers shown reference Table 46.

3/5

2/4

MPC5607B Microcontroller Data Sheet, Rev. 5

Package characteristics

Freescale Semiconductor90

5 Package characteristics

5.1 Package mechanical data

5.1.1 176 LQFP

Figure 33. 176 LQFP package mechanical drawing (Par t 1 of 3)

Package characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 91

Figure 34. 176 LQFP package mechanical drawing (Par t 2 of 3)

MPC5607B Microcontroller Data Sheet, Rev. 5

Package characteristics

Freescale Semiconductor92

Figure 35. 176 LQFP package mechanical drawing (Par t 3 of 3)

Package characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 93

5.1.2 144 LQFP

Figure 36. 144 LQFP package mechanical drawing (Par t 1 of 2)

MPC5607B Microcontroller Data Sheet, Rev. 5

Package characteristics

Freescale Semiconductor94

Figure 37. 144 LQFP package mechanical drawing (Par t 2 of 2)

Package characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 95

5.1.3 100 LQFP

Figure 38. 100 LQFP package mechanical drawing (Par t 1 of 3)

MPC5607B Microcontroller Data Sheet, Rev. 5

Package characteristics

Freescale Semiconductor96

Figure 39. 100 LQFP package mechanical drawing (Par t 2 of 3)

Package characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 97

Figure 40. 100 LQFP package mechanical drawing (Par t 3 of 3)

MPC5607B Microcontroller Data Sheet, Rev. 5

Package characteristics

Freescale Semiconductor98

5.1.4 208 MAPBGA

Figure 41. 208 MAPBGA package mechanical drawing (Part 1 of 2)

Package characteristics

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 99

Figure 42. 208 MAPBGA package mechanical drawing (Part 2 of 2)

MPC5607B Microcontroller Data Sheet, Rev. 5

Ordering information

Freescale Semiconductor100

6 Ordering information

Figure 43. Commercial product code structure

1208 MAPBGA is available only as development package for Nexus2+.

Qualification Status

Power Architecture Core

Automotive Platfor m

Core Version

Flash Size (core dependent)

Product

Temperature spec.

MPC56 B MLL6

Examp le co de: 07

Package Code

Frequency

Qualification Status

M = general market qualified

S = Automotive qualified

P = Engineering samples

Automotive Plat form

56 = PPC in 90nm

Core Version

0 = e200z0

Flash Size (for z0 core)

5 = 768 KB

6 = 1024 KB

7 = 1.5 MB

Product

B = Body

Fab and Mask Indicator

F = ATMC Fab

0 = Version of the maskset

A = Mask set in dicato r (Blank = 1s t

production maskset, A = 2nd,

B = 3rd, etc)

R = Tape & Reel (blank if Tray)

Temperature spec.

C = -40 to 85 ° C

V = -40 to 105 °C

M = -40 to 125 °C

Package Code

LL = 100 LQFP

LQ = 144 LQFP

LU = 176 LQFP

MG = 208 MAPBGA1

Frequency

4 = Up to 48 MHz

6 = Up to 64 MHz

Fab and Mask Indicator

F1A

Abbreviations

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 101

Appendix A Abbreviations

Table 47 lists abbreviations used but not defined elsewh ere in this document.

Table 47. Abbreviations

Abbreviation Meaning

CMOS Complementary metal oxide semiconductor

CPHA Clock phase

CPOL Clock polarity

CS Peripheral chip select

EVTO Event out

MCKO Message clock out

MDO Message data out

MSEO Message start/end out

MTFE Modified timing f ormat enable

SCK Serial communications clock

SOUT Serial data out

TBD To be defined

TCK Test clock input

TDI Test data input

TDO Test data output

TMS Test mode select

MPC5607B Microcontroller Data Sheet, Rev. 5

Revision history

Freescale Semiconductor102

7 Re vision history

Table 48 summarizes revisions to this document.

Table 48. Revision history

Revision Date Substantive changes

1 12-Jan-2009 Initial release

2 09 Nov-2009 Updated Features

Replaced 27 IRQs in place of 23

ADC features

External Ballast resistor support conditions

Updated device summary-added 208 BGA details

Updated block diagram to include WKUP

Updated block diagram to include 5 ch ADC 12 -bit

Updated Block summary table

Updated LQFP 144, 176 and 100 pinouts. Applied new naming convention for ADC

signals as ADCx_P[x] and ADCx_S[x]

Section 1, “General description

Updated device comparison table

Updated block diagram-aligned with 512k

Updated block summary-aligned with 512k

Section 2, “P ackage pinouts

Updated 100,144,176,208 packages according to cut2.0 changes

Added Section 3.5.1, “External ball ast resistor recommendations

Added NVUSRO [WATCHDOG_EN] field description

Updated Absolute maximum ratings

Updated LQFP thermal characteristics

Updated I/O supply segments

Updated Voltage regulator capacitance conne ction

Updated Low voltage monitor electrical characteristics

Updated Low voltage power domain electrical characteristics

Updated DC electrical characteristics

Updated Program/Erase specifications

Updated Conv ersion characteristics (10 bit ADC)

Updated FMPLL electrical characteristic s

Updated Fast RC oscillator electrical characteristics-aligned with MPC5604B

Updated On-chip peripherals current consumption

Updated ADC characteristics and error definitions diagram

Updated ADC conversion characteristics (10 bit and 12 bit)

Added ADC characteristics and error definitions diagram for 12 bit ADC

3 25 Jan-2010 Updated Features

Updated block diagram to connect peripherals to pad I/O

Updated block summary to include ADC 12-bit

Updated 144, 176 and 100 pinouts to ad just format issues

Table 26 Flash module life-retention value changed from 1-5 to 5 yrs

Minor editing changes

Revision history

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 103

4 24 Aug 2010 Editorial changes and improvements.

Updated “Features“ section

Table 1: updated footnote concerning 208 MAPBGA

In the block diagram:

• Added “5ch 12-bit ADC“ block.

• Updated Legend.

• Added “Interrupt request with wakeup functionality” as an input to the WKPU block.

Figure 2: removed alternate functions

Figure 3: removed alternate functions

Figure 4: removed alternate functions

Table 3: added contents concerning the follo wing b loc ks: CMU, eDMA, ECSM, MC_ME,

MC_PCU, NMI, SSCM, SWT and WKPU

Added Section 3.2, “Pin muxing

Section 4, “Electrical characteristics: removed “Caution” note

Section 4.2, “NVUSRO register: remo ve d “NVUSRO[W ATCHDOG_EN] field description“

section

Table 7: VIN: removed min value in “relative to VDD” row

Table 8

•T

A C-Gr ade Part, TJ C-Grade Part, TA V -Grade P art, TJ V -Grade P art, TA M-Grade Part, TJ M-Grade Part:

added new rows

•TV

DD: contents merged into one row

•V

DD_BV: changed min value in “relative to VDD” row

Section 4.5, “Thermal characteristics

• Se ction 4.5.1, “Extern al ballast resistor recommendations: added new paragraph

about power supply

• Table 10: added R



JB and R



JC rows

• Removed “208 MAPBGA thermal characteristics” table

Table 11: rewrote parameter description of WFI and WNFI

Section 4.6.5, “I/O pad current specification

• Removed I DYNSEG information

• Updated “I/O supply segments” table

Table 18: removed IDYNSEG row

Added Table 19

Table 21

• Updated all values

• Removed I VREGREF and IVREDLVD12 rows

• Added the footnote “The duration of the in-rush current depends on the capacitance

placed on LV pins. BV decaps must be sized accordingly. Refer to IMREG value for

minimum amount of current to be provided in cc.” to the IDD_BV specification.

Table 22

• Updated VPORH min/max value

• Updated VLVDLVCORL min value

Updated Table 23

Table 24

•T

dwprogram: added initial max value

• Inserted Teslat row

Table 25: removed the “To be confirmed” footnote

In the “Cr ystal oscillator and resonator connection scheme” figure, removed RP

Table 36

• Removed gmSXOSC row

•I

SXOSCBIAS: added min/typ/max value

Table 48. Revision history (continued)

Revision Date Substantive changes

MPC5607B Microcontroller Data Sheet, Rev. 5

Revision history

Freescale Semiconductor104

(cont.) 24 Aug 2010

(cont.) Table 37:

• A dded fVCO row

• Added tSTJIT row

Table 38

•I

FIRCPWD: removed ro w for TA = 55 °C

• Updated TFIRCSU row

Table 41: Added two rows: IADC0pwd and IADC0run

Table 42

• Added two rows: IADC1pwd and IADC1run

• Updated values of fADC_1 and tADC1_PU

• Updated tADC1_C row

Updated Table 43

Updated Table 44

Updated Figure 43

Section 6, “Ordering inf ormation: deleted “Orderable part number summary“ table

5 27 Aug 2010 Removed “Preliminary—Sub ject to Change Without Notice” marking. This data sheet

contains specifications based on characterization data.

Table 48. Revision history (continued)

Revision Date Substantive changes

MPC5607B Microcontroller Data Sheet, Rev. 5

Freescale Semiconductor 105

THIS PAGE INTENTIONALLY BLANK

Document Number : MPC5607B

Rev. 5

08/2010

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