Features * High-speed - 100 ps Gate Delay - 2-input NAND, FO = 2 (nominal) * Up to 6.9 Million Used Gates and 976 Pins * System Level Integration Technology - Cores: ARM7TDMITM and AVR(R) RISC Microcontrollers, OakDSPTM and LodeDSPCoresTM, 10T/100 Ethernet MAC, USB and PCI Cores - Memory: SRAM, ROM and FIFO; Gate Level or Embedded - I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB - Output Currents up to 16 mA, 2.5 I/O and 3.3V Tolerant/Compliant * Deep Submicron CAD Flow ATL25 Array Organization Device Number 4LM Routable Gates(1) 5LM Routable Gates(1) Available Routing Sites(2) Max Pad Count Max I/O Count Gate Speed(3) ATL25/44 9,535 10,727 15,892 44 36 100 ps ATL25/68 30,096 33,858 50,161 68 60 100 ps ATL25/84 50,410 56,712 84,018 84 76 100 ps ATL25/100 75,472 84,906 125,788 100 92 100 ps ATL25/120 106,278 120,449 188,940 120 112 100 ps ATL25/132 131,670 149,226 234,080 132 124 100 ps ATL25/144 159,778 181,081 284,050 144 136 100 ps ATL25/160 200,998 227,797 357,330 160 152 100 ps ATL25/184 270,663 306,751 481,179 184 176 100 ps ATL25/208 329,281 376,321 627,203 208 200 100 ps ATL25/228 401,010 458,298 763,830 228 220 100 ps ATL25/256 512,398 585,598 975,998 256 248 100 ps ATL25/304 733,635 838,440 1,397,400 304 296 100 ps ATL25/352 925,815 1,068,248 1,899,108 352 344 100 ps ATL25/388 1,133,594 1,307,994 2,325,323 388 380 100 ps ATL25/432 1,417,125 1,635,145 2,906,925 432 424 100 ps ATL25/484 1,651,406 1,926,640 3,669,792 484 476 100 ps ATL25/540 2,069,052 2,413,894 4,597,895 540 532 100 ps ATL25/600 2,567,790 2,995,755 5,706,200 600 592 100 ps ATL25/700 3,520,954 4,107,780 7,824,344 700 692 100 ps ATL25/800 4,231,979 5,001,430 10,259,344 800 792 100 ps ATL25/900 5,378,257 6,356,122 13,038,200 900 892 100 ps 976 968 100 ps ATL25/976 5,765,320 6,918,384 15,374,188 Notes: 1. One gate = NAND2 2. Routing site = 4 transistors 3. Nominal 2-input NAND gate FO = 2 at 2.5V Gate Array/ Embedded Array ATL25 Series Preliminary Rev. 1414B-10/99 1 Description The ATL25 Series Gate Array and Embedded Array families from Atmel are fabricated on a 0.25 CMOS process with 5 levels of metal. This family features arrays with up to 6.9 million routable gates and 976 pins. The high density and high pin-count capabilities of the ATL25 family, cou- pled with the ability to embed microcontroller cores, DSP engines and memory, all on the same silicon, make the ATL25 series of arrays an ideal choice for System Level Integration. The following design systems are supported: System Version Tools Cadence(R) 4.4.3 2.1.p2 4.1-s051 2.5 3.4B 2.3 OpusTM - Schematic and Layout NC VerilogTM - Verilog Simulator PearlTM - Static Path Verilog-XLTM - Verilog Simulator Logic Design PlannerTM - Floorplanner BuildGatesTM - Synthesis (Ambit) Mentor/Model TechTM 5.2e B2 and Later Modelsim Verilog and VHDL (VITAL) Simulator QuickVHDLTM 98.08, 98.05 5.0.1A VSSTM - VHDL Simulator Design CompilerTM - Synthesis Test CompilerTM - Scan Insertion and ATPG PrimetimeTM - Static Path VCSTM - Verilog Simulator 1998.2f Leonardo SpectrumTM - Synthesis V2.2 V2.2 V1.6 TurboCheck - Gate TurboScan TurboFault SynopsysTM Exemplar TM Syntest Design Design Systems Supported Atmel supports several major software systems for design with complete cell libraries, as well as utilities for netlist verification, test vector verification and accurate delay simulations. Design Flow and Tools Atmel's Gate Array/Embedded Array design flow is structured to allow the designer to consolidate the greatest number of system components onto the same silicon chip, using widely available third party design tools. Atmel's cell library reflects silicon performance over extremes of temperature, voltage and process, and includes the effects of metal loading, inter-level capacitance and edge rise and fall times. The design flow includes clock tree synthesis to customer-specified skew and latency goals. RC extraction is performed on the final design database and incorporated into the timing analysis. 2 ATL25 Series The Gate Array/Embedded Array Design Flow, shown on the following page, provides a pictorial description of the typical interaction between Atmel's design staff and the customer. Atmel will deliver design kits to support the customer's synthesis, verification, floorplanning and scan insertion activities. Tools such as SynopsysTM, Cadence(R), Verilog-HDL TM , CTgen TM , Exemplar TM , PathMILL TM and TimeMILL TM are used, and many others are available. Should a design include embedded memory (SRAM or ROM) or an embedded core, Atmel will conduct a design review with the customer to understand the partition of the Gate Array/Embedded Array and to define the location of the memory blocks and/or cores so that an underlayer layout model can be created. Following Database Acceptance, automated test pattern generation (ATPG) is performed, if required, on scan paths using SynopsysTM or SunriseTM tools, the design is routed, and post-route RC data is extracted. After post-route verification and a Final Design Review, the design is taped out for fabrication. ATL25 Series Gate Array/Embedded Array Design Flow Deliver Design Kit Kickoff Meeting If Embedded Array Define Underlayer If Embedded Array Create Underlayer Synthesis/ Translation/ Conversion Scan/JTAG Simulation/ Static Path Floorplan Database Handoff Tape Out Underlayer Database Acceptance Fabricate Underlayer Place and Route/ Clock Tree Verification/ Resimulation Final Design Review Tape Out Personality Layers Fabricate Personality Customer Atmel Joint DVS Assembly and Test 3 Pin Definition Requirements The corner pads are reserved for Power and Ground only. All other pads are fully programmable as Input, Output, Bidirectional, Power or Ground. When implementing a design with 5V compliant buffers, one buffer site must be reserved for the VDD5 pin, which is used to distribute 5V power to the compliant buffers. Gate Array Design Options Logic Synthesis Atmel can accept netlists in VHDL (MIL-STD-454, IEEE STD 1076) or Verilog-HDLTM format. Atmel fully supports Synopsys for VHDL TM simulation as well as synthesis. VHDL or Verilog-HDL is Atmel's preferred database format for ASIC design. ASIC Design Translation Atmel has successfully translated existing designs from most major ASIC vendors (LSI Logic (R) , Motorola TM , SMOSTM, Oki(R), NEC(R), Fujitsu(R), AMI(R) and others) into Atmel ASICs. These designs have been optimized for speed and gate count and modified to add logic or memory, or replicated as a pin-for-pin compatible, drop-in replacement. FPGA and PLD Conversions Embedded Array 4 ATL25 Series Atmel has successfully translated existing FPGA/PLD designs from most major vendors (Xilinx(R), Actel(R), Altera(R), AMD (R) and Atmel) into Atmel ASICs. There are four primary reasons to convert from an FPGA/PLD to an ASIC. Conversion of high volume devices for a single or combined design is cost effective. Performance can often be optimized for speed or low power consumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing on-board space requirements. Finally, in situations where an FPGA/PLD was used for fast cycle time prototyping, an ASIC may provide a lower cost answer for long-term volume production. ATL25 Series Macro Cores AVR (8-bit RISC) Microcontroller The AVR RISC microcontroller is a true 8-bit RISC architecture, ideally suited for embedded control applications. The AVR is offered as a gate level, soft macro in the ATL25 family. The Fast Access RISC register file consists of 32 general purpose working registers. These 32 registers eliminate the data transfer delay in the traditional program code intensive accumulator architectures. The AVR supports a powerful set of 120 instructions. The AVR pre-fetches an instruction during prior instruction execution, enabling the execution of one instruction per clock cycle. The AVR can incorporate up to 8K x 8 program memory (ROM) and 64K x 8 data memory (SRAM). Also included are several optional peripherals: UART, 8-bit timer/counter, 16-bit timer/counter, external and internal interrupts and programmable watchdog timer. AVR (8-bit RISC) ASIC Core 8-bit Data Bus 16-bit ARM7TDMI Embedded Microcontroller Core The ARM7TDMI is a powerful 32-bit processor offered as an embedded core in the ATL25 series arrays. The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance for very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles. The instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard SRAMs. 5 The ARM7TDMI core includes several optional peripheral macros. The options offered are Real-time Clock, DMA Controller, USART, External Bus Interface, Interrupt, Timer and Advanced Power Management and Controller. ARM7TDMI Embedded Microcontroller Core LodeDSPCoreTM The Lode DSPCore will be offered in the ATL25 series of arrays as an embedded core. Lode is an advanced, 16-bit Digital Signal Processor (DSP) core designed for optimal performance in digital cellular, speech and voice communications applications. correction, and modem functions-required by digital cellular standards. The Lode core architecture efficiently performs the baseband functions-speech compression, forward error Lode's suite of user-friendly development tools are easy to learn, thus accelerating the time it takes to get your product to market. 6 ATL25 Series Lode is the first general-purpose DSP that provides two multiplier-accumulators (MACs) that reduce power consumption by effectively cutting cycle times in half. ATL25 Series Absolute Maximum Ratings* Operating Ambient Temperature................................................... -55C to +125C *NOTICE: Storage Temperature ..................................... -65C to +150C Maximum Input Voltage: Inputs .......................................................................VDD + 0.5V 3.3V Tolerant/Compliant ........................................ VDD3 + 0.5V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage (VDD) ................................... 2.7V Maximum Operating Voltage (VDD3).................................. 3.6V 2.5V DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted. Symbol Parameter Buffer Test Condition Min Typ TA Operating Temperature All -55 VDD Supply Voltage All 2.3 IIH High-level Input Current CMOS VIN = VDD, VDD = VDD (max) IIL Low-level Input Current CMOS VIN = VSS, VDD = VDD (max) Pull-up = 620K -10 IOZ High-impedance State Output Current All VIN = VDD or VSS, VDD = VDD (max) No pull-up or pull-down -10 Output Short-circuit Current PO11 VOUT = VDD, VDD = VDD (max) 14 IOS PO11 VOUT = VSS, VDD = VDD (max) -9 VIH High-level Input Voltage VIL Low-level Input Voltage VHYS Hysteresis 2.5 VOL Note: Low-level Output Voltage 125 C 2.7 V 10 A 10 A mA CMOS 0.7VDD CMOS Schmitt 0.7VDD V 1.3 0.3VDD CMOS Schmitt 1.1 CMOS +-Schmitt 0.4 PO11 IOH = TBD, VDD = VDD (max) 0.7VDD 3.3V Tolerant IOH = TBD 0.7VDD PO11 IOL = TBD, VDD = VDD (max) High-level Output Voltage Units A CMOS VOH Max V 0.3VDD V V 0.4 V All I/Os 2.5V Compliant 7 3.3 Volt DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted. Symbol Parameter Buffer Test Condition TA Operating Temperature All -55 VDD Supply Voltage All Except 3.3V Compliant I/O 2.3 VDD3 Supply Voltage 3.3V Compliant I/O 3.0 IIH High-level Input Current CMOS VIN = VDD, VDD = VDD (max) IIL Low-level Input Current CMOS VIN = VSS, VDD = VDD (max) Pull-up = 620K -10 IOZ High-impedance State Output Current All VIN = VDD or VSS, VDD = VDD (max) No pull-up -10 2 ma Buffer VOUT = VDD, VDD = VDD (max) 14 IOS Output Short-circuit Current 2 ma Buffer VOUT = VSS, VDD = VDD (max) -9 CMOS, LVTTL VIH High-level Input Voltage Min Typ Max Units 125 C 2.5 2.7 V 3.3 3.6 V 10 A A 10 mA 2.0 PCI 0.475VDD3 CMOS/TTL-level Schmitt 2.0 V 1.7 CMOS VIL Low-level Input Voltage 1.1 0.6 TTL-level Schmitt High-level Output Voltage PO11 VOH Low-level Output Voltage IOH = 2 mA, VDD3 = VDD (min) 0.7VDD3 PCI IOH = 500 A 0.9VDD3 PO11 IOL = 2 mA, VDD3 = VDD (min) PCI Note: 8 0.325VDD3 CMOS/TTL-level Schmitt Hysteresis VOL 0.8 PCI VHYS All I/Os 3.3V Tolerant/Compliant ATL25 Series A IOL = 1.5 mA V 0.8 V V 0.4 V 0.1VDD ATL25 Series I/O Buffer DC Characteristics Symbol Parameter Test Condition Typical Units CIN Capacitance, Input Buffer (die) 3.3V 2.4 pF COUT Capacitance, Output Buffer (die) 3.3V 5.6 pF CI/O Capacitance, Bidirectional 3.3V 6.6 pF Testability Techniques For complex designs, involving blocks of memory and/or cores, careful attention must be given to design-for-test techniques. The sheer size of complex designs and the number of functional vectors that would need to be created to exercise them fully, strongly suggests the use of more efficient techniques. Combinations of SCAN paths, multiplexed access to memory and/or core blocks, and built-inself-test logic must be employed, in addition to functional test patterns, to provide both the user and Atmel the ability to test the finished product. An example of a highly complex design could include a PLL for clock management or synthesis, a microcontroller or DSP engine or both, SRAM to support the microcontroller or DSP engine, and glue logic to support the interconnectivity of each of these blocks. The design of each of these blocks must take into consideration the fact that the manufactured device will be tested on a high performance digital tester. Combinations of parametric, functional, and structural tests, defined for digital testers, should be employed to create a suite of manufacturing tests. The type of block dictates the type of testability technique to be employed. The PLL will, by construction, provide access to key nodes so that functional and/or parametric testing can be performed. Since a digital tester must control all the clocks during the testing of a Gate Array/Embedded Arr ay, pr ovisi on must be made for the VCO to be bypassed. Atmel's PLLs include a multiplexing capability for just this purpose. The addition of a few pins will allow other portions of the PLL to be isolated for test, without impinging upon the normal functionality. In a similar vein, access to microcontroller, DSP and SRAM blocks must be provided so that controllability and observability of the inputs and outputs to the blocks are achieved with the minimum amount of preconditioning. The AVR and ARM microcontrollers support SCAN testing, as do the three main execution units of the Oak DSP. SRAM and CAM blocks need to provide access to both address and data ports so that comprehensive memory tests can be performed. Multiplexing I/O pins provides a method for providing this accessibility. The glue logic can be designed using full SCAN techniques to enhance its testability. It should be noted that, in almost all of these cases, the purpose of the testability technique is to provide Atmel a means to assess the structural integrity of a Gate Array/Embedded Array, i.e., sort devices with manufacturing-induced defects. All of the techniques described above should be considered supplemental to a set of patterns which exercise the functionality of the design in its anticipated operating modes. 9 Advanced Packaging The ATL25 Series gate arrays are offered in a wide variety of standard packages, including plastic and ceramic quad flatpacks, thin quad flatpacks, ceramic pin grid arrays, and ball grid arrays. High volume onshore and offshore contractors provide assembly and test for commercial product, with prototype capability in Colorado Springs. Custom package designs are also available as required to meet a customer's specific needs, and are supported through Atmel's package design center. When a standard package cannot meet a customer's need, a package can be designed to precisely fit the application and to maintain the performance obtained in silicon. Atmel has delivered custom-designed packages in a wide variety of configurations. Packaging Options Package Type Pin Count PQFP 44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304 Power Quad 144, 160, 208, 240, 304 L/TQFP 32, 44, 48, 64, 80, 100, 120, 128, 144, 160, 176, 216 PLCC 20, 28, 32, 44, 52, 68, 84 CPGA 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391 CQFP 64, 68, 84, 100, 120, 132, 144, 160, 224, 340 PBGA 121, 169, 208, 217, 225, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 456 Super BGA 168, 204, 240, 256, 304, 352, 432, 560, 600 Low-profile Mini BGA (1) Chip-scale BGA Note: 1. Partial list 10 132, 144, 160, 180, 208 40, 49, 56, 64, 81, 84, 96, 100, 128 ATL25 Series Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 e-mail literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 1414B-10/99/xM