ATL25/600-BGA240 - Atmel Corporation

Features

•High-speed - 100 ps Gate Delay - 2-input NAND, FO = 2 (nominal)

•Up to 6.9 Million Used Gates and 976 Pins

•System Level Integration Technology

– Cores: ARM7TDMI™ and AVR® RISC Microcontrollers, OakDSP™ and

LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores

–Memory: SRAM, ROM and FIFO; Gate Level or Embedded

–I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB - Output Currents up to 16 mA,

2.5 I/O and 3.3V Tolerant/Compliant

•Deep Submicron CAD Flow

Notes : 1. One gate = NAND2

2. Routing site = 4 transistors

3. Nominal 2-input NAND gate FO = 2 at 2.5V

ATL25 Array Organization

Device

Number

4LM

Routable

Gates(1)

5LM

Routable

Gates(1)

Available

Routing

Sites(2) Max Pa d

Count Max I/O

Count Gate

Speed(3)

ATL25/44 9,535 10,727 15,892 44 36 100 ps

ATL25/68 30,096 33,858 50,161 68 60 100 ps

ATL25/84 50,410 56,712 84,018 84 76 100 ps

ATL25/100 75,472 84,906 125,788 100 92 100 ps

ATL25/120 106,278 120,449 188,940 120 112 100 ps

ATL25/132 131,670 149,226 234,080 132 124 100 ps

ATL25/144 159,778 181,081 284,050 144 136 100 ps

ATL25/160 200,998 227,797 357,330 160 152 100 ps

ATL25/184 270,663 306,751 481,179 184 176 100 ps

ATL25/208 329,281 376,321 627,203 208 200 100 ps

ATL25/228 401,010 458,298 763,830 228 220 100 ps

ATL25/256 512,398 585,598 975,998 256 248 100 ps

ATL25/304 733,635 838,440 1,397,400 304 296 100 ps

ATL25/352 925,815 1,068,248 1,899,108 352 344 100 ps

ATL25/388 1,133,594 1,307,994 2,325,323 388 380 100 ps

ATL25/432 1,417,125 1,635,145 2,906,925 432 424 100 ps

ATL25/484 1,651,406 1,926,640 3,669,792 484 476 100 ps

ATL25/540 2,069,052 2,413,894 4,597,895 540 532 100 ps

ATL25/600 2,567,790 2,995,755 5,706,200 600 592 100 ps

ATL25/700 3,520,954 4,107,780 7,824,344 700 692 100 ps

ATL25/800 4,231,979 5,001,430 10,259,344 800 792 100 ps

ATL25/900 5,378,257 6,356,122 13,038,200 900 892 100 ps

ATL25/976 5,765,320 6,918,384 15,374,188 976 968 100 ps

Gate Array/

Embedded Array

ATL25 Series

Preliminary

Rev. 1414B–10/99

ATL25 Series

Description

The ATL25 Ser ies Gate Array and Embedde d Array fami-

lies fr om Atmel are fabric ated on a 0. 25µ CMOS process

with 5 levels of metal. This family features arrays with up to

6.9 million routable gates and 976 pins. The high density

and high pin-count capabilities of the ATL25 family, cou-

pled wi th the abi lity to embed mi crocontro ller cores , DSP

engines and memory, all on the same silicon, make the

ATL25 series of array s an ideal choice for Sys tem Level

Integration.

Design

Design Systems Supported

Atmel supports several major software systems for design

with c omp le te ce ll li bra rie s, as wel l as u til it ies f or n etl ist ve r-

ification, test vector verification and accurate delay

simulations.

Design Flow and Tools

Atmel’s Gate Array/Embedded Array design flow is struc-

tured to allow the designer to consolidate the greatest

number of system components onto the same silicon chip,

using widely available third party design tools. Atmel’s cell

libra ry reflects s ilicon perfor mance over ex tremes of tem-

perature, voltage and process, and includes the effects of

metal loading, inter-level capacitance and edge rise and fall

times. The design flow includes clock tree synthesis to cus-

tomer-specified skew and latency goals. RC extraction is

performed on the final design database and incorporated

into the timing analysis.

The Gate Array/Embedded Array Design Flow, shown on

the following page, provides a pictorial description of the

typical interaction between Atmel’s design staff and the

customer. Atmel will deliver design kits to support the cus-

tomer’s synthesis, verification, floorplanning and scan

inserti on activities. Tool s such as Synopsys ™, Cadence®,

Verilog-HDL™, CTgen™, Exemplar™, PathMILL™ and

TimeMILL™ are used, and many others are available.

Should a design include embedded memory (SRAM or

ROM) or an embedded core, Atmel will conduct a design

review with the customer to understand the partition of the

Gate Array/Embedded Array and to define the location of

the memor y block s and/or co res so that an underlay er lay-

out model can be created.

Following Databa se Acceptance, automated test patter n

generati on (ATPG ) i s perfor m ed, if r eq uire d, o n s can p aths

using S ynopsy s™ or Su nrise™ tools, th e design i s routed,

and post-route RC data is extracted. After post-route

verifica tion an d a F inal De sign Review, the desi gn is tape d

out for fabrication.

The following design systems are supported:

System Version Tools

Cadence®

4.4.3

2.1.p2

4.1-s051

2.5

3.4B

2.3

Opus™ - Schematic and Layout

NC Verilog™ - Verilog Simulator

Pearl™ - Static Path

Verilog-XL™ - Verilog Simulator

Logic Design Planner™ - Floorplanner

BuildGates™ - Synthesis (Ambit)

Mentor/Model Tech™5.2e

B2 and Later Modelsim Ver ilog and VHDL (VITAL) Simulator

QuickVHDL™

Synopsys™

98.08, 98. 05

5.0.1A

VSS™ - VHDL Simulator

Design Compiler™ - Synthesis

Test Compiler™ - Scan Insertion and ATPG

Primetime™ - Static Path

VCS™ - Verilog Simulator

Exemplar™1998.2f Leonardo Spectrum™ - Synthesis

Syntest V2.2

V2.2

V1.6

TurboCheck - Gate

TurboScan

TurboFault

ATL25 Series

Gate Array/Embedded Array Design Flow

Fabricate

Personality

Tape Out

Personality Layers

Final Design

Review

DVS Assembly

and Test

Place and Route/

Clock Tree

Verification/

Resimulation

Define

Underlayer

Fabricate

Underlayer

Create

Underlayer

Tape Out

Underlayer

Scan/JTAG

Floorplan

Simulation/

Static Path

Synthesis/

Translation/

Conversion

Deliver

Design Kit

Kickoff

Meeting

Atmel

Joint

Database

Handoff

If Embedded Array

Customer

Database

Acceptance

If Embedded Array

ATL25 Series

Pin Definition Requirements

The corner pads are reserved for Power and Ground only.

All other pads are fully programmable as Input, Output,

Bidirectional, Power or Ground. When implementing a

design with 5 V com pliant buffers, one bu ffer sit e must be

reserv ed for the VD D5 pin, which is used to distr ibute 5V

power to the compliant buffers.

Gate Array

Embedded Array

Design Options

Logic Synthesis

Atmel can accept netlists in VHDL (MIL-STD-454, IEEE

STD 1076) or Verilog-HDL™ format. Atmel fully s upports

Synopsys for VHDL™ simulation as well as synthesis.

VHDL or V erilog-HDL is A tmel’s preferred database format

for ASIC design.

ASIC Design Translat ion

Atmel has successfully translated existing designs from

most major ASIC vendors (LSI Logic®, Motorola™,

SMOS™, Oki®, N EC ®, Fujitsu®, AMI® and others) into Atmel

ASICs. These designs have been optimized for speed and

gate co unt and modi fied to add lo gic or memo ry, or repli-

cated as a pin-for-pin compatible, drop-in replacement.

FPGA and PLD Conversions

Atmel has successfully translated existing FPGA/PLD

designs from most major vendors (Xilinx®, Ac tel®, Altera®,

AMD® and Atmel) into Atmel ASICs. There are four pri-

mary reasons to convert from an FPGA/PLD to an ASIC.

Conversion of high volume devices for a single or com-

bined design is cost effective. Performance can often be

optimi zed for speed o r low powe r consum ption. Several

FPGA/PLDs can be combined onto a single chip to mini-

mize cost while reducing on-board space requirements.

Finally, in situations where an FPGA/PLD was used for

fast cycle time prototyping, an ASIC may provide a lower

cost answer for long-term volume production.

ATL25 Series

Macro Cores

AVR (8-bit RISC) Microcontroller

The A VR RISC micr ocontro ller is a tru e 8-bit RIS C archi-

tecture, ideally suited for embedded control applications.

The AVR is offered as a gate level, soft macro in the ATL25

family.

The AVR supp orts a powerful set of 120 ins tructions. The

AVR pre-fe tch es an ins truc tion du ring pr ior ins truc tion ex e-

cution, enabling the execution of one ins truction per clock

cycle.

The Fast A ccess RISC register file consists of 3 2 general

purpose working registers. These 32 registers eliminate the

data transfer delay in the traditional program code intensive

accumulator architectures.

The AVR can i ncorporate up to 8K x 8 program memory

(ROM) and 64K x 8 data memory (SRAM). Also included

are several optional peripherals: UART, 8-bit timer/counter,

16-bit timer /counter, external and internal i nterrupts and

programmable watchdog timer.

AVR (8-bit RISC) ASIC Core

ARM7TDMI Embedded Microcontroller Core

The ARM7TD MI is a powerful 32-bit proces sor offered as

an embedded core in the ATL25 series arrays.

The ARM7TDMI is a member of the Advanced RISC

Machines (ARM) family of general purpose 32-bit micropro-

cessor s, which offer high performance for very low power

consumption.

The ARM architectu r e is bas ed on Red uc ed Inst ruc ti on Se t

Comp u ter ( RI SC ) pri n ci pl es . Th e in st ru ction s et a nd re la t ed

decode mechanism are much simpler than those of micro-

programm ed Complex Instruction Set Computers. This

simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and

cost -e f fe c ti ve ch ip.

Pipelining is employed so that all parts of the processing

and memory systems can operate continuously. Typically,

while on e instruction is be ing executed, its successor is

being decoded, and a third instruction is being fetched from

memory.

The ARM memory interface has been designed to allow the

performance potential to be realized without incurring high

costs in the memory system. Speed critical control signals

are pip elined to all ow syste m con trol f unctio ns to be imple-

mented in standard low-power logic, and these control

signals facilitate the exploitation of the fast local access

modes offered by industry standard SRAMs.

8-bit Data Bus

16-bit

ATL25 Series

The ARM7TDMI core i nclud es se veral o ptio nal peri pheral

macros. The options offered are Real-time Clock, DMA Con tr oller , US ART, E xt ernal Bus Int erfac e, Int er rupt, T imer

and Advanced Power Management and Controller.

ARM7TDMI Embedded Microcontroller Core

LodeDSPCore™

The Lo de DSPCor e will be offered in the ATL25 se ries o f

arrays as an embedded core. Lode is an advanced, 16-bit

Digita l Sign al P rocesso r (DSP ) cor e desi gned for o ptimal

perform ance in di gi tal c ell ular , s pe ech a nd voi c e c om mun i-

cations applications.

The Lode core architecture efficiently performs the base-

band functions-speech compression, forward error

correction, and modem functions-required by digital cellular

standards.

Lode i s the fi rst genera l-purpo se D SP that pr ovides tw o

multiplier-accumulators (MACs) that reduce power con-

sumption by effectively cutting cycle times in half.

Lode’s sui te of user-fr iendl y develo pment tools are easy t o

learn, thus accelerating the time it takes to get your product

to market.

ATL25 Series

Note: All I/Os 2.5V Compliant

Absolute Maxim u m Ratings*

Operating Ambient

Temperature................................................... -55°C to +125°C*NOTICE: Stresses beyo nd thos e lis ted under “Absolute

Maximum Ratings” may cause permanent dam-

age t o the dev ice . This is a s tress ratin g only an d

functio nal oper a tion of the device at these or an y

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device rel iabilit y.

Storage Te mperature..................................... -65°C to +150°C

Maxim u m Inpu t Voltag e:

Inputs.......................................................................VDD + 0.5V

3.3V Tolerant/Compliant ........................................VDD3 + 0.5V

Maxim u m Op erating Voltage (VDD)................................... 2.7V

Maxim u m Op erating Voltage (VDD3).................................. 3.6V

2.5V DC Characteristics

Applicable over recommended operating temperature and voltage range unless otherwise noted.

Symbol Parameter Buffer Test Condition Min Typ Max Units

TAOperating Temperature All -55 125 °C

VDD Supply Voltage All 2.3 2.5 2.7 V

IIH High-lev el Inpu t Current CMOS VIN = VDD, VDD = VDD (max) 10 µA

IIL Low-level Input Current CMOS VIN = VSS, VDD = VDD (max)

Pull-up = 620KΩ-10 µA

IOZ High-impedance State

Output Current All VIN = VDD or VSS,

VDD = VDD (max)

No pull-up or pull-down -10 10 µA

IOS Output Short-circ uit

Current PO11 VOUT = VDD, VDD = VDD (max) 14 mA

PO11 VOUT = VSS, VDD = VDD (max) -9

VIH High-lev el Inpu t Voltag e CMOS 0.7VDD V

CMOS Schmitt 0.7VDD 1.3

VIL Low-level Input Voltage CMOS 0.3VDD V

CMOS Schmitt 1.1 0.3VDD

VHYS Hysteresis CMOS +-Schmitt 0.4 V

VOH High-level Output Voltage PO11 IOH = TBD, VDD = VDD (max) 0.7VDD V

3.3V Tolerant IOH = TBD 0.7VDD

VOL Low-level Output Voltage PO11 IOL = TBD, VDD = VDD (max) 0.4 V

ATL25 Series

Note: All I/Os 3.3V Tolerant/Compliant

3.3 Vol t DC Characteristics

Applicable over recommended operating temperature and voltage range unless otherwise noted.

Symbol P aramete r Buffer Test Condition Min Typ M ax Units

TAOperating

Temperature All -55 125 °C

VDD Supply Voltage All Except 3.3V

Compliant I/O 2.3 2.5 2.7 V

VDD3 Supply Voltage 3.3V Compliant I/O 3.0 3.3 3.6 V

IIH High-level Input

Current CMOS VIN = VDD,

VDD = VDD (max) 10 µA

IIL Low -l evel Inpu t

Current CMOS VIN = VSS,

VDD = VDD (max)

Pull-up = 620KΩ-10 µA

IOZ

High-impedance

State Output

Current All VIN = VDD or VSS,

VDD = VDD (max)

No pull-up -10 10 µA

IOS Output Short-circuit

Current

2 ma Buffer VOUT = VDD,

VDD = VDD (max) 14 mA

2 ma Buffer VOUT = VSS,

VDD = VDD (max) -9

VIH High-level Input

Voltage

CMOS, LVTTL 2.0

PCI 0.475VDD3

CMOS/TTL-level

Schmitt 2.0 1.7

VIL Low -l evel Inpu t

Voltage

CMOS 0.8

PCI 0.325VDD3

CMOS/TTL-level

Schmitt 1.1 0.8

VHYS Hysteresis TTL-level Schmitt 0.6 V

VOH High-level Output

Voltage PO11 IOH = 2 mA,

VDD3 = VDD (min) 0.7VDD3 V

PCI IOH = 500 µA 0.9VDD3

VOL Low-level Output

Voltage PO11 IOL = 2 mA ,

VDD3 = VDD (min) 0.4 V

PCI IOL = 1.5 mA 0.1VDD

ATL25 Series

Testability Techniques

For complex designs, involving blocks of memory and/or

cores, careful attention must be given to design-for-test

techniques. The sheer size of complex designs and the

number o f fun ction al v ec tors tha t wou ld need to b e c reate d

to exercise them fully, strongly suggests the use of more

efficient techniques. Combinations of SCAN paths, multi-

plexed access to memory and/or core blocks, and built-in-

self-test logic must be employed, in addition to functional

test patte rns, to pr ovid e both the us er and Atm el the abil ity

to test the finished product.

An example of a highly complex design could include a PLL

for clock management or synthesis, a microcont roller or

DSP engine or both, S RAM to support the micr ocontroller

or DSP engine, and glue logic to suppor t the interconnec-

tivity of each of these blocks. The design of each of thes e

blocks must take into co nsidera tion the fact tha t the manu-

factured devi ce wil l be te sted on a h igh per fo rmanc e d igi tal

tester. Combinations of parametric, functional, and struc-

tural tests , defined for digita l testers, shoul d be employe d

to create a suite of manufacturing tests.

The type of block dictates the type of testability technique

to be em ployed. The PLL will, by construction, provide

access to key nodes so that functional and/or parametric

testing can be performed. Since a digital tester must control

all the clo cks during the tes ting of a Gate Arr ay/Embedde d

Array, provision must be made for the VCO to be

bypassed. Atmel’s PLLs include a multiplexing capability

for just this purpose. The addition of a few pins will allo w

other portions of the PLL to be isolated for test, without

impinging upon the normal functionality.

In a similar vein, access to microcontroller, DSP and SRAM

blocks must be provided so that controllability and observ-

ability of the inputs and outputs to the blocks are achieved

with the minimum amount of preconditioning. The AVR and

ARM microcontrollers supp ort SCAN testing, as do the

three main execution units of the Oak DSP. SRAM and

CAM blocks need to provide access to both address and

data ports so that comprehensive memory tests can be

performed. Multiplexing I/O pins provides a method for pro-

viding this acces s ibili ty .

The glue logic can be designed using full SCAN techniques

to enhance its tes tab il ity .

It should be noted that , in almost all of these cases, the

purpose of the testability technique is to provide Atmel a

means to assess the structural integrity of a Gate

Array/Embedded Array, i.e., sort devices with manufactur-

ing-i nduced defects. All of the tech niques describe d above

should be considered supplemental to a set of patterns

which exercise the functionality of the design in its antici-

pated operating modes.

I/O Buffer DC Characteristics

Symbol Parameter Test Condition Typical Units

CIN Capacitance, Input Buffer (die) 3.3V 2.4 pF

COUT Capacitance, Output Buffer (die) 3.3V 5.6 pF

CI/O Capacitance, Bidirectional 3.3V 6.6 pF

ATL25 Series

Advanced Packaging

The ATL25 Seri es gate ar rays ar e offer ed in a w ide va riety

of standard packages, including plastic and ceramic quad

flatpacks, thin quad flatpacks, ceramic pin grid arrays, and

ball grid arrays. High volume onshore and offshore contrac-

tors provide assembly and test for commercial product,

with prototype capability in Colorado Springs. Custom

package des igns are also availabl e as required to meet a

customer’s specific needs, and are supported through

Atmel’s pac kag e desi gn c ente r. Whe n a stan dard pac kage

cannot meet a customer’s need, a package can be

designe d to prec isely fit the applic ation and to ma intain the

performanc e obtained i n silicon . Atmel has delivered cus-

tom-designed packages in a wide variety of configurations.

Note: 1. Partial list

Packaging Options

Package Type Pin Count

PQFP 44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304

Power Quad 144, 160, 208, 240, 304

L/TQFP 32, 44, 48, 64, 80, 100, 120, 128, 144, 160, 176, 216

PLCC 20, 28, 32, 44, 52, 68, 84

CPGA 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391

CQFP 64, 68, 84, 100, 120, 132, 144, 160, 224, 340

PBGA 121, 169, 208, 217, 225, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 456

Super BGA 168, 204, 240, 256, 304, 352, 432, 560, 600

Low-profile Mini BGA 132, 144, 160, 180, 208

Chip-scale BGA(1) 40, 49, 56, 64, 81, 84, 96, 100, 128

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ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or s pecifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

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not authorized for use as critical components in life support devices or systems.

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1414B–10/99/xM

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