1. Product profile
1.1 General description
200 W LDMOS avionics power transistor for transmitter applications at frequencies from
1030 MHz to 1090 MHz.
1.2 Features and benefits
Typical pulsed class-AB performance at a frequencies from 1030 MHz to 1090 MHz,
a supply voltage of 36 V and an IDq of 150 mA:
Load power ≥200 W
Gain ≥13 dB
Efficiency ≥45 %
Rise time ≤50 ns
Fall time ≤50 ns
High power gain
Easy power control
Excellent ruggedness
Source on mounting flange eliminates DC isolato rs, reducing common mode
inductance
Compliant to Directive 2002/95/EC, rega rd in g Re str ictio n of Haza rd ous Sub s tances
(RoHS)
BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
Rev. 01 — 23 February 2010 Product data sheet
Table 1. Typical performance
RF performance at Th = 25
°
C in a common source class-AB test circuit; IDq = 150 mA;
typical values.
Mode of operation Conditions VDS
(V) PL
(W) Gp
(dB) ηD
(%) tr
(ns) tf
(ns)
Pulsed class-AB:
1030 MHz to 1090 MHz tp=50μs; δ= 2 % 36 200 15 50 35 6
tp= 128 μs; δ= 2 % 36 250 14 50 35 6
tp= 340 μs; δ= 1 % 36 250 14 50 35 6
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 2 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
1.3 Applications
Avionics transmitter app lications in the 1030 MHz to 1090 MHz frequency range.
2. Pinning information
[1] Connected to flange.
3. Ordering information
4. Limiting values
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
BLA1011-200R (SOT502A)
1drain
2gate
3source [1]
BLA1011S-200R (SOT502B)
1drain
2gate
3source [1]
3
2
11
3
2
sym03
9
3
2
11
3
2
sym03
9
Table 3. Ordering informati on
Type number Package
Name Description Version
BLA1011-2 00R - flanged LDMOST ceramic package; 2 mounting holes;
2 leads SOT502A
BLA1011S-200R - earless flanged LDMOST ceramic package; 2 leads SOT502B
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage - 75 V
VGS gate-source voltage - ±22 V
Ptot total power dissipation Th≤25 °C; tp=50μs; δ=2% - 700 W
Tstg storage temperature −65 +150 °C
Tjjunction temperature - 200 °C
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 3 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
5. Thermal characteristics
[1] Thermal resistance is determined under RF operating conditions; tp = 50 μs, δ = 10 %.
6. Characteristics
7. Application information
7.1 Ruggedness in class-AB operation
The BLA1011-200R and BLA1011S-200R are capable of withstanding a load mismatch
corresponding to VSWR = 5 : 1 through all phases under the following conditions:
VDS = 36 V; f = 1030 MHz to 1090 MHz at rated load power.
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Zth(j-h) transient thermal impedance from junction to
heatsink Th = 25 °C[1] 0.15 K/W
Table 6. Characteristics
Tj = 25
°
C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source breakdown voltage VGS =0V; I
D=3mA 75--V
VGS(th) gate-source threshold voltage VDS = 10 V; ID=300mA 4 - 5 V
IDSS drain leakage current VGS =0V; V
DS =36V - - 1 μA
IDSX drain cut-off current VGS =V
GS(th) +9 V;
VDS =10V 45--A
IGSS gate leakage current VGS =±20 V; VDS =0V - - 1 μA
gfs forward transconductance VDS =10V; I
D=10A - 9 - S
RDS(on) drain-source on-state resistance VGS =9V; I
D=10A - 60 - mΩ
Table 7. Application information
RF performance in a common source pulsed class-AB circuit; (tp=50
μ
s;
δ
= 2 %); f = 1030 MHz
and 1090 MHz; Th = 25
°
C; Zth(mb-h) = 0.15 K/W; IDq = 150 mA; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source volt ag e - 36 - V
PLoutput po w er tp=50μs; δ=2% - 200 W
Gppower gain PL=200W 13 - dB
ηDdrain efficiency tp=50μs; δ=2% 45 - %
trrise time - - 50 ns
tffall time - - 50 ns
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 4 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
VDS = 36 V; IDq = 150 mA; f = 1060 MHz; tp=50μs;
δ=2% VDS = 36 V; IDq = 150 mA; f = 1060 MHz; tp=50μs;
δ=2%
Fig 1. Power gain and drain efficiency as functions
of load power; typical values Fig 2. Load power as a function of drive power;
typical values
VDS = 36 V; f = 1060 MHz; tp=50μs; δ=2% V
DS = 36 V; IDq = 150 mA; Pi = 5.5 W; f = 1060 MHz;
tp=50μs; δ=2%
Fig 3. Power gain as a function of load po wer; typical
values Fig 4. Load power and power gain as functions of
gate-source voltage; typical values
0
20
G
p
(dB) G
p
η
D
(%)
η
D
10
15
5
0
80
40
60
20
0
50 250
P
L
(W)
mgw033
100 150 200 0
250
PL
(W)
150
200
50
100
0
PD (W)
mgw034
2468
0
20
G
p
(dB)
12
16
4
8
0
50
P
L
(W)
mgw035
100 150 200 250
I
Dq
= 1.5 A
150 mA
0
250
P
L
(W)
P
L
150
200
50
100
0
20
12
16
4
8
0
G
p
(dB)
G
p
1
V
GS
(V)
mgw036
234 5
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 5 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
VDS = 36 V; IDq = 150 mA; PL = 200 W; tp=50μs;
δ=2% VDS = 36 V; IDq = 150 mA; PL = 200 W; tp=50μs;
δ=2%
Fig 5. Power gain and drain efficiency a fun ctions of
frequency; typical values Fig 6. Input Impedance as a function of freq uency
(series components); typical values
VDS = 36 V; IDq = 150 mA; PL = 200 W; tp=50μs; δ=2%
Fig 7. L oad impedance as a function of frequency (series components); typical values
1020
20
Gp
(dB) Gp
ηD
(%)
ηD
10
15
5
0
80
40
60
20
0
1040 1100
f (MHz)
mgw037
1060 1080 1020
5
Zi
(W)
ri
xi
3
4
2
0
1
1040 1100
f (MHz)
mgw038
1060 1080
1020
4
ZL
(W)
RL
XL
0
2
−2
−4
1040 1100
f (MHz)
mgw039
1060 1080
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 6 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
8. Test information
Dimensions in mm.
The components are situated on one side of the copper-clad Duroid Printed-Circuit Board (PCB) with εr = 6.2 and thickness
0.64 mm.
The other side is unetched and serves as a ground plane.
See Table 8 for list of components.
Fig 8. Component layout for 1030 MHz to 1090 MHz test circuit
40 40
60
C2
C11
L1
R1
C1 C7
C9
C10
C8
C6
R2
C3
C4
C5
+
+
mgw032
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 7 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
[1] American Technical Ceramics type 100A or capacitor of same quality.
[2] American Technical Ceramics type 100B or capacitor of same quality.
[3] American Technical Ceramics type 700 or capacitor of same quality.
Table 8. List of compo ne nts (see Figure 8)
Component Description Value Dimensions
C1 multilayer ceramic chip capacitor [1] 39 pF
C2 multilayer ceramic chip capacitor [2] 4.3 pF
C3 multilayer ceramic chip capacitor [1] 11 pF
C4, C7 multilayer ceramic chip capacitor [1] 62 pF
C5 multilayer ceramic chip capacitor [1] 100 pF
C6 electrolytic capacitor 47 μF; 20 V
C8 multilayer ceramic chip capacitor [2] 20 pF
C9 multilayer ceramic chip capacitor [1] 47 pF
C10 multilayer ceramic chip capacitor [3] 1.2 nF
C11 electrolytic capacitor 47 μF; 63 V
L1 Ω-shaped enamelled 1 mm copper wire length = 38 mm
R1 metal film resistor 301 Ω
R2 SMD 0508 resistor 18 Ω
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 8 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
9. Package outline
Fig 9. Package outline SOT502A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT502A 99-12-28
03-01-10
0 5 10 mm
scale
Flanged LDMOST ceramic package; 2 mounting holes; 2 leads SOT502
A
p
L
A
F
b
D
U2
H
Q
c
1
3
2
D1
E
A
C
q
U1
C
B
E1
M M
w2
UNIT A
mm
Db
12.83
12.57
0.15
0.08
20.02
19.61
9.53
9.25
19.94
18.92
9.91
9.65
4.72
3.43
cU2
0.25 0.5127.94
qw
2
w1
F
1.14
0.89
U1
34.16
33.91
L
5.33
4.32
p
3.38
3.12
Q
1.70
1.45
EE
1
9.50
9.30
inches 0.505
0.495
0.006
0.003
0.788
0.772
D1
19.96
19.66
0.786
0.774
0.375
0.364
0.785
0.745
0.390
0.380
0.186
0.135 0.01 0.021.100
0.045
0.035
1.345
1.335
0.210
0.170
0.133
0.123
0.067
0.057
0.374
0.366
H
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
w1AB
M M M
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 9 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
Fig 10. Package outline SOT502B
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT502B 03-01-10
07-05-09
0 5 10 mm
scale
Earless flanged LDMOST ceramic package; 2 leads SOT502
B
A
F
b
D
U2
L
H
Q
c
1
3
2
D1
E
D
U1
D
E1
M M
w2
UNIT A
mm
Db
12.83
12.57
0.15
0.08
20.02
19.61
9.53
9.25
19.94
18.92
9.91
9.65
4.72
3.43
cU2
0.25
w2
F
1.14
0.89
U1
20.70
20.45
L
5.33
4.32
Q
1.70
1.45
EE
1
9.50
9.30
inches 0.505
0.495
0.006
0.003
0.788
0.772
D1
19.96
19.66
0.786
0.774
0.375
0.364
0.785
0.745
0.390
0.380
0.186
0.135 0.010
0.045
0.035
0.815
0.805
0.210
0.170
0.067
0.057
0.374
0.366
H
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 10 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
10. Abbreviations
11. Revision history
Table 9. Abbreviations
Acronym Description
IDq quiescent drain current
LDMOS Laterally Diffused Metal-Oxide Semiconductor
LDMOST Laterally Diffused Metal-Oxide Semiconductor Transistor
RF Radio Frequency
SMD Surface Mount Device
VSWR Voltage Standing-Wave Ratio
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BLA1011-200R_1011S-200R_1 20100223 Product data sheet - -
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 11 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
12. Legal information
12.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict wit h the short data sheet, th e
full data sheet shall pre va il.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
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Notwithstanding any damages that customer might incur for any reason
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changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
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Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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NXP Semiconductors accepts no liability for inclusion and/or use of
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In the event that customer uses the product for design-in and use in
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(a) shall use the product without NXP Semiconductors’ warranty of the
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development .
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
BLA1011-200R_1011S-200R_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 23 February 2010 12 of 13
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive appl ications beyond NXP Semiconductors’
standard warrant y and NXP Semiconductors’ product specifications.
12.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BLA1011-200R; BLA1011S-200R
Avionics LDMOS transistors
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 February 2010
Document identifier: BLA1011-200R_1011S-200R_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14. Contents
1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 3
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Application information. . . . . . . . . . . . . . . . . . . 3
7.1 Ruggedness in class-AB operation . . . . . . . . . 3
8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 10
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Contact information. . . . . . . . . . . . . . . . . . . . . 12
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
