INTEGRATED CIRCUITS DATA SHEET 74LVC273 Octal D-type flip-flop with reset; positive-edge trigger Product specification Supersedes data of 2003 Oct 30 2004 Mar 12 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 FEATURES DESCRIPTION * Wide supply voltage range from 1.2 to 3.6 V The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. * Inputs accept voltages up to 5.5 V * CMOS low power consumption The 74LVC273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. * Direct interface with TTL levels * Output drive capability 50 transmission lines at 85 C * Complies with JEDEC standard no. 8-1A * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. * Specified from -40 to +85 C and -40 to +125 C. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH PARAMETER CONDITIONS TYPICAL UNIT propagation delay CP to Qn CL = 50 pF; VCC = 3.3 V 4.8 ns propagation delay MR to Qn CL = 50 pF; VCC = 3.3 V 4.8 ns fmax maximum clock frequency 230 MHz CI input capacitance 5.0 pF CPD power dissipation capacitance per flip-flop outputs disabled; notes 1 and 2 22 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The definition is VI = GND to VCC. 2004 Mar 12 2 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 FUNCTION TABLE See note 1. INPUT OUTPUT OPERATING MODES MR CP Dn Qn Reset (clear) L X X L Load `1' H h H Load `0' H l L Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition; = LOW-to-HIGH transition; X = don't care. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVC273D -40 to +125 C 20 SO20 plastic SOT163-1 74LVC273DB -40 to +125 C 20 SSOP20 plastic SOT339-1 74LVC273PW -40 to +125 C 20 TSSOP20 plastic SOT360-1 74LVC273BQ -40 to +125 C 20 DHVQFN20 plastic SOT764-1 PINNING PIN SYMBOL DESCRIPTION PIN SYMBOL DESCRIPTION 11 CP clock input (LOW-to-HIGH, edge-triggered) 1 MR master reset input (active LOW) 2 Q0 flip-flop output 12 Q4 flip-flop output 3 D0 data input 13 D4 data input D5 data input 4 D1 data input 14 5 Q1 flip-flop output 15 Q5 flip-flop output 6 Q2 flip-flop output 16 Q6 flip-flop output D6 data input data input 7 D2 data input 17 8 D3 data input 18 D7 9 Q3 flip-flop output 19 Q7 flip-flop output ground (0 V) 20 VCC supply voltage 10 2004 Mar 12 GND 3 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 handbook, halfpage MR VCC 1 20 handbook, halfpage MR 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 16 Q6 Q1 5 Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 273 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP GND(1) Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 MNA762 Top view 10 11 GND CP MNA975 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO20 and (T)SSOP20. Fig.2 Pin configuration DHVQFN20. handbook, halfpage CP 11 handbook, halfpage 3 4 7 8 13 14 17 18 MR CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 1 C1 R 2 5 D0 6 D1 9 D2 12 D3 15 16 D4 19 D5 MR D6 1 11 MNA763 D7 3 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MNA764 Fig.3 Logic symbol. 2004 Mar 12 Fig.4 Logic symbol (IEEE/IEC). 4 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage VI input voltage CONDITIONS MIN. MAX. UNIT maximum speed performance 2.7 3.6 V low-voltage applications 1.2 3.6 V 0 5.5 V VO output voltage 0 VCC V Tamb operating ambient temperature in free air -40 +125 C tr, tf input rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. -0.5 MAX. VCC supply voltage IIK input diode current VI < 0 - -50 mA VI input voltage note 1 -0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 - 50 mA VO output voltage note 1 -0.5 VCC + 0.5 V IO output source or sink current VO = 0 to VCC - 50 mA ICC, IGND VCC or GND current - 100 mA Tstg storage temperature -65 +150 C Ptot power dissipation per package - 500 mW Tamb = -40 to +125 C; note 2 +6.5 UNIT V Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO20 packages: above 70 C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K. 2004 Mar 12 5 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = -40 to +85 C; note 1 HIGH-level input voltage 1.2 VCC - - V 2.7 to 3.6 2.0 - - V VIL LOW-level input voltage 1.2 - - GND V 2.7 to 3.6 - - 0.8 V VOH HIGH-level output voltage IO = -100 A 2.7 to 3.6 VCC - 0.2 - - V IO = -12 mA 2.7 VCC - 0.5 - - V IO = -18 mA 3.0 VCC - 0.6 - - V IO = -24 mA 3.0 VCC - 0.8 - - V IO = 100 A 2.7 to 3.6 - - 0.2 V IO = 12 mA 2.7 - - 0.4 V IO = 24 mA 3.0 - - 0.55 V VIH VOL LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND 3.6 - 0.1 5 A ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - 0.1 10 A ICC additional quiescent VI =VCC - 0.6 V; supply current per IO = 0 input pin 2.7 to 3.6 - 5 500 A 2004 Mar 12 6 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = -40 to +125 C VIH VIL VOH VOL HIGH-level input voltage 1.2 VCC - - V 2.7 to 3.6 2.0 - - V LOW-level input voltage 1.2 - - GND V 2.7 to 3.6 - - 0.8 V HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = -100 A 2.7 to 3.6 VCC - 0.3 - - V IO = -12 mA 2.7 VCC - 0.65 - - V IO = -18 mA 3.0 VCC - 0.75 - - V IO = -24 mA 3.0 VCC - 1.0 - - V IO = 100 A 2.7 to 3.6 - - 0.3 V IO = 12 mA 2.7 - - 0.6 V IO = 24 mA 3.0 - - 0.8 V VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND 3.6 - - 20 A ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - - 40 A ICC additional quiescent VI =VCC - 0.6 V; supply current per IO = 0 input pin 2.7 to 3.6 - - 5000 A Note 1. Typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2004 Mar 12 7 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 AC CHARACTERISTICS GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 . TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = -40 to +85 C; note 1 tPHL/tPLH tPHL tW tW trem tsu th fmax tsk(0) 2004 Mar 12 propagation delay CP to Qn propagation delay MR to Qn see Fig.5 and Fig.8 see Fig.6 and Fig.8 clock pulse width HIGH or LOW see Fig.5 and Fig.8 master reset pulse width LOW removal time MR to CP set-up time Dn to CP hold time Dn to CP maximum clock frequency skew see Fig.6 and Fig.8 see Fig.6 and Fig.8 see Fig.7 and Fig.8 see Fig.7 and Fig.8 see Fig.5 and Fig.8 note 3 8 1.2 - 18 - 2.7 1.5 4.9 8.4 ns 3.0 to 3.6 1.5 4.8(2) 8.2 ns 1.2 - 18 - ns 2.7 1.5 5.2 8.9 ns 3.0 to 3.6 1.5 4.8(2) 8.7 ns 1.2 - - - ns 2.7 5.0 1.8 - ns 3.0 to 3.6 4.0 1.2(2) - ns 1.2 - - - ns 2.7 5.0 1.7 - ns 3.0 to 3.6 4.0 1.2(2) - ns 1.2 - - - ns 2.7 +3.0 -1.0 - ns 3.0 to 3.6 +2.0 -1.0(2) - ns 1.2 - - - ns 2.7 3.0 1.0 - ns 3.0 to 3.6 1.0 0.0(2) - ns 1.2 - - - ns 2.7 +3.0 -0.2 - ns 3.0 to 3.6 1.0 0.0(2) - ns 1.2 - - - MHz 2.7 150 - - MHz 3.0 to 3.6 150 230(2) - MHz 3.0 to 3.6 - - 1.0 ns ns Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = -40 to +125 C tPHL/tPLH tPHL tW tW trem tsu th fmax tsk(0) propagation delay CP to Qn propagation delay MR to Qn see Fig.5 and Fig.8 see Fig.6 and Fig.8 clock pulse width HIGH or LOW see Fig.5 and Fig.8 master reset pulse width LOW removal time MR to CP set-up time Dn to CP hold time Dn to CP maximum clock frequency skew see Fig.6 and Fig.8 see Fig.6 and Fig.8 see Fig.7 and Fig.8 see Fig.7 and Fig.8 see Fig.5 and Fig.8 note 3 1.2 - - - ns 2.7 1.5 - 10.5 ns 3.0 to 3.6 1.5 - 10.5 ns 1.2 - - - ns 2.7 1.5 - 11.5 ns 3.0 to 3.6 1.5 - 11.0 ns 1.2 - - - ns 2.7 5.0 - - ns 3.0 to 3.6 4.0 - - ns 1.2 - - - ns 2.7 5.0 - - ns 3.0 to 3.6 4.0 - - ns 1.2 - - - ns 2.7 3.0 - - ns 3.0 to 3.6 2.0 - - ns 1.2 - - - ns 2.7 3.0 - - ns 3.0 to 3.6 1.0 - - ns 1.2 - - - ns 2.7 3.0 - - ns 3.0 to 3.6 1.0 - - ns 1.2 - - - MHz 2.7 150 - - MHz 3.0 to 3.6 150 - - MHz 3.0 to 3.6 - - 1.5 ns Notes 1. All typical values are measured at Tamb = 25 C. 2. This typical value is measured at VCC = 3.3 V. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2004 Mar 12 9 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 AC WAVEFORMS 1/fmax handbook, full pagewidth VI CP input VM VM GND tW t PHL t PLH VOH VM Qn output VOL MNA765 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency. VI handbook, full pagewidth VM MR input GND tW t rem VI CP input VM GND t PLH VM Qn output MNA464 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. Fig.6 Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time. 2004 Mar 12 10 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 VI handbook, full pagewidth VM CP input GND t su t su th th VI VM Dn input GND VOH VM Qn output VOL MNA767 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.7 Data set-up and hold times for the data input (Dn). 2004 Mar 12 11 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 VEXT handbook, full pagewidth VCC VI PULSE GENERATOR RL VO D.U.T. CL RT RL MNA616 VCC VI CL RL (1) VEXT tPLH/tPHL tPZH/tPHZ tPZL/tPLZ open GND 2 x VCC 1.2 V VCC 50 pF 500 2.7 V 2.7 V 50 pF 500 open GND 2 x VCC 3.0 to 3.6 V 2.7 V 50 pF 500 open GND 2 x VCC Note 1. The circuit performs better when RL = 1000 . Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.8 Load circuitry for switching times. 2004 Mar 12 12 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 2004 Mar 12 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 13 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 2004 Mar 12 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 14 o Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 2004 Mar 12 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 15 o Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- 2004 Mar 12 16 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Mar 12 17 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA76 (c) Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/04/pp18 Date of release: 2004 Mar 12 Document order number: 9397 750 12969