Advance Product Brief April 2003 MRC2G13 Multirate CDR (MRC) Serializer/Deserializer Macro Features Designed for SONET/SDH OC-3, OC-12, and OC-48, and 1 Gigabit Ethernet (GbE) applications. Meets the SONET OC-3/12/48 jitter generation, tolerance, and transfer specifications. Selectable data rate: -- 155 Mbits/s. -- 622 Mbits/s. -- 1.25 Gbits/s. -- 2.488 Gbits/s. 155.52 MHz reference clock frequency for SONET and SDH and 125 MHz clock for GbE. Parallel I/O interface: -- 16 bit for OC-48. -- 4 bit for OC-12. -- 1 bit for OC-3. -- 20 bit for GbE. Programmable control and configuration interface to define the various device configurations. Automatic lock-to-reference in absence of receive data. CML high-speed interface I/O for use with backplane or cable media. Input tolerance of higher voltages for support of optical transceiver interfaces. Description The MRC2G13 is a high-speed serializer/deserializer (SerDes) macrocell. This macrocell includes a current mode logic (CML) high-speed serial interface and uses a proprietary CDR architecture. The specifications are targeted at devices that directly drive OC-3, OC-12, and OC-48 small form-factor pluggable (SFP) optical transceivers. The macrocell can also drive small form-factor (SFF) pin through-hole optical transceivers and one gigabit optical transceivers for Ethernet. Modular Macrocell Consists of the following five smaller blocks: -- PLL. -- Transmit channel block (Tx). -- Receive channel block (Rx). -- Reference clock block. -- Voltage reference block. Initial configuration is 16 channels of OC-3/12 of which four can run independently at OC-48. Other configurations are available upon request. A channel is defined as one receiver and one transmitter. Multiple output amplitude modes for reduced power consumption in chip-to-chip applications. Interfaces 1.2 V 5% power supply and 3.3 V 5% power supply for the receiver. High speed: current mode logic (CML) with ac and dc coupling, and LVDS compatibility. LVPECL compatibility requires some off-chip components. Parallel data: CMOS selectable between 16 bit for OC-48, 20 bit for 1GE, 4 bit for OC-12, and 1 bit for OC-3. Registers and control logic: a four-line serial interface, allowing each channel to be addressed individually with minimal routing. Applications SONET OC-3. SONET OC-12. SONET OC-48. SDH. IEEE (R) 802.3-2002 gigabit Ethernet. MRC2G13 Multirate CDR (MRC) Serializer/Deserializer Macro Reset Resets any macro or any Rx/Tx block within the device. Includes a power-on-reset circuit within the macros. This circuit is used solely to reset the SerDes blocks within a macro after a powerup event. (No external access to the output of this circuit is provided.) Advance Product Brief April 2003 Transmit Pre-Emphasis The transmit block output buffer can be programmed through the serial register interface to select between no pre-emphasis and one of four levels of preemphasis. Pre-emphasis boosts the high frequencies in the transmitted data to compensate for losses present in backplanes, therefore, extending the useful range of transmission. Independent Power Down Independent user-selectable power down of the following: -- PLL. -- CML buffers. -- Individual transmit blocks. -- Individual receive blocks. Reduced Amplitude Output The Tx block output buffer can be programmed through the serial interface to provide one of four different levels of output amplitude: 1.0 V, 0.85 V, 0.7 V, and 0.55 V. These amplitude modes meet most standard requirements and allow chip-to-chip applications and other less stringent applications to reduce the power consumption. Power Consumption 2.3 W for 16 channels of OC-12. 730 mW for 4 channels of OC-48. Phase-Locked Loop (PLL) PLL is based on an LC oscillator. PLL relock without reset: the PLL can relock without requiring a reset (e.g., after switching reference clocks). PLL lock indicator is provided. Receiver The receive block (Rx) transforms a high-speed serial bit stream into a stream of parallel words, and recovers a high-speed clock from the serial data. The receive block (Rx) further divides this clock down to provide a clock that has a frequency equal to the parallel word rate and that is phase-aligned to the word boundary. The CDR block that forms the core of the receiver is a proprietary design that results in significant power and area savings. The Rx block input buffers are 3.3 V tolerant to handle LVPECL inputs from SFF transceivers. Transmitter Each transmit (Tx) block serializes a parallel data word with a width of 16 bits, 20 bits, 4 bits, or 1 bit, depending on the control register setting. The Tx block transforms the parallel input word into a serial data stream by using a high-speed clock that is synthesized from the Tx reference clock by the PLL. 2 Agere Systems Inc. MRC2G13 Multirate CDR (MRC) Serializer/Deserializer Macro Advance Product Brief April 2003 Testability Digital Library Interface Allows testability within the ASIC. Test modes are not encoded, allowing mixing and matching of test modes. Self-synchronizing PRBS compatible with Agilent (R) and Anritsu (R) bit error rate test systems. Internal loopback for parallel and serial data for Rx/ Tx macro option. Independent transmit and receive built-in self-test. Standard digital library interface allowing digital blocks from the Agere library or custom blocks to be integrated into the device. Examples include PRBS, link state machine, 8b/10b encoder, byte aligner, and custom blocks. RATE_SEL[1:0] LOCK DETECTOR LPF_A/ CLOCK DIVIDER VC LP FREQUENCY DETECTOR REFCLK 16 DAT 2 VARIABLE 1:4, 10:16 MUX DATA RETIMING DATA XCLK LOCK DETECTOR LO DIN RCLK 2 SFP PHASE AND FREQUENCY DETECTOR LP LPF_A/ VC RATE DETECT CLOCK DIVIDER 16 2 VARIABLE 1:4, 10:16 DEMUX DATA RCLK DATA RETIMING BIAS REX RATE_SEL[1:0] Figure 1. TSRD212G5 Block Diagram Agere Systems Inc. 3 IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Agilent is a registered trademark of Agilent Technologies, Inc. Anritsu is a registered trademark of Anritsu Corporation. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. Copyright (c) 2003 Agere Systems Inc. All Rights Reserved April 2003 PB03-108SRDS