1
Features
•Single Voltage Operation
–5V Read
– 5V Reprogramming
•Fast Read Access Time - 55 ns
•Internal Program Control and Timer
•Sector Architecture
–One 16K Byte Boot Block with Programming Lockout
–Two 8K Byte Parameter Blocks
–Two Main Memory Blocks (32K, 64K Bytes)
•Fast Erase Cycle Time - 10 seconds
•Byte-by-byte Programming - 10 µs/Byte Typical
•Hardware Data Protection
•DATA Polling for End of Program Detection
•Low Power Dissipation
–50 mA A cti ve Current
–100 µA CMOS Standby Current
•Typical 10,000 Write Cycles
Description
The AT49F001(N)(T) is a 5-volt only in-system reprogrammable Flash Memory. Its 1
megabit of memory is organized as 131,072 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
55 ns wit h power d issipat ion of just 275 mW over the c ommerc ial t emperatur e range .
Rev. 1008C–08/99
1-megabit
(128K x 8)
5-volt Only
Flash Memory
AT49F001
AT49F001N
AT49F001T
AT49F001NT
Pin Configurations
Pin Name Function
A0 - A16 Addresses
CE Chip Enab le
OE Output Enable
WE Write Enable
RESET RESET
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
DIP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
* RESET
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PLCC Top View
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
RESET *
VCC
WE
NC
(continued)
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
VCC
* RESET
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
*Note: This pin is a DC on the AT49F001N(T).
AT49F001(N)(T)
2
When th e device i s dese lecte d, the CMO S standby curren t
is less than 100 µA. F or the AT49F001N(T) pin 1 for the
DIP and PLCC packages and pin 9 for the TSOP package
are don’t connect pins.
To allow for simple in-system reprogrammability, the
AT49F001(N)(T) does not require high input voltages for
programming. Five-volt-only commands determine the read
and programmi ng operation of the device. Readin g data
out of the device is similar to reading from an EPROM; it
has stan dard CE, OE, an d WE inputs to avoid bus co nten-
tion. Reprogramming the AT 49F001(N)(T) is performed by
erasing a block of data and then prog ramming on a by te-
by-byte basis. The byte programming time is a fast 50 µs.
The end of a program cycle can be optionally detected by
the DATA polling feature. Once the end of a byte program
cycle has been detected, a new access fo r a r ead or pro-
gram ca n begin. Th e typica l number of program and eras e
cycles is in excess of 10,000 cycles.
The device is erased by execu ting the erase command
sequence; the device internally controls the erase opera-
tions. Ther e are two 8K byte par ameter bl ock sect ions and
two main memory blocks.
The device has the capability to protect the data in the boot
block; this feature is enabled by a command sequence.
The 16K-byte boot block section includes a reprogramming
lock ou t fea t ure to pr ov ide data in tegr it y. Th e bo ot s ec tor is
design ed to contain us er secure co de, and when the fea-
ture is enabled, the boot sector is protected from being
reprogrammed.
In the AT49F001(N)(T), once the boot block programming
lockout feature is enabled, the contents of the boot block
are permanent and cannot be changed. In the
AT49F001( T), once the boot block programm ing lockout
feature is enabled, the contents of the boot block cannot be
changed with input voltage levels of 5.5 volts or less.
Block Diagram
CONTROL
LOGIC
Y DECODER
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
OE
WE
CE
RESET
ADDRESS
INPUTS
VCC
GND
AT49F001(N)T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
X DECODER
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
PROGRAM
DATA LATCHES
Y-GATING
INPUT/OUTPUT
BUFFERS
1FFFF
1C000
1BFFF
1A000
19FFF
18000
17FFF
10000
0FFFF
00000
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
AT49F001(N)
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
PROGRAM
DATA LATCHES
Y-GATING
INPUT/OUTPUT
BUFFERS
1FFFF
10000
0FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
AT49F001(N)(T)
3
Device Operation
READ: The AT49F001(N)(T) is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the
high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENC ES: When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table.
The command sequences are written by applying a low
pulse on th e WE or CE i nput with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocess or write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
RESET: A RESET input pin is provided to ease some sys-
tem appl icati ons. When RE SET is at a logic high level, the
device is in i ts sta nda rd operating mod e. A low l evel on th e
RESET input halts the prese nt device op eration and puts
the outputs of the device in a high impedence state. If the
RESET pin makes a high-to-low tr ansition during a pro-
gram or eras e o perati on, the operation may n ot b e s uc ess-
fully completed and the operation will have to be repeated
after a hig h level is ap pli ed to the RE SE T pi n. W hen a hig h
leve l is reasser ted on th e RES ET pin , the device r eturns t o
the read o r stan dby mo de, d epe ndi ng u pon t he s tate of th e
control input s. By apply ing a 12V ± 0.5V in put signa l t o the
RESET pin, the boot block array can be reprogrammed
even if the boot block lockout feature has been enabled
(see Boot Bl ock Pr ogrammi ng Loc kout Ov erride s ection ).
The RESET feature is not available for the AT49F001N(T).
ERASURE: Befor e a byte can b e reprogr amme d, the mai n
memory block or parameter block which contains the byte
must be erased . The erased state of th e memory bits is a
logical “1”. Th e entire device can be erased at on e time by
using a 6-byte software code. The software chip erase
code consists of 6-byte load commands to specific address
locations with a specific data pattern (please refer to the
Chip Erase Cycle Waveforms).
After th e so ftwar e c hi p e rase h as b een i niti ate d, the d evi c e
will internal ly time the erase opera tion so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot bl ock lockout feature has
been enabled, the data in the boot sector will not be
erased.
CHIP E RAS E: If the boot block lockout has been enabled,
the Chip Erase function will erase Parameter Block 1,
Parame ter Bloc k 2, M ain Me mory B lock 1, a nd Mai n Mem-
ory Block 2 but not the boot block. If the Boot Block Lockout
has not been enabled, the Chip Erase function will erase
the entire chip. After the full chip erase the device will
return ba ck to re ad mo de. A ny c omm and dur ing chip er ase
will be ignored.
SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into sectors that can be individually
erased. There are two 8K-byte parameter block sections
and two main memory blocks. The 8K-byte parameter
block sections can be independently erased and repro-
grammed. The two main memory sections are designed to
be used as alternative memory sectors. T hat is, whenever
one of the blocks h as bee n er as ed and repr og rammed, the
other bl ock should be erased and rep rogrammed be fore
the fir st bloc k i s ag ain e ra sed. T he Se ct or E ra se c om man d
is a six bus cycle operation. The sector address is latched
on the falling WE edge of the sixth cycle while the 30H data
input command is latched at the rising edge of WE. The
sector erase starts after the rising edge of WE of the sixth
cycle. The erase operation is internally controlled; it will
automatically time to completion.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte- by-byte basis . Please not e that a data “0” cannot be
progra mmed ba ck to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The devi ce wil l au toma tic al ly gen er ate th e re quir ed in ter na l
program pulses.
The program cycle ha s addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE , whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DA TA polling fe ature may als o be used to ind i-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: Th e dev ice
has one designated block that has a pr ogramming lockout
feature. This feature prev ents programm ing of data in th e
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the sys tem. En ablin g the l ockou t feature w ill al low the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boo t blo ck ’s u sag e as a wr i te protected reg io n is
optional to the user. The address range of the boot block is
00000 to 03FFF for the AT49F001(N) while the address
AT49F001(N)(T)
4
range of the boot block is 1C000 to 1FFFF for the
AT49F001(N)T.
Once the fe ature is en abled, the data in th e boot blo ck can
no longer be er ased or prog rammed wi th inpu t voltage lev-
els of 5.5V or less . Data in the ma in memo ry blo ck ca n still
be changed through the regular programming method. To
activ ate the lockout featu re, a series of si x program co m-
mands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the de vice is in the soft-
ware product i dentificati on mode (see Sof tware Produ ct
Identification Entry and Exit sections) a read from address
loca tion 0000 2H will show i f progr ammin g the boot bl ock is
locke d out fo r the AT49F00 1(N) and a rea d from a ddress
1C002H will show if programming the boot block is locked
out for the AT49F001(N)T. If the data on I/O0 is low, the
boot bloc k can be pro grammed; i f the data on I/O0 i s high,
the program lockout feature has been activated and the
block c annot be progra mmed. The softw are produ ct identi-
fication exit code should be used to return to standard
operation.
BOOT BLOCK PROGRAMMI NG LOCKOUT OVERRIDE:
The use r can overri de the boot blo ck progra mming lo ckout
by taking the RESET pin to 12 volts. By do ing this, pro-
tected boot block data can be altered through a chip erase,
sector erase or word programming. When the RESET pin is
brought back to TTL levels the boot block programming
lockou t featur e is agai n acti ve. Thi s feat ure is n ot ava ilabl e
on the AT49F001N(T).
PRODUCT IDE NTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. T he
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For d etails, see Ope rating Mo des (f or hardw are ope ratio n)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F001(N)(T) features DATA
polling to indicate the end of a program cycle. During a pro-
gram cycle an at tempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the
AT49F001(N)(T) provides another method for determining
the end of a program or erase cycle. During a program or
erase ope ratio n, s ucces siv e atte mpt s to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Ex amining the to ggle bit
may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49F001(N)(T) in the following ways: (a) VCC sense: if
VCC is below 3.8V (typical), the program function is inhib-
ited. (b) Program inhibit : holding any one of OE low, CE
high or WE high inhibits program cycles . (c) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
AT49F001(N)(T)
5
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex)
2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F001(N) and
1C000H to 1FFFFH for the AT49F001(N)T.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses
For the AT49F001(N):
SA = 00000 to 03FFF for BOOT BLOCK
Nothing will happen and the device goes back to the read mode in 100 ns
SA = 04000 to 05FFF for PARAMETER BLOCK 1
SA = 06000 to 07FFF for PARAMETER BLOCK 2
SA = 08000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 1
This command will erase - PB1, PB2 and MMB1
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2
For the AT49F001(N)T:
SA = 1C000 to 1FFFF for BOOT BLOCK
Nothing will happen and the device goes back to the read mode in 100 ns
SA = 1A000 to 1BFFF for PARAMETER BLOCK 1
SA = 18000 to 19FFF for PARAMETER BLOCK 2
SA = 10000 to 17FFF for MAIN MEMORY ARRAY BLOCK 1
This command will erase - PB1, PB2 and MMB1
SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 2
Absolute Maximum Ratings*
Command Definition (in Hex)(1)
Command
Sequence Bus
Cycles
1st Bus
Cycle 2nd Bus
Cycle 3rd Bus
Cycle 4th Bus
Cycle 5th Bus
Cycle 6th Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read 1 Addr DOUT
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA(4) 30
Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr DIN
Boot Block Lockout(2) 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit(3) 3 5555 AA 2AAA 55 5555 F0
Product ID Exit(3) 1 XXXX F0
Te mperature Under Bias................................ -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Vo ltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
AT49F001(N)(T)
6
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 05H - AT49F001(N), 04H - AT49F001(N)T
5. See detail s under Software Product Identification Entry/Exit.
6. This pin is not available on the AT49F001N(T).
Note: 1. In the erase mode, ICC is 90 mA.
DC and AC Operating Range
AT49F001(N)(T)-55 AT49F001(N)(T)-70 AT49F001(N)(T)-90 AT49F001(N)(T)-12
Operating
Temperature (Case) Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
Operating Modes
Mode CE OE WE RESET(6) Ai I/O
Read VIL VIL VIH VIH Ai DOUT
Program/Erase(2) VIL VIH VIL VIH Ai DIN
Standby/Write Inhibit VIH X(1) XV
IH X High Z
Program Inhibit X X VIH VIH
Program Inhibit X VIL XV
IH
Output Disable X VIH XV
IH High Z
Reset X X X VIL X High Z
Product Identification
Hardware VIL VIL VIH A1 - A16 = VIL, A9 = VH,(3) A0 = VIL Manufacturer Code (4)
A1 - A16 = VIL, A9 = VH,(3) A0 = VIH Devi ce Code(4)
Software(5) A0 = VIL, A1 - A16=VIL Manufacturer Code(4)
A0 = VIH, A1 - A16=VIL Device Code (4)
DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC Com. 100 µA
Ind. 300 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3mA
ICC(1) VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low V oltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
AT49F001(N)(T)
7
AC Read Waveforms (1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be del ayed up to tCE - tOE after the falling edge of CE witho ut impa ct on tCE or by tACC - tOE after an addres s chan ge
withou t impa ct on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveform and
Measurement Level
tR, tF < 5 ns
Output Load Test
Note: 1. This para me ter is characterized and is not 100% tested.
AC Read Characteristics
Symbol Parameter
AT49F001(N)(T)-50 AT49F001(N)(T)-70 AT49F001(N)(T)-90 AT49F001(N)(T)-12
UnitsMin Max Min Max Min Max Min Max
tACC Address to Output Delay 50 70 90 120 ns
tCE(1) CE to Output Delay 50 70 90 120 ns
tOE(2) OE to Output Delay 0 30 0 35 0 40 0 50 ns
tDF(3)(4) CE or OE to Output Float 0 25 0 25 0 25 0 30 ns
tOH
Output Hold from OE, CE
or Address, which ever
occurred first 0000ns
ADDRESS
OUTPUT
HIGH Z
OUTPUT
OE
CE
tACC
tOE
tDF
tOH
tCE
VALID
ADDRESS VALID
5.0V
1.8K
100 pF
30 pF 1.3K
5.0V
1.8K
OUTPUT
PIN
1.3K
OUTPUT
PIN
55 ns 70/90/120 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 46pFV
IN = 0V
COUT 812pFV
OUT = 0V
AT49F001(N)(T)
8
AC Byte Load Waveforms
WE Controlled
CE Controlled
AC Byte Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address H old Time 50 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write P ulse Width (WE or CE)90ns
tDS Data Set-up Time 50 ns
tDH, tOEH Data, OE Hold Ti me 0ns
tWPH Write Pulse Width High 90 ns
t
DH
t
DS
t
AS
t
AH
t
WP
CE
ADDRESS
DATA IN
OE t
OES
t
OEH
WE t
CS
t
CH
t
WPH
tDH
tDS
tAS tAH
tWP
WE
ADDRESS
DATA IN
OE tOES tOEH
CE tCS
tCH
tWPH
AT49F001(N)(T)
9
Program Cycle Waveforms
Sector or Chip Eras e Cycle Waveforms
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under command definitions.)
3. For chip e rase, the data should be 10H, and for s ector erase, the data should be 30H.
Program Cycle Ch aracteristics
Symbol Parameter Min Typ Max Units
tBP Byte Programmin g Time 10 50 µs
tAS Address Set-u p Time 0 ns
tAH Address H old Time 50 ns
tDS Data Set-up Time 50 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 90 ns
tWPH Write Pulse Width High 90 ns
tEC Erase Cycle Time 10 seconds
OE
PROGRAM CYCLE
INPUT
DATA
ADDRESS
A0
55
5555 5555
AA
2AAA
t
BP
t
WPH
t
WP
CE
WE
A0-A16
DATA
t
AS
tAH tDH
tDS
OE
(1)
AA
80 Note 3
55 55
5555 5555 Note 2
AA
BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5
2AAA 2AAA
t
WPH
t
WP
CE
WE
A0-A16
DATA
t
AS
t
AH
t
EC
t
DH
t
DS
5555
AT49F001(N)(T)
10
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteris tic s .
Data Polling Waveforms
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteris tic s .
To ggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
Data Polling Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Dela y(2) ns
tWR Write Reco very Time 0 ns
HIGH Z
An An An An An
WE
CE
OE
I/O7
A0-A16
t
OEH
t
OE
t
DH
t
WR
To ggle Bit Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Dela y(2) ns
tOEHP OE High Pulse 150 ns
tWR Write Reco very Time 0 ns
WE
CE
OE
I/O6
t
OEH
HIGH Z
t
DH
t
OE
t
WR
t
OEHP
AT49F001(N)(T)
11
Software Product
Identification Entry(1)
Software Product
Identification Exit(1)
Notes for software product identification
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A16 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufactu rer Code : 1FH
Device Code: 05H - AT49F001(N)
04H - AT49F001(N)T
Boot Block Lockout
Feature Enable Algorithm(1)
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE
(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
OR
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
PAUSE 1 second(2)
AT49F001(N)(T)
12
AT49F001 Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
55 50 0.1 AT49F001-55JC
AT49F001-55PC
AT49F001-55TC
AT49F001-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001-55JI
AT49F001-55PI
AT49F001-55TI
AT49F001-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70 50 0.1 AT49F001-70JC
AT49F001-70PC
AT49F001-70TC
AT49F001-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001-70JI
AT49F001-70PI
AT49F001-70TI
AT49F001-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
90 50 0.1 AT49F001-90JC
AT49F001-90PC
AT49F001-90TC
AT49F001-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001-90JI
AT49F001-90PI
AT49F001-90TI
AT49F001-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
120 50 0.1 AT49F001-12JC
AT49F001-12PC
AT49F001-12TC
AT49F001-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001-12JI
AT49F001-12PI
AT49F001-12TI
AT49F001-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J 32-lead, Plastic, J-leaded Chip Carrier Package (PLCC)
32P6 32-lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T 32-lead, Plastic Thin Small Outline Package (TSOP)
32V 32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)
AT49F001(N)(T)
13
AT49F001 N Ordering Inf ormatio n
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
55 50 0.1 AT49F001N-55JC
AT49F001N-55PC
AT49F001N-55TC
AT49F001N-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001N-55JI
AT49F001N-55PI
AT49F001N-55TI
AT49F001N-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70 50 0.1 AT49F001N-70JC
AT49F001N-70PC
AT49F001N-70TC
AT49F001N-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001N-70JI
AT49F001N-70PI
AT49F001N-70TI
AT49F001N-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
90 50 0.1 AT49F001N-90JC
AT49F001N-90PC
AT49F001N-90TC
AT49F001N-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001N-90JI
AT49F001N-90PI
AT49F001N-90TI
AT49F001N-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
120 50 0.1 AT49F001N-12JC
AT49F001N-12PC
AT49F001N-12TC
AT49F001N-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001N-12JI
AT49F001N-12PI
AT49F001N-12TI
AT49F001N-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J 32-lead, Plastic, J-leaded Chip Carrier Package (PLCC)
32P6 32-lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T 32-lead, Plastic Thin Small Outline Package (TSOP)
32V 32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)
AT49F001(N)(T)
14
AT49F001T Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
55 50 0.1 AT49F001T-55JC
AT49F001T-55PC
AT49F001T-55TC
AT49F001T-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001T-55JI
AT49F001T-55PI
AT49F001T-55TI
AT49F001T-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70 50 0.1 AT49F001T-70JC
AT49F001T-70PC
AT49F001T-70TC
AT49F001T-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001T-70JI
AT49F001T-70PI
AT49F001T-70TI
AT49F001T-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
90 50 0.1 AT49F001T-90JC
AT49F001T-90PC
AT49F001T-90TC
AT49F001T-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001T-90JI
AT49F001T-90PI
AT49F001T-90TI
AT49F001T-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
120 50 0.1 AT49F001T-12JC
AT49F001T-12PC
AT49F001T-12TC
AT49F001T-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001T-12JI
AT49F001T-12PI
AT49F001T-12TI
AT49F001T-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J 32-lead, Plastic, J-leaded Chip Carrier Package (PLCC)
32P6 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T 32-lead, Plastic Thin Small Outline Package (TSOP)
32V 32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)
AT49F001(N)(T)
15
AT49F001NT Ordering Inform ation
tACC
(ns) ICC (mA) Ordering Code Package Operation Range
55 50 0.1 AT49F001NT-55JC
AT49F001NT-55PC
AT49F001NT-55TC
AT49F001NT-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001NT-55JI
AT49F001NT-55PI
AT49F001NT-55TI
AT49F001NT-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70 50 0.1 AT49F001NT-70JC
AT49F001NT-70PC
AT49F001NT-70TC
AT49F001NT-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001NT-70JI
AT49F001NT-70PI
AT49F001NT-70TI
AT49F001NT-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
90 50 0.1 AT49F001NT-90JC
AT49F001NT-90PC
AT49F001NT-90TC
AT49F001NT-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001NT-90JI
AT49F001NT-90PI
AT49F001NT-90TI
AT49F001NT-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
120 50 0.1 AT49F001NT-12JC
AT49F001NT-12PC
AT49F001NT-12TC
AT49F001NT-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001NT-12JI
AT49F001NT-12PI
AT49F001NT-12TI
AT49F001NT-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T 32-Lead, Plastic Thin Small Outline Package (TSOP)
32V 32-Lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)
AT49F001(N)(T)
16
Packaging Informati on
.045(1.14) X 45˚ PIN NO. 1
IDENTIFY .025(.635) X 30˚ - 45˚
.012(.305)
.008(.203)
.021(.533)
.013(.330)
.530(13.5)
.490(12.4)
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.032(.813)
.026(.660)
.050(1.27) TYP
.553(14.0)
.547(13.9)
.595(15.1)
.585(14.9)
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
.022(.559) X 45˚ MAX (3X)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
1.67(42.4)
1.64(41.7) PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
.005(.127)
MIN
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0) 0
15 REF
.690(17.5)
.610(15.5)
.012(.305)
.008(.203)
.110(2.79)
.090(2.29)
.161(4.09)
.125(3.18)
SEATING
PLANE
.220(5.59)
MAX
1.500(38.10) REF
*Controlling dimension: millimeters
INDEX
MARK
18.5(.728)
18.3(.720) 20.2(.795)
19.8(.780)
0.25(.010)
0.15(.006)
0.50(.020)
BSC 7.50(.295)
REF
8.20(.323)
7.80(.307) 1.20(.047) MAX
0.15(.006)
0.05(.002)
0
5REF
0.70(.028)
0.50(.020)
0.20(.008)
0.10(.004)
*Controlling dimension: millimeters
INDEX
MARK
12.5(.492)
12.3(.484) 14.2(.559)
13.8(.543)
0.25(.010)
0.15(.006)
0.50(.020)
BSC 7.50(.295)
REF
8.10(.319)
7.90(.311) 1.20(.047) MAX
0.15(.006)
0.05(.002)
0
5REF
0.70(.028)
0.50(.020)
0.20(.008)
0.10(.004)
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STAND ARD MS -016 AE
32P6, 32-lead, 0.600" Wide,
Plastic Dual In-line Package (PDIP)
Dimensions in Inches and (Millimeters)
32T, 32-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
32V, 32-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 BA
© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-
erty of Atmel are grant ed by the Company in connection with the sale of A tmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
Atmel Headquarters Atmel Operations
Corporate Headquart ers
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441- 0311
FAX (408) 487-2600
Europe
Atmel U.K., Ltd.
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
TEL (44) 1276-686- 677
FAX (44) 1276-686-697
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721 -9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24 -8 Shinka wa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Atmel Rousset
Zone Indu strie lle
13106 Ro usset Cedex
France
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
Printed on recycled paper.
1008C–08/99/xM
Marks bearing ® and/or ™ are re giste red t radem arks a nd tr adem arks of Atm el Co rpora tion.
Terms and product names in this document may be trademarks of others.
