PIC24FJ128GB204 FAMILY PIC24FJ128GB204 Family Silicon Errata and Data Sheet Clarification The PIC24FJ128GB204 family devices that you have received conform functionally to the current Device Data Sheet (DS30005009C), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. 2. 3. 1. 4. The errata described in this document will be addressed in future revisions of the PIC24FJ128GB204 family silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (B3). 5. Data Sheet clarifications and corrections start on page 10, following the discussion of silicon issues. Note: The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: Using the appropriate interface, connect the device to the hardware debugger. Open an MPLAB IDE project. Configure the MPLAB IDE project for the appropriate device and hardware debugger. Based on the version of MPLAB IDE you are using, do one of the following: a) For MPLAB IDE 8, select Programmer > Reconnect. b) For MPLAB X IDE, select Window > Dashboard and click the Refresh Debug Tool Status icon ( ). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC24FJ128GB204 family silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number (1) Revision ID for Silicon Revision(2) Device ID B3 PIC24FJ128GB204 0x4C5B PIC24FJ128GB202 0x4C5A PIC24FJ64GB204 0x4C59 PIC24FJ64GB202 0x4C58 Note 1: 2: 0x04 The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory space. They are shown in hexadecimal in the format "DEVID DEVREV". Refer to the "PIC24FJXXXGA2/GB2 Families Flash Programming Specification" (DS30000510) for detailed information on Device and Revision IDs for your specific device. 2014-2017 Microchip Technology Inc. DS80000613E-page 1 PIC24FJ128GB204 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Issue Summary Affected Revisions(1) B3 UART Break Character Transmission 1. The Transmit Shift Register Empty (TRMT) bit is unreliable when there is back-to-back Break character transmission. X A/D Converter Band Gap Voltage Measurement 2. Incorrect Band Gap Reference (VBG/2) measurement with the A/D Converter at full speed. X Input Capture Synchronous Cascade mode 3. Even numbered timer does not reset on a source clock rollover in synchronous cascaded operation. X Output Compare 3, PWM mode 4, 5 and 6 4. In the scaled down timer source for the Output Compare module, the first PWM pulse may not appear on the OCx pin. X CTMU Edge Enable bit (EDGEN) 5. The Edge Enable bit (EDGEN) generates a glitch on the CTEDx input. X UART1 and UART2 SmartCard/ Interrupt 6. Early interrupt for the last byte in T = 1 mode. X UART1 and UART2 SmartCard/ Guard Time Counter 7. Guard Time Counter (GTC) is off by one count in T = 0 and T = 1 modes. X POR/BOR Reset 8. If the Brown-out Reset (BOR) is disabled, the part may fail to come out of the Reset state during the VDD power-down and the subsequent power-up condition. X POR/BOR Reset 9. When the BOR is disabled, the part may not start at the minimum VDD specification. X Output Compare Sync Mode 10. The Output Compare (OC) module does not get synchronized with the source timer in Sync mode when the source timer is running with an external clock. X Input Capture Sync Mode 11. The Input Capture (IC) module does not get synchronized with the source timer in Sync mode when the source timer is running with an external clock. X UART1 and UART2 SmartCard/ Receive 12. UART receive interrupt is asserted early. X UART1 and UART2 SmartCard/ Interrupt 13. Clearing a UxSCINT register status bit clears all status bits. X UART1 and UART2 SmartCard/ Waiting Time Counter 14. Waiting time is extended by 11 ETUs when WTCx > 10. X SPI Master Mode 15. Transmit watermark interrupt is not asserted in Master mode with more than one data packet in FIFO. X I2C Slave Mode 16. Bus data corruption with multiple slaves on bus. X I2C Slave Mode 17. With Slave in Receive mode, the Acknowledge Time Status bit (ACKTIM) has no effect if Address Hold Enable (AHEN) and Data Hold Enable (DHEN) are disabled (AHEN = 0 and DHEN = 0). X I2C Slave Mode 18. In 10-Bit Addressing mode with Address Hold Enable (AHEN = 1), the Acknowledge Time Status bit (ACKTIM) is not asserted only for the upper address byte (A9 and A8). X Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80000613E-page 2 2014-2017 Microchip Technology Inc. PIC24FJ128GB204 FAMILY TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Module Feature Item Number Affected Revisions(1) Issue Summary B3 I2C Address Hold 19. In Slave mode when AHEN = 1 (Address Hold Enabled), if ACKDT (Acknowledge Data bit) is set at the beginning of address reception, clock stretching will not happen after the 8th clock. X I2C Data Hold 20. In Slave mode when DHEN = 1 (Data Hold Enable), if ACKDT (Acknowledge Data bit) is set at the beginning of data reception, then a slave interrupt will not occur after the 8th clock. X I2C Slave Mode 21. In Slave mode with general call and address hold enabled, when the general call address is received, the slave interrupt is not asserted after the 8th clock. X Output Compare (OC) Cascade Mode 22. In Cascade mode with the Output Compare Data register (OCxR) and Secondary Data register (OCxRS) of the even OC module set to zero, then cascaded OC does not generate output. X SPI Slave Mode 23. In Slave mode, the RX watermark interrupt does not wake the device from Sleep, which causes loss of the first few receive bytes. X SPI Audio PCM/DSP 24. SPI module follows the Right Justified mode of transmission and reception in PCM/DSP mode. X SPI Slave Mode Audio 25. In Slave mode, the Most Significant bit (MSb) is missed in Left and Right Justified modes. X Note 1: Only those issues indicated in the last column apply to the current silicon revision. 2014-2017 Microchip Technology Inc. DS80000613E-page 3 PIC24FJ128GB204 FAMILY Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B3). 1. Module: UART The Transmit Shift Register Empty (TRMT) bit is unreliable when there is back-to-back Break character transmission. For back-to-back Break characters, the TRMT bit may not reflect the actual status. If user software is polling for this bit to be set, it may result in dummy bytes getting transmitted instead of Break characters. Work around Poll the UARTx Transmit Break bit, UTXBRK (UxSTA<11>), to be cleared instead of the TRMT bit (UxSTA<8>) to be set. The UTXBRK status bit will be cleared after a Break character transmission. Affected Silicon Revisions B3 X 2. Module: A/D Converter Incorrect VBG/2 voltage measurement of the A/D Converter at full speed. When the A/D Converter is converting at full speed (500 ksps for 10-bit and 200 ksps for 12-bit), the A/D Converter count may not match the VBG/2 voltage. Work around The A/D Converter clock should be lowered to below 100 ksps (in 12-bit mode) to read the correct value of the VBG/2 voltage. In 10-bit mode, the clock must be lowered to below 200 ksps. 3. Module: Input Capture The even numbered timer does not reset on a source clock rollover in Synchronous Cascaded mode operation. In the cascaded configuration, ICy:ICx (ICy represents the even numbered modules and ICx represents the odd numbered modules) form a single 32-bit module. In Synchronous Cascaded mode (IC32 = 1, ICTRIG = 0 and the SYNCSEL<4:0> bits are not equal to 0h), both timers, ICyTMR:ICxTMR, must reset on a Sync_trig input from the 32-bit source timers, but only the odd timer (ICxTMR) is getting reset on a Sync_trig input. Work around None. Affected Silicon Revisions B3 X 4. Module: Output Compare 3, 4, 5 and 6 The first PWM pulse may not appear on the OCx pin if the timer source of the Output Compare x module is scaled down. The first pulse on the OCx pin is missed in PWM mode when the timer source for the Output Compare x module is scaled down (1:8, 1:64 or 1:256) using the Timerx Input Clock Prescale Select bits, TCKPS<1:0> (TxCON<5:4>). Work around * Configure the prescaler for the source timer to 1:1 for Output Compare 3, 4, 5 and 6. * The Output Compare 1 or 2 module can be used. The scaled down timer (1:8, 1:64 or 1:256) can be used as a source for the Output Compare 1 and 2 modules. Affected Silicon Revisions B3 X Affected Silicon Revisions B3 X DS80000613E-page 4 2014-2017 Microchip Technology Inc. PIC24FJ128GB204 FAMILY 5. Module: CTMU 7. Module: UART1 and UART2 The Edge Enable bit, EDGEN (CTMUCON1<11>), generates a glitch on the CTEDx input. This issue applies to SmartCard/ISO7816 operation. Enabling the edges (EDGEN = 1) generates a glitch (edge): The Guard Time Counter (GTC) is off by one count in T = 0 and T = 1 modes. * If the CTMU External Edge Input (CTEDx) is set for a falling edge and the level on this pin is low; or * If CTEDx is set for a rising edge and the level on this pin is high. The GTC value stored in the UxGTC register is off by one count in both T = 0 and T = 1 modes. The actual guard time is, a +1 ETU more, than the value specified in the GTC<8:0> bit. Work around None. The guard time value to be programmed in the GTC<8:0> bits must be decremented by one count. Affected Silicon Revisions Affected Silicon Revisions Work around B3 B3 X X 6. Module: UART1 and UART2 This issue applies to SmartCard/ISO7816 operation. In T = 1 mode, for the last byte and when the LAST bit is set, an interrupt shall always be generated after 22 Elementary Time Units (ETUs), irrespective of the Guard Time Interrupt Enable bit, GTCIE (UxSCINT<0>), state. The interrupt is occurring before 22 ETUs. 8. Module: POR/BOR If Brown-out Reset (BOR) is disabled, the part may fail to come out of the Reset state during the VDD power-down and the subsequent power-up condition. When BOR is disabled, in extremely rare cases, the part remains in the Reset state during the VDD power-down (not till VSS), followed by the subsequent power-up condition. Work around Work around To use the Guard Time Counter (GTC) for T = 1 block guard time, the last byte in a message block must have the GTC value set to 11 ETUs and the GTCIE (UxSCINT<0>) bit set. The LAST bit (UxTXREG<15>) should not be set. There are three known work arounds for this issue: Affected Silicon Revisions B3 X * Always enable BOR by setting the Configuration Fuse bit, BOREN = 1 (CW3<12>). * Use an external voltage supervisor chip on the MCLR pin to hold the MCLR low when the power supply voltage is between 1.4V and 2.0V. Release MCLR after the VDD is in the operating range. * Make sure that VDD goes all the way to VSS before powering on. Affected Silicon Revisions B3 X 2014-2017 Microchip Technology Inc. DS80000613E-page 5 PIC24FJ128GB204 FAMILY 9. Module: POR/BOR When BOR is disabled, the part may not start at the minimum VDD specification. Work around There are two known work arounds for this issue: * Always enable BOR by setting the Configuration Fuse bit, BOREN (CW3<12>) = 1. * For initial start-up, make sure that the minimum VDD is more than 2.2V. Once the device is powered, it will operate down to the minimum VDD voltage specified in the data sheet specifications. This is a typical battery-operated application with a fully charged battery installed into the application. The part will continue to operate to the data sheet specifications. 11. Module: Input Capture The Input Capture x module does not get synchronized with the source timer in Sync mode when the source timer is running with an external clock. In Synchronous mode, the internal 16-bit counter, ICxTMR, is synchronized with TMRx. When the source clock (TMRx) to the ICx module is running on an external clock, TCS (TxCON<1>) = 1, the ICxTMR is not synchronized with TMRx. Work around None. Affected Silicon Revisions B3 X Affected Silicon Revisions B3 X 10. Module: Output Compare The Output Compare x module does not get synchronized with the source timer in Sync mode when the source timer is running with an external clock. In Synchronous mode, the internal 16-bit counter, OCxTMR, is synchronized with TMRx. When the source clock (TMRx) to the OCx module is running on an external clock, TCS (TxCON<1>) = 1, the OCxTMR is not synchronized with TMRx. Work around None. Affected Silicon Revisions B3 X 12. Module: UART1 and UART2 The UARTx Receive Interrupt Flag (UxRXIF) may be asserted early, before the entire incoming data byte is received. As a result, during SmartCard operations, the data byte read from the UARTx Receive Buffer will not be valid. Work around None. Affected Silicon Revisions B3 X 13. Module: UART1 and UART2 Clearing any one of the interrupt status bits in the UxSCINT register (i.e., GTCIF, WTCIF, TXRPTIF or RXRPTIF) may result in clearing of all of the status bits. The status of corresponding interrupt enable bits is not affected. Work around Before clearing any of the UxSCINT status bits, copy the contents of the register to memory. Affected Silicon Revisions B3 X DS80000613E-page 6 2014-2017 Microchip Technology Inc. PIC24FJ128GB204 FAMILY 14. Module: UART1 and UART2 16. Module: I2C When the value of the Waiting Time Counter (WTC) stored in UxWTC is greater than 10, the actual waiting time is extended by an additional 11 Elementary Time Units (ETUs). For example, when UxWTC = 11, the application will assert a waiting time of 22 ETUs. In applications with multiple I2C slaves, bus data can become corrupted when the data payload sent to an addressed slave device matches the bus address of another (unaddressed) slave device. Work around Keep track of the bus address and data phases in software. When Address Hold Enable is used (the AHEN bit is set), the application can assert a NACK for any of the received bytes (invalid addresses and data bytes for other slave devices) until a Stop bit is received. None. Affected Silicon Revisions B3 X Work around Affected Silicon Revisions B3 15. Module: SPI While operating in Master mode (MSTEN = 1), the Transmit Watermark interrupt is not asserted if there is more than one entry in the FIFO buffer. This means, for various modes, that the interrupt is not asserted for: * More than one byte to be transmitted in 8-bit mode; * More than one word to be transmitted in 16-bit mode; or * More than one double word to be transmitted in 32-bit mode. Work around None. Affected Silicon Revisions X 17. Module: I2C With Slave in Receive mode, the Acknowledge Time Status bit (ACKTIM) has no effect if Address Hold Enable (AHEN) and Data Hold Enable (DHEN) are disabled. The Acknowledge Time Status bit (ACKTIM) is asserted only if Address Hold Enable (AHEN) or Data Hold Enable (DHEN) is enabled. Work around Instead of polling for the ACKTIM bit to be asserted, poll for assertion of the Receive Buffer Full (RBF) flag. Affected Silicon Revisions B3 X B3 X 18. Module: I2C In 10-Bit Addressing mode with Address Hold Enable (AHEN = 1), the Acknowledge Time Status bit (ACKTIM) is not asserted only for the upper address byte (A9 and A8). The ACKTIM bit is asserted for the lower address byte (A7 to A0). Work around Instead of polling for the ACKTIM bit to be asserted, poll for assertion of the Receive Buffer Full (RBF) flag. Affected Silicon Revisions B3 X 2014-2017 Microchip Technology Inc. DS80000613E-page 7 PIC24FJ128GB204 FAMILY 19. Module: I2C In Slave mode when AHEN = 1 (Address Hold Enabled), if ACKDT (Acknowledge Data bit) is set at the beginning of address reception, clock stretching will not happen after the 8th clock. Work around In Slave mode, user software should clear the ACKDT (Acknowledge Data) bit on receiving the Start bit. Affected Silicon Revisions B3 X 22. Module: Output Compare (OC) When the OC module is used in Cascade mode with the Output Compare Data register (OCxR) and Secondary Data register (OCxRS) of the even OC module set to zero, then the cascaded OC does not generate output. In the cascaded configuration, OCy:OCx (OCy represents the even numbered modules and OCx represents the odd numbered modules) form a single 32-bit module. In such a configuration, if OCyR and OCyRS are set to zero, then the cascaded OCyTMR:OCxTMR registers do not compare with the cascaded OCyR:OCxR and OCyRS:OCxRS registers. Hence, cascaded OC does not generate any output. Work around 20. Module: I2C In Slave mode when DHEN = 1 (Data Hold Enabled), if the ACKDT (Acknowledge Data) bit is set at the beginning of data reception, then a slave interrupt will not occur after the 8th clock. None. Affected Silicon Revisions B3 X Work around In Slave mode, user software should clear the ACKDT (Acknowledge Data) bit on receiving the Start bit. Affected Silicon Revisions B3 X 21. Module: I2C In Slave mode with general call (GCEN = 1) and address hold (AHEN = 1) enabled, when the general call address (0x00) is received, a slave interrupt is not asserted after the 8th clock. 23. Module: SPI The RX watermark interrupt is not asserted for the first few bytes in Sleep mode when the SPI slave is configured for 8, 16 or 32-Bit Enhanced Buffer mode (MSTEN = 0, ENHBUF = 1). The interrupt does not get asserted for any value of the buffer mask (RXMSK<5:0>). For 8-bit mode, interrupt after 32; for 16-bit mode, interrupt after 16; for 32-bit mode, interrupt after 8. Work around Tie the SPI clock pin to the external interrupt in the slave device. This work around has a limitation on the SPI speed of 5 MHz. Affected Silicon Revisions Work around Mask the address bits. Upon address reception, verify if it is a device/general call address and ACK address accordingly. B3 X Affected Silicon Revisions B3 X DS80000613E-page 8 2014-2017 Microchip Technology Inc. PIC24FJ128GB204 FAMILY 24. Module: SPI 25. Module: SPI The SPI module, irrespective of master or slave configured for PCM/DSP mode, follows the Right Justified mode of transmission and reception. In Slave Left Justified or Right Justified modes, the Most Significant bit (MSb) of the data is missed. Work around None. None. Affected Silicon Revisions B3 Work around Affected Silicon Revisions B3 X X 2014-2017 Microchip Technology Inc. DS80000613E-page 9 PIC24FJ128GB204 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS30005009C): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 5. Module: 12-Bit A/D Converter with Threshold Detect In Figure 25-1, Note 1 has been updated to include AN9: Note 1: AN9 through AN12 are implemented on 44-pin devices only. 6. Module: 12-Bit A/D Converter with Threshold Detect 1. Module: Pin Diagrams AN9 has been removed from all 28-pin diagrams and tables. This analog channel is unimplemented in 28-pin devices. In Register 25-6, AN9 has been added to Note 2 to indicate that it is unimplemented in 28-pin devices. 7. Module: Memory Organization 2. Module: Timer2/3 and Timer4/5 At the beginning of the Timer2/3 and Timer4/5 section, the following bullet item: * Timer Operation during Idle and Sleep modes has been changed to: In Table 4-4, the CN0PDE (CNPD1<0>), CN1PDE (CNPD1<1>), CN0PUE (CNPU1<0>) and CN1PUE (CNPU1<1>) bits are unimplemented. 8. Module: Power-Saving Features * Timer Operation during Idle mode 2 3. Module: Inter-Integrated Circuit (I C) In Table 10-2, Note 2 has been removed because it does not apply. In Register 17-2, the following note has been added to the SDAHT bit description: Note 1: This bit must be set to `0' for 1 MHz operation. 4. Module: Inter-Integrated Circuit (I2C) Equation 17-1 has been updated. The changes are shown below in bold: EQUATION 17-1: I2CxBRG = Note 1: COMPUTING BAUD RATE RELOAD VALUE(1) (( F 1 SCL ) - Delay ) FCY -2 2 Based on FCY = FOSC/2; Doze mode and PLL are disabled. DS80000613E-page 10 2014-2017 Microchip Technology Inc. PIC24FJ128GB204 FAMILY 9. Module: I2C Figure 33-14 and Figure 33-16 are modified as shown in the figures below. FIGURE 33-14: I2C BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM11 IM21 SCLx IM10 IM26 IM25 IM20 SDAx In IM45 IM40 SDAx Out Note: Refer to Figure 33-2 for load conditions. FIGURE 33-16: I2C BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS11 IS21 SCLx IS10 IS20 IS26 IS25 SDAx In IS45 IS40 SDAx Out 10. Module: I2C In Register 17-3: I2CxSTAT, the S (I2CxSTAT<3>) and P (I2CxSTAT<4>) bits are read-only. 11. Module: RTCC 12. Module: Device Overview In Figure 1-1: PIC24FJ128GB204 Family General Block Diagram, the BGBUF1 and BGBUF2 pins are removed. 13. Module: SPI In Section 22.1, the following information is added: Section 16.3 changes to: "Enhanced Master Mode". If the RTCC is running from the external VBAT supply pin, the SOSC or LPRC clock source must be used. The external oscillator will not function in VBAT modes. Section 16.4 changes to: "Enhanced Slave Mode". 2014-2017 Microchip Technology Inc. DS80000613E-page 11 PIC24FJ128GB204 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (6/2014) Initial release of this document; issued for silicon revision B3. This version includes the following silicon issues 1 (UART), 2 (A/D Converter), 3 (Input Capture), 4 (Output Compare 3, 4, 5 and 6), 5 (CTMU), 6-7 (UART1 and UART2), 8-9 (POR/BOR), 10 (Output Compare) and 11 (Input Capture). Rev B Document (1/2015) Adds silicon issues 12 through 14 (UART1 and UART2), 15 (SPI) and 16 (I2C). Updates the title of existing silicon issues 6 and 7 as "UART1 and UART2", in accordance with standard documentation practice. The actual issues themselves, as they relate to the SmartCard/ISO7816 functionality of the UART, remain unchanged. Adds data sheet clarifications 1 (Triple Comparator) and 2 (Packaging). Rev C Document (6/2015) Adds silicon issues 17 (I2C) and 18 (I2C). Removes data sheet clarifications 1 (Triple Comparator) and 2 (Packaging). Adds new data sheet clarifications 1 (Pin Diagrams), 2 (Timer2/3 and Timer4/5), 3 (Inter-Integrated Circuit (I2C)), 4 (Inter-Integrated Circuit (I2C)), 5 (12-Bit A/D Converter with Threshold Detect), 6 (12-Bit A/D Converter with Threshold Detect) and 7 (Memory Organization). Rev D Document 7/2015 Adds new data sheet clarification 8 (Power-Saving Features). Rev E Document 2/2017 Adds silicon issues 19 (I2C), 20 (I2C), 21 (I2C), 22 (Output Compare (OC)), 23 (SPI), 24 (SPI) and 25 (SPI). Adds new data sheet clarifications 9 (I2C), 10 (I2C), 11 (RTCC), 12 (Device Overview) and 13 (SPI). DS80000613E-page 12 2014-2017 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2014-2017 Microchip Technology Inc. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2014-2017, Microchip Technology Incorporated, All Rights Reserved. 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