General Description
The MAX16997/MAX16998 are microprocessor (µP)
supervisory circuits for high-input-voltage and low-qui-
escent-current applications. These devices detect
downstream circuit failures and provide switchover to
redundant circuitry. See the
Selector Guide
for the dif-
ferent versions of this product family.
The MAX16997/MAX16998 family has four independent
inputs for reset and watchdog functions. SWT and SRT
inputs independently set the timeout periods of watch-
dog and reset timers through external capacitors.
RESETIN/EN monitor voltages at respective inputs. A
resistive voltage-divider sets the reset threshold.
The MAX16998A/B/D generate two output signals,
RESET and ENABLE. RESET asserts whenever
RESETIN drops below its threshold voltage or when the
watchdog timer detects a timing fault at WDI. Once
asserted, and after all reset conditions are removed,
RESET remains low for the reset timeout period, tRESET,
and then goes high. The MAX16997A generates one
output signal (ENABLE) based on the voltage level at
EN and the signal at WDI.
The MAX16997A does not have a RESET output. The
watchdog is disabled if the voltage at EN is below its
threshold. The MAX16997A watchdog timer starts tim-
ing when the voltage at EN becomes higher than the
preset threshold voltage level. Each time EN rises
above the preset threshold voltage, the initial watchdog
timeout period is 8 times the normal watchdog timeout
period (tWP).
The MAX16997/MAX16998 are available in 8-pin lead-
free µMAX®packages and are fully specified over the
-40°C to +125°C automotive temperature range.
Applications
Automotive
Industrial
Features
oWide 5V to 40V Input Voltage Range
o18µA Quiescent Current (Typical at +125°C)
oCapacitor-Adjustable Timeout Period for
Watchdog and Reset
oWindowed Watchdog Timer Options
(MAX16998B/D)
oExternal Voltage Monitoring (RESETIN for the
MAX16998A/B/D and EN for the MAX16997A)
oCar Battery-Compatible EN Input
oTTL- and CMOS-Compatible Open-Drain Outputs
o18V Maximum Open-Drain Reset Output Voltage
o28V Maximum Open-Drain Enable Output Voltage
oPower-On/Power-Off Reset Functionality
(MAX16998A/B/D Only)
oAEC-Q100 Qualified
o-40°C to +125°C Operating Temperature Range
oSmall (3mm x 3mm) µMAX Package
oWDI Narrow Pulse Immunity
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
________________________________________________________________
Maxim Integrated Products
1
PART TEMP RANGE PIN-PACKAGE
MAX16997AAUA+ -40°C to +125°C 8 µMAX
MAX16997AAUA/V+ -40°C to +125°C 8 µMAX
MAX16998AAUA+ -40°C to +125°C 8 µMAX
MAX16998AAUA/V+ -40°C to +125°C 8 µMAX
MAX16998BAUA+ -40°C to +125°C 8 µMAX
MAX16998BAUA/V+ -40°C to +125°C 8 µMAX
MAX16998DAUA+ -40°C to +125°C 8 µMAX
MAX16998DAUA/V+ -40°C to +125°C 8 µMAX
PART WATCHDOG
WINDOW SIZE (%) ENABLE RESET EN RESETIN
MAX16997A 100 ✓—✓—
MAX16998A 100 ✓✓ —✓
MAX16998B 50 ✓✓ —✓
MAX16998D 75 ✓✓ —✓
Selector Guide
Ordering Information
19-4000; Rev 2; 8/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V Denotes Automotive qualified part.
Pin Configurations appear at end of data sheet.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = 14V, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
(All pins referenced to GND, unless otherwise noted.)
IN, ENABLE ............................................................-0.3V to +45V
WDI, RESET, EN .....................................................-0.3V to +20V
RESETIN .................................................................-0.3V to +20V
SRT, SWT................................................................-0.3V to +12V
Maximum Current (all pins).................................................30mA
Continuous Power Dissipation (TA= +70°C)
8-Pin µMAX (derate 4.8mW/°C above +70°C) ..........387.8mW
Junction-to-Case Thermal Resistance (θJC) (Note 1) ......42°C/W
Junction-to-Ambient Thermal Resistance (θJA ) (Note 1).....206.3°C/W
Operating Temperature Range (TA) ..................-40°C to +125°C
Junction Temperature (TJ) ...............................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Voltage Range VIN 5.0 40.0 V
TA = -40°C to +85°C 18 30
Supply Current IIN TA = -40°C to +125°C 18 60 µA
SWT Ramp Current IRAMP_SWT VSWT = 1.0V 450 500 550 nA
SRT Ramp Current IRAMP_SRT VSRT = 1.0V 410 500 600 nA
SWT/SRT Ramp Threshold
Voltage VRAMP 1.115 1.235 1.363 V
RESET TIMER
VRESETIN rising 1.135 1.255 1.383
Power-On Reset Input Threshold
Voltage VPON VRESETIN falling 1.115 1.235 1.363 V
RESETIN Input Leakage Current ILPON VRESETIN = 2V 0.1 µA
RESET asserted, ISINK = 1mA 0.9
VIN = 1.1V, ISINK = 160µA, RESET asserted 0.4
RESET Output Low Voltage VOLRST
RESET asserted, ISINK = 0.4mA 0.4
V
RESET Leakage Current ILKGR VRESET = 20V, RESET not asserted 0.1 µA
ENABLE Output Low Voltage VOLEN ENABLE asserted, ISINK = 5mA 0.4 V
ENABLE Leakage Current ILKGE VENABLE = 14V, ENABLE not asserted 0.1 µA
Minimum Reset Timeout Period tRESETmin CSRT = 390pF (Note 3) 1 ms
Reset Timeout Period tRESET CSRT = 2000pF (Note 3) 5 ms
Maximum Reset Time Period tRESETmax CSRT = 47nF 116.09 ms
RESET to ENABLE Delay tREDL 1.5 µs
RESETIN to RESET Delay tRRDL RESETIN falling below VPON to RESET
falling edge 1µs
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
_______________________________________________________________________________________ 3
Note 2: RRESET and RENABLE are external pullup resistors for open-drain outputs. Connect RRESET and RENABLE to a minimum 2.5V
voltage. Connect RRESET to a maximum voltage of 18V and connect RENABLE to a maximum voltage of 28V.
Note 3: Calculated based on VRAMP = 1.235V and IRAMP = 500nA.
Note 4: WDI pulses narrower than 1µs will be ignored. WDI pulses wider than 6.5µs will be recognized.
Note 5: Not production tested, guaranteed by design.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
WATCHDOG TIMER
VIH 2.25
WDI Input Threshold VIL 0.9 V
WDI Input Hysteresis WDIHYST 200 mV
WDI Minimum Pulse Width tWDImin (Note 4) 6.5 µs
WDI Input Current IWDI WDI = 0 or 14V 0.1 µA
Minimum Watchdog Timeout tWPmin CSWT = 680pF (Note 3) 6.8 ms
Watchdog Timeout Period tWP CSWT = 1200pF (Note 3) 12 ms
Maximum Watchdog Timeout tWPmax CSWT = 22nF 217.36 ms
MAX16998B 45 50 55
Watchdog Window DWDI MAX16998D 67.5 75 82.5 %tWP
WDI to ENABLE Output Delay Start from WDI third wrong trigger 100 µs
RESET Pullup Resistor Supply
Voltage (Note 5) 2.25 2.5 18.00 V
ENABLE Pullup Resistor Supply
Voltage (Note 5) 2.25 2.5 28.00 V
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 14V, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
RESET TIMEOUT PERIOD
vs. CSRT
MAX16997/98 toc01
CSRT (nF)
RESET TIMEOUT PERIOD (ms)
100101
1
10
100
1000
10,000
0.1
0.1 1000
IRAMP = 500nA
WATCHDOG TIMEOUT PERIOD
vs. CSWT
MAX16997/98 toc02
CSWT (nF)
WATCHDOG TIMEOUT PERIOD (ms)
100101
10
100
1000
10,000
1
0.1 1000
IRAMP = 500nA
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX16997/98 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
403010 20
12
14
16
18
22
20
24
26
10
050
RESET AND ENABLE NOT
ASSERTED
Typical Operating Characteristics
(CSWT = CSRT = 1500pF, TA= +25°C, unless otherwise noted.)
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
4 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(CSWT = CSRT = 1500pF, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX16997/98 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
1109565 80-10 5 20 35 50-25
15.5
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
15.0
-40 125
RESET AND ENABLE NOT
ASSERTED
RESETIN/EN THRESHOLD VOLTAGE
vs. TEMPERATURE
MAX16997/98 toc05
TEMPERATURE (°C)
RESETIN/EN THRESHOLD VOLTAGE (V)
1109565 80-10 5 20 35 50-25
1.13
1.15
1.18
1.20
1.23
1.25
1.28
1.30
1.33
1.35
1.10
-40 125
RISING
FALLING
RESETIN/EN THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX16997/98 toc06
SUPPLY VOLTAGE (V)
RESETIN/EN THRESHOLD VOLTAGE (V)
363224 2812 16 208
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.00
440
RISING
FALLING
RESETIN TO RESET DELAY
vs. TEMPERATURE
MAX16997/98 toc07
TEMPERATURE (°C)
RESETIN TO RESET DELAY (µs)
11095-25 -10 535 50 6520 80
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0
-40 125
RESETIN FROM 2V TO 0V
100mV OVERDRIVE
50mV OVERDRIVE
RESETIN/WATCHDOG PERIOD
vs. SUPPLY VOLTAGE
MAX16997/98 toc08
SUPPLY VOLTAGE (V)
RESET/WATCHDOG TIMEOUT PERIOD (ms)
36328 12 16 2420 28
1
2
3
4
5
6
7
8
0
440
WATCHDOG TIMEOUT
PERIOD (CSWT = 680pF)
RESET TIMEOUT
PERIOD (CSRT = 680pF)
RESETIN/WATCHDOG PERIOD
vs. SUPPLY VOLTAGE
MAX16997/98 toc09
SUPPLY VOLTAGE (V)
RESET/WATCHDOG TIMEOUT PERIOD (ms)
363224 2812 16 208
20
30
40
50
60
70
80
90
100
110
10
440
WATCHDOG TIMEOUT
PERIOD (CSWT = 10nF)
RESET TIMEOUT
PERIOD (CSRT = 10nF)
IRAMP
vs. TEMPERATURE
MAX16997/98 toc10
TEMPERATURE (°C)
IRAMP (nA)
1109565 80-10 5 20 35 50-25
475
480
485
490
495
500
505
510
515
520
470
-40 125
RESET OUTPUT VOLTAGE
vs. SINK CURRENT
MAX16997/98 toc11
SINK CURRENT (mA)
RESET OUTPUT VOLTAGE (V)
2.52.01.51.00.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
03.0
ENABLE OUTPUT VOLTAGE
vs. SINK CURRENT
MAX16997/98 toc12
SINK CURRENT (mA)
ENABLE OUTPUT VOLTAGE (V)
25205 10 15
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
030
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
_______________________________________________________________________________________ 5
Pin Description
PIN
MAX16997A MAX16998A/B/D NAME FUNCTION
1 1 IN Power-Supply Input. Bypass IN to GND with a 0.1µF capacitor.
2—EN
High-Impedance Input to the Enable Comparator. Depending on the voltage level
at EN, the internal watchdog timer is turned on or off (see the EN Input section).
3, 7 — N.C. No Connection. Not internally connected.
44SWT
Watchdog Timeout Adjustment Input. Connect a capacitor between SWT and GND
to set the basic watchdog timeout period. Connect SWT to ground to disable the
watchdog timer function. See the Selecting the Watchdog Timeout Capacitor
section.
5 5 GND Ground
6 6 WDI
Watchdog Input.
MAX16997A/MAX16998A (Timeout Watchdog): Two consecutive WDI falling
edges must occur at WDI within the watchdog timeout period or RESET asserts.
The watchdog timer clears when a falling edge occurs on WDI or whenever RESET
is asserted. ENABLE asserts if three consecutive watchdog timeout periods have
expired without a falling edge at WDI. WDI is a high-impedance input. Leaving
WDI unconnected will cause improper operation of the watchdog timer.
MAX16998B/D (Window Watchdog): WDI falling transitions within periods shorter
than the closed window width or longer than the basic watchdog timeout period
force RESET to assert low for the reset timeout period. The watchdog timer begins
to count after RESET is deasserted. The watchdog timer clears when a WDI falling
edge occurs or whenever RESET is asserted. ENABLE asserts if three consecutive
watchdog timeout periods have expired without a falling edge at WDI. WDI is a
high-impedance input. Leaving WDI unconnected will cause improper operation of
the watchdog timer.
88ENABLE
Open-Drain Enable Output. ENABLE asserts when three consecutive WDI faults
occur. ENABLE remains low until three consecutive good WDI falling edges occur.
ENABLE does not assert if the voltage at RESETIN (EN) is below its threshold.
These devices are guaranteed to be in correct ENABLE output logic state when
VIN remains greater than 1.1V.
— 2 RESETIN
Reset Input. High-impedance input to the reset comparator. When VRESETIN falls
below 1.235V, RESET asserts. RESET remains asserted as long as VRESETIN is low
and for the reset timeout period after RESETIN goes high. Connect VRESETIN to the
center point of an external resistive divider to set the threshold for the externally
monitored voltage. Connect RESETIN to a defined voltage logic-level.
— 3 SRT
Reset Timeout Adjustment Input. Connect a capacitor between SRT and GND to
set the reset timeout period. See the Selecting the Reset Timeout Capacitor
section.
—7RESET
Open-Drain Reset Output. RESET asserts whenever RESETIN drops below the
selected reset threshold voltage (VPON). RESET remains low for the reset timeout
period after all reset conditions are removed, and then goes high. RESET asserts
for a period of tRESET whenever a WDI fault occurs. Connect RESET to a pullup
resistor connected to a voltage higher than 2.5V (typ).
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
6 _______________________________________________________________________________________
Functional Diagram
IN
RESETIN (MAX16998)
EN (MAX16997)
WDI
RESET
ENABLE
SWT
SRT
(MAX16998)
VBG
VBG
IRAMP
PREG
BUFFER
MAX16997A/
MAX16998A/B/D
LOGIC
GND
VBG
IRAMP
MAX16997/MAX16998
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
_______________________________________________________________________________________ 7
Timing Diagrams
VEN
VHYST
tWP INITIAL
tWP INITIAL = WATCHDOG TIMEOUT PERIOD x 8 tWP = WATCHDOG TIMEOUT PERIOD tWDI = WDI TRIGGER PERIOD
3 CONSECUTIVE tWP WITHOUT TRIGGER ENABLE GOES LOW 3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
tWP
tWD
tWP tWP
12312
3
tWP tWP
tWDI tWDI tWDI tWDI
VPON
WDI
ENABLE
Figure 1. MAX16997A Timing Diagram
VRESETIN
VHYST
tRESET = RESET TIMEOUT PERIOD tWP = WATCHDOG TIMEOUT PERIOD tWDI = WDI TRIGGER PERIOD
3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW 3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
1
1
2
2
3
3
tWP
tWDI tWP tWP tWP tWDI tWDI tWDI
tRESET
VPON
WDI
ENABLE
RESET
Figure 2. MAX16998A Timing Diagram
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
8 _______________________________________________________________________________________
Timing Diagrams (continued)
VRESETIN VHYST
PROPER WATCHDOG TRIGGER RESETS THE INTERNAL ENABLE COUNTER
tRESET = RESET TIMEOUT PERIOD tOW = T OPEN WINDOW tCW = T CLOSED WINDOW tWP = tCW + tOW tWDI = WDI TRIGGER PERIOD
3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW 3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
tWP
123
123
tWDI
tRESET tOW tCW tWP tWP tWP tWDI tWDI tWDI
VPON
WDI
ENABLE
RESET
Figure 3. MAX16998B/D Timing Diagram
VHYST
tOW
t = 0
tCW tWP
tRESET
tCW ≤ tWDI ≤ tWP
tCW ≤ tWDI ≤ tWP
tWP
ENABLE DOES NOT GET ASSERTED IF THE VOLTAGE
AT RESETIN IS BELOW ITS THRESHOLD.
THE WATCHDOG TIMER CLEARS
WHENEVER RESET IS ASSERTED.
tRRDL
tWDI
tWDI tWDI tWDI tWDI tWDI tWDI tWDI
VRESETIN
VPON
WDI
1.1V
VIN = ENABLE
RESET
tRESET tRESET
Figure 4. RESETIN,
RESET
, VIN,
ENABLE
, and WDI Voltage Monitoring
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
_______________________________________________________________________________________ 9
Detailed Description
The MAX16997/MAX16998 are µP supervisory circuits
for high-input-voltage and low-quiescent-current appli-
cations. These devices improve system reliability by
monitoring the sub-system for software code execution
errors. The MAX16997A/MAX16998A/B/D detect down-
stream circuit failures, and provide switchover to
redundant circuitry. These devices provide complete
adjustability for reset and watchdog functions.
The MAX16998A/B/D generate two output signals,
RESET and ENABLE, that depend on the voltage level
at RESETIN and the signal at WDI. RESET asserts
whenever RESETIN drops below the selected reset
threshold voltage. RESET remains low for the reset
timeout period after all reset conditions are deasserted,
and then goes high. RESET also asserts for a period of
tRESET whenever a WDI fault occurs. The MAX16997A
generates one output signal (ENABLE) based on the
voltage level at EN and the signal at WDI.
The MAX16997A/MAX16998A provide watchdog time-
out adjustability with an external capacitor. The
MAX16998A asserts RESET when two consecutive WDI
falling edges do not occur within the watchdog timeout
period. This device also asserts ENABLE if three con-
secutive watchdog timeout periods have elapsed with-
out a falling edge at WDI. ENABLE remains low until
three consecutive good WDI falling edges occur.
ENABLE does not assert if the voltage at RESETIN (EN)
is below its threshold. For the MAX16997A, the watch-
dog timer starts timing if the voltage at EN is higher
than a preset threshold level. Each time the voltage at
EN rises from below to above the preset threshold volt-
age, the initial watchdog timeout period is 8 times the
normal watchdog timeout period (tWP). Other than
described above, the MAX16997A behaves the same
as the MAX16998A.
The MAX16998B/MAX16998D contain a window watch-
dog timer that looks for activity outside an expected
window of operation. The window size is factory-set to
50% (MAX16998B) or 75% (MAX16998D) of the adjust-
ed watchdog timeout period.
Reset Output (
RESET
) (MAX16998A/B/D)
The reset output is typically connected to the reset
input of the µC to start or restart it in a known state. The
MAX16998A/B/D provide an active-low open-drain
reset logic to prevent code execution errors.
For the MAX16998A/B/D, RESET asserts whenever
RESETIN drops below the selected reset threshold volt-
age (VPON). RESET remains low for the reset timeout
period after RESETIN exceeds the selected threshold
voltage, and then goes high.
The MAX16998A asserts RESET for a period of tRESET
when two consecutive WDI falling edges do not occur
within the adjusted watchdog timeout period. The
MAX16998B/D also assert RESET for a period of tRESET
when a WDI falling edge does not occur within the
open window period.
Anytime reset asserts, the watchdog timer clears. At
the end of the reset timeout period, RESET goes high,
and the watchdog timer is restarted from zero (see the
Selecting the Watchdog Timeout Capacitor
section).
Enable Output (
ENABLE
)
If the µC fails to operate correctly (e.g., the software
execution is stuck in a loop), WDI does not trigger any
more and RESET pulls low, resetting the µC. If the µC
does not work properly in the next loop either, the
device asserts RESET again. After three watchdog
timeout periods elapse with no falling edges at WDI,
ENABLE asserts and flags a backup circuit that can
take over the operation.
ENABLE remains low until three consecutive WDI
falling edges with periods shorter than the watchdog
timeout occur. ENABLE does not assert if the voltage at
RESETIN (EN) is below its threshold. These devices are
guaranteed to be in correct ENABLE output logic state
when VIN remains greater than 1.1V.
Power-On/Power-Off Sequence
Figure 5 shows the power-up and power-down
sequence for RESET and ENABLE for the
MAX16998A/B/D.
On power-up, once VIN reaches 1.1V, RESET goes
logic-low. As RESETIN rises, RESET remains low. When
RESETIN rises above VPON, the reset timer starts and
RESET remains low. When the reset timeout period
ends, RESET goes high.
On power-down, once RESETIN goes below VPON,
RESET goes low and remains low until VIN drops below
1.1V. Figure 6 shows the detailed power-up sequence
for the MAX16998A/B/D.
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
10 ______________________________________________________________________________________
VHYST
tRESET
tWP
tCW ≤ tWDI ≤ tWP
tCW ≤ tWDI ≤ tWP
THE THREE CONSECUTIVE RESET COULD BE CAUSED BY THREE
TIMEOUTS AS SHOWN HERE OR BY THREE WDI FALLING EDGE
OUTSIDE THE OPEN WINDOW, OR A COMBINATION OF ANY RESET
CONDITIONS EXCEPT VRESETIN DROPS TOO LOW.
tOW
t = 0
tCW tWP
tRESET tRESET tRESET
tWDI
tWDI tWDI tWDI tWDI tWDI tWDI tWDI
VRESETIN
VIN
VIN = 1.1V
VPON
WDI
ENABLE
RESET
RESET
WDT CLEARS AND
STARTS COUNTING
FROM O
WDI
tWP tWP
Figure 5. Power-On Reset and Power-Down Reset for the MAX16998A/B/D
VHYST
VIN = 1.1V
VPON
VIN = VENABLE
VRESETIN
VRESET
tRESET
Figure 6. Detailed Power-Up Sequence for the MAX16998A/B/D
RESETIN Input (MAX16998A/B/D)
The MAX16998A/B/D monitor the voltage at RESETIN
using an adjustable reset threshold, set with an external
resistive divider (see Figure 7). RESET asserts when
VRESETIN is below 1.235V.
Use the following equations to calculate the externally
monitored voltage (VCC).
where VTH is the desired reset threshold voltage, and
VPON = 1.235V. To simplify the resistor selection,
choose a value for R2(< than 1MΩ) and calculate R1.
EN Input
The MAX16997A provides a high-impedance input (EN)
to the enable comparator. Based on the voltage level at
EN, the watchdog timer is turned on or off. The watch-
dog timer starts timing if the voltage level at EN is high-
er than a preset threshold voltage (VPON). Each time
the voltage at EN rises from below to above the preset
threshold voltage, the initial watchdog timeout period is
8 times the normal watchdog timeout period (tWP).
Watchdog Timer
MAX16997A
The watchdog circuit monitors the µC’s activity. For the
MAX16997A, the watchdog timer starts timing once the
voltage at EN is higher than a preset threshold voltage.
ENABLE asserts if three consecutive watchdog timeout
periods have elapsed without a falling edge at WDI.
ENABLE remains low until three consecutive WDI falling
edges with periods shorter than the watchdog timeout
period occur.
Each time the voltage at EN rises from below to above
the preset threshold voltage, the first watchdog timeout
period extends by a factor of 8 (8 x tWP). If a WDI falling
edge occurs during that time, then the watchdog time-
out period is immediately switched over to a single tWP.
If no watchdog falling edge occurs during this pro-
longed watchdog timeout period, ENABLE goes low at
the end of this period and stays low. After this, the first
falling edge at WDI switches the watchdog timeout
period to a single tWP. See Figure 1. The MAX16997A
watchdog timeout period (tWP) is adjustable by a single
capacitor at SWT.
MAX16998A
The MAX16998A asserts RESET when two consecutive
WDI falling edges do not occur within the adjusted
watchdog timeout period (tWP). RESET remains assert-
ed for the reset timeout period (tRESET) and then goes
high. This device also asserts ENABLE if three consec-
utive watchdog timeout periods have elapsed without a
falling edge at WDI. ENABLE remains low until three
consecutive WDI falling edges with periods shorter
than the watchdog timeout period occur (see Figure 2).
The internal watchdog timer is cleared by a RESET ris-
ing edge or by a falling edge at WDI. The watchdog
timer remains cleared while RESET is asserted; as soon
as RESET is released, the timer starts counting. WDI
falling edges are ignored when RESET is low. If no WDI
falling edge occurs within the watchdog timeout period,
RESET immediately goes low and stays low for the
adjusted reset timeout period.
MAX16998B/D
The MAX16998B/D have a windowed watchdog timer.
The watchdog timeout period (tWP) is the sum of a
closed window period (tCW) and an open window period
(tOW). If the µC issues a WDI falling edge within the open
window period, RESET stays high. Once a WDI falling
edge occurs within the closed window period, RESET
immediately goes low and stays low for the adjusted
reset timeout period (see Figure 3). If no WDI falling
edge occurs within the watchdog timeout period, RESET
immediately goes low and stays low for the adjusted
reset timeout period. The open window size is factory-set
to 50% of the watchdog timeout period for the
MAX16998B and 75% for the MAX16998D.
Figure 8 shows a WDI falling edge identified as a
good
or
a
bad
WDI signal edge. In case 1, the WDI falling edge
occurs within the closed window period and is considered
a
bad
WDI falling edge (early fault); therefore, it asserts
RESET. Case 2 also shows another fault. In this case, no
RRV
V
TH
PON
12 1=−
⎡
⎣
⎢⎤
⎦
⎥
VV R
R
TH PON
=+
⎡
⎣
⎢⎤
⎦
⎥
1
2
1
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
______________________________________________________________________________________ 11
MAX16998A/B/D
RESETIN
VIN
VCC
R1
R2
Figure 7. Setting RESETIN Voltage for the MAX16998A/B/D
MAX16997/MAX16998
WDI falling edge occurs within the watchdog timeout
period (tWP) and is considered a late fault that asserts
RESET. In case 3, the WDI falling edge occurs within the
open window period and is considered a
good
WDI sig-
nal falling edge. In this case, RESET stays high. In case
4, the WDI falling edge occurs within the indeterminate
region. In this case, the RESET state is indeterminate.
These devices assert ENABLE after three consecutive
bad WDI falling edges. ENABLE returns high after three
consecutive good WDI signal falling edges (see Figure 3).
Either a rising edge at RESET or a falling edge at WDI
clears the internal watchdog timer. The watchdog timer
remains cleared while RESET is asserted. The watch-
dog timer begins counting when RESET goes high.
WDI falling edges are ignored when RESET is low.
Applications Information
Selecting the Reset Timeout Capacitor
The reset timeout period is adjustable to accommodate a
variety of µP applications. Adjust the reset timeout period
(tRESET) by connecting a capacitor (CSRT) between SRT
and ground. See the Reset Timeout Period vs. CSRT
graph in the
Typical Operating Characteristics
. Calculate
the reset timeout capacitance using the equation below:
where VRAMP is in volts, tRESET is in seconds, IRAMP is
in nA, and CSRT is in nF.
Leakage currents and stray capacitance (e.g., a scope
probe, which induces both) at SRT may cause errors in
the reset timeout period. If precise time control is
required, use capacitors with low leakage current and
high stability.
Selecting the Watchdog
Timeout Capacitor
The watchdog timeout period is adjustable to accom-
modate a variety of µP applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer determines how often the
watchdog timer should be serviced. Adjust the watch-
dog timeout period (tWP) by connecting a capacitor
(CSWT) between SWT and GND. For normal mode
operation, calculate the watchdog timeout capacitance
using the following equation:
where VRAMP is in volts, tWP is in seconds, IRAMP is in nA,
and CSWT is in nF. See the Watchdog Timeout Period vs.
CSWT graph in the
Typical Operating Characteristics
.
For the MAX16998B/MAX16998D, the open window size
is factory-set to 50% (MAX16998B) or 75% (MAX16998D)
of the watchdog period. Leakage currents and stray
capacitance (e.g., a scope probe, which induces both) at
SWT may cause errors in the watchdog timeout period. If
precise time control is required, use capacitors with low
leakage current and high stability. To disable the watch-
dog timer function, connect SWT to ground and connect
WDI to either the high- or low-logic state.
Ct I
V
SWT WP RAMP
RAMP
=×
×4
Ct I
V
SRT RESET RAMP
RAMP
=×
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
12 ______________________________________________________________________________________
tWDImin
RESET RISING EDGE tWDImax tWP
(50% or 75%) x tWP
CASE 1 (FAST FAULT)
CASE 2 (SLOW FAULT)
CASE 3 (GOOD WDI)
CASE 4 (INDETERMINATE)
CLOSED WINDOW OPEN WINDOWINDETERMINATE
Figure 8. The MAX16998B/D Window Watchdog Diagram
Interfacing to Other Voltages for
Logic Compatibility
As shown in Figure 9, the open-drain RESET output can
operate in the 2.5V to 18V range. This allows the device
to interface a µP with other logic levels.
WDI Glitch Immunity
For additional glitch immunity, connect an RC lowpass
filter as close as possible to WDI (see Figure 10).
For example, for glitches with duration of 1µs, a 12kΩ
resistor and a 47pF capacitor will provide immunity.
Layout Considerations
SRT and SWT are connected to internal precision cur-
rent sources. When developing the layout for the appli-
cation, minimize stray capacitance attached to SRT
and SWT as well as leakage currents that can reach
those nodes. SRT and SWT traces should be as short
as possible. Route traces carrying high-speed digital
signals and traces with large voltage potentials as far
from SRT and SWT as possible. Leakage currents and
stray capacitance (e.g., a scope probe, which induces
both) at these pins may cause errors in the reset and/or
watchdog timeout period. When evaluating these parts,
use clean prototype boards to ensure accurate reset
and watchdog timeout periods.
RESETIN is a high-impedance input and a high-imped-
ance resistive divider (e.g., 100kΩto 1MΩ) sets the
threshold level. Minimize coupling to transient signals
by keeping the connections to this input short. Any DC
leakage current at RESETIN (e.g., a scope probe)
causes errors in the programmed reset threshold.
Typical Operating Circuits
RESET remains asserted as long as RESETIN is below
the regulated voltage and for the reset timeout period
after RESETIN goes high to assure that the monitored
LDO voltage is settled. Then, the µC starts operating
and triggers WDI.
If the µC fails to operate correctly (e.g., the software
execution is stuck in a loop), the WDI signal does not
trigger the watchdog timer any more, and RESET is
pulled low, resetting the µC. If the µC does not work
properly in the next loop either, the device asserts
RESET again. After three watchdog timeout periods
with no WDI falling edges, ENABLE asserts and flags
backup or safety circuits that take over the operation.
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
______________________________________________________________________________________ 13
MAX16998A/B/D
RESET
RESET
GND
GND
5V TO 40V 2.5V TO 18V
IN
VCC
µP
N
10kΩ
MAX16998A/B/D
WDI I/O
GND
GND
IN
VCC
R
C
µP
Figure 9. Interfacing to Other Voltage Levels Figure 10. Additional WDI Glitch Immunity Circuit
MAX16997A
ENABLE
RESET
5V
BACKUP CIRCUITRY,
PERIPHERAL
BACKUP
CIRCUITRY FLAGS
SEPARATE
WATCHDOG
EN
SWT
GND
IN
VBATT
VCC
R1
R2
WATCHDOG
LDO
5V
REGULATOR
I/O
GND
µC
I/O
WDI
Figure 12. MAX16997A Application Diagram
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
14 ______________________________________________________________________________________
MAX16998A/B/D
ENABLE EN
RESET
SRT BACKUP CIRCUITRY,
PERIPHERAL
5V
REGULATOR
RESETIN
SWT
GND
IN
VBATT
VCC
VCC
R1
R2
RESET
I/O
GND
µC
WDI
Figure 11. MAX16998A/B/D Switch Over to Backup Circuitry
MAX16997/MAX16998
Pin Configurations
TOP VIEW
1
2
3
4
8
7
6
5
ENABLE
N.C.
WDI
GNDSWT
N.C.
EN
IN
MAX16997A
µMAX
+
1
2
3
4
8
7
6
5
ENABLE
RESET
WDI
GNDSWT
SRT
RESETIN
IN
MAX16998A/B/D
µMAX
+
Chip Information
PROCESS: BiCMOS
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
______________________________________________________________________________________ 15
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 µMAX U8-1 21-0036
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 2/08 Initial release —
1 4/09 Added bullet to Features section, revised Electrical Characteristics table. 1, 2, 3
2 8/09 Added automotive qualified parts. 1
