1994-2012 Microchip Technology Inc. DS2109 5K-page 1
24LC21
Features:
• Single supply with operation down to 2.5V
• Completely implements DDC1™/DDC2™ interface
for monitor identification
• Low-power CMOS technology:
- 1 mA active current typical
-10 A standby current typical at 5.5V
• 2-wire serial interface bus, I2C™ co m pat i ble
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Factory programming (QTP) available
• 1,000,000 erase/wr ite cycles ensured
• Data retention > 200 years
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
Description:
The Microchip Technology Inc. 24LC21 is a 128 x 8 bit
Electrically Erasable PROM. This device is designed
for use in applications requiring storage and serial
transmission of configuration and control information.
Two modes of operation have been implemented:
Transmit-only mode and Bidirectional mode. Upon
power-up, the device will be in the Transmit-only mode,
sending a serial bit s tream of the entire mem ory array
contents, cloc ked by the V CLK p in. A valid high-to-low
transition on the SCL pin will cause the device to enter
the Bidirectional m ode, with by te selectable read/write
capability of the memory array . The 24LC21 is available
in a standard 8-pin PDIP and SOIC package, in both
commercial an d industrial temperature ranges.
Package Types
Block Diagram
Commercial (C): 0°C to +70°C
Industrial (I): -40°C to +85°C
24LC21
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
24LC21
NC
NC
NC
VSS
1
2
3
4
8
7
5
5
VCC
VCLK
SCL
SDA
PDIP
SOIC
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp
R/W Control
Memory
Control
Logic
I/O
Control
Logic
VCLK
SDA SCL
VCC
VSS
1K 2.5V Dual Mode I2C™ Serial EEPROM
Not recommended for new designs –
Please use 24LCS21A.
21095K.book Page 1 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 2 1994-2012 Microchip Technology Inc.
1.0 ELECTRICAL CHA RACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................ -40°C to +125°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection o n all pins 4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed u nder “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC CHARACTE RI STICS VCC = +2.5V to 5.5V
Commercial (C): TA = 0°C to +70°C
Industrial (I): TA = -40°C to +85°C
Parameter Symbol Min Max Units Conditions
SCL and SDA pins:
High-level input voltage
Low-level input voltage VIH
VIL .7 VCC
——
.3 VCC V
V—
—
Input levels on VCLK pin:
High-level input voltage
Low-level input voltage VIH
VIL 2.0
—.8
.2 VCC V
VVCC 2.7V (Note 1)
VCC < 2.7V (Note 1)
Hysteresis of Schmitt Trigger inputs VHYS .05 V CC —V(Note 1)
Low-level output voltage VOL1—.4VIOL = 3 mA, VCC = 2.5V ( Note 1)
Low-level output voltage VOL2—.6VIOL = 6 mA, VCC = 2.5V
Input leakage current ILI -10 10 AVIN = .1V to VCC
Output leakage current ILO -10 10 AVOUT = .1V to VCC
Pin capacitance (all inputs/outputs) CIN, COUT —10pFVCC = 5.0V (Note1),
TA = 25C, FCLK = 1 MHz
Operating current ICC Write
ICC Read —
—3
1mA
mA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS —
—30
100 A
AVCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
(Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: VLCK must be grounded.
21095K.book Page 2 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS2109 5K-page 3
24LC21
TABLE 1-2: AC CHARACTERISTICS
Parameter Symbol Standard M ode Vcc= 4.5 - 5.5V
Fast Mode Units Remarks
Min Max Min Max
Clock frequency FCLK — 100 — 400 kHz —
Clock high time THIGH 4000 — 600 — ns —
Clock low time TLOW 4700 — 1300 — ns —
SDA and SCL rise time TR— 1000 — 300 ns (Note 1)
SDA and SCL fall time TF— 300 — 300 ns (Note 1)
Start condition hold time THD:STA 4000 — 600 — ns After this period the first clock
pulse is generated
Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated
Start condi tion
Data input hold time THD:DAT 0—0—ns(Note 2)
Data input setup time TSU:DAT 250 — 100 — ns —
Stop c ondition setup time TSU:STO 4000 — 600 — ns —
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
min. to VIL max. TOF — 250 20 + .1
CB250 ns (Note 1), CB 100 pF
Input filter spike suppres-
sion (SDA and SCL pins) TSP — 50 — 50 ns (Note 3)
Write cycle time TWR — 10 — 10 ms Byte or Page mode
Transmit-only Mode Parameters
Output valid from VCLK TVAA — 2000 — 1000 ns —
VCLK high time TVHIGH 4000 — 600 — ns —
VCLK low time TVLOW 4700 — 1300 — ns —
Mode transition time TVHZ — 500 — 500 ns —
Transmit-only power-up
time TVPU 0—0—ns—
Endurance — 1M — 1M — cycles 25°C, VCC = 5.0V, Block
mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns ) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at: www.microchip.com
21095K.book Page 3 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 4 1994-2012 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LC21 operat es in two modes, the Transmit-only
mode and the Bid irectional mode. There is a separate
two-wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-only mode upon
power-up. I n this mode, the device t ransmits data bits
on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high-to-lo w transition is placed on th e SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bidirectional mode. The only
way to switch the device back to the Transmit-only
mode is to remove power from the device.
2.1 Transmit-only Mode
The device will power-up in the Transmit-only mode.
This mode supports a unidirectional two-wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-only mode (see Initial-
ization Procedure, below). In this mode, data is trans-
mitted on t he SDA pin in 8-b it bytes, eac h followed by
a ninth, null bit (see Figure 2-1). The clock source for
the Transmit-only mode is provided on the VCLK pin,
and a data bit is ou tput on the rising edge on thi s pin.
The eight bits in each byte are transmitted Most Signif-
icant bit first. Each byte within the memory array will be
output in sequenc e. Whe n the last byte in the memor y
array is transmitted, the outpu t will wrap around to the
first location and continue. The Bidirectional mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-only mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the Tr ans-
mit-only mode. Nine clock cycles on the VCLK pin must
be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a
high-impedance s tate. O n the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit of a byte. The
device will power-up at an indeterminate byte address.
(Figure 2-2).
FIGURE 2-1: TRANS MIT-ONLY MODE
FIGURE 2-2: DEVICE INITIALIZATION
SCL
SDA
VCLK
TVAA TVAA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB) Bit 7
TVLOWTVHIGH
TVAA TVAA
Bit 8 Bit 7High-impedance for 9 clock cycles
TVPU
12 891011
SCL
SDA
VCLK
VCC
21095K.book Page 4 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS2109 5K-page 5
24LC21
3.0 BIDIRECTIONAL MODE
The 24LC21 can be switched into the Bidirectional
mode (see Figur e 3-1) by ap plying a valid high-to-low
transition on the Bidirectional mode clock (SCL). When
the device has been switched into the Bidirectional
mode, the VCLK input is disregarded, with the exception
that a logic high level is required to enable write capa-
bility. This mod e suppor ts a two-wir e bidirec tional data
transmission protocol. In this protocol, a device that
sends data on the bus is defined to be the transmitter,
and a device that receives data from the bus is defined
to be the receiver. The bus must be controlled by a
master device that generates the Bidirectional mode
clock (SCL), contr ols access to the bus and generat es
the St art and Stop conditions, while the 24LC21 acts as
the slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
3.1 Bidirectional Mode Bus
Characteristics
The following bus pro toc ol ha s been defined:
• Data transfer may be initiated only when the bus
is not busy.
• Dur ing data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (see F igure 3-2).
3.1.1 B US NOT BUSY (A)
Both data and clock line s remain high.
3.1.2 START DATA TRANSFER (B)
A high-to-low tran sition of the SDA line w hile the cloc k
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.3 STOP DATA TRANSFER (C)
A low-to-high tran sition of the SD A line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 3-1: MODE TRANSITION
FIGURE 3-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
VCLK
Bidirectional mode
TVHZ
Transmit-only mode
(A) (B) (D) (D) (A)(C)
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL
SDA
21095K.book Page 5 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 6 1994-2012 Microchip Technology Inc.
3.1.4 DATA VALID (D)
The state of the data line repre sen ts valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock s ignal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a S tart condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, al though only the last eight will
be stored when doing a write operation. When an
overwrite does occur , it will replace data in a first in first
out fashion.
3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The maste r device must genera te an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.
FIGURE 3-3: BUS TIMING START/STOP
FIGURE 3-4: BUS TIMING DATA
Note: The 24LC21 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
TSU:STA THD:STA
VHYS
TSU:STO
Start Stop
SCL
SDA
TSU:STA
TF
TLOW
THIGH
TR
THD:DAT TSU:DAT TSU:STO
THD:STA TBUF
TAA
TAA
TSP
THD:STA
SCL
SDA
IN
SDA
OUT
21095K.book Page 6 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS2109 5K-page 7
24LC21
3.1.6 SLAVE ADDRESS
After generating a St art condition, the bus master trans-
mits the slave address consisting of a 7-bit device code
‘1010’ for the 24LC21, followed by three “don’t care”
bits.
The eighth bit of slave address determines if the master
devi ce want s to read o r wri te to the 24 LC21 (F igure 3-5).
The 24LC21 monitors the bus for its corresponding
slave address all the time. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.
FIGURE 3-5: CONTROL BYTE
ALLOCATION
4.0 WRITE OPERATION
4.1 Byte Write
Following the Start signal from the master, the slave
address (4 bits), the “don’t care” bits (3 bits) and the
R/W bit which is a logic low, is placed onto the bus by
the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an Acknowl-
edge bit during the ninth clock cycle. Therefore, the
next byte transmitted by the master is the word
address and will be written into the address pointer of
the 24LC21. After receiving another Acknowledge
signal f rom the 2 4LC21 the ma ster device wi ll tran smit
the data word to be written into the addressed mem-
ory location. The 24LC21 acknowledges again and
the master generates a Stop condition. This initiates
the internal write cycle, and during this time the
24LC21 will not generate Acknowledge signals
(Figure 4-1).
It is required that VCLK be hel d at a l ogic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the devi ce is in its self-timed program operation
and not affect programming.
4.2 Page Write
The write control byte, word addres s and the first data
byte are transmitted to the 24LC21 in the same way as
in a byte write. But instead of generating a Stop condi-
tion the master transmits up to eight data bytes to the
24LC21, which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a Stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received an
internal wr ite cycle will begin (Figure 4-3).
Operation Control Code Chip Select R/W
Read 1010 xxx 1
Write 1010 xxx 0
SLAVE ADDRESS
1010xx x
R/W A
Start Read/Write
21095K.book Page 7 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 8 1994-2012 Microchip Technology Inc.
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the devi ce is in its self-timed p rogram operation
and not affect programming.
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: BYTE WRITE
Note: Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size - 1]. If a
page Write command attempts to write
across a physical page boundary, the
result is that the d ata wraps around to the
beginning of the current page (overwriti ng
data previously stored there), instead of
being written to the next page as might be
expected. It is ther efore nec essa ry for the
application software to pre vent page write
operations that would attempt to cross a
page boundary.
S P
BUS ACTIV ITY
MASTER
SDA LINE
BUS ACTIV ITY
S
T
A
R
T
S
T
O
P
Control
Byte Word
Address Data
A
C
K
A
C
K
A
C
K
VCLK
S P
BUS ACTIV ITY
MASTER
SDA LINE
BUS ACTIV ITY
S
T
A
R
T
S
T
O
P
Control
Byte Word
Address Data
A
C
K
A
C
K
A
C
K
VCLK
21095K.book Page 8 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS2109 5K-page 9
24LC21
FIGURE 4-3: PAGE WRITE
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
TControl
Byte Word
Address Data (n) Data (n + 15)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n + 1)
VCLK
21095K.book Page 9 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 10 1994-2012 Microchip Technology Inc.
5.0 ACKNOWLEDG E POLLING
Since the device will not acknowledge during a write
cycle, this can be us ed t o determine w hen the c ycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immedi ately. This involves t he master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the devi ce will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for the flow
diagram.
FIGURE 5-1: ACKNOWLEDGE
POLLING FLOW
6.0 WRITE PROTECTION
When usin g the 24LC21 i n th e Bidirectiona l mode, the
VCLK pin operates as the write-protect control pin.
Setting VCLK high allows normal write operations, while
setting VCLK low prevents writing to any location in the
array. Connec ting th e VCLK pin to VSS wou ld al low the
24LC21 to operate as a serial ROM, although this
configuration would prevent using the device in the
Transmit-only mode.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
21095K.book Page 10 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS21095K-pag e 11
24LC21
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1 Current Address Read
The 24LC21 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 24LC21
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24LC21
discontinues transmission (Figure 7-1).
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC21 as part of a write operation. After the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘1’. The 24LC21 will then issue
an acknowl edge and trans mits the eig ht bit da ta word.
The mas ter will not ac knowledge the transfer but does
generate a Stop condition and the 24LC21
discontinues transmission (Figure 7-2).
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LC21 transmits the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the 24LC21 to transmit the next sequentially
addressed 8- bit word (see Figure 7-3).
To provide sequential reads the 24LC21 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
7.4 Noise Protection
The 24LC21 employ s a VCC threshold detector circuit
which disables the internal erase/w rite logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
FIGURE 7-1: CURRENT ADDRESS READ
SP
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
Control
Byte Data (n)
A
C
K
N
O
A
C
K
S
T
O
P
21095K.book Page 11 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 12 1994-2012 Microchip Technology Inc.
FIGURE 7-2: RANDOM READ
FIGURE 7-3: SEQUENTIAL READ
S P
S
BUS ACTIVI TY
MASTER
SDA LINE
BUS ACTIVI TY
S
T
A
R
T
S
T
O
P
Control
Byte Word
Address Data (n)
A
C
K
A
C
K
N
O
A
C
K
Control
Byte
A
C
K
S
T
A
R
T
P
BUS ACTIV ITY
MASTER
SDA LINE
BUS ACTIV ITY
S
T
O
P
Control
Byte
A
C
K
N
O
A
C
K
Data (n) Data (n + 1) Data (n + 2) Data (n + X)
A
C
K
A
C
K
A
C
K
21095K.book Page 12 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS21095K-pag e 13
24LC21
8.0 PIN DESCRIPTIONS
TABLE 8-1: PIN FUNCTION TABLE
8.1 SDA
This pin is used to transfer addresses and data into and
out of the device, when the device is in the Bidirectional
mode. In the Transmit-only mode, which only allows
data to be read from the device, data is also transferred
on the SDA pin. This pin is an open drain terminal,
therefore the SDA bus requires a pull-up resistor to
VCC (typical 10K for 100 kHz, 2K for 400 kHz).
For normal data transfer in the Bidirectional mode, SDA
is allowed to change only during SCL low. Changes
during SCL high are reserved for indicating the Start
and Stop conditions.
8.2 SCL
This pin is the clock input for the Bidirectional mode,
and is used to synchronize data transfer to and from the
device. It is also us ed as the signaling input to switch
the device from the Transmit-only mode to the
Bidirectional mode. It m ust remain high for the chip to
continue operation in the Transmit-only mode.
8.3 VCLK
This pin is the clock input for the Transmit-o nly mode.
In the Transmit-only mode, each bit is c locked out on
the rising edge of this signal. In the Bidirectional mode,
a high logic level is required on this pin to enable write
capability.
Name Function
VSS Ground
SDA Serial Address/Data I/O
SCL Serial Clock (Bidirectional mode)
VCLK Serial Clock (Transmit-only mode)
VCC +2.5V to 5.5V Power Supply
NC No C onnection
21095K.book Page 13 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 14 1994-2012 Microchip Technology Inc.
9.0 PACKAGING I NFORMATION
9.1 Package Marking Inform ation
XXXXXNNN
8-Lead PDIP
XXXXXXXX
YYWW 017
Example
24LC21
0410
8-Lead SOIC (.150”)
XXXXXXXX
XXXXYYWW
NNN
Example
24LC21
/SN0410
017
Legend: XX...X Customer-spec ific information
Y Year code (last digit of calendar year)
YY Year code (last 2 di gits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
21095K.book Page 14 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS21095K-pag e 15
24LC21
8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
B1
B
A1
A
L
A2
p
E
eB
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoul der Width E .300 .313 .325 7.62 7.94 8.26
Molde d P ac kag e W idt h E1 .2 40 .250 .26 0 6. 10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top 5 10 15 5 10 15
Mold Draft Angle Bottom 5 10 15 5 10 15
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold fl ash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
Note: For the most cur rent package draw ings, please s ee the Microchi p Packaging Sp ecific ation located
at http://www.microchip.com/packaging
21095K.book Page 15 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 16 1994-2012 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC)
Foot Angle 048048
1512015120
Mold Draft Angle Bottom 1512015120
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Le ng th 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Package Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
c
45
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flas h or protrusions. Mol d flash or protrusions shall not exceed
.010” (0.254mm) per sid e.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
Note: For the most curr ent package drawings , please s ee the Mic rochip Packag ing Specification located
at http://www.microchip.com/packaging
21095K.book Page 16 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS21095K-pag e 17
24LC21
APPENDIX A: REVISION HISTORY
Revision J
Added note to page 1 header (Not recommended for
new designs).
Added Section 9.0: Pac kage Marking Information.
Added On-line Support page.
Updated document format.
Revision K
Added a note to each package outline drawing.
21095K.book Page 17 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 18 1994-2012 Microchip Technology Inc.
NOTES:
21095K.book Page 18 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS21095K-pag e 19
24LC21
THE MICROCH IP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Prod uct Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical su pport requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHA NGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers curren t on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through sever al channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
21095K.book Page 19 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 20 1994-2012 Microchip Technology Inc.
READER RES PONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO: Technical Publications Manager
RE: Reader Response Total Pages Sent _____ ___
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21095K24LC21
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you i mprove this document?
21095K.book Page 20 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS21095K-pag e 21
24LC21
PRODUCT IDENTIFI CATI ON SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
21095K.book Page 21 Wednesday, December 5, 2012 2:28 PM
24LC21
DS2109 5K-page 22 1994-2012 Microchip Technology Inc.
NOTES:
21095K.book Page 22 Wednesday, December 5, 2012 2:28 PM
1994-2012 Microchip Technology Inc. DS21095K-pag e 23
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk , and the buyer agr ees to def end, ind emnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microc hip name and logo, the Mic roc hip logo , dsPI C,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Comp any are r egi st ere d tr ade mar ks of Mic roc hi p Technol ogy
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP i s a servi ce mark of Micr ochip Techno logy In corpor ated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respect ive com panie s.
© 1994-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620767306
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today , when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code pro tect ion i s co nstan tly e volv ing . We at Microch ip ar e co mm itte d to con tinu ou sly im pr ovin g th e co de pro tect ion feat ure s of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such a ct s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Mic roc h ip rece iv e d IS O/T S- 1 69 49 :2 00 9 certi fi cat io n for its world w id e
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and de sign centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
device s , Ser ial EEPRO Ms, mic ro pe ri p her als, nonvolat i le mem or y an d
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
21095K.book Page 23 Wednesday, December 5, 2012 2:28 PM
DS2109 5K-page 24 1994-2012 Microchip Technology Inc.
AMERICAS
Corpora te Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
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Mississauga, Ontario,
Canada
Tel: 905-673-0699
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Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 852-2401-1200
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Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
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Tel: 86-10-8569-7000
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Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
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Tel: 86-23-8980-9588
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Tel: 86-571-2819-3187
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China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-850 2-7355
Fax: 86-532-8502-7205
China - Shangha i
Tel: 86-21-5407-5533
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China - Shen yan g
Tel: 86-24-2334-2829
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Tel: 86-755-8203-2660
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Tel: 86-27-5980-5300
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Tel: 86-29-8833-7252
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Tel: 86-592-238 8138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-32 10049
ASIA/PACIFIC
India - Bangalo re
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
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Tel: 91-11-4160-8631
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Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
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Tel: 81-66-152-7160
Fax: 81-66-152-9310
Japan - Yokohama
Tel: 81-45-471- 6166
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Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
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Philippin es - Manil a
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Tel: 65-6334-8870
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Tel: 886-3-5778-366
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Tel: 886-7-213-7828
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Tel: 886-2-2508-8600
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Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-724 2-2 244 -39 3
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-448 5-2 829
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Tel: 33-1-69-53-63-20
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Tel: 49-89-627-144-0
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Worldwide Sales and Service
10/26/12
21095K.book Page 24 Wednesday, December 5, 2012 2:28 PM