www.latticesemi.com
1
ip1014_02
Convolutional Encoder
March 2003 IP Data Sheet
© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
The product described herein is subject to continuing development, and applicable specifications and information are subject to change without notice. Such specifica-
tions and information are provided in good faith; actual performance is not guaranteed, as it is dependent on many factors, including the user's system design.
Features
■
Parameterizable continuous convolutional
encoder
■
Parameterizable constraint length from 3 to 12
■
Parameterizable convolutional codes
■
Parameterizable puncture codes
■
Puncturing input rates from 2 to 12
■
Puncturing output rates from 2 to 23
General Description
The top-level representation of the convolutional
encoder is shown in Figure 1. For detailed signal
descriptions, see Table 1.
Convolutional Encoding Example
Convolutional encoding is a process of adding redun-
dancy to a signal stream. Figure 2 shows an e xample of
convolutional encoding.
In this example, each input symbol has 2 corresponding
output symbols, hence the encoding is called 1/2 rate
convolutional encoding. To generate the output, the
encoder uses 3 v alues of the input signal, 1 present and
2 past. The set of past values of input data is called a
“state.” The number of input data values used to gener-
ate the code is called the constraint length. In this case,
the constraint length is 3. Each set of outputs is gener-
ated by XORing a pattern of current and shifted values
of inupt data. The patterns used to generate the coded
output value can be expressed as binary strings called
generator polynomials. In this example, the generator
polynomials are 111 and 101. The MSB of the generator
polynomial corresponds to the input; the LSBs of the
generator polynomial correspond to the state as shown
in Figure 2. A bit value of ‘1’ in the generator polynomial
represents a used XOR bit and a v alue of ‘0’ signifies an
unused bit.
Block Diagram
Figure 1. Convolutional Encoder Top-level Block Diagram
Convolutional
Encoder
din dout
clk
reset_b
dout_valid
pd_start
din_valid rfi
Lattice Semiconductor Convolutional Encoder
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Figure 2. 1/2 Rate Convolutional Encoding
Convolutional Encoder Application
Figure 3 shows a digital transmit-receive system using the convolutional encoder. The digital data stream (such as
voice, image or any packetized data) is first convolutionally encoded, then modulated and finally transmitted
through a channel. The noise block in the following diagram represents channel noise added to the channel. The
data received from the channel at the receiver side is first demodulated and then decoded using a Viterbi decoder.
The decoded output is equivalent to the original transmitted data stream.
Figure 3. Digital Transmit-Receive System
Puncturing
After convolutional encoding, some of the encoded symbols can be selectively removed before transmission. This
process, called “puncturing,” is used to reduce the number of bits transmitted for the same information size.
Figure 4 shows an example of puncturing.
Figure 4. Example of Puncturing
If puncturing is employed in the encoder, the decoder has to “depuncture” the data before decoding. Depuncturing
is done by inserting NULL symbols for the punctured symbols. NULL symbols are chosen such that they are equi-
distant from either ‘0’ or ‘1’.
data in DQ DQ
data out
1/2 convolutional coding with constraint length = 3
and generator polynomials 111 and 101
Transmitted
data stream Modulator Channel Demodulator Viterbi
Decoder
Received
data stream
Noise
Convolutional
Encoder
i
0
i
1
i
2
i
3
i
4
i
5
i
6
a
0
b
0
a
1
a
2
a
3
a
4
a
5
a
6
b
1
b
2
b
3
b
4
b
5
b
6
a
0
b
0
b
1
a
2
a
3
b
3
b
4
1
1
01
10
a
0
b
0
a
1
a
2
a
3
a
4
a
5
a
6
b
1
b
2
b
3
b
4
b
5
b
6
a
5
Input data
After convolutional coding
Puncture pattern
superimposed
Puncture pattern
Final punctured output
Lattice Semiconductor Convolutional Encoder
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Functional Description
The convolutional encoder core is a parameterizable core for encoding a continuous input data stream. The core
allows variab le code rates, constraint lengths and generator polynomials. The core also supports puncturing. Punc-
turing enables a large range of tr ansmission rates and reduces the bandwidth requirement on the channel. The top-
level block diagram is shown in Figure 1. Figure 5 shows the modules of the core.
Figure 5. Modules of the Convolutional Encoder
Encoder
This module takes input data and perfor ms convolutional encoding. The encoder uses generator polynomials con-
figured by the user. When punctured encoding is enabled, the encoder perfor ms 1/2 rate encoding irrespective of
the encoder rate. The puncture unit will use the 1/2 rate code to generate the appropriate user-programmed rate.
Puncture Unit
This unit perfor ms data punctur ing, as explained in the General Descr iption section. The input is a 2-channel data
stream and the output is always a one-channel output. The unit is capable of performing puncturing of any block
size and any rate.
Control Unit
The control unit generates the handshake signals
dout_valid,
rfi
and
pd_start
using
din_valid
and the
status of the decoder. It also generates various control signals required by the encoder and puncture unit.
Parameters Description
The following core parameters allow the user to tailor the core to realize different configurations of convolutional
encoder. These parameters can be configured through graphical user interface dialog box accessible through the
IP/Module Manager tool in Lattice’s ispLEVER™ design tool suite. An example of this dialog box is shown in
Figure 6.
dout
dout_valid
pd_start
rfi
Encoder Puncture
Unit
Control Unit
din
clk
reset_b
din_valid
Lattice Semiconductor Convolutional Encoder
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Figure 6. Core Parameter Configuration Dialog Box
Constraint Length
This defines the constraint register length. The value can be any integer from 3 to 12.
Input Rate
This defines the input symbol rate for the encoder. The input rate for non-punctured codes is always 1. For punc-
tured codes, it can be any value from 2 to 12.
Output Rate
This defines the output symbol rate f or the encoder. The output rate f or non-punctured codes can be any value from
2 to 8. For punctured codes , the output rate can be any value from 3 to 23 (
k
+1 to 2
k
-1, where
k
is the input rate).
Generator Polynomials
GP0, GP1, GP2, GP3, GP4, GP5, GP6 and GP7 are generator polynomials. For non-punctured encoders, the
number of generator polynomials is always equal to the output rate. For punctured encoders, the number of gener-
ator polynomials is 2. The user has the option to enter the generator polynomial values either in binary, octal or
hexadecimal by selecting the appropriate radio button in the configuration dialog box.
Punctured Data Support
The encoder suppor ts punctured or non-punctured data. For punctured data, the punctured block size is equal to
the input rate. The encoder also supports 2 user-defined puncture patterns (PP0 and PP1).
Signal Description
The top-level representation of the convolutional encoder is shown in Figure 1. Table 1 contains the signal descrip-
tion. Timing diagrams for the signals are shown in the Timing Diagram section.
Lattice Semiconductor Convolutional Encoder
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Table 1. Core Signals
Timing Diagrams
The timing diagrams of various core configurations are sho wn in Figures 7 and 8. (F or inf ormation regarding
din
to
dout
latency, see Appendix A).
Figure 7. Timing Diagram for a 1/2 Rate Non-punctured Encoder
Figure 8. Timing Diagram for a 3/5 Rate Punctured Encoder
Port Bits I/O Description
clk
1 Input System clock. The clock speed is equal to the input symbol rate.
reset_b
1 Input System-wide asynchronous reset signal, active low.
din_valid
1 Input Denotes valid data being presented at the encoder input. Must be
asserted only if the output
rfi
is high.
din
1 Input Input data to the encoder. Must be presented only if the encoder output
rfi
is high.
dout_valid
1 Output Denotes valid data is present at the encoder output.
pd_start
1 Output Signifies start of a punctured block.
rfi
1 Output Indicates the encoder is ready for input.
dout
2 to 8 (non-punctured)
1 (punctured) Output Output data of the encoder. The data is valid only if the signal
dout_valid
is high.
clk
dout
din d0 d1 d2 x xd3 d4 d5
din_valid
xd7 d8 d9 x
xxxd3
x
dout_valid
d0 d1 d2 x
d6
d4 d5 d7
d6 d8
clk
dout
1
1. For information regarding din to dout latency, see Appendix A.
din d0 d1 d2 xx
d3 d4 d5
din_valid
xx67 8 x
xd2++ d3
rfi
d4 d5
x
dout_valid
pd_start
d0 d1 d2 d2+
Lattice Semiconductor Convolutional Encoder
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Custom Core Configurations
For custom convolutional encoder core configurations beyond those available in the standard evaluation package,
please contact your Lattice sales office. See the appendix for the available core configurations.
Related Information
For more information regarding verification and usage of the core, please refer to the User’s Guide.
Lattice Semiconductor Convolutional Encoder
7
Appendix A. ORCA Series 4 FPGAs
Table 2. Core Configurations for ORCA Series 4 FPGAs
Supplied Netlist Configurations
The Ordering Part Number (OPN) for all configurations of this core in ORCA Series 4 devices is CONV-ENCO-04-
N1. Table 2 lists the netlist configurations that are available in the Evaluation Package for this core, which can be
downloaded from the Lattice web site at www.latticesemi.com.
To load the preset parameters for this core , clic k on the "Load Parameters" button inside the IP Manager tool. Make
sure that you are looking for a file inside of this core's director y location. The Lattice Parameter Configuration files
(.lpc) are located within the .lpc folder inside this directory.
Table 3. Performance and Resource Utilization
1
Configuration #1
Constraint length 7
Input rate 1
Output rate 2
Generator Polynomials
GP0 (octal) 171
GP1 (octal) 133
GP2 (octal) —
GP3 (octal) —
GP4 (octal) —
GP5 (octal) —
GP6 (octal) —
GP7 (octal) —
Punctured Data Support
Punctured encoder No
Puncture pattern – PP0 —
Puncture pattern – PP1 —
Configuration ORCA 4
PFUs
2
LUTs Registers External
I/Os sysMEM™
EBRs f
MAX
(MHz) Latency
3
conv_enco_o4_1_001.lpc 4 6 16 7 N/A 333 3
1. Performance and utilization characteristics using ispLEVER v.3.0 software and targeting the OR4E02, package BA352, speed 2. Synthe-
sized using Synplicity's Synplify Pro v.7.1.1. When using this IP core in a different density, package, speed, or grade within the OR4E fam-
ily, performance and utilization may vary slightly.
2. Programmable Function Unit (PFU) is a standard logic block of Lattice FPGA devices. For more information, check the data sheet of the
device.
3. The latency values are for
din
to
dout
with
din_valid
is high whenever
rfi
is high. The
din
to
dout
latency relationship can be
explained as follows. For non-punctured encoders, the latency value is 3 when constraint length is greater than 4, otherwise the value is 2.
For punctured encoders , the latency value is (output rate + 6) when constraint length is greater than 4, otherwise the v alue is (output rate +
4).
Lattice Semiconductor Convolutional Encoder
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Appendix B. ispXPGA™ FPGAs
Supplied Core Configurations
Table 4 shows the description of core configurations available in the standard evaluation package.
Table 4. Core Configurations for ispXPGA FPGAs
Supplied Netlist Configurations
The Ordering Part Number (OPN) for all configurations of this core in ispXPGA devices is CONV-ENCO-XP-N1.
Table 4 lists the netlist configurations that are a vailable in the Ev aluation Package f or this core , which can be do wn-
loaded from the Lattice web site at www.latticesemi.com.
To load the preset parameters for this core , clic k on the "Load Parameters" button inside the IP Manager tool. Make
sure that you are looking for a file inside of this core's director y location. The Lattice Parameter Configuration files
(.lpc) are located within the .lpc folder inside this directory.
Table 5. Performance and Resource Utilization
1
Configuration #1
Constraint Length 7
Input Rate 1
Output Rate 2
Generator Polynomials
GP0 (Octal) 171
GP1 (Octal) 133
GP2 (Octal) —
GP3 (Octal) —
GP4 (Octal) —
GP5 (Octal) —
GP6 (Octal) —
GP7 (Octal) —
Punctured Data Support
Punctured Encoder No
Puncture Pattern -PP0 —
Puncture Pattern -PP1 —
Configuration XPGA
PFUs
2
LUT-4s Registers External
I/Os sysMEM
EBRs f
MAX
(MHz) Latency
3
conv_enco_xp_1_001.lpc 6 8 22 7 N/A 510 3
1. Performance and utilization characteristics using ispLEVER v.3.0 software and targeting the LFX1200B, package FE680, speed 4. Synthe-
sized using Synplicity's Synplify Pro v.7.1.1. When using this IP core in a different density, package, speed, or g rade within the ispXPGA fam-
ily, performance and utilization may vary slightly.
2. Programmable Function Unit (PFU) is a standard logic block of Lattice FPGA devices. For more information, check the data sheet of the
device.
3. The latency values are for
din
to
dout
with
din_valid
is high whenever
rfi
is high. The
din
to
dout
latency relationship can be
explained as follows: For Non-punctured encoders , the latency value is 3 when Constraint Length is greater than 4 or else the value is 2. For
punctured encoders, the latency value is (Output Rate + 6) when Constraint Length is greater than 4 or else the value is (Output Rate + 4).
