Features * * * * * * * * * * * * * * * * 18SPECint95, 16SPECfp95 @ 266 MHz with 1-MB L2 @ 200 MHz 3.2 GFLOPS @ 400 MHz (Peak Performance) Selectable Bus Clock (14 CPU Bus Dividers Up To 9x) Seven Selectable Core-to-L2 Frequency Divisors Selectable Interface Voltage Below 3.3V (1.8V, 2.5V) PD Typical 5W @ 400 MHz, Full Operating Conditions Nap, Doze and Sleep Modes for Power Saving Superscalar (Three Instructions per Clock Cycle) 4-GB Direct Addressing Range 4P.Byte of Virtual Memory 64-bit Data and 32-bit Address Bus Interface 32-KB Instruction and Data Cache Eight Independent Execution Units and Three Register Files Write-back and Write-through Operations fINT Max = 400 MHz fBUS Max = 100 MHz Description The PC7400 is the first microprocessor that uses the fourth (G4) full implementation of the PowerPC Reduced Instruction Set Computer (RISC) architecture. It is fully JTAGcompliant. The PC7400 maintains some of the characteristics of G3 microprocessors: * The design is superscalar, capable of issuing three instructions per clock cycle into six independent execution units * The microprocessor provides four software controllable power-saving modes and a thermal assist unit management * The microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches with dedicated L2 cache interface with on-chip L2 tags PowerPC7400 RISC Microprocessor PC7400 Preliminary Specification -site In addition, the PC7400 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency protocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVec technology instruction set. New features have been developed to make latency equal for double-precision and single-precision floating-point operations involving multiplication. Additionally, in memory subsystem (MSS) bandwidth, the PC7400 offers an optional, high-bandwidth MPX bus interface. Screening * CBGA upscreenings based on Atmel standards * Full military temperature range (Tj = -55C, +125C), industrial temperature range (Tj = -40C, +110C) * CI-CGA package versions Rev. 2103A-06/01 1 Instruction Queue 6-word Branch Processing Unit 128-entry ITLB 64-entry BTIC/512-entry BHT LR/CTR Tags IBAT Array 32-Kbyte iCache Data MMU Dispatch Unit EA SRs (Original) 2 Instructions PA 128-entry DTLB Tags DBAT Array 32-Kbyte DCache 64-bit (2 Instructions) Reservation Station Reservation Station Reservation Station Reservation Station VR File Reservation Station Reservation Station 2-entry GPR File 6 Rename Buffers 6 Rename Buffers Vector ALU Integer Unit 1 Integer Unit 2 Add-MultiplyCompare - Add - - Add EA Calculation Finished Stores Completed Stores System Register Unit Reservation Station 6 Rename Buffers Load/Store Unit 32-bit Vector Permute Unit FPR File 64-bit Floating 64-bit Point Unit Add-MultiplyCompare VSIU VCIU VFPU FPSCR VSCR 32-bit 32-bit 128-bit 128-bit Bus Interface Unit Completion Unit Data Reload Table 8-entry Reorder Buffer Data Reload Queue Instruction Reload Queue Instruction Reload Table Load Fold Queue L1 Operations Queue 32-bit 60x/MAX Address Bus 2103A-06/01 64-bit 60x Data Bus/128-bit MAX Data Bus 19-bit L2 Address Bus 64-/128-bit L2 Data Bus L2 Bus Interface Unit L2 Data Transaction L2 Miss L2 Castout L2 Controller L2 Tags Block Diagram PC7400 Fetcher SRs (Shadow) Figure 1. PC7400 Microprocessor Block Diagram 2 Instruction MMU Instruction Unit PC7400 General Parameters Features Table 1 provides a summary of the general parameters of the PC7400. Table 1. Device Parameters Parameter Description Technology 0.18 m CMOS, five-layer metal Die size 7.86 mm x 10.58 mm (83 mm2) Transistor count 10.5 million Logic design Fully-static Packages Surface-mount, ceramic 360-ball or -column grid array (CBGA/CI-CGA) Core power supply 1.8V 100 mV dc (nominal; see Table 5 for recommended operating conditions) I/O power supply 1.8V 100 mV dc or 2.5V 100 mV dc or 3.3V 5% (input thresholds are configuration pin selectable) This section summarizes features of the PC7400's implementation of the PowerPC architecture. Major features of the PC7400 are as follows: * * * * * Branch processing unit - Four instructions fetched per clock - One branch processed per cycle (plus resolving two speculations) - Up to one speculative stream in execution, one additional speculative stream in fetch - 512-entry branch history table (BHT) for dynamic prediction - 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay slots Dispatch unit - Full hardware detection of dependencies (resolved in the execution units) - Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU) - Serialization control (predispatch, postdispatch, execution serialization) Decode - Register file access - Forwarding control - Partial instruction decode Completion - 8-entry completion buffer - Instruction tracking and peak completion of two instructions per cycle - Completion of instructions in program order while supporting out-of-order instruction execution, completion serialization and all instruction flow changes Fixed-point units (FXUs) that share 32 GPRs for integer operands - Fixed-point unit 1 (FXU1)--multiply, divide, shift, rotate, arithmetic, logical - Fixed-point unit 2 (FXU2)--shift, rotate, arithmetic, logical - Single-cycle arithmetic, shifts, rotates, logical 3 2103A-06/01 * * * * * 4 - Multiply and divide support (multi-cycle) - Early out multiply Three-stage floating-point unit and a 32-entry FPR file - Support for IEEE-754 standard single- and double-precision floating-point arithmetic - Three-cycle latency, one-cycle throughput (single or double precision) - Hardware support for divide - Hardware support for denormalized numbers - Time deterministic non-IEEE mode System unit - Executes CR logical instructions and miscellaneous system instructions - Special register transfer instructions AltiVec unit - Full 128-bit data paths - Two dispatchable units: vector permute unit and vector ALU unit - Contains its own 32-entry 128-bit vector register file (VRF) with six renames - The vector ALU unit is further sub-divided into the vector simple integer unit (VSIU), the vector complex integer unit (VCIU) and the vector floating-point unit (VFPU). - Fully pipelined Load/store unit - One-cycle load or store cache access (byte, half-word, word, double-word) - Two-cycle load latency with one-cycle throughput - Effective address generation - Hits under misses (multiple outstanding misses) - Single-cycle unaligned access within double-word boundary - Alignment, zero padding, sign extend for integer register file - Floating-point internal format conversion (alignment, normalization) - Sequencing for load/store multiples and string operations - Store gathering - Executes the cache and TLB instructions - Big- and little-endian byte addressing supported - Misaligned little-endian supported - Supports FXU, FPU, and AltiVec load/store traffic - Complete support for all four architecture AltiVec DST streams Level 1 (L1) cache structure - 32K 32-byte line, 8-way set associative instruction cache (iL1) - 32K 32-byte line, 8-way set associative data cache (dL1) - Single-cycle cache access - Pseudo least-recently-used (LRU) replacement - Data cache supports AltiVec LRU and transient instructions algorithm - Copy-back or write-through data cache (on a page-per-page basis) - Supports all PowerPC memory coherency modes - Non-blocking instruction and data cache PC7400 2103A-06/01 PC7400 * * * * - Separate copy of data cache tags for efficient snooping - No snooping of instruction cache except for ICBI instruction Level 2 (L2) cache interface - Internal L2 cache controller and tags; external data SRAMs - 512K, 1M and 2Mbyte 2-way set associative L2 cache support - Copyback or write-through data cache (on a page basis or for all L2) - 32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size - Supports pipelined (register-register) synchronous burst SRAMs and pipelined (register-register) late-write synchronous burst SRAMs - Core-to-L2 frequency divisors of /1, /1.5, /2, /2.5, /3, /3.5, and /4 supported - 64-bit data bus - Selectable interface voltages of 1.8, 2.5, and 3.3V Memory management unit - 128 entry, 2-way set associative instruction TLB - 128 entry, 2-way set associative data TLB - Hardware reload for TLBs - Four instruction BATs and four data BATs - Virtual memory support for up to four petabytes (252) of virtual memory - Real memory support for up to four gigabytes (232) of physical memory - Snooped and invalidated for TLBI instructions Efficient data flow - All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are 128 bits wide - dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF - L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s - Up to eight outstanding out-of-order cache misses between dL1 and L2/bus - Up to seven outstanding out-of-order transactions on the bus - Load folding to fold new dL1 misses into older outstanding load and store misses to the same line - Store miss merging for multiple store misses to the same line. Only coherency action taken (i.e., address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed). - Two-entry finished store queue and four-entry completed store queue between load/store unit and dL1 - Separate additional queues for efficient buffering of outbound data (castouts, write throughs, etc.) from dL1 and L2 Bus interface - New MPX bus extension to 60X processor interface - Mode-compatible with 60x processor interface - 32-bit address bus - 64-bit data bus - Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x supported - Selectable interface voltages of 1.8 and 3.3V 5 2103A-06/01 * * * Power management - Low-power design with thermal requirements very similar to PC740 and PC750 - 1.8V processor core - Selectable interface voltages below 3.3V can reduce power in output buffers - Three static power saving modes: doze, nap, and sleep - Dynamic power management Testability - LSSD scan design - IEEE 1149.1 JTAG interface - Array built-in self test (ABIST) - factory test only - Redundancy on L1 data arrays and L2 tag arrays Reliability and serviceability - 6 Parity checking on 60x and L2 cache buses PC7400 2103A-06/01 PC7400 Pin Assignment BGA360 Package Figure 2, Figure 3, Figure 4 and Figure 5 show top views of the packages available for the PC7400. Note that these drawings are not to scale. Figure 2. Top View of 360-pin CBGA and 360-ball CI-CGA Packages Pin A1 Index Figure 3. Top View of 360-pin CBGA and CI-CGA Packages 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B C D E F G H J K L M N P R T U V W 7 2103A-06/01 Figure 4. Cross-section of 360-ball CBGA Package View Substrate Assembly Die Encapsulant Figure 5. Cross-section of 360-column CI-CGA Package View Substrate Assembly Die Encapsulant Table 2. Pinout Listing for the PC7400, 360-ball CBGA Package I/F Voltages Supported(1) Signal Name Pin Number Active I/O 1.8V A[0:31] A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2 High I/O AACK N3 Low Input ABB AMON[0](12) L7 Low Output AP[0:3] C4, C5, C6, C7 High I/O ARTRY L6 Low I/O AVDD A8 BG H1 Low Input E7 Low Output W1 High Input GND CHK K11 Low Input CI C2 Low I/O CKSTP_IN B8 Low Input CKSTP_OUT D7 Low Output CLK_OUT E3 High Output DBB DMON[0](12) K5 Low Output DBG K1 Low Input BR (3, 8, 9) BVSEL (4, 8, 9) 8 1.8V 2.5V 1.8V N/A 3.3V 1.8V 3.3V PC7400 2103A-06/01 PC7400 Table 2. Pinout Listing for the PC7400, 360-ball CBGA Package (Continued) I/F Voltages Supported(1) Signal Name Pin Number Active I/O 1.8V DH[0:31] W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3, U4, R5 High I/O DL[0:31] M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2, V3, U3, W2 High I/O DP[0:7] L1, P2, M2, V2, M1, N2, T3, R1 High I/O DRDY(6, 8, 13) K9 Low Output DBWO DTI[0] D1 Low Input H6, G1 High Input EMODE A3 Low Input GBL B1 Low I/O GND D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16 HIT(6, 8) B5 Low Output HRESET B6 Low Input C11 Low Input L1_TSTCLK F8 High Input L2ADDR[0:16] L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18, H17, J14, J13, H19, G18 High Output L2ADDR[17](8) K19 High Output L2ASPARE W19 High Output L2AVDD L13 1.8V 1.8V 1.8V L2CE P17 Low Output L2CLKOUTA N15 High Output L2CLKOUTB L16 High Output L2DATA[0:63] U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18, V18, U18, V19, U19, T18, T17, R19, R18, R17, R15, P19, P18, P13, N14, N13, N19, N17, M17, M13, M18, H13, G19, G16, G15, G14, G13, F19, F18, F13, E19, E18, E17, E15, D19, D18, D17, C18, C17, B19, B18, B17, A18, A17, A16, B16, C16, A14, A15, C15, B14, C14, E13 High I/O L2DP[0:7] V14, U16, T19, N18, H14, F17, C19, B15 High I/O 1.8V 2.5V 3.3V DTI[1:2](10, 13) (7, 10) INT (2) (8) L2OVDD (11) L2SYNC_IN GND D15, E14, E16, H16, J15, L15, M16, K13, P15, R14, R16, T15, F15 L14 High Input 2.5V GND 3.3V GND 9 2103A-06/01 Table 2. Pinout Listing for the PC7400, 360-ball CBGA Package (Continued) I/F Voltages Supported(1) Signal Name Pin Number Active I/O 1.8V 2.5V 3.3V L2SYNC_OUT M14 High Output L2_TSTCLK F7 High Input L2VSEL(1, 3, 8, 9) A19 High Input GND HRESET 3.3V L2WE N16 Low Output G17 High Output LSSD_MODE F9 Low Input MCP B11 Low Input OVDD D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4, R6, R9, R11, T5, T8, T12 1.8V 3.3V PLL_CFG[0:3] A4, A5, A6, A7 High Input QACK B2 Low Input QREQ J3 Low Output RSRV D3 Low Output SHD0(5, 8) B3 Low I/O (5, 8) B4 Low I/O SMI A12 Low Input SRESET E10 Low Input SYSCLK H9 Input TA F1 Low Input TBEN A2 High Input TBST A11 Low Output TCK B10 High Input B7 High Input TDO D9 High Output TEA J1 Low Input C8 High Input A10 Low Input TS K7 Low I/O TSIZ[0:2] A9, B9, C9 High Output TT[0:4] C10, D11, B12, C12, F11 High I/O WT C3 Low I/O VDD G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12 L2ZZ (2) SHD1 TDI (9) TMS(9) TRST 10 (9) 1.8V 1.8V 1.8V PC7400 2103A-06/01 PC7400 Note: 1. OVDD supplies power to the processor bus, JTAG and all control signals except the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:16], L2ASPARE, L2DATA[0:63], L2DP[0:7] and L2SYNC_OUT) and the L2 control signals; VDD supplies power to the processor core and the PLL and DLL (after filtering to become AVDD and L2AVDD respectively). These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL/L2VSEL pin configurations of Table 4 and the voltage supplied. For actual recommended value of VIN or supply voltages, see Table 5. 2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. 3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD (selects 3.3V), OGND (selects 1.8V), or to HRESET (selects 2.5V). The processor bus and L2 bus support all three options (see Table 4). 4. Connect to HRESET to trigger post power-on-reset (por) internal memory test. 5. Ignored in 60x bus mode. 6. Unused output in 60x bus mode. 7. Deasserted (pulled high) at HRESET for 60x bus mode. 8. Uses one of 9 existing no-connects in PC750's 360-ball BGA package. 9. Internal pull-up on die. 10. Reuses PC750's DRTRY, DBDIS and TLBISYNC pins (DTI1, DTI2 and EMODE respectively). 11. The VOLTDET pin position on the PC750 360-ball CBGA package is now an L2OVDD pin on the PC7400 360-ball CBGA package. 12. Output only for PC7400, was I/O for PC750. 13. Enhanced mode only. 11 2103A-06/01 Signal Description Figure 6. PC7400 Microprocessor Signal Groups L2OVDD L2AVDD BR Address Arbitration BG ABB Address Start TS A[0:31] Address Bus AP[0:3] TT[0:4] TBST TSIZ[0:2] Transfer Attribute GBL WT CI 1 17 64 1 8 1 1 1 1 1 32 2 4 1 5 1 1 1 1 3 1 1 1 1 1 1 PCX7400 1 1 CHK Address Termination AACK ARTRY DBG Data Arbitration DBWO, DTI(0) D[0:63] DP[0:7] 1 1 2 1 1 1 1 1 1 1 1 1 64 1 8 4 DBDIS/DTI(2) TA Data Termination 1 1 DBB, DMON(0) Data Transfer 1 DTI1 TEA 1 1 1 12 L2 Cache Address/Data L2SPARE L2CE L2WE L2CLKOUTA, L2CLKOUTB L2 Cache Clock/Control L2SYNC_OUT L2SYNC_IN L2ZZ INT SMI MCP SRESET HRESET CKSTP_IN Interrupts Reset CKSTP_OUT HIT SHDO, SHD1 RSRV TBEN EMODE QREQ Processor Status Control QACK DRDY SYSCLK PLL_CFG[0:3] CLK_OUT JTAG:COP 3 1 OVDD L2DP[0:7] Factory Test 1 VDD L2DATA[0:63] 5 1 1 L2ADDR[0:17] L1_TSTCLK, L2_TSTCLK BVSEL L2VSEL Clock Control Test Interface LSSD_MODE I/O Voltage Selection AVDD PC7400 2103A-06/01 PC7400 Detailed Specification Scope This drawing describes the specific requirements for the microprocessor PC7400 in compliance with Atmel-Grenoble standard screening. Applicable Documents 1. MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535: Appendix A: General specifications for microcircuits Requirements General The microcircuits are in accordance with the applicable documents and as specified herein. Design and Construction Terminal Connections Absolute Maximum Ratings Depending on the package, the terminal connections are as shown in Table 2, Table 5 and Figure 6. Table 3. Absolute Maximum Ratings(1) Symbol Characteristic Core supply voltage VDD Value Unit (4) V (4) -0.3 to 2.1 AVDD PLL supply voltage -0.3 to 2.1 V L2AVDD L2 DLL supply voltage -0.3 to 2.1(4) V OVDD 60x bus supply voltage -0.3 to 3.465(3) V (3) V (2, 5) V L2OVDD L2 bus supply voltage VIN Processor bus input voltage VIN L2 bus input voltage VIN TSTG Notes: -0.3 to 3.465 -0.3 to 3.6 -0.3 to 3.6V(2, 5) V JTAG signal input voltage -0.3 to 3.6 V Storage temperature range -65 to 150 C 1. Functional and tested operating conditions are given in Table 5. Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: VIN must not exceed OVDD or L2OVDD by more than 0.3V at any time including during power-on reset. 3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0V at any time including during power-on reset. 4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4V at any time including during power-on reset. In addition, operation at nominal VDD/AVDD/L2AVDD greater than nominal L2OVDD or OVDD in the 1.8V input threshold select mode can cause erratic operation and AC timing values worse than described in this specification. 5. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 7. 13 2103A-06/01 Figure 7. Overshoot/Undershoot Voltage (L2)OVDD + 20% (L2)OVDD + 5% (L2)OVDD VIH VIL GND GND - 0.3V GND - 0.7V Not to exceed 10% of tSYSCLK The PC7400 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The PC7400 "core" voltage must always be provided at nominal 1.8V (see Table 5 for actual recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 4. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the OVDD or L2OVDD power pins. Table 4. Input Threshold Voltage Setting BVSEL Signal Processor Bus Input Threshold is Relative to: L2VSEL Signal L2 Bus Input Threshold is Relative to: 0(1) 1.8V 0 1.8 HRESET(1, 2) 2.5V HRESET 2.5 3.3V 1 3.3 1 (1) Notes: 14 1. Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied. 2. To select the 2.5 volt threshold option, L2VSEL/BVSEL should be tied to HRESET so that the two signals change state together. PC7400 2103A-06/01 PC7400 Recommended Operating Conditions Table 5. Recommended Operating Conditions(1) Recommended Value Unit Core supply voltage 1.8 100 mV V AVDD PLL supply voltage 1.8 100 mV V L2AVDD L2 DLL supply voltage 1.8 100 mV V OVDD Processor bus supply voltage BVSEL = 0 1.8 100 mV V BVSEL = HRESET 2.5 100 mV V BVSEL = 1 3.3 165 mV V L2VSEL = 0 1.8 100 mV V L2OVDD L2VSEL = HRESET 2.5 100 mV V L2OVDD L2VSEL = 1 3.3 165 mV V Processor bus GND to OVDD V GND to L2OVDD V GND to OVDD V -55 to 125 C Symbol Characteristic VDD OVDD OVDD L2OVDD VIN L2 bus supply voltage Input voltage VIN L2 Bus VIN JTAG Signals Tj Note: Die-junction temperature These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Thermal Characteristics Package Characteristics Table 6. Package Thermal Characteristics Symbol Characteristic Value Rating JC CBGA and CI-CBGA packages thermal resistance, die junctionto-case thermal resistance (typical) 0.03 C/W JB CBGA package thermal resistance, die junction-to-lead thermal resistance (typical) 3.8 C/W JB CI-CBGA package thermal resistance, die junction-to-lead thermal resistance (typical) 4 C/W The board designer can choose between several commercially available heat sink types to place on the PC7400. For exposed-die packaging technology as in Table 6, the intrinsic conduction thermal resistance paths are shown in Figure 8. Internal Package Conduction Resistance Figure 8 depicts the primary heat transfer path for a package with an attached heat sink mounted on a printed circuit board. Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material) and finally to the heat sink where it is removed by forced-air convection. 15 2103A-06/01 Since the silicon thermal resistance is quite small, for a first-order analysis the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. Figure 8. C4 Package with Heat Sink Mounted on a Printed Circuit Board Radiation External Resistance Convection Heat Sink Thermal Interface Material Die Junction Internal Resistance Die/Package Package/Leads Printed Circuit Board External Resistance Thermal Management Assistance Radiation Convection The PC7400 incorporates a thermal management assist unit (TAU) composed of a thermal sensor, digital-to-analog converter, comparator, control logic and dedicated special-purpose registers (SPRs). More information on the use of this feature is given in the MPC750P RISC Microprocessor User's Manual. Table 7. Thermal Sensor Specifications at VDD = AVDD = L2VDD = 1.8V 100 mV, OVDD = L2OVDD = 3.3 5% Vdc, GND = 0Vdc, -55C Tj 125C Characteristic Temperature range Max Unit 0 127 C 20 s Resolution(3) 4 C Notes: 16 Min Comparator settling time(2) Accuracy Thermal Management Information (1) -12 +12 C 1. The temperature is the junction temperature of the die. The thermal assist unit's raw output does not indicate an absolute temperature, but it must be interpreted by software to derive the absolute junction temperature. For information about the use and calibration of the TAU, see Motorola application note, "Programming the Thermal Assist Unit in the MPC750 Microprocessor". 2. The comparator settling time value must be converted into the number of CPU clocks that need to be written into the THRM3 SPR. 3. The resolution is guaranteed by design and characterization. This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design - the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package and mounting clip and screw assembly; see Figure 9. This spring force should not exceed 5.5 pounds of force. Ultimately, the final selection of an appropriate heat sink depends on many factors such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly and cost. PC7400 2103A-06/01 PC7400 Figure 9. CBGA Package Cross-section with Heat Sink Options Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material Option Printed-Circuit Board Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 10 shows the thermal performance of three thin-sheet thermalinterface materials (silicone, graphite/oil, floroether oil), a bare joint and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 9). This spring force should not exceed 5.5 pounds of force. Therefore, synthetic grease offers the best thermal performance, considering the low interface pressure. The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet must have adequate mechanical strength to meet equipment shock/vibration requirements. 17 2103A-06/01 Figure 10. Thermal Performance of Different Thermal Interface Materials Silicone Sheet (0.006 inch) Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease Specific Thermal Resistance (Kin2/W) 2 1.5 1 0.5 0 0 Heat Sink Selection Example 10 20 30 40 50 Contact Pressure (psi) 60 70 80 For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: T j = T a + T r + ( jc + int + sa ) x P d where: Tj = die-junction temperature Ta = inlet cabinet ambient temperature Tr = air temperature rise within the computer cabinet jc = junction-to-case thermal resistance int = adhesive or interface material thermal resistance sa = heat sink base-to-ambient thermal resistance Pd = power dissipated by the device During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 5. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30C to 40C. The air temperature rise within a cabinet (Tr) may be in the range of 5C to 10C. The thermal resistance of the thermal interface material (int) is typically about 1C/W. Assuming a Ta of 30C, a Tr of 5C, a CBGA package jc = 0.03, and a power consumption (Pd) of 5.0 watts, the following expression for Tj is obtained: T j = 30 C + 5 C + ( 0.03 C W + 1.0 C W + sa ) x 4.5 W 18 PC7400 2103A-06/01 PC7400 For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (sa) versus airflow velocity is shown in Figure 11. Figure 11. Thermalloy #2328B Heat Sink-to-ambient Thermal Resistance vs. Airflow Velocity 8 Thermalloy #2328B Pin-fin Heat Sink (25 x28 x 15 mm) Heat Sink Thermal Resistance (C/W) 7 6 5 4 3 2 1 0 0.5 1 1.5 2 2.5 3 3.5 Approach Air Velocity (m/s) Assuming an air velocity of 0.5 m/s, the effective Rsa is 7C/W, thus T j = 30 C + 5 C + ( 0.03 C W + 1.0 C W + 7 C W ) x 5 W , resulting in a die-junction temperature of approximately 75C which is well within the maximum operating temperature of the component. Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering and Aavid Engineering offer different heat sink-to-ambient thermal resistances and may or may not need air flow. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure of merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but of the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature - airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, it is recommended to use conjugate heat transfer models for the board, as well as system-level designs. To expedite 19 2103A-06/01 system-level thermal analysis, several "compact" thermal-package models are available within FLOTHERM(R). These are available upon request. Power Consideration Power Management The PC7400 provides four power modes, selectable by setting the appropriate control bits in the MSR and HIDO registers. The four power modes are: * Full-power: This is the default power state of the PC7400. The PC7400 is fully powered and the internal functional units are operating at the full processor clock speed. If the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution or external hardware. * Doze: All the functional units of the PC7400 are disabled except for the time base/decrementer registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or machine check brings the PC7400 into the full-power state. The PC7400 in doze mode maintains the PLL in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to the full-power state takes only a few processor clock cycles. * Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the PLL in a powered state. The PC7400 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or a machine check input (MCP). A return to full-power state from a nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK is negated, the processor is put in doze mode to support snooping. * Sleep: Sleep mode minimizes power consumption by disabling all internal functional units, after which external system logic may disable the PLL and SYSCLK. Returning the PC7400 to the full-power state requires the enabling of the PLL and SYSCLK, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset or a machine check input (MCP) signal after the time required to relock the PLL. Power Dissipation Table 8. Power Consumption for PC7400 Processor (CPU) Frequency Power Mode 350 MHz 400 MHz Unit 4.4 5.0 W 10.9 11.5 W 4.4 5.0 W 1.75 2.0 W 1.75 2.0 W Full-On Mode Typical(1, 3) Maximum (1, 2, 4) Doze Mode Maximum(1, 2) Nap Mode Maximum(1, 2) Sleep Mode Maximum(1, 2) 20 PC7400 2103A-06/01 PC7400 Table 8. Power Consumption for PC7400 (Continued) Processor (CPU) Frequency Power Mode 350 MHz 400 MHz Unit Typical(1, 3) 600 600 mW Maximum(1, 2) 1.0 1.0 W Sleep Mode - PLL and DLL Disabled Notes: 1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OVDD and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but is typically <10% of VDD power. Worst case power consumption for AVDD = 15 mw and L2AVDD = 15 mW. 2. Maximum power is measured at VDD = 1.9V while running an entirely cache-resident, contrived sequence of instructions which keep the execution units, including AltiVec, maximally busy. 3. Typical power is an average value measured at VDD = AVDD = L2AVDD = 1.8V, OVDD = L2OVDD = 3.3V in a system while running a codec application that is AltiVec intensive. 4. These values include the use of AltiVec. Without AltiVec operation, estimate a 25% decrease. 21 2103A-06/01 Electrical Characteristics Static Characteristics Table 9. DC Electrical Specifications (see Table 5 for recommended operating conditions) Nominal Bus Voltage(1) Symbol Characteristic Min Max Unit VIH Input high voltage (all inputs except SYSCLK)(2, 3) 1.8 0.65 x (L2)OVDD (L2)OVDD + 0.3 V VIH 2.5 1.7 (L2)OVDD + 0.3 V VIH 3.3 2.0 (L2)OVDD + 0.3 V 1.8 -0.3 0.35 x OVDD V 2.5 -0.3 0.2 x (L2)OVDD V 3.3 -0.3 0.8 V 1.8 1.5 OVDD + 0.3 V 3.3 2.4 OVDD + 0.3 V 1.8 -0.3 0.2 V 3.3 -0.3 0.4 V VIL VIL Input low voltage (all inputs except SYSCLK) VIL CVIH SYSCLK input high voltage CVIH CVIL SYSCLK input low voltage CVIL IIN Input leakage current, VIN = L2OVDD/OVDD(2, 3) 10 A ITSI High-Z (off-state) leakage current, VIN = L2OVDD/OVDD(2, 3, 5) 10 A VOH Output high voltage, IOH = -6 mA 1.8 (L2)OVDD 0.45 V VOH 2.5 1.7 V VOH 3.3 2.4 V VOL VOL Output low voltage, IOL = 6 mA VOL CIN Notes: 22 (2) Capacitance, VIN = 0V, f = 1 MHz(3, 4) 1.8 0.45 V 2.5 0.4 V 3.3 0.4 V 7.5 pF 1. Nominal voltages; see Table 5 for recommended operating conditions. 2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals. 3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals. 4. Capacitance is periodically sampled rather than 100% tested. 5. The leakage is measured for nominal OVDD and VDD, or both OVDD and VDD must vary in the same direction (for example, both OVDD and VDD vary by either +5% or -5%). PC7400 2103A-06/01 PC7400 Dynamic Characteristics After fabrication, parts are sorted by maximum processor core frequency as shown in "Clock AC Specifications" and tested for conformance to the AC specifications for that frequency. These specifications are for valid processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency. Clock AC Specifications Table 10 provides the clock AC timing specifications as defined in Figure 12. Table 10. Clock AC Timing Specifications (See Table 5 for recommended operating conditions) Maximum Processor Core Frequency 350 MHz Symbol fCORE fVCO (1) (1) fSYSCLK (1) tSYSCLK tKR & tKF (2) tKR & tKF (3) tKHKL/tSYSCLK Note: Characteristic Min Max Min Max Unit Processor frequency 300 350 300 400 MHz VCO frequency 600 700 600 800 MHz SYSCLK frequency 25 100 25 100 MHz SYSCLK cycle time 10 40 7.5 40 ns 1.0 1.0 ns 0.5 0.5 ns 60 % SYSCLK rise and fall time (4) 400 MHz SYSCLK duty cycle measured at OVDD/2 40 60 40 SYSCLK jitter(5) 150 150 ps Internal PLL relock time(6) 100 100 s 1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in "Clock Selection" on page 38 for valid PLL_CFG[0:3] settings 2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OVDD = 3.3V nominal. 3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V when OVDD = 1.8V nominal. 4. Timing is guaranteed by design and characterization. 5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design. 6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the poweron reset sequence. 23 2103A-06/01 Figure 12. SYSCLK Input Timing Diagram tKR tSYSCLK tKF tKHKL CVIH SYSCLK VM VM VM CVIL Note: Processor Bus AC Specifications VM = Midpoint Voltage (OVDD/2) Table 11 provides the processor AC timing specifications for the PC7400 as defined in Figure 13 and Figure 15. Timing specifications for the L2 bus are provided in "L2 Bus AC Specifications" on page 30. Table 11. Processor Bus AC Timing Specifications(1) at VDD = AVDD = 1.8V 100mV; -55C =Tj =125C, OVDD = 3.3V 165mV or OVDD = 2.5V 100mV or OVDD = 1.8V 100mV 350, 400 MHz Symbol tMVRH 24 (2) (3, 4, 5, 6) Parameter Min Max Unit Mode select input setup to HRESET 8 tSYSCLK tMXRH(2, 3, 5) HRESET to mode select input hold 0 ns tAVKH(7) tTSVKH tDVKH(8) tARVKH tIVKH(9) Setup Times Address/Transfer Attribute Transfer Start (TS) Data/Data Parity ARTRY/SHD0/SHD1 All Other Inputs 1.6 1.6 1.6 1.6 1.6 tAXKH(7) tTSXKH tDXKH(8) tARXKH tIXKH(9) Input Hold Times Address/Transfer Attribute Transfer Start (TS) Data/Data Parity ARTRY/SHD0/SHD1 All Other Inputs 0 0 0 0 0 tKHAV(7) tKHTSV tKHDV(8) tKHDPV(8) tKHARV tKHOV(10) Valid Times Address/Transfer Attribute TS, ABB, DBB Data Data Parity ARTRY/SHD0/SHD1 All Other Outputs tKHAX(7) tKHTSX tKHDX(8) tKHARX tKHOX(10) Output Hold Times Address/Transfer Attribute TS, ABB, DBB Data/Data Parity ARTRY/SHD0/SHD1 All Other Outputs 0.75 0.75 0.6 0.75 0.75 tKHOE SYSCLK to Output Enable 0.5 ns ns 3.2 3.4 3.5 3.5 2.5 3.2 ns ns ns PC7400 2103A-06/01 PC7400 Table 11. Processor Bus AC Timing Specifications(1) at VDD = AVDD = 1.8V 100mV; -55C =Tj =125C, OVDD = 3.3V 165mV or OVDD = 2.5V 100mV or OVDD = 1.8V 100mV 350, 400 MHz Symbol (2) Parameter Min Max Unit tKHOZ SYSCLK to Output High Impedance (all except TS, ABB/AMON[0], ARTRY/SHD, DBB/DMON[0]) 4.0 ns tKHABPZ(5, 11, 13) SYSCLK to TS, ABB/AMON[0], DBB/DMON[0] High Impedance after precharge 1.0 tSYSCLK tKHARP(5, 12, 13) Maximum Delay to ARTRY/SHD0/SHD1 Precharge 1 tSYSCLK tKHARPZ(5, 12, 13) SYSCLK to ARTRY/SHD0/SHD1 High Impedance After Precharge 2 tSYSCLK Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question. All output timings assume a purely resistive 50 ohm load (see Figure 14). Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias and connectors in the system. 2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. tKHOV symbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position of the reference and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). For additional explanation of AC timing specifications in Motorola PowerPC microprocessors, see the application note "Understanding AC Timing Specifications for PowerPC Microprocessors." 3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 15). 4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL re-lock time during the poweron reset sequence. 5. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds(ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0:3] 7. Address/Transfer Attribute signals are composed of the following - A[0:31], AP[0:3], TT[0:4], TBST, TSIZ[0:2], GBL, WT, CI. 8. Data signals are composed of the following - DH[0:31], DL[0:31]; Data Parity signals are composed of DP[0:7]. 9. All other input signals are composed of the following: AACK, BG, CKSTP_IN, DBG, DBWO/DTI[0], DTI[1:2], HRESET, INT, MCP, QACK, SMI, SRESET, TA, TBEN, TEA, TLBISYNC. 10. All other output signals are composed of the following - BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV 11. According to the 60x bus protocol, TS, ABB and DBB are driven only by the currently active bus master. They are asserted low then precharged high before returning to high-Z as shown in Figure 13. The nominal precharge width for TS, ABB or DBB is 0.5 x tSYSCLK, i.e., less than the minimum tSYSCLK period, to ensure that another master asserting TS, ABB, or DBB on the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The high-Z behavior is guaranteed by design. 25 2103A-06/01 12. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; i.e., it should be high-Z as shown in Figure 13 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The high-Z behavior is guaranteed by design. 13. Guaranteed by design and not tested. Figure 13. Input/Output Timing Diagram VM VM VM SYSCLK tAVKH tAXKH tTSVKH tTSXKH tDVKH tDXKH tARVKH tARXKH tIVKH tIXKH All Inputs tKHAV tKHAX tKHDV tKHDX tKHDPV All Outputs (except TS, ABB, ARTRY, DBB) All Outputs (except TS, ABB, ARTRY, DBB) tKHOX tKHOV tKHOE tKHOZ tKHABPZ TS, ABB/AMON[0], DBB/DMON[0] tKHTSV tKHTSV tKHTSX tKHARPZ tKHARP ARTRY, tKHARV SHD0, SHD1 26 tKHARV tKHARX PC7400 2103A-06/01 PC7400 Figure 14. AC Test Load for the L2 Interface Output OVDD Z0 = 50 Ohms RL = 50 Ohms Figure 15. Mode Input Timing Diagram VM HRESET tMVRH tMXRH MODE SIGNALS where VM = Midpoint Voltage (OVDD/2) L2 Clock AC Specifications The L2CLK frequency is programmed by the L2 configuration register (L2CR[4:6]) core-to-L2 divisor ratio. See Table 17 for example core and L2 frequencies at various divisors. Table 12 provides the potential range of L2CLK output AC timing specifications as defined in Figure 16. The minimum L2CLK frequency of Table 12 is specified by the maximum delay of the internal DLL. The variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock (divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below this minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase aligned with the PC7400 core clock at the SRAMs. The maximum L2CLK frequency shown in Table 12 is the core frequency divided by one. Very few L2 SRAM designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK frequency for any application of the PC7400 will be a function of the AC timings of the PC7400, the AC timings for the SRAM, bus loading and printed circuit board trace length. Atmel is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed part on a functional tester at the maximum frequencies of Table 12. Therefore, functional operation and AC timing information are tested at core-to-L2 divisors of 2 or greater. L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC timings of Table 13 are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs. However, since in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the signals of Table 13 are referenced to this signal rather than the not-externally-visible internal L2CLK. During manufacturing test, these times are actually measured relative to SYSCLK. 27 2103A-06/01 Table 12. L2CLK Output AC Timing Specifications at recommended operating conditions (See Table 5) 350 MHz Symbol Parameter Min Max Min Max Unit fL2CLK(1, 4) L2CLK frequency 100 350 133 400 MHz L2CLK cycle time 2.86 10 2.5 7.5 ns tL2CLK tCHCL/tL2CLK (2) L2CLK duty cycle Internal DLL-relock time 50 (3) DLL capture window(5) tL2CSKW L2CLKOUT output-tooutput skew(6) L2CLKOUT output jitter(6) Notes: 28 400 MHz 50 640 0 % 640 10 0 L2CLK 10 ns 50 50 ps 150 150 ps 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. The maximum L2LCK frequency will be system-dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading. 2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage. 3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization. 4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL. 5. Allowable skew between L2SYNC_OUT and L2SYNC_IN. 6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects L2CLKOUT and the L2 address/data/control signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L2 timing analysis. PC7400 2103A-06/01 PC7400 Figure 16. L2CLK_OUT Output Timing Diagram L2 Single-Ended Clock Mode tL2CLK tCHCL tL2CR L2CLK_OUTA VM VM VM L2CLK_OUTB VM VM VM tL2CF tL2CSKW L2SYNC_OUT VM VM L2 Differential Clock Mode VM VM tL2CLK tCHCL L2CLK_OUTB L2CLK_OUTA VM VM VM L2SYNC_OUT VM VM VM Note: VM = Midpoint Voltage (L2OVDD/2) 29 2103A-06/01 L2 Bus AC Specifications Table 13 provides the L2 bus interface AC timing specifications for the PC7400 as defined in Figure 17 and Figure 18 for the loading conditions described in Figure 19. Table 13. L2 Bus Interface AC Timing Specifications at V DD = AV DD = L2AV DD = 1.8V 100mV; -55C =Tj 125C, L2OVDD = 3.3V 165mV or L2OVDD = 2.5V 100mV or L2OVDD = 1.8V100mV 350, 400 MHz Symbol Parameter tL2CR & tL2CF(1) L2SYNC_IN rise and fall time tDVL2CH(2) Setup Times Data and parity tDXL2CH (2) tL2CHOV (3, 4) tL2CHOX(3) tL2CHOZ Notes: 30 Input Hold Times Data and parity Min L2SYNC_IN to high impedance All outputs when L2CR[14:15] = 00 All outputs when L2CR[14:15] = 01 All outputs when L2CR[14:15] = 10 All outputs when L2CR[14:15] = 11 Unit 1.0 ns ns 1.5 ns 0.0 ns Valid Times All outputs when L2CR[14:15] = 00 All outputs when L2CR[14:15] = 01 All outputs when L2CR[14:15] = 10 All outputs when L2CR[14:15] = 11 Output Hold Times All outputs when L2CR[14:15] = 00 All outputs when L2CR[14:15] = 01 All outputs when L2CR[14:15] = 10 All outputs when L2CR[14:15] = 11 Max 2.5 3.0 3.5 4.0 ns 0.4 1.0 1.4 1.8 ns 2.0 2.5 3.0 3.5 1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD. 2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L2SYNC_IN (see Figure 17). Input timings are measured at the pins. 3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 ohm load (see Figure 19). 4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous burst RAMs, L2CR[14:15] = 00 is recommended. For pipelined latewrite synchronous burst SRAMs, L2CR[14:15] = 10 is recommended. PC7400 2103A-06/01 PC7400 Figure 17. L2 Bus Input Timing Diagram tL2CR tL2CF VM L2SYNC_IN tDVL2CH tDXL2CH L2 Data and Data Parity Inputs Note: VM = Midpoint Voltage (L2OVDD/2) Figure 18. L2 Bus Output Timing Diagram VM VM L2SYNC_IN tL2CHOV tL2CHOX All Outputs tL2CHOZ L2DATA BUS Note: VM = Midpoint Voltage (L2OVDD/2) Figure 19. AC Test Load for the L2 Interface Output L2OVDD/2 Z0 = 50 Ohms RL = 50 Ohms 31 2103A-06/01 IEEE 1149.1 AC Timing Specifications Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 20, Figure 21, Figure 22 and Figure 23. Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) (1) at recommended operating conditions (see Table 5) Symbol Parameter Min Max Unit fTCLK TCK frequency of operation 0 33.3 MHz t TCLK TCK cycle time 30 ns tJHJL TCK clock pulse width measured at 1.4V 15 ns tJR & tJF TCK rise and fall times 0 (2) TRST assert time 25 (3) Input Setup Times Boundary-scan data TMS, TDI (3) Input Hold Times Boundary-scan data TMS, TDI 20 25 tJLDV(4) tJLOV Valid Times Boundary-scan data TDO 4 4 20 25 tJLDX tJLOX Output Hold Times Boundary-scan data TDO tJLDZ(4, 5) tJLOZ(5) TCK to output high impedance Boundary-scan data TDO 3 3 19 9 tTRST tDVJH tIVJH tDXJH tIXJH Notes: 2 ns ns ns 4 0 ns ns ns 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 ohm load (see Figure 20). Time-of-flight delays must be added for trace lengths, vias and connectors in the system. 2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 3. Non-JTAG signal input timing with respect to TCK. 4. Non-JTAG signal output timing with respect to TCK. 5. Guaranteed by design and characterization Figure 20. Alternate AC Test Load for the JTAG Interface Output OVDD/2 Z0 = 50 Ohms RL = 50 Ohms 32 PC7400 2103A-06/01 PC7400 Figure 21. JTAG Clock Input Timing Diagram tJR tJF VM TCLK tJHJL tTCLK Note: VM = Midpoint Voltage (OVDD/2) Figure 22. TRST Timing Diagram tT125T VM VM T125T Note: VM = Midpoint Voltage (OVDD/2) Figure 23. Boundary-scan Timing Diagram TCK VM VM tDVJH Boundary Data Inputs tDXJH Input Data Valid tJLDV tJLDX Boundary Data Outputs Output Data Valid tJLDZ Boundary Data Outputs Note: Output Data Valid VM = Midpoint Voltage (OVDD/2) 33 2103A-06/01 Figure 24. Test Access Port Timing Diagram TCK VM VM tIVJH TDI, TMS tIXJH Input Data Valid tJLOV tJLOX TDO Output Data Valid tJLOZ TDO Note: Output Data Valid VM = Midpoint Voltage (OVDD/2) Preparation for Delivery Packaging Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. Certificate of Compliance Atmel-Grenoble supplies a certificate of compliance with each shipment of parts, confirming the parts are in compliance either with MIL-PRF-883 and guaranteeing the parameters not tested at extreme temperatures for the entire temperature range. Handling MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of static buildup. However, the following handling practices are recommended: 34 * Devices should be handled on benches with conductive and grounded surfaces. * Ground test equipment, tools and operator. * Do not handle devices by the leads. * Store devices in conductive foam or carriers. * Avoid use of plastic, rubber or silk in MOS areas. * Maintain relative humidity above 50 percent if practical. * For CI-CGA packages, use specific tray to take care of the highest height of the package compared with the normal CBGA. PC7400 2103A-06/01 PC7400 Package Mechanical Data Parameters The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead CBGA and CI-CGA. Table 15. Package Parameters Parameter Package outline 25 mm x 25 mm Interconnects 360 (19 x 19 ball array minus one) Pitch 1.27 mm (50 mil) Minimum module height 2.65 mm (CBGA), 3.65 mm (CI-CGA) Maximum module height 3.20 mm (CBGA), 4.20 mm (CI-CGA) Ball or column diameter 0.89 mm (35 mil) The following remarks apply to Figure 25 and Figure 26: * Dimensions and tolerancing are as per ASME Y14.5M-1994. * All dimensions are in millimeters. * Top side A1 corner index is a metalized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array. * Dimension B is the maximum solder ball diameter measured parallel to datum A. * D2 and E2 define the area occupied by the die and underfill. Actual size of this area may be smaller than shown. D3 and E3 are the minimum clearance from the package edge to the chip capacitors. 35 2103A-06/01 Figure 25. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball CBGA Package 2X 0.2 D PIN A1 INDEX 2X 0.2 B A 360 X C6 2 0.15 1 A A3 A4 C5 E2 E4 C1 1 1 2 1 2 1 C4 0.35 2 2 A E C2 C3 1 2X 2 0.2 C D4 D3 D2 E 3 TOP VIEW D1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 W V U T R P N M L K J H G F E D C B A K K G 360X B A1 A E1 GND : C1.2 C1.1 C3.2 C4.2 C5.2 C6.2 0.3 T 0.15 T BOTTOM VIEW E F C1.1, C2.1 : L2OVDD C3.1, C6.1 : VDD C4.1, C5.1 : OVDD Parameter Min Max Parameter Min Max A 2.62 3.20 D3 2.75 - A1 0.8 1.00 D4 6.00 A2 1.10 1.30 E 25.00 BASIC A3 - 0.6 E1 22.86 BASIC A4 0.82 0.9 E2 - 15 B 0.82 0.93 E3 3.00 - D 25.00 BASIC E4 1.5 D1 22.86 BASIC G 1.27 BASIC D2 36 A2 - 13 PC7400 2103A-06/01 PC7400 Figure 26. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-column CI-CGA Package 2X 0.2 D PIN A1 INDEX 2X 0.2 B A 360 X C6 0.15 2 1 A A3 A4 C5 E2 E4 C1 1 1 2 1 2 1 C4 0.35 2 2 A E C2 C3 1 2X 2 0.2 C D4 D3 D2 E3 TOP VIEW D1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 W V U T R P N M L K J H G F E D C B A K A1 A E1 GND : C1.2 C1.1 C3.2 C4.2 C5.2 C6.2 K G A2 C1.1, C2.1 : L2OVDD 360X B 0.3 T 0.15 T E F C3.1, C6.1 : VDD C4.1, C5.1 : OVDD Parameter Min Max Parameter Min Max A 3.4 4.20 D3 2.75 - A1 1.545 1.695 D4 6.00 A2 1.10 1.30 E 25.00 BASIC A3 - 0.6 E1 22.86 BASIC A4 0.82 0.9 E2 - 15 B 0.82 0.93 E3 1.5 - D 25.00 BASIC E4 8.00 D1 22.86 BASIC G 1.27 BASIC D2 - 13 37 2103A-06/01 Clock Selection The PC7400's PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the PC7400 is shown in Table 16 for example frequencies. Table 16. PC7400 Microprocessor PLL Configuration Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_CFG[0:3] Bus-to-Core Multiplier Core-to-VCO Multiplier 0100 2x 2x 0110 2.5x 2x 1000 3x 2x 300 (600) 1110 3.5x 2x 350 (700) 1010 4x 2x 0111 4.5x 2x 300(600) 337 (675) 1011 5x 2x 333 (666) 375 (750) 1001 5.5x 2x 366 (733) 1101 6x 2x 300 (600) 0101 6.5x 2x 325 (630) 0010 7x 2x 350 (700) 0001 7.5x 2x 375 (750) 1100 8x 2x 400 (800) 0000 9x 2x Notes: 38 Bus 25 MHz Bus 33.3 MHz Bus 50 MHz Bus 66.6 MHz Bus 75 MHz 300 (600) Bus 100 MHz 400 (800) 400 (800) 300 (600) 0011 PLL off/bypass PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied 1111 PLL off PLL off, no core clocking occurs 1. PLL_CFG[0:3] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the PC7400; see "Clock AC Specifications" on page 23 for valid SYSCLK, core, and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In PLL-off mode, no clocking occurs inside the PC7400 regardless of the SYSCLK input. PC7400 2103A-06/01 PC7400 The PC7400 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock frequency of the PC7400. The divided-down clock is then phase-adjusted by an onchip delay-lock-loop (DLL) circuit and should be routed from the PC7400 to the external RAMs. A separate clock output, L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2 bus interface. The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register. Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the frequency of the PC7400 core and the phase adjustment range that the L2 DLL supports. Table 17 shows various examples of L2 clock frequencies that can be obtained for a given set of core frequencies. The minimum L2 frequency target is 100MHz. Table 17. Sample Core-to-L2 Frequencies Core Frequency in MHz /1 /1.5 /2 /2.5 /3 300 300 200 150 120 100 333 333 222 166 133 111 350 175 140 117 100 366 183 147 122 105 400 200 160 133 114 Note: /3.5 /4 100 The core and L2 frequencies are for reference only. Some examples may represent core or L2 frequencies which are not useful, not supported or not tested for by the PC7400; see "L2 Clock AC Specifications" on page 27 for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. System Design Information PLL Power Supply Filtering The AVDD and L2AVDD power signals are provided on the PC7400 to provide power to the clock generation phase-locked loop and L2 cache delay-locked loop, respectively. To ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 27 using surface mount capacitors with minimum effective series inductance (ESL) is recommended. The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby circuits. An identical but separate circuit should be placed as close as possible to the L2AVDD pin. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360-ball CBGA footprint without the inductance of vias. The L2AVDD pin may be more difficult to route but is proportionately less critical. Figure 27. PLL Power Supply Filter Circuit 10 AVDD (or L2AVDD) VDD 2.2 F 2.2 F GND 39 2103A-06/01 The notes in Table 3 contain cautions about the sequencing of the external bus voltages and core voltage of the PC7400 (when they are different). These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward-biased and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, one or both of the circuits of Figure 28 can be added to meet these requirements. The MUR420 Schottky diodes of Figure 28 control the maximum potential difference between the external bus and core power supplies on power-up and the 1N5820 diodes regulate the maximum potential difference on power-down. Figure 28. Example Voltage Sequencing Circuits 3.3V MUR420 MUR420 MUR420 1N5820 2.5V MUR420 MUR420 1.8V 1N5820 1N5820 Decoupling Recommendations 1.8V 1N5820 Due to the PC7400's dynamic power management feature, large address and data buses and high operating frequencies, the PC7400 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the PC7400 system and the PC7400 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, and L2OVDD pin of the PC7400. It is also recommended that these decoupling capacitors receive their power from separate VDD, (L2)OVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.01 F or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling PowerPC microprocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, L2OVDD, and OVDD planes to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are 100-330 F (AVX TPS tantalum or Sanyo OSCON). Connection Recommendations 40 To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. PC7400 2103A-06/01 PC7400 Power and ground connections must be made to all external VDD, OVDD, L2OVDD, and GND pins of the PC7400. See "L2 Clock AC Specifications" on page 27 for a discussion of the L2SYNC_OUT and L2SYNC_IN signals. Output Buffer DC Impedance The PC7400 60x and L2 I/O drivers are characterized over process, voltage and temperature. To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 29). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then Z0 = (RP + RN)/2. Figure 29. Driver Impedance Measurement OVDD RN SW2 Pad Data SW1 RP OGND Table 18 summarizes the signal impedance results. The impedance increases with junction temperature and is relatively unaffected by bus voltage. Table 18. Impedance Characteristics with VDD = 1.8V, OVDD = 3.3V, Tj = -55C to 125C Pull-up Resistor Requirements Impedance Processor bus L2 Bus Symbol Unit RN 32 - 43 39 - 48 Z0 Ohms RP 36 - 48 41 - 50 Z0 Ohms The PC7400 requires high-resistive (weak: 10 K) pull-up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the PC7400 or other bus masters. These pins are TS, ARTRY, SHDO and SHD1. In addition, the PC7400 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7 K-10 K) if it is used by the system. This pin is CKSTP_OUT. 41 2103A-06/01 During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may therefore float in the high-impedance state for relatively long periods of time. Since the PC7400 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the PC7400 or by other receivers in the system. It is recommended that these signals be pulled up through weak (10 K) pull-up resistors by the system, or that they may be otherwise driven by the system during inactive periods of the bus. The snooped address and transfer attribute inputs are A[0:31], AP[0:3], TT[0:4], and GBL. The data bus input receivers are normally turned off when no read operation is in progress and therefore do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are D[0:63], DP[0:7] If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. The L2 interface does not normally require pull-up resistors. JTAG Configuration Signals Figure 30. Suggested TRST Connection PC7400 HRESET HRESET From Target Board Sources QACK QACK TRST 2K 2K COP Header 42 PC7400 2103A-06/01 PC7400 CKSTP_OUT HRESET SRESET TMS TCK RUN/STOP TDI TDO Figure 31. COP Connector Diagram 15 13 11 9 7 5 3 1 Note: 8 6 4 2 QACK 10 TRST 12 VDD_SENSE KEY No pin Ground 16 CKSTP_IN Top View Pins 10, 12 and 14 are no connects. Pin 14 is not physically present. Table 19. COP Pin Definitions Pins Signal Connection Special Notes 1 TDO TDO 2 QACK QACK 3 TDI TDI 4 TRST TRST Add 2K pull-down to ground. Must be merged with onboard TRST if any. See Figure 30. 5 RUN/STOP No Connect Used on 604e; leave no-connect for all other processors. 6 VDD_SENSE VDD Add 2K pull-up to OVDD (for short circuit limiting protection only). 7 TCK TCK 8 CKSTP_IN CKSTP_IN 9 TMS TMS 10 N/A 11 SRESET 12 N/A 13 HRESET 14 N/A 15 CKSTP_OUT CKSTP_OUT 16 Ground Digital Ground Add 2K pull-down to ground. Must be merged with onboard QACK, if any. Optional. Add 10K pull-up to OVDD. Used on several emulator products. Useful for checkstopping the processor from a logic analyzer of other external trigger. SRESET Merge with on-board SRESET, if any. HRESET Merge with on-board HRESET. Key location; pin should be removed. Add 10K pull-up to OVDD. 43 2103A-06/01 Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the PC7400 are available on the Internet at www.mot.com/PowerPC/teksupport.) The TRST signal is optional in the IEEE 1149.1 specification but is provided on all PowerPC implementations. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Since the JTAG interface is also used for accessing the common on-chip processor (COP) function of PowerPC processors, simply tying TRST to HRESET is not practical. The common on-chip processor (COP) function of PowerPC processors allows a remote computer system (typically a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 30 allows the COP to independently assert HRESET or TRST, while insuring that the target can drive HRESET as well. The pull-down resistor on TRST ensures that the JTAG scan chain is initialized during power-on if a JTAG interface cable is not attached; if it is, it is responsible for driving TRST when needed. The COP header shown in Figure 30 adds many benefits - breakpoints, watchpoints, register and memory examination/modification and other standard debugger features are possible through this interface - and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100" centered header assembly (often called a "Berg" header). The connector typically has pin 14 removed as a connector key, as shown in Figure 31. Definitions Datasheet Status Description Table 20. Datasheet Status Datasheet Status 44 Validity Objective specification This datasheet contains target and goal specifications for discussion with customer and application validation. Before design phase Target specification This datasheet contains target or goal specifications for product development. Valid during the design phase Preliminary specification -site This datasheet contains preliminary data. Additional data may be published later; could include simulation results. Valid before characterization phase Preliminary specification -site This datasheet also contains characterization results. Valid before the industrialization phase Product specification This datasheet contains final product specification. Valid for production purposes PC7400 2103A-06/01 PC7400 Table 20. Datasheet Status Datasheet Status Validity Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification. Life Support Applications These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. Ordering Information PC (X) 7400 M GS U 400 L x Revision Level(1) Rev. K Manufacturer's Prefix Prototype Bus Divider (TBC) L: Any valid PLL configura Type Temperature Range: Tj M: -55 C, +125 C V: -40 C, +110 C Package G: CBGA GS: CI_CBGA Note: Screening Level(1) U: Upscreening Max Internal Processor Speed(1) 350 MHz 400 MHz 1. For availability of the different versions, contact your Atmel sales office. 45 2103A-06/01 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 1150 E. Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel Corporation. PowerPC is the trademark of IBM Corporation. Other terms and product names may be the trademark of others. Printed on recycled paper. Rev. 2103A-06/01