High Rel Microprocessors - Datsheet - Atmel Corporation

Features

•18SPECint95, 16SPECfp95 @ 266 MHz with 1-MB L2 @ 200 MHz

•3.2 GFLOPS @ 400 MHz (Peak Performance)

•Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)

•Seven Selectable Core-to-L2 Frequency Divisors

•Selectable Interface Voltage Below 3.3V (1.8V, 2.5V)

•PD Typical 5W @ 400 MHz, Full Operating Conditions

•Nap, Doze and Sleep Modes for Power Saving

•Superscalar (Three Instructions per Clock Cycle)

•4-GB Direct Addressing Range

•4P.Byte of Virtual Memory

•64-bit Data and 32-bit Address Bus Interface

•32-KB Instruction and Data Cache

•Eight Independent Execution Units and Three Register Files

•Write-back and Write-through Operations

•fINT Max = 400 MHz

•fBUS Max = 100 MHz

Description

The PC7400 is the first microprocessor that uses the fourth (G4) full implementation of

the PowerPC Reduced Instruction Set Computer (RISC) architecture. It is fully JTAG-

compliant.

The PC7400 maintains some of the characteristics of G3 microprocessors:

• The design is superscalar, capable of issuing three instructions per clock cycle

into six independent execution units

• The microprocessor provides four software controllable power-saving modes and

a thermal assist unit management

• The microprocessor has separate 32-Kbyte, physically-addressed instruction and

data caches with dedicated L2 cache interface with on-chip L2 tags

In addition, the PC7400 integrates full hardware-based multiprocessing capability,

including a 5-state cache coherency protocol (4 MESI states plus a fifth state for

shared intervention) and an implementation of the new AltiVec technology instruction

set.

New features have been developed to make latency equal for double-precision and

single-precision floating-point operations involving multiplication. Additionally, in mem-

ory subsystem (MSS) bandwidth, the PC7400 offers an optional, high-bandwidth MPX

bus interface.

Screening

• CBGA upscreenings based on Atmel standards

• Full military temperature range (Tj = -55°C, +125°C),

industrial temperature range (Tj = -40°C, +110°C)

• CI-CGA package versions

PowerPC7400

RISC

Microprocessor

PC7400

Preliminary

Specification

α-site

Rev. 2103A–06/01

2PC7400

2103A–06/01

Block Diagram

Figure 1. PC7400 Microprocessor Block Diagram

Fetcher Branch Processing Unit

Instruction

Queue

6-word Dispatch Unit

Instruction Unit

Data MMU

SRs

(Original)

128-entry

DTLB

DBAT

Array

Instruction MMU

SRs

(Shadow)

128-entry

ITLB

IBAT

Array

Reservation

Station

Vector

Permute

Unit

Vector

ALU

Integer

Unit 1

Integer

Unit 2

System

Unit

Reservation

Station

Reservation

Station

Reservation

Station

Reservation

Station

Reservation

Station

2-entry

Reservation

Station

VR File

6 Rename

Buffers

GPR File

6 Rename

Buffers

FPR File

6 Rename

Buffers

Load/Store

Unit

Floating

Point Unit

Completion Unit

8-entry

Reorder Buffer

Bus Interface Unit

VSIU VCIU VFPU

Tags 32-Kbyte

iCache

Tags 32-Kbyte

DCache

L2 Controller

Bus Interface

Unit

64-entry BTIC/512-entry BHT

LR/CTR

Add-Multiply-

Compare - Add -

VSCR

- Add -

Add-Multiply-

Compare

FPSCR

EA Calculation

Finished Stores

Completed

Stores

L2 Data Transaction

L2 Miss

L2 Castout

L2 Tags

Data Reload

Ta b l e

Data Reload

Queue

Instruction

Reload Queue

Load Fold

Queue

Instruction

Reload Table

L1 Operations

Queue

128-bit 32-bit

128-bit

2 Instructions

32-bit

64-bit

(2 Instructions)

32-bit 60x/MAX Address Bus

64-bit 60x Data Bus/128-bit MAX Data Bus

19-bit L2 Address Bus

64-/128-bit L2 Data Bus

32-bit

64-bit 64-bit

PC7400

2103A–06/01

General

Parameters

Table 1 provides a summary of the general parameters of the PC7400.

Features This section summarizes features of the PC7400’s implementation of the PowerPC architec-

ture. Major features of the PC7400 are as follows:

•Branch processing unit

–Four instructions fetched per clock

–One branch processed per cycle (plus resolving two speculations)

–Up to one speculative stream in execution, one additional speculative stream in

fetch

–512-entry branch history table (BHT) for dynamic prediction

–64-entry, 4-way set associative branch target instruction cache (BTIC) for

eliminating branch delay slots

•Dispatch unit

–Full hardware detection of dependencies (resolved in the execution units)

–Dispatch two instructions to eight independent units (system, branch, load/store,

fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU)

–Serialization control (predispatch, postdispatch, execution serialization)

•Decode

–Register file access

–Forwarding control

–Partial instruction decode

•Completion

–8-entry completion buffer

–Instruction tracking and peak completion of two instructions per cycle

–Completion of instructions in program order while supporting out-of-order

instruction execution, completion serialization and all instruction flow changes

•Fixed-point units (FXUs) that share 32 GPRs for integer operands

–Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical

–Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical

–Single-cycle arithmetic, shifts, rotates, logical

Table 1. Device Parameters

Parameter Description

Technology 0.18 µm CMOS, five-layer metal

Die size 7.86 mm x 10.58 mm (83 mm2)

Transistor count 10.5 million

Logic design Fully-static

Packages Surface-mount, ceramic 360-ball or -column grid array

(CBGA/CI-CGA)

Core power supply 1.8V ± 100 mV dc (nominal; see Table 5 for recommended

operating conditions)

I/O power supply 1.8V ± 100 mV dc or

2.5V ± 100 mV dc or

3.3V ± 5% (input thresholds are configuration pin selectable)

4PC7400

2103A–06/01

–Multiply and divide support (multi-cycle)

–Early out multiply

•Three-stage floating-point unit and a 32-entry FPR file

–Support for IEEE-754 standard single- and double-precision floating-point

arithmetic

–Three-cycle latency, one-cycle throughput (single or double precision)

–Hardware support for divide

–Hardware support for denormalized numbers

–Time deterministic non-IEEE mode

•System unit

–Executes CR logical instructions and miscellaneous system instructions

–Special register transfer instructions

•AltiVec unit

–Full 128-bit data paths

–Two dispatchable units: vector permute unit and vector ALU unit

–Contains its own 32-entry 128-bit vector register file (VRF) with six renames

–The vector ALU unit is further sub-divided into the vector simple integer unit

(VSIU), the vector complex integer unit (VCIU) and the vector floating-point unit

(VFPU).

–Fully pipelined

•Load/store unit

–One-cycle load or store cache access (byte, half-word, word, double-word)

–Two-cycle load latency with one-cycle throughput

–Effective address generation

–Hits under misses (multiple outstanding misses)

–Single-cycle unaligned access within double-word boundary

–Alignment, zero padding, sign extend for integer register file

–Floating-point internal format conversion (alignment, normalization)

–Sequencing for load/store multiples and string operations

–Store gathering

–Executes the cache and TLB instructions

–Big- and little-endian byte addressing supported

–Misaligned little-endian supported

–Supports FXU, FPU, and AltiVec load/store traffic

–Complete support for all four architecture AltiVec DST streams

•Level 1 (L1) cache structure

–32K 32-byte line, 8-way set associative instruction cache (iL1)

–32K 32-byte line, 8-way set associative data cache (dL1)

–Single-cycle cache access

–Pseudo least-recently-used (LRU) replacement

–Data cache supports AltiVec LRU and transient instructions algorithm

–Copy-back or write-through data cache (on a page-per-page basis)

–Supports all PowerPC memory coherency modes

–Non-blocking instruction and data cache

PC7400

2103A–06/01

–Separate copy of data cache tags for efficient snooping

–No snooping of instruction cache except for ICBI instruction

•Level 2 (L2) cache interface

–Internal L2 cache controller and tags; external data SRAMs

–512K, 1M and 2Mbyte 2-way set associative L2 cache support

–Copyback or write-through data cache (on a page basis or for all L2)

–32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size

–Supports pipelined (register-register) synchronous burst SRAMs and pipelined

(register-register) late-write synchronous burst SRAMs

–Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported

–64-bit data bus

–Selectable interface voltages of 1.8, 2.5, and 3.3V

•Memory management unit

–128 entry, 2-way set associative instruction TLB

–128 entry, 2-way set associative data TLB

–Hardware reload for TLBs

–Four instruction BATs and four data BATs

–Virtual memory support for up to four petabytes (252) of virtual memory

–Real memory support for up to four gigabytes (232) of physical memory

–Snooped and invalidated for TLBI instructions

•Efficient data flow

–All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are 128 bits

wide

–dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF

–L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s

–Up to eight outstanding out-of-order cache misses between dL1 and L2/bus

–Up to seven outstanding out-of-order transactions on the bus

–Load folding to fold new dL1 misses into older outstanding load and store misses

to the same line

–Store miss merging for multiple store misses to the same line. Only coherency

action taken (i.e., address only) for store misses merged to all 32 bytes of a cache

line (no data tenure needed).

–Two-entry finished store queue and four-entry completed store queue between

load/store unit and dL1

–Separate additional queues for efficient buffering of outbound data (castouts, write

throughs, etc.) from dL1 and L2

•Bus interface

–New MPX bus extension to 60X processor interface

–Mode-compatible with 60x processor interface

–32-bit address bus

–64-bit data bus

–Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x,

7x, 7.5x, 8x, 9x supported

–Selectable interface voltages of 1.8 and 3.3V

6PC7400

2103A–06/01

•Power management

–Low-power design with thermal requirements very similar to PC740 and PC750

–1.8V processor core

–Selectable interface voltages below 3.3V can reduce power in output buffers

–Three static power saving modes: doze, nap, and sleep

–Dynamic power management

•Testability

–LSSD scan design

–IEEE 1149.1 JTAG interface

–Array built-in self test (ABIST) – factory test only

–Redundancy on L1 data arrays and L2 tag arrays

•Reliability and serviceability

–Parity checking on 60x and L2 cache buses

PC7400

2103A–06/01

Pin Assignment

BGA360 Package Figure 2, Figure 3, Figure 4 and Figure 5 show top views of the packages available for the

PC7400. Note that these drawings are not to scale.

Figure 2. Top View of 360-pin CBGA and 360-ball CI-CGA Packages

Figure 3. Top View of 360-pin CBGA and CI-CGA Packages

Pin A1 Index

12 3 4 5678 91011121314151617 18 19

8PC7400

2103A–06/01

Figure 4. Cross-section of 360-ball CBGA Package

Figure 5. Cross-section of 360-column CI-CGA Package

Substrate Assembly

Encapsulant

View

Die

View

Die

Substrate Assembly

Encapsulant

Table 2. Pinout Listing for the PC7400, 360-ball CBGA Package

Signal Name Pin Number Active I/O

I/F Voltages Supported(1)

1.8V 2.5V 3.3V

A[0:31] A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12,

G3, G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3,

J7, M3, H3, J2, J6, K3, K2, L2

High I/O √√

AACK N3 Low Input √√

ABB

AMON[0](12)

L7 Low Output √√

AP[0:3] C4, C5, C6, C7 High I/O √√

ARTRY L6 Low I/O √√

AVDD A8 1.8V 1.8V 1.8V

BG H1 Low Input √√

BR E7 Low Output √√

BVSEL(3, 8, 9) W1 High Input GND N/A 3.3V

CHK(4, 8, 9) K11 Low Input √√

CI C2 Low I/O √√

CKSTP_IN B8 Low Input √√

CKSTP_OUT D7 Low Output √√

CLK_OUT E3 High Output √√

DBB

DMON[0](12)

K5 Low Output √√

DBG K1 Low Input √√

PC7400

2103A–06/01

DH[0:31] W12, W11, V11, T9, W10, U9, U10, M11, M9, P8,

W7, P9, W9, R10, W6, V7, V6, U8, V9, T7, U7, R7,

U6, W5, U5, W4, P7, V5, V4, W3, U4, R5

High I/O √√

DL[0:31] M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13,

U12, P12, T13, W13, U13, V10, W8, T11, U11,

V12, V8, T1, P1, V1, U1, N1, R2, V3, U3, W2

High I/O √√

DP[0:7] L1, P2, M2, V2, M1, N2, T3, R1 High I/O √√

DRDY(6, 8, 13) K9 Low Output √√

DBWO

DTI[0]

D1 Low Input √√

DTI[1:2](10, 13) H6, G1 High Input √√

EMODE(7, 10) A3 Low Input √√

GBL B1 Low I/O √√

GND D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14,

F16, G9, G11, H5, H8, H10, H12, H15, J9, J11, K4,

K6, K8, K10, K12, K14, K16, L9, L11, M5, M8, M10,

M12, M15, N9, N11, P4, P6, P10, P14, P16, R8,

R12, T4, T6, T10, T14, T16

GND GND GND

HIT(6, 8) B5 Low Output √√

HRESET B6 Low Input √√

INT C11 Low Input √√

L1_TSTCLK(2) F8 High Input √√

L2ADDR[0:16] L17, L18, L19, M19, K18, K17, K15, J19, J18, J17,

J16, H18, H17, J14, J13, H19, G18

High Output √√ √

L2ADDR[17](8) K19 High Output √√ √

L2ASPARE(8) W19 High Output √√ √

L2AVDD L13 1.8V 1.8V 1.8V

L2CE P17 Low Output √√ √

L2CLKOUTA N15 High Output √√ √

L2CLKOUTB L16 High Output √√ √

L2DATA[0:63] U14, R13, W14, W15, V15, U15, W16, V16, W17,

V17, U17, W18, V18, U18, V19, U19, T18, T17,

R19, R18, R17, R15, P19, P18, P13, N14, N13,

N19, N17, M17, M13, M18, H13, G19, G16, G15,

G14, G13, F19, F18, F13, E19, E18, E17, E15,

D19, D18, D17, C18, C17, B19, B18, B17, A18,

A17, A16, B16, C16, A14, A15, C15, B14, C14, E13

High I/O √√ √

L2DP[0:7] V14, U16, T19, N18, H14, F17, C19, B15 High I/O √√ √

L2OVDD(11) D15, E14, E16, H16, J15, L15, M16, K13, P15,

R14, R16, T15, F15

1.8V 2.5V 3.3V

L2SYNC_IN L14 High Input √√ √

Table 2. Pinout Listing for the PC7400, 360-ball CBGA Package (Continued)

Signal Name Pin Number Active I/O

I/F Voltages Supported(1)

1.8V 2.5V 3.3V

10 PC7400

2103A–06/01

L2SYNC_OUT M14 High Output √√ √

L2_TSTCLK F7 High Input √√

L2VSEL(1, 3, 8, 9) A19 High Input GND HRESET 3.3V

L2WE N16 Low Output √√ √

L2ZZ G17 High Output √√ √

LSSD_MODE(2) F9 Low Input √√

MCP B11 Low Input √√

OVDD D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4,

P5, R4, R6, R9, R11, T5, T8, T12

1.8V 3.3V

PLL_CFG[0:3] A4, A5, A6, A7 High Input √√

QACK B2 Low Input √√

QREQ J3 Low Output √√

RSRV D3 Low Output √√

SHD0(5, 8) B3 Low I/O √√

SHD1(5, 8) B4 Low I/O √√

SMI A12 Low Input √√

SRESET E10 Low Input √√

SYSCLK H9 Input √√

TA F1 Low Input √√

TBEN A2 High Input √√

TBST A11 Low Output √√

TCK B10 High Input √√

TDI(9) B7 High Input √√

TDO D9 High Output √√

TEA J1 Low Input √√

TMS(9) C8 High Input √√

TRST(9) A10 Low Input √√

TS K7 Low I/O √√

TSIZ[0:2] A9, B9, C9 High Output √√

TT[0:4] C10, D11, B12, C12, F11 High I/O √√

WT C3 Low I/O √√

VDD G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10,

N12

1.8V 1.8V 1.8V

Table 2. Pinout Listing for the PC7400, 360-ball CBGA Package (Continued)

Signal Name Pin Number Active I/O

I/F Voltages Supported(1)

1.8V 2.5V 3.3V

PC7400

2103A–06/01

Note: 1. OVDD supplies power to the processor bus, JTAG and all control signals except the L2 cache controls (L2CE, L2WE, and

L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:16], L2ASPARE, L2DATA[0:63], L2DP[0:7] and

L2SYNC_OUT) and the L2 control signals; VDD supplies power to the processor core and the PLL and DLL (after filtering to

become AVDD and L2AVDD respectively). These columns serve as a reference for the nominal voltage supported on a given

signal as selected by the BVSEL/L2VSEL pin configurations of Table 4 and the voltage supplied. For actual recommended

value of VIN or supply voltages, see Table 5.

2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.

3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD

(selects 3.3V), OGND (selects 1.8V), or to HRESET (selects 2.5V). The processor bus and L2 bus support all three options

(see Table 4).

4. Connect to HRESET to trigger post power-on-reset (por) internal memory test.

5. Ignored in 60x bus mode.

6. Unused output in 60x bus mode.

7. Deasserted (pulled high) at HRESET for 60x bus mode.

8. Uses one of 9 existing no-connects in PC750’s 360-ball BGA package.

9. Internal pull-up on die.

10. Reuses PC750’s DRTRY

, DBDIS and TLBISYNC pins (DTI1, DTI2 and EMODE respectively).

11. The VOLTDET pin position on the PC750 360-ball CBGA package is now an L2OVDD pin on the PC7400 360-ball CBGA

package.

12. Output only for PC7400, was I/O for PC750.

13. Enhanced mode only.

12 PC7400

2103A–06/01

Signal

Description

Figure 6. PC7400 Microprocessor Signal Groups

PCX7400

VDD OVDD AVDD

L2OVDD

L2AVDD

CHK

GBL

ARTRY

DBG

D[0:63]

DP[0:7]

DTI1

TEA

ABB

A[0:31]

AP[0:3]

TT[0:4]

TBST

TSIZ[0:2]

AACK

DBWO, DTI(0)

DBB, DMON(0)

DBDIS/DTI(2)

L2CE

L2WE

SRESET

HRESET

HIT

L2ADDR[0:17]

L2DATA[0:63]

L2DP[0:7]

L2SPARE

L2CLKOUTA,

L2CLKOUTB

L2SYNC_OUT

L2SYNC_IN

L2ZZ

INT

SMI

MCP

CKSTP_IN

CKSTP_OUT

SHDO, SHD1

RSRV

TBEN

EMODE

QREQ

QACK

DRDY

SYSCLK

PLL_CFG[0:3]

CLK_OUT

JTAG:COP

Factory Test

L1_TSTCLK,

L2_TSTCLK

BVSEL

L2VSEL

L2 Cache

Address/Data

Address

Arbitration

Address

Bus

Address

Start

Transfer

Attribute

Address

Termination

Data

Arbitration

Data

Transfer

Data

Termination

L2 Cache

Clock/Control

Interrupts

Reset

Processor

Status

Control

Clock

Control

Test Interface

LSSD_MODE

I/O Voltage

Selection

PC7400

2103A–06/01

Detailed Specification

Scope This drawing describes the specific requirements for the microprocessor PC7400 in compli-

ance with Atmel-Grenoble standard screening.

Applicable

Documents

1. MIL-STD-883: Test methods and procedures for electronics

2. MIL-PRF-38535: Appendix A: General specifications for microcircuits

Requirements

General The microcircuits are in accordance with the applicable documents and as specified herein.

Design and

Construction

Terminal Connections Depending on the package, the terminal connections are as shown in Table 2, Table 5 and

Figure 6.

Absolute

Maximum Ratings

Notes: 1. Functional and tested operating conditions are given in Table 5. Absolute maximum ratings

are stress ratings only and functional operation at the maximums is not guaranteed.

Stresses beyond those listed may affect device reliability or cause permanent damage to the

device.

2. Caution: VIN must not exceed OVDD or L2OVDD by more than 0.3V at any time including dur-

ing power-on reset.

3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0V at any time

including during power-on reset.

4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4V at any time

including during power-on reset. In addition, operation at nominal VDD/AVDD/L2AVDD greater

than nominal L2OVDD or OVDD in the 1.8V input threshold select mode can cause erratic

operation and AC timing values worse than described in this specification.

5. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure

Table 3. Absolute Maximum Ratings(1)

Symbol Characteristic Value Unit

VDD Core supply voltage -0.3 to 2.1(4) V

AVDD PLL supply voltage -0.3 to 2.1(4) V

L2AVDD L2 DLL supply voltage -0.3 to 2.1(4) V

OVDD 60x bus supply voltage -0.3 to 3.465(3) V

L2OVDD L2 bus supply voltage -0.3 to 3.465(3) V

VIN Processor bus input voltage -0.3 to 3.6(2, 5) V

VIN L2 bus input voltage -0.3 to 3.6V(2, 5) V

VIN JTAG signal input voltage -0.3 to 3.6 V

TSTG Storage temperature range -65 to 150 °C

14 PC7400

2103A–06/01

Figure 7. Overshoot/Undershoot Voltage

The PC7400 provides several I/O voltages to support both compatibility with existing systems

and migration to future systems. The PC7400 “core” voltage must always be provided at nom-

inal 1.8V (see Table 5 for actual recommended core voltage). Voltage to the L2 I/Os and

processor interface I/Os are provided through separate sets of supply pins and may be pro-

vided at the voltages shown in Table 4. The input voltage threshold for each bus is selected by

sampling the state of the voltage select pins at the negation of the signal HRESET. The output

voltage will swing from GND to the maximum voltage applied to the OVDD or L2OVDD power

pins.

Notes: 1. Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied.

2. To select the 2.5 volt threshold option, L2VSEL/BVSEL should be tied to HRESET so that

the two signals change state together.

Table 4. Input Threshold Voltage Setting

BVSEL Signal

Processor Bus Input

Threshold is Relative to: L2VSEL Signal

L2 Bus Input Threshold

is Relative to:

0(1) 1.8V 0 1.8

HRESET(1, 2) 2.5V HRESET 2.5

1(1) 3.3V 1 3.3

Not to exceed

10% of tSYSCLK

(L2)OVDD + 20%

(L2)OVDD + 5%

(L2)OVDD

VIH

VIL

GND

GND - 0.3V

GND - 0.7V

PC7400

2103A–06/01

Recommended

Operating

Conditions

Note: These are the recommended and tested operating conditions. Proper device operation outside

of these conditions is not guaranteed.

Thermal

Characteristics

Package

Characteristics

The board designer can choose between several commercially available heat sink types to

place on the PC7400. For exposed-die packaging technology as in Table 6, the intrinsic con-

duction thermal resistance paths are shown in Figure 8.

Internal Package

Conduction

Resistance

Figure 8 depicts the primary heat transfer path for a package with an attached heat sink

mounted on a printed circuit board.

Heat generated on the active side of the chip is conducted through the silicon, then through

the heat sink attach material (or thermal interface material) and finally to the heat sink where it

is removed by forced-air convection.

Table 5. Recommended Operating Conditions(1)

Symbol Characteristic

Recommended

Value Unit

VDD Core supply voltage 1.8 ± 100 mV V

AVDD PLL supply voltage 1.8 ± 100 mV V

L2AVDD L2 DLL supply voltage 1.8 ± 100 mV V

OVDD Processor bus supply

voltage

BVSEL = 0 1.8 ± 100 mV V

OVDD BVSEL = HRESET 2.5 ± 100 mV V

OVDD BVSEL = 1 3.3 ± 165 mV V

L2OVDD L2 bus supply voltage L2VSEL = 0 1.8 ± 100 mV V

L2OVDD L2VSEL = HRESET 2.5 ± 100 mV V

L2OVDD L2VSEL = 1 3.3 ± 165 mV V

VIN Input voltage Processor bus GND to OVDD V

VIN L2 Bus GND to L2OVDD V

VIN JTAG Signals GND to OVDD V

TjDie-junction temperature -55 to 125 °C

Table 6. Package Thermal Characteristics

Symbol Characteristic Value Rating

θJC CBGA and CI-CBGA packages thermal resistance, die junction-

to-case thermal resistance (typical)

0.03 °C/W

θJB CBGA package thermal resistance, die junction-to-lead thermal

resistance (typical)

3.8 °C/W

θJB CI-CBGA package thermal resistance, die junction-to-lead

thermal resistance (typical)

4°C/W

16 PC7400

2103A–06/01

Since the silicon thermal resistance is quite small, for a first-order analysis the temperature

drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink

conduction/convective thermal resistances are the dominant terms.

Figure 8. C4 Package with Heat Sink Mounted on a Printed Circuit Board

Thermal Management

Assistance

The PC7400 incorporates a thermal management assist unit (TAU) composed of a thermal

sensor, digital-to-analog converter, comparator, control logic and dedicated special-purpose

registers (SPRs). More information on the use of this feature is given in the MPC750P RISC

Microprocessor User’s Manual.

Notes: 1. The temperature is the junction temperature of the die. The thermal assist unit’s raw output

does not indicate an absolute temperature, but it must be interpreted by software to derive

the absolute junction temperature. For information about the use and calibration of the TAU,

see Motorola application note, “Programming the Thermal Assist Unit in the MPC750

Microprocessor”.

2. The comparator settling time value must be converted into the number of CPU clocks that

need to be written into the THRM3 SPR.

3. The resolution is guaranteed by design and characterization.

Thermal Management

Information

This section provides thermal management information for the ceramic ball grid array (CBGA)

package for air-cooled applications. Proper thermal control design is primarily dependent upon

the system-level design – the heat sink, airflow and thermal interface material. To reduce the

die-junction temperature, heat sinks may be attached to the package by several methods:

adhesive, spring clip to holes in the printed-circuit board or package and mounting clip and

screw assembly; see Figure 9. This spring force should not exceed 5.5 pounds of force. Ulti-

mately, the final selection of an appropriate heat sink depends on many factors such as

thermal performance at a given air velocity, spatial volume, mass, attachment method, assem-

bly and cost.

External Resistance

Internal Resistance

Radiation Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Printed Circuit Board

Radiation Convection

Table 7. Thermal Sensor Specifications at VDD = AVDD = L2VDD = 1.8V ± 100 mV,

OVDD = L2OVDD = 3.3 ± 5% Vdc, GND = 0Vdc, -55°C ≤ Tj ≤ 125°C

Characteristic Min Max Unit

Temperature range(1) 0 127 °C

Comparator settling time(2) 20 µs

Resolution(3) 4°C

Accuracy -12 +12 °C

PC7400

2103A–06/01

Figure 9. CBGA Package Cross-section with Heat Sink Options

Adhesives and

Thermal Interface

Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to mini-

mize the thermal contact resistance. For those applications where the heat sink is attached by

spring clip mechanism, Figure 10 shows the thermal performance of three thin-sheet thermal-

interface materials (silicone, graphite/oil, floroether oil), a bare joint and a joint with thermal

grease as a function of contact pressure. As shown, the performance of these thermal inter-

face materials improves with increasing contact pressure. The use of thermal grease

significantly reduces the interface thermal resistance. That is, the bare joint results in a ther-

mal resistance approximately seven times greater than the thermal grease joint.

Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit

board (see Figure 9). This spring force should not exceed 5.5 pounds of force. Therefore, syn-

thetic grease offers the best thermal performance, considering the low interface pressure.

The board designer can choose between several types of thermal interface. Heat sink adhe-

sive materials should be selected based upon high conductivity, yet must have adequate

mechanical strength to meet equipment shock/vibration requirements.

Printed-Circuit Board

Adhesive or

Thermal Interface Material

Heat Sink Clip

Heat Sink

Option

18 PC7400

2103A–06/01

Figure 10. Thermal Performance of Different Thermal Interface Materials

Heat Sink Selection

Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:

where:

Tj = die-junction temperature

Ta = inlet cabinet ambient temperature

Tr = air temperature rise within the computer cabinet

θjc = junction-to-case thermal resistance

θint = adhesive or interface material thermal resistance

θsa = heat sink base-to-ambient thermal resistance

Pd = power dissipated by the device

During operation, the die-junction temperatures (Tj) should be maintained less than the value

specified in Table 5. The temperature of the air cooling the component greatly depends upon

the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An

electronic cabinet inlet-air temperature (Ta) may range from 30°C to 40°C. The air temperature

rise within a cabinet (Tr) may be in the range of 5°C to 10°C. The thermal resistance of the

thermal interface material (θint) is typically about 1°C/W. Assuming a Ta of 30°C, a Tr of 5°C, a

CBGA package θjc = 0.03, and a power consumption (Pd) of 5.0 watts, the following expres-

sion for Tj is obtained:

0.5

1.5

0 1020304050607080

Silicone Sheet (0.006 inch)

Bare Joint

Floroether Oil Sheet (0.007 inch)

Graphite/Oil Sheet (0.005 inch)

Synthetic Grease

Contact Pressure (psi)

Specific Thermal Resistance (Kin

/W)

TjTaTrθjc θint θsa

++()Pd

×++=

Tj30°C5°C0.03°CW⁄1.0°CW⁄θ

++()4.5W×++=

PC7400

2103A–06/01

For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (θsa) versus

airflow velocity is shown in Figure 11.

Figure 11. Thermalloy #2328B Heat Sink-to-ambient Thermal Resistance vs. Airflow Velocity

Assuming an air velocity of 0.5 m/s, the effective Rsa is 7°C/W, thus

resulting in a die-junction temperature of approximately 75°C which is well within the maxi-

mum operating temperature of the component.

Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering and

Aavid Engineering offer different heat sink-to-ambient thermal resistances and may or may not

need air flow.

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a

common figure of merit used for comparing the thermal performance of various microelec-

tronic packaging technologies, one should exercise caution when only using this metric in

determining thermal management because no single parameter can adequately describe

three-dimensional heat flow. The final die-junction operating temperature is not only a function

of the component-level thermal resistance, but of the system-level design and its operating

conditions. In addition to the component's power consumption, a number of factors affect the

final operating die-junction temperature – airflow, board population (local heat flux of adjacent

components), heat sink efficiency, heat sink attach, heat sink placement, next-level intercon-

nect technology, system air temperature rise, altitude, etc.

Due to the complexity and the many variations of system-level boundary conditions for today's

microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation,

convection and conduction) may vary widely. For these reasons, it is recommended to use

conjugate heat transfer models for the board, as well as system-level designs. To expedite

00.511.522.533.5

Approach Air Velocity (m/s)

Heat Sink Thermal Resistance (ºC/W)

Thermalloy #2328B Pin-fin Heat Sink

(25 x28 x 15 mm)

Tj30°C5°C0.03°CW⁄1.0°CW⁄7°CW⁄++()5W×++=

20 PC7400

2103A–06/01

system-level thermal analysis, several “compact” thermal-package models are available within

FLOTHERM®. These are available upon request.

Power

Consideration

Power Management The PC7400 provides four power modes, selectable by setting the appropriate control bits in

the MSR and HIDO registers. The four power modes are:

•Full-power: This is the default power state of the PC7400. The PC7400 is fully powered

and the internal functional units are operating at the full processor clock speed. If the

dynamic power management mode is enabled, functional units that are idle will

automatically enter a low-power state without affecting performance, software execution or

external hardware.

•Doze: All the functional units of the PC7400 are disabled except for the time

base/decrementer registers and the bus snooping logic. When the processor is in doze

mode, an external asynchronous interrupt, a system management interrupt, a

decrementer exception, a hard or soft reset or machine check brings the PC7400 into the

full-power state. The PC7400 in doze mode maintains the PLL in a fully powered state and

locked to the system external clock input (SYSCLK) so a transition to the full-power state

takes only a few processor clock cycles.

•Nap: The nap mode further reduces power consumption by disabling bus snooping,

leaving only the time base register and the PLL in a powered state. The PC7400 returns to

the full-power state upon receipt of an external asynchronous interrupt, a system

management interrupt, a decrementer exception, a hard or soft reset or a machine check

input (MCP). A return to full-power state from a nap state takes only a few processor clock

cycles. When the processor is in nap mode, if QACK is negated, the processor is put in

doze mode to support snooping.

•Sleep: Sleep mode minimizes power consumption by disabling all internal functional units,

after which external system logic may disable the PLL and SYSCLK. Returning the

PC7400 to the full-power state requires the enabling of the PLL and SYSCLK, followed by

the assertion of an external asynchronous interrupt, a system management interrupt, a

hard or soft reset or a machine check input (MCP) signal after the time required to relock

the PLL.

Power Dissipation

Table 8. Power Consumption for PC7400

Power Mode

Processor (CPU) Frequency

Unit350 MHz 400 MHz

Full-On Mode

Ty p i c al (1, 3) 4.4 5.0 W

Maximum(1, 2, 4) 10.9 11.5 W

Doze Mode

Maximum(1, 2) 4.4 5.0 W

Nap Mode

Maximum(1, 2) 1.75 2.0 W

Sleep Mode

Maximum(1, 2) 1.75 2.0 W

PC7400

2103A–06/01

Notes: 1. These values apply for all valid processor bus and L2 bus ratios. The values do not include

I/O supply power (OVDD and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD

and L2OVDD power is system dependent, but is typically <10% of VDD power. Worst case

power consumption for AVDD = 15 mw and L2AVDD = 15 mW.

2. Maximum power is measured at VDD = 1.9V while running an entirely cache-resident, con-

trived sequence of instructions which keep the execution units, including AltiVec, maximally

busy.

3. Typical power is an average value measured at VDD = AVDD = L2AVDD = 1.8V, OVDD =

L2OVDD = 3.3V in a system while running a codec application that is AltiVec intensive.

4. These values include the use of AltiVec. Without AltiVec operation, estimate a 25%

decrease.

Sleep Mode - PLL and DLL Disabled

Ty p i c al (1, 3) 600 600 mW

Maximum(1, 2) 1.0 1.0 W

Table 8. Power Consumption for PC7400 (Continued)

Power Mode

Processor (CPU) Frequency

Unit350 MHz 400 MHz

22 PC7400

2103A–06/01

Electrical

Characteristics

Static

Characteristics

Notes: 1. Nominal voltages; see Table 5 for recommended operating conditions.

2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2

bus signals.

3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 bound-

ary scan (JTAG) signals.

4. Capacitance is periodically sampled rather than 100% tested.

5. The leakage is measured for nominal OVDD and VDD, or both OVDD and VDD must vary in the

same direction (for example, both OVDD and VDD vary by either +5% or -5%).

Table 9. DC Electrical Specifications (see Table 5 for recommended operating conditions)

Symbol Characteristic

Nominal

Bus

Voltage (1) Min Max Unit

VIH Input high voltage

(all inputs except SYSCLK)(2, 3)

1.8 0.65 x

(L2)OVDD

(L2)OVDD + 0.3 V

VIH 2.5 1.7 (L2)OVDD + 0.3 V

VIH 3.3 2.0 (L2)OVDD + 0.3 V

VIL Input low voltage

(all inputs except SYSCLK)

1.8 -0.3 0.35 x OVDD V

VIL 2.5 -0.3 0.2 x (L2)OVDD V

VIL 3.3 -0.3 0.8 V

CVIH SYSCLK input high voltage(2) 1.8 1.5 OVDD + 0.3 V

CVIH 3.3 2.4 OVDD + 0.3 V

CVIL SYSCLK input low voltage 1.8 -0.3 0.2 V

CVIL 3.3 -0.3 0.4 V

IIN Input leakage current,

VIN = L2OVDD/OVDD(2, 3)

10 µA

ITSI High-Z (off-state) leakage

current,

VIN = L2OVDD/OVDD(2, 3, 5)

10 µA

VOH Output high voltage,

IOH = -6 mA

1.8 (L2)OVDD -

0.45

VOH 2.5 1.7 V

VOH 3.3 2.4 V

VOL Output low voltage,

IOL = 6 mA

1.8 0.45 V

VOL 2.5 0.4 V

VOL 3.3 0.4 V

CIN Capacitance, VIN = 0V,

f = 1 MHz(3, 4)

7.5 pF

PC7400

2103A–06/01

Dynamic

Characteristics

After fabrication, parts are sorted by maximum processor core frequency as shown in “Clock

AC Specifications” and tested for conformance to the AC specifications for that frequency.

These specifications are for valid processor core frequencies. The processor core frequency is

determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals.

Parts are sold by maximum processor core frequency.

Clock AC

Specifications

Table 10 provides the clock AC timing specifications as defined in Figure 12.

Note: 1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the

resulting SYSCLK (bus) frequency, CPU (core) frequency and PLL (VCO) frequency do not

exceed their respective maximum or minimum operating frequencies. Refer to the

PLL_CFG[0:3] signal description in “Clock Selection” on page 38 for valid PLL_CFG[0:3]

settings

2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OVDD = 3.3V

nominal.

3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V when OVDD = 1.8V

nominal.

4. Timing is guaranteed by design and characterization.

5. This represents total input jitter, short-term and long-term combined, and is guaranteed by

design.

6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maxi-

mum amount of time required for PLL lock after a stable VDD and SYSCLK are reached

during the power-on reset sequence. This specification also applies when the PLL has been

disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be

held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-

on reset sequence.

Table 10. Clock AC Timing Specifications (See Table 5 for recommended operating

conditions)

Symbol Characteristic

Maximum Processor Core

Frequency

Unit

350 MHz 400 MHz

Min Max Min Max

fCORE(1) Processor frequency 300 350 300 400 MHz

fVCO(1) VCO frequency 600 700 600 800 MHz

fSYSCLK(1) SYSCLK frequency 25 100 25 100 MHz

tSYSCLK SYSCLK cycle time 10 40 7.5 40 ns

tKR & tKF(2) SYSCLK rise and fall time 1.0 1.0 ns

tKR & tKF(3) 0.5 0.5 ns

tKHKL/tSYSCLK(4) SYSCLK duty cycle

measured at OVDD/2

40 60 40 60 %

SYSCLK jitter(5) ±150 ±150 ps

Internal PLL relock time(6) 100 100 µs

24 PC7400

2103A–06/01

Figure 12. SYSCLK Input Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2)

Processor Bus AC

Specifications

Table 11 provides the processor AC timing specifications for the PC7400 as defined in Figure

13 and Figure 15. Timing specifications for the L2 bus are provided in “L2 Bus AC Specifica-

tions” on page 30.

SYSCLK

VM VM VM

CVIL

CVIH

tKHKL

tSYSCLK

tKR

Table 11. Processor Bus AC Timing Specifications(1) at VDD = AVDD = 1.8V ± 100mV;

-55°C ≤=Tj ≤=125°C, OVDD = 3.3V ± 165mV or OVDD = 2.5V ± 100mV or OVDD = 1.8V ± 100mV

Symbol(2) Parameter

350, 400 MHz

UnitMin Max

tMVRH(3, 4, 5, 6) Mode select input setup to HRESET 8t

SYSCLK

tMXRH(2, 3, 5) HRESET to mode select input hold 0 ns

tAVKH(7)

tTSVKH

tDVKH(8)

tARVKH

tIVKH(9)

Setup Times

Address/Transfer Attribute

Transfer Start (TS)

Data/Data Parity

ARTRY/SHD0/SHD1

All Other Inputs

1.6

tAXKH(7)

tTSXKH

tDXKH(8)

tARXKH

tIXKH(9)

Input Hold Times

Address/Transfer Attribute

Transfer Start (TS)

Data/Data Parity

ARTRY/SHD0/SHD1

All Other Inputs

tKHAV(7)

tKHTSV

tKHDV(8)

tKHDPV(8)

tKHARV

tKHOV(10)

Valid Times

Address/Transfer Attribute

TS, ABB, DBB

Data

Data Parity

ARTRY/SHD0/SHD1

All Other Outputs

3.2

3.4

3.5

2.5

3.2

tKHAX(7)

tKHTSX

tKHDX(8)

tKHARX

tKHOX(10)

Output Hold Times

Address/Transfer Attribute

TS, ABB, DBB

Data/Data Parity

ARTRY/SHD0/SHD1

All Other Outputs

0.75

0.6

0.75

tKHOE SYSCLK to Output Enable 0.5 ns

PC7400

2103A–06/01

Notes: 1. All input specifications are measured from the midpoint of the signal in question to the mid-

point of the rising edge of the input SYSCLK. All output specifications are measured from

the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question. All out-

put timings assume a purely resistive 50 ohm load (see Figure 14). Input and output timings

are measured at the pin; time-of-flight delays must be added for trace lengths, vias and con-

nectors in the system.

2. The symbology used for timing specifications herein follows the pattern of

t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH

symbolizes the time input signals (I) reach the valid state (V) relative to the SYSCLK refer-

ence (K) going to the high (H) state or input setup time. tKHOV symbolizes the time from

SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold

time can be read as the time that the input signal (I) went invalid (X) with respect to the rising

clock edge (KH) - note the position of the reference and its state for inputs -and output hold

time can be read as the time from the rising edge (KH) until the output went invalid (OX). For

additional explanation of AC timing specifications in Motorola PowerPC microprocessors,

see the application note “Understanding AC Timing Specifications for PowerPC

Microprocessors.”

3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 15).

4. This specification is for configuration mode select only. Also note that the HRESET must be

held asserted for a minimum of 255 bus clocks after the PLL re-lock time during the power-

on reset sequence.

5. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds(ns). The numbers

given in the table must be multiplied by the period of SYSCLK to compute the actual time

duration (in nanoseconds) of the parameter in question.

6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0:3]

7. Address/Transfer Attribute signals are composed of the following - A[0:31], AP[0:3], TT[0:4],

TBST, TSIZ[0:2], GBL, WT, CI.

8. Data signals are composed of the following - DH[0:31], DL[0:31]; Data Parity signals are

composed of DP[0:7].

9. All other input signals are composed of the following: AACK, BG, CKSTP_IN, DBG,

DBWO/DTI[0], DTI[1:2], HRESET, INT, MCP, QACK, SMI, SRESET, TA, TBEN, TEA,

TLBISYNC.

10. All other output signals are composed of the following - BR, CKSTP_OUT, DRDY, HIT,

QREQ, RSRV

11. According to the 60x bus protocol, TS, ABB and DBB are driven only by the currently active

bus master. They are asserted low then precharged high before returning to high-Z as

shown in Figure 13. The nominal precharge width for TS, ABB or DBB is 0.5 x tSYSCLK,

i.e., less than the minimum tSYSCLK period, to ensure that another master asserting TS, ABB,

or DBB on the following clock will not contend with the precharge. Output valid and output

hold timing is tested for the signal asserted. Output valid time is tested for precharge.The

high-Z behavior is guaranteed by design.

tKHOZ SYSCLK to Output High Impedance (all

except TS, ABB/AMON[0], ARTRY/SHD,

DBB/DMON[0])

4.0 ns

tKHABPZ(5, 11, 13) SYSCLK to TS, ABB/AMON[0],

DBB/DMON[0] High Impedance after

precharge

1.0 tSYSCLK

tKHARP(5, 12, 13) Maximum Delay to ARTRY/SHD0/SHD1

Precharge

SYSCLK

tKHARPZ(5, 12, 13) SYSCLK to ARTRY/SHD0/SHD1 High

Impedance After Precharge

SYSCLK

Table 11. Processor Bus AC Timing Specifications(1) at VDD = AVDD = 1.8V ± 100mV;

-55°C ≤=Tj ≤=125°C, OVDD = 3.3V ± 165mV or OVDD = 2.5V ± 100mV or OVDD = 1.8V ± 100mV

Symbol(2) Parameter

350, 400 MHz

UnitMin Max

26 PC7400

2103A–06/01

12. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through

the clock period immediately following AACK. Bus contention is not an issue since any mas-

ter asserting ARTRY will be driving it low. Any master asserting it low in the first clock

following AACK will then go to high-Z for one clock before precharging it high during the sec-

ond cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0

tSYSCLK; i.e., it should be high-Z as shown in Figure 13 before the first opportunity for another

master to assert ARTRY

. Output valid and output hold timing is tested for the signal

asserted. Output valid time is tested for precharge.The high-Z behavior is guaranteed by

design.

13. Guaranteed by design and not tested.

Figure 13. Input/Output Timing Diagram

tAVKH

tTSVKH

tDVKH

tARVKH

tIVKH

tAXKH

tTSXKH

tDXKH

tARXKH

tIXKH

tKHAV

tKHDV

tKHDPV

tKHOV

tKHAX

tKHDX

tKHOX

tKHOE tKHOZ

tKHTSV

tKHABPZ

tKHTSX

tKHARV

tKHARPZ

tKHARP

tKHARX

SYSCLK

All Inputs

VM VM VM

All Outputs

(except TS, ABB,

ARTRY, DBB)

TS,

ABB/AMON[0],

DBB/DMON[0]

All Outputs

(except TS, ABB,

ARTRY, DBB)

ARTRY,

SHD0,

SHD1

PC7400

2103A–06/01

Figure 14. AC Test Load for the L2 Interface

Figure 15. Mode Input Timing Diagram

where VM = Midpoint Voltage (OVDD/2)

L2 Clock AC

Specifications

The L2CLK frequency is programmed by the L2 configuration register (L2CR[4:6]) core-to-L2

divisor ratio. See Table 17 for example core and L2 frequencies at various divisors. Table 12

provides the potential range of L2CLK output AC timing specifications as defined in Figure 16.

The minimum L2CLK frequency of Table 12 is specified by the maximum delay of the internal

DLL. The variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA,

L2CLKOUTB and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase

aligned with the next core clock (divided by the L2 divisor ratio). Do not choose a core-to-L2

divisor which results in an L2 frequency below this minimum, or the L2CLKOUT signals pro-

vided for SRAM clocking will not be phase aligned with the PC7400 core clock at the SRAMs.

The maximum L2CLK frequency shown in Table 12 is the core frequency divided by one. Very

few L2 SRAM designs will be able to operate in this mode. Most designs will select a greater

core-to-L2 divisor to provide a longer L2CLK period for read and write access to the L2

SRAMs. The maximum L2CLK frequency for any application of the PC7400 will be a function

of the AC timings of the PC7400, the AC timings for the SRAM, bus loading and printed circuit

board trace length.

Atmel is similarly limited by system constraints and cannot perform tests of the L2 interface on

a socketed part on a functional tester at the maximum frequencies of Table 12. Therefore,

functional operation and AC timing information are tested at core-to-L2 divisors of 2 or greater.

L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is

SYSCLK multiplied up to the core frequency and divided down to the L2CLK frequency). In

other words, the AC timings of Table 13 are entirely independent of L2SYNC_IN. In a closed

loop system, where L2SYNC_IN is driven through the board trace by L2SYNC_OUT,

L2SYNC_IN only controls the output phase of L2CLKOUTA and L2CLKOUTB which are used

to latch or enable data at the SRAMs. However, since in a closed loop system L2SYNC_IN is

held in phase alignment with the internal L2CLK, the signals of Table 13 are referenced to this

signal rather than the not-externally-visible internal L2CLK. During manufacturing test, these

times are actually measured relative to SYSCLK.

Z0 = 50 Ohms

RL = 50 Ohms

Output

tMVRH tMXRH

HRESET

MODE SIGNALS

28 PC7400

2103A–06/01

Notes: 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK fre-

quency to core frequency settings must be chosen such that the resulting L2CLK frequency

and core frequency do not exceed their respective maximum or minimum operating frequen-

cies. The maximum L2LCK frequency will be system-dependent. L2CLK_OUTA and

L2CLK_OUTB must have equal loading.

2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.

3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be mul-

tiplied by the period of L2CLK to compute the actual time duration in nanoseconds. Re-lock

timing is guaranteed by design and characterization.

4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds

more delay to each tap of the DLL.

5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.

6. Guaranteed by design and not tested. This output jitter number represents the maximum

delay of one tap forward or one tap back from the current DLL tap as the phase comparator

seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK. This

number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects

L2CLKOUT and the L2 address/data/control signals equally and therefore is already com-

prehended in the AC timing and does not have to be considered in the L2 timing analysis.

Table 12. L2CLK Output AC Timing Specifications at recommended operating conditions

(See Table 5)

Symbol Parameter

350 MHz 400 MHz

UnitMin Max Min Max

fL2CLK(1, 4) L2CLK frequency 100 350 133 400 MHz

tL2CLK L2CLK cycle time 2.86 10 2.5 7.5 ns

tCHCL/tL2CLK(2) L2CLK duty cycle 50 50 %

Internal DLL-relock time(3) 640 640 L2CLK

DLL capture window(5) 010010ns

tL2CSKW L2CLKOUT output-to-

output skew(6)

50 50 ps

L2CLKOUT output jitter(6) ±150 ±150 ps

PC7400

2103A–06/01

Figure 16. L2CLK_OUT Output Timing Diagram

Note: VM = Midpoint Voltage (L2OVDD/2)

tCHCL

tL2CLK

tL2CR tL2CF

L2 Single-Ended Clock Mode

L2CLK_OUTA

L2CLK_OUTB

L2SYNC_OUT

L2CLK_OUTA

L2CLK_OUTB

L2SYNC_OUT

tCHCL

tL2CLK

VM VM VM

tL2CSKW

L2 Differential Clock Mode

30 PC7400

2103A–06/01

L2 Bus AC

Specifications

Table 13 provides the L2 bus interface AC timing specifications for the PC7400 as defined in

Figure 17 and Figure 18 for the loading conditions described in Figure 19.

Notes: 1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD.

2. All input specifications are measured from the midpoint of the signal in question to the mid-

point voltage of the rising edge of the input L2SYNC_IN (see Figure 17). Input timings are

measured at the pins.

3. All output specifications are measured from the midpoint voltage of the rising edge of

L2SYNC_IN to the midpoint of the signal in question. The output timings are measured at

the pins. All output timings assume a purely resistive 50 ohm load (see Figure 19).

4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined reg-

istered synchronous burst RAMs, L2CR[14:15] = 00 is recommended. For pipelined late-

write synchronous burst SRAMs, L2CR[14:15] = 10 is recommended.

Table 13. L2 Bus Interface AC Timing Specifications at VDD = AVDD = L2AVDD = 1.8V ±

100mV; -55°C ≤=Tj ≤ 125°C, L2OVDD = 3.3V ± 165mV or L2OVDD = 2.5V ± 100mV or L2OVDD =

1.8V±100mV

Symbol Parameter

350, 400 MHz

UnitMin Max

tL2CR & tL2CF(1) L2SYNC_IN rise and fall time 1.0 ns

tDVL2CH(2)

Setup Times

Data and parity 1.5

tDXL2CH(2)

Input Hold Times

Data and parity 0.0

tL2CHOV(3, 4) Valid Times

All outputs when L2CR[14:15] = 00

All outputs when L2CR[14:15] = 01

All outputs when L2CR[14:15] = 10

All outputs when L2CR[14:15] = 11

2.5

3.0

3.5

4.0

tL2CHOX(3) Output Hold Times

All outputs when L2CR[14:15] = 00

All outputs when L2CR[14:15] = 01

All outputs when L2CR[14:15] = 10

All outputs when L2CR[14:15] = 11

0.4

1.0

1.4

1.8

tL2CHOZ L2SYNC_IN to high impedance

All outputs when L2CR[14:15] = 00

All outputs when L2CR[14:15] = 01

All outputs when L2CR[14:15] = 10

All outputs when L2CR[14:15] = 11

2.0

2.5

3.0

3.5

PC7400

2103A–06/01

Figure 17. L2 Bus Input Timing Diagram

Note: VM = Midpoint Voltage (L2OVDD/2)

Figure 18. L2 Bus Output Timing Diagram

Note: VM = Midpoint Voltage (L2OVDD/2)

Figure 19. AC Test Load for the L2 Interface

L2SYNC_IN

L2 Data and Data

Parity Inputs

tL2CR tL2CF

tDVL2CH tDXL2CH

L2SYNC_IN

All Outputs

L2CHOV

L2CHOX

L2CHOZ

L2DATA BUS

Z0 = 50 Ohms

RL = 50 Ohms

L2OVDD/2

Output

32 PC7400

2103A–06/01

IEEE 1149.1 AC Timing

Specifications

Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 20,

Figure 21, Figure 22 and Figure 23.

Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the

midpoint of the signal in question. The output timings are measured at the pins. All output

timings assume a purely resistive 50 ohm load (see Figure 20). Time-of-flight delays must

be added for trace lengths, vias and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization

Figure 20. Alternate AC Test Load for the JTAG Interface

Table 14. JTAG AC Timing Specifications (Independent of SYSCLK)(1) at recommended

operating conditions (see Table 5)

Symbol Parameter Min Max Unit

fTCLK TCK frequency of operation 0 33.3 MHz

t TCLK TCK cycle time 30 ns

tJHJL TCK clock pulse width measured at 1.4V 15 ns

tJR & tJF TCK rise and fall times 0 2 ns

tTRST(2) TRST assert time 25 ns

tDVJH(3)

tIVJH

Input Setup Times

Boundary-scan data

TMS, TDI

tDXJH(3)

tIXJH

Input Hold Times

Boundary-scan data

TMS, TDI

tJLDV(4)

tJLOV

Valid Times

Boundary-scan data

TDO

tJLDX

tJLOX

Output Hold Times

Boundary-scan data

TDO

tJLDZ(4, 5)

tJLOZ(5)

TCK to output high impedance

Boundary-scan data

TDO

Z0 = 50 Ohms

RL = 50 Ohms

Output

PC7400

2103A–06/01

Figure 21. JTAG Clock Input Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2)

Figure 22. TRST Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2)

Figure 23. Boundary-scan Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2)

TCLK

tJR tJF

tJHJL

tTCLK

T125T

tT125T

TCK

tJLDX

Boundary

Data Inputs

Boundary

Data Outputs

Boundary

Data Outputs

Input Data

Valid

tDVJH tDXJH

tJLDV

tJLDZ

Output Data Valid

34 PC7400

2103A–06/01

Figure 24. Test Access Port Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2)

Preparation for

Delivery

Packaging Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.

Certificate of

Compliance

Atmel-Grenoble supplies a certificate of compliance with each shipment of parts, confirming

the parts are in compliance either with MIL-PRF-883 and guaranteeing the parameters not

tested at extreme temperatures for the entire temperature range.

Handling MOS devices must be handled with certain precautions to avoid damage due to accumulation

of static charge. Input protection devices have been designed in the chip to minimize the effect

of static buildup. However, the following handling practices are recommended:

•Devices should be handled on benches with conductive and grounded surfaces.

•Ground test equipment, tools and operator.

•Do not handle devices by the leads.

•Store devices in conductive foam or carriers.

•Avoid use of plastic, rubber or silk in MOS areas.

•Maintain relative humidity above 50 percent if practical.

•For CI-CGA packages, use specific tray to take care of the highest height of the package

compared with the normal CBGA.

TCK

tJLOX

TDI, TMS

TDO

Input Data

Valid

tIVJH tIXJH

tJLOV

tJLOZ

Output Data Valid

PC7400

2103A–06/01

Package

Mechanical

Data

Parameters The package parameters are as provided in the following list. The package type is 25 x 25

mm, 360-lead CBGA and CI-CGA.

The following remarks apply to Figure 25 and Figure 26:

•Dimensions and tolerancing are as per ASME Y14.5M-1994.

•All dimensions are in millimeters.

•Top side A1 corner index is a metalized feature with various shapes. Bottom side A1

corner is designated with a ball missing from the array.

•Dimension B is the maximum solder ball diameter measured parallel to datum A.

•D2 and E2 define the area occupied by the die and underfill. Actual size of this area may

be smaller than shown. D3 and E3 are the minimum clearance from the package edge to

the chip capacitors.

Table 15. Package Parameters

Parameter

Package outline 25 mm x 25 mm

Interconnects 360 (19 x 19 ball array minus one)

Pitch 1.27 mm (50 mil)

Minimum module height 2.65 mm (CBGA), 3.65 mm (CI-CGA)

Maximum module height 3.20 mm (CBGA), 4.20 mm (CI-CGA)

Ball or column diameter 0.89 mm (35 mil)

36 PC7400

2103A–06/01

Figure 25. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball CBGA

Package

Parameter Min Max Parameter Min Max

A 2.623.20D32.75–

A1 0.8 1.00 D4 6.00

A2 1.10 1.30 E 25.00 BASIC

A3 –0.6 E1 22.86 BASIC

A4 0.82 0.9 E2 –15

B 0.820.93E33.00–

D 25.00 BASIC E4 1.5

D1 22.86 BASIC G 1.27 BASIC

D2 –13

0.15 A

360X

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

E0.3

0.15

17 18 19

PIN A1

0.22X

TOP VIEW

INDEX

0.2

BOTTOM VIEW

0.2

360 X

0.35 A

GND : C1.2 C1.1 C3.2 C4.2 C5.2 C6.2

C1.1, C2.1 : L2OVDD

C3.1, C6.1 : VDD

C4.1, C5.1 : OVDD

PC7400

2103A–06/01

Figure 26. Mechanical Dimensions and Bottom Surface Nomenclature of the

360-column CI-CGA Package

Parameter Min Max Parameter Min Max

A 3.4 4.20 D3 2.75 –

A1 1.545 1.695 D4 6.00

A2 1.10 1.30 E 25.00 BASIC

A3 –0.6 E1 22.86 BASIC

A4 0.82 0.9 E2 –15

B 0.82 0.93 E3 1.5 –

D 25.00 BASIC E4 8.00

D1 22.86 BASIC G 1.27 BASIC

D2 –13

0.15 A

360X

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

E0.3

0.15

17 18 19

PIN A1

0.22X

TOP VIEW

INDEX

0.2

360 X

0.35 A

GND : C1.2 C1.1 C3.2 C4.2 C5.2 C6.2

C1.1, C2.1 : L2OVDD

C3.1, C6.1 : VDD

C4.1, C5.1 : OVDD

38 PC7400

2103A–06/01

Clock Selection The PC7400’s PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) fre-

quency, the PLL configuration signals set the internal CPU and VCO frequency of operation.

The PLL configuration for the PC7400 is shown in Table 16 for example frequencies.

Notes: 1. PLL_CFG[0:3] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

frequencies which are not useful, not supported, or not tested for by the PC7400; see “Clock AC Specifications” on page 23

for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode

is set for 1:1 mode operation. This mode is intended for factory use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the PC7400 regardless of the SYSCLK input.

Table 16. PC7400 Microprocessor PLL Configuration

PLL_CFG[0:3]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-Core

Multiplier

Core-to-VCO

Multiplier

Bus

25 MHz

Bus

33.3 MHz

Bus

50 MHz

Bus

66.6 MHz

Bus

75 MHz

Bus

100 MHz

0100 2x 2x

0110 2.5x 2x

1000 3x 2x 300 (600)

1110 3.5x 2x 350 (700)

1010 4x 2x 300 (600) 400 (800)

0111 4.5x 2x 300(600) 337 (675)

1011 5x 2x 333 (666) 375 (750)

1001 5.5x 2x 366 (733)

1101 6x 2x 300 (600) 400 (800)

0101 6.5x 2x 325 (630)

0010 7x 2x 350 (700)

0001 7.5x 2x 375 (750)

1100 8x 2x 400 (800)

0000 9x 2x 300 (600)

0011 PLL off/bypass PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

1111 PLL off PLL off, no core clocking occurs

PC7400

2103A–06/01

The PC7400 generates the clock for the external L2 synchronous data SRAMs by dividing the

core clock frequency of the PC7400. The divided-down clock is then phase-adjusted by an on-

chip delay-lock-loop (DLL) circuit and should be routed from the PC7400 to the external

RAMs. A separate clock output, L2SYNC_OUT is sent out half the distance to the SRAMs and

then returned as an input to the DLL on pin L2SYNC_IN so that the rising-edge of the clock as

seen at the external RAMs can be aligned to the clocking of the internal latches in the L2 bus

interface.

The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the

L2CR register. Generally, the divisor must be chosen according to the frequency supported by

the external RAMs, the frequency of the PC7400 core and the phase adjustment range that

the L2 DLL supports. Table 17 shows various examples of L2 clock frequencies that can be

obtained for a given set of core frequencies. The minimum L2 frequency target is 100MHz.

Note: The core and L2 frequencies are for reference only. Some examples may represent core or L2

frequencies which are not useful, not supported or not tested for by the PC7400; see “L2 Clock

AC Specifications” on page 27 for valid L2CLK frequencies. The L2CR[L2SL] bit should be set

for L2CLK frequencies less than 110 MHz.

System Design

Information

PLL Power Supply

Filtering

The AVDD and L2AVDD power signals are provided on the PC7400 to provide power to the

clock generation phase-locked loop and L2 cache delay-locked loop, respectively. To ensure

stability of the internal clock, the power supplied to the AVDD input signal should be filtered of

any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to

the one shown in Figure 27 using surface mount capacitors with minimum effective series

inductance (ESL) is recommended.

The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled

from nearby circuits. An identical but separate circuit should be placed as close as possible to

the L2AVDD pin. It is often possible to route directly from the capacitors to the AVDD pin, which

is on the periphery of the 360-ball CBGA footprint without the inductance of vias. The L2AVDD

pin may be more difficult to route but is proportionately less critical.

Figure 27. PLL Power Supply Filter Circuit

Table 17. Sample Core-to-L2 Frequencies

Core Frequency in MHz ÷1÷1.5÷2÷2.5÷3÷3.5÷4

300 300 200 150 120 100

333 333 222 166 133 111

350 175 140 117 100

366 183 147 122 105

400 200 160 133 114 100

VDD

10Ω

2.2 µF2.2 µF

GND

AVDD (or L2AVDD)

40 PC7400

2103A–06/01

The notes in Table 3 contain cautions about the sequencing of the external bus voltages and

core voltage of the PC7400 (when they are different). These cautions are necessary for the

long term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection

diodes will be forward-biased and excessive current can flow through these diodes. If the sys-

tem power supply design does not control the voltage sequencing, one or both of the circuits

of Figure 28 can be added to meet these requirements. The MUR420 Schottky diodes of Fig-

ure 28 control the maximum potential difference between the external bus and core power

supplies on power-up and the 1N5820 diodes regulate the maximum potential difference on

power-down.

Figure 28. Example Voltage Sequencing Circuits

Decoupling

Recommendations

Due to the PC7400’s dynamic power management feature, large address and data buses and

high operating frequencies, the PC7400 can generate transient power surges and high fre-

quency noise in its power supply, especially while driving large capacitive loads. This noise

must be prevented from reaching other components in the PC7400 system and the PC7400

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the

system designer place at least one decoupling capacitor at each VDD, OVDD, and L2OVDD pin

of the PC7400. It is also recommended that these decoupling capacitors receive their power

from separate VDD, (L2)OVDD, and GND power planes in the PCB, utilizing short traces to min-

imize inductance.

These capacitors should have a value of 0.01 µF or 0.1 µF. Only ceramic SMT (surface mount

technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603

orientations where connections are made along the length of the part. Consistent with the rec-

ommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black

Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling Pow-

erPC microprocessors, multiple small capacitors of equal value are recommended over using

multiple values of capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed around

the PCB, feeding the VDD, L2OVDD, and OVDD planes to enable quick recharging of the smaller

chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance)

rating to ensure the quick response time necessary. They should also be connected to the

power and ground planes through two vias to minimize inductance. Suggested bulk capacitors

are 100-330 µF (AVX TPS tantalum or Sanyo OSCON).

Connection

Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appro-

priate signal level. Unused active low inputs should be tied to OVDD. Unused active high inputs

should be connected to GND. All NC (no-connect) signals must remain unconnected.

MUR420 MUR420 MUR420

1N5820

MUR420 MUR420

1N5820

3.3V 1.8V 1.8V

2.5V

PC7400

2103A–06/01

Power and ground connections must be made to all external VDD, OVDD, L2OVDD, and GND

pins of the PC7400.

See “L2 Clock AC Specifications” on page 27 for a discussion of the L2SYNC_OUT and

L2SYNC_IN signals.

Output Buffer DC

Impedance

The PC7400 60x and L2 I/O drivers are characterized over process, voltage and temperature.

To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then the

value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 29).

The output impedance is the average of two components, the resistances of the pull-up and

pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed

until the voltage at the pad equals OVDD/2. RN then becomes the resistance of the pull-down

devices. When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the

voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP

and RN are designed to be close to each other in value. Then Z0 = (RP + RN)/2.

Figure 29. Driver Impedance Measurement

Table 18 summarizes the signal impedance results. The impedance increases with junction

temperature and is relatively unaffected by bus voltage.

Pull-up Resistor

Requirements

The PC7400 requires high-resistive (weak: 10 KΩ) pull-up resistors on several control pins of

the bus interface to maintain the control signals in the negated state after they have been

actively negated and released by the PC7400 or other bus masters. These pins are TS,

ARTRY, SHDO and SHD1.

In addition, the PC7400 has one open-drain style output that requires a pull-up resistor (weak

or stronger: 4.7 KΩ–10 KΩ) if it is used by the system. This pin is CKSTP_OUT.

Table 18. Impedance Characteristics with VDD = 1.8V, OVDD = 3.3V, Tj = -55°C to 125°C

Impedance Processor bus L2 Bus Symbol Unit

RN32 - 43 39 - 48 Z0Ohms

RP36 - 48 41 - 50 Z0Ohms

OVDD

OGND

SW2

SW1

Pad

Data

42 PC7400

2103A–06/01

During inactive periods on the bus, the address and transfer attributes may not be driven by

any master and may therefore float in the high-impedance state for relatively long periods of

time. Since the PC7400 must continually monitor these signals for snooping, this float condi-

tion may cause excessive power draw by the input receivers on the PC7400 or by other

receivers in the system. It is recommended that these signals be pulled up through weak (10

KΩ) pull-up resistors by the system, or that they may be otherwise driven by the system during

inactive periods of the bus. The snooped address and transfer attribute inputs are A[0:31],

AP[0:3], TT[0:4], and GBL.

The data bus input receivers are normally turned off when no read operation is in progress and

therefore do not require pull-up resistors on the bus. Other data bus receivers in the system,

however, may require pull-ups, or that those signals be otherwise driven by the system during

inactive periods by the system. The data bus signals are D[0:63], DP[0:7]

If address or data parity is not used by the system, and the respective parity checking is dis-

abled through HID0, the input receivers for those pins are disabled, and those pins do not

require pull-up resistors and should be left unconnected by the system. If all parity generation

is disabled through HID0, then all parity checking should also be disabled through HID0, and

all parity pins may be left unconnected by the system.

The L2 interface does not normally require pull-up resistors.

JTAG

Configuration

Signals

Figure 30. Suggested TRST Connection

COP Header

2KΩ2KΩ

PC7400

HRESET

QACK

TRST

HRESET

QACK

From Target

Board Sources

PC7400

2103A–06/01

Figure 31. COP Connector Diagram

Note: Pins 10, 12 and 14 are no connects. Pin 14 is not physically present.

Table 19. COP Pin Definitions

Pins Signal Connection Special Notes

1TDO TDO

2QACK QACK Add 2K pull-down to ground. Must be merged with on-

board QACK, if any.

3TDI TDI

4TRST TRST Add 2K pull-down to ground. Must be merged with on-

board TRST if any. See Figure 30.

5 RUN/STOP No Connect Used on 604e; leave no-connect for all other

processors.

6 VDD_SENSE VDD Add 2K pull-up to OVDD (for short circuit limiting

protection only).

7TCK TCK

8 CKSTP_IN CKSTP_IN Optional. Add 10K pull-up to OVDD. Used on several

emulator products. Useful for checkstopping the

processor from a logic analyzer of other external trigger.

9TMS TMS

10 N/A

11 SRESET SRESET Merge with on-board SRESET, if any.

12 N/A

13 HRESET HRESET Merge with on-board HRESET.

14 N/A Key location; pin should be removed.

15 CKSTP_OUT CKSTP_OUT Add 10K pull-up to OVDD.

16 Ground Digital

Ground

1315

KEY

No pin

TMS

TCK

TDI

TDO

CKSTP_OUT

HRESET

SRESET

RUN/STOP

CKSTP_IN

VDD_SENSE

TRST

QACK

Ground

Top View

44 PC7400

2103A–06/01

Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of

the PC7400 are available on the Internet at www.mot.com/PowerPC/teksupport.) The TRST

signal is optional in the IEEE 1149.1 specification but is provided on all PowerPC implementa-

tions. While it is possible to force the TAP controller to the reset state using only the TCK and

TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is

asserted during power-on reset. Since the JTAG interface is also used for accessing the com-

mon on-chip processor (COP) function of PowerPC processors, simply tying TRST to

HRESET is not practical.

The common on-chip processor (COP) function of PowerPC processors allows a remote com-

puter system (typically a PC with dedicated hardware and debugging software) to access and

control the internal operations of the processor. The COP interface connects primarily through

the JTAG port of the processor with some additional status monitoring signals. The COP port

requires the ability to independently assert HRESET or TRST in order to fully control the pro-

cessor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures or push-button switches, then the COP reset signals

must be merged into these signals with logic.

The arrangement shown in Figure 30 allows the COP to independently assert HRESET or

TRST, while insuring that the target can drive HRESET as well. The pull-down resistor on

TRST ensures that the JTAG scan chain is initialized during power-on if a JTAG interface

cable is not attached; if it is, it is responsible for driving TRST when needed.

The COP header shown in Figure 30 adds many benefits - breakpoints, watchpoints, register

and memory examination/modification and other standard debugger features are possible

through this interface - and can be as inexpensive as an unpopulated footprint for a header to

be added when needed.

The COP interface has a standard header for connection to the target system, based on the

0.025” square-post 0.100” centered header assembly (often called a “Berg” header). The con-

nector typically has pin 14 removed as a connector key, as shown in Figure 31.

Definitions

Datasheet Status

Description Table 20. Datasheet Status

Datasheet Status Validity

Objective specification This datasheet contains target and

goal specifications for discussion with

customer and application validation.

Before design phase

Target specification This datasheet contains target or goal

specifications for product

development.

Valid during the design phase

Preliminary specification

α-site

This datasheet contains preliminary

data. Additional data may be

published later; could include

simulation results.

Valid before characterization

phase

Preliminary specification

β-site

This datasheet also contains

characterization results.

Valid before the industrialization

phase

Product specification This datasheet contains final product

specification.

Valid for production purposes

PC7400

2103A–06/01

Life Support

Applications

These products are not designed for use in life support appliances, devices or systems where

malfunction of these products can reasonably be expected to result in personal injury. Atmel

customers using or selling these products for use in such applications do so at their own risk

and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.

Ordering

Information

Note: 1. For availability of the different versions, contact your Atmel sales office.

Limiting Values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress

above one or more of the limiting values may cause permanent damage to the device. These are

stress ratings only and operation of the device at these or at any other conditions above those given in

the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

Table 20. Datasheet Status

Datasheet Status Validity

PC 7400 M GS U L x

Manufacturer's

Prefix

Type

Package

G: CBGA

GS: CI_CBGA

Screening Level(1)

U: Upscreening

Revision Level(1)

Rev. K

Bus Divider (TBC)

L: Any valid PLL configur

Temperature Range: Tj

M: -55 C, +125 C

V: -40 C, +110 C

Prototype

(X)

Max Internal Processor Speed(1

)

350 MHz

400 MHz

400

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