SST/U401 Series
Vishay Siliconix
Document Number: 70247
S-04031—Rev. F, 04-Jun-01 www.vishay.com
8-1
Monolithic N-Channel JFET Duals
SST404
SST406 U401
U404 U406
PRODUCT SUMMARY
Part Number VGS(off) (V) V(BR)GSS Min (V) gfs Min (mS) IG Typ (pA) VGS1 – VGS2 Max (mV)
U401 –0.5 to –2.5 –40 1 –2 5
SST/U404 –0.5 to –2.5 –40 1 –2 15
SST/U406 –0.5 to –2.5 –40 1 –2 40
FEATURES BENEFITS APPLICATIONS
DMonolithic Design
DHigh Slew Rate
DLow Offset/Drift Voltage
DLow Gate Leakage: 2 pA
DLow Noise
DHigh CMRR: 102 dB
DTight Differential Match vs. Current
DImproved Op Amp Speed, Settling Time Accuracy
DMinimum Input Error/Trimming Requirement
DInsignificant Signal Loss/Error Voltage
DHigh System Sensitivity
DMinimum Error with Large Input Signal
DWideband Differential Amps
DHigh-Speed,Temp-Compensated,
Single-Ended Input Amps
DHigh-Speed Comparators
DImpedance Converters
DESCRIPTION
The SST/U401 series of high-performance monolithic dual
JFETs features extremely low noise, tight offset voltage and
low drift over temperature specifications, and is targeted for
use in a wide range of precision instrumentation applications.
This series has a wide selection of offset and drift
specifications with the U401 featuring a 5-mV offset and
10-mV/_C drift.
The U series, hermetically sealed TO-71 package is available
with full military processing (see Military Information). The SST
series SO-8 package provides ease of manufacturing, and the
symmetrical pinout prevents improper orientation. The SO-8
package is available with tape-and-reel options for
compatibility with automatic assembly methods (see
Packaging Information).
For similar high-gain products in TO-78 packaging, see the
2N5911/5912 data sheet.
TO-71
Top View
U401, U404, U406
G1
S1
D1
G2
D2
S2
1
2
3
6
5
4
S1NC
D1G2
G1D2
NC S2
Narrow Body SOIC
5
6
7
8
2
3
4
1
Top View
SST404, SST406
ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage –40 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate Current 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (1/16” from case for 10 sec.) 300_C. . . . . . . . . . . . . . . . . . .
Storage Temperature : U Prefix –65 to 200_C. . . . . . . . . . . . . . . . . . . . .
SST Prefix –55 to 150_C. . . . . . . . . . . . . . . . . . .
Operating Junction Temperature –55 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation : Per Sidea300 mW. . . . . . . . . . . . . . . . . . . . . . . .
Totalb500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
a. Derate 2.4 mW/_C above 25_C
b. Derate 4 mW/_C above 25_C
For applications information see AN106.