INTEGRATED CIRCUITS DATA SHEET 74LVC161 Presettable synchronous 4-bit binary counter; asynchronous reset Product specification Supersedes data of 1998 May 20 2004 Mar 30 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset FEATURES is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level or a LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four outputs of the flip-flops (pins Q0 to Q3) to LOW-level regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). * 5 V tolerant inputs for interfacing with 5 V logic * Wide supply voltage range from 1.2 V to 3.6 V * CMOS low power consumption * Direct interface with TTL levels * Inputs accept voltages up to 5.5 V * Complies with JEDEC standard no. JESD8B/JESD36 * Asynchronous reset * Synchronous counting and loading * Two count enable inputs for n-bit cascading * Positive edge-triggered clock * ESD protection: The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pins CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by tPHL (propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the following 1 formula: f max = ------------------------------------t PHL ( max ) + t su - HBM EIA/JESD22-A114-B exceeds 2000 V - MM EIA/JESD22-A115-A exceeds 200 V. * Specified from -40 C to +85 C and -40 C to +125 C. DESCRIPTION The 74LVC161 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC161 is a synchronous presettable binary counter which features an internal look-head carry and can be used for high-speed counting. Synchronous operation 2004 Mar 30 74LVC161 2 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH PARAMETER CONDITIONS propagation delay TYPICAL UNIT CL = 50 pF; VCC = 3.3 V CP to Qn 3.9 ns CP to TC 4.5 ns MR to Qn 3.5 ns MR to TC 4.7 ns CET to TC 3.3 ns fclk(max) maximum clock frequency 200 MHz CI input capacitance 5.0 pF CPD power dissipation capacitance per gate 18 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVC161D -40 C to +125 C 16 SO16 plastic SOT109-1 74LVC161DB -40 C to +125 C 16 SSOP16 plastic SOT338-1 74LVC161PW -40 C to +125 C 16 TSSOP16 plastic SOT403-1 74LVC161BQ -40 C to +125 C 16 DHVQFN16 plastic SOT763-1 TYPE NUMBER 2004 Mar 30 3 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 FUNCTION TABLE See note 1. INPUT OPERATING MODES OUTPUT MR CP CEP CET PE Dn Qn TC L X X X X X L L Reset (clear) H X X l l L L H X X l h H * Count H h h h X count * Hold (do nothing) H X l X h X qn * H X X l h X qn L Parallel load Note 1. * = The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH). H = HIGH voltage level. h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition. L = LOW voltage level. l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition. q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition. X = don't care. = LOW-to-HIGH clock transition. PINNING PIN SYMBOL DESCRIPTION 1 MR synchronous master reset (active LOW) 2 CP clock input (LOW-to-HIGH, edge-triggered) 3 D0 data input 4 D1 data input 5 D2 data input 6 D3 data input 7 CEP count enable inputs 8 GND ground (0 V) 9 PE parallel enable input (active LOW) 10 CET count enable carry input 11 Q3 flip-flop output 12 Q2 flip-flop output 13 Q1 flip-flop output 14 Q0 flip-flop output 15 TC terminal count output 16 VCC supply voltage 2004 Mar 30 4 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 handbook, halfpage handbook, halfpage MR VCC 1 16 MR 1 16 VCC CP 2 15 TC CP 2 15 TC D0 3 14 Q0 D0 3 14 Q0 13 Q1 D1 4 13 Q1 D1 4 GND(1) 161 D2 5 12 Q2 D2 5 12 Q2 D3 6 11 Q3 D3 6 11 Q3 CEP 7 10 CET CEP 7 10 CET GND 8 9 PE MNA904 Top view 8 9 GND PE MNA980 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO16 and (T)SSOP16. Fig.2 Pin configuration DHVQFN16. handbook, halfpage 15 handbook, halfpage 1 9 7 TC 10 CTR4 R M1 G3 G4 3 D0 Q0 14 4 D1 Q1 13 5 D2 Q2 12 3 6 D3 Q3 11 4 13 9 PE 5 12 6 11 CEP CET 7 10 CP MR 2 1 2 C2 /1,3,4+ 14 1,2D 4 CT = 15 MNA905 15 MNA906 Fig.3 Logic symbol. 2004 Mar 30 Fig.4 Logic symbol (IEEE/IEC). 5 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 3 handbook, halfpage 4 D0 9 10 5 D1 6 D2 D3 handbook, halfpage PARALLEL LOAD CIRCUITRY PE 2 1 0 1 2 3 4 15 5 14 6 13 7 CET TC 7 74LVC161 CEP 15 BINARY COUNTER CP MR 12 Q0 Q1 Q2 11 10 Q3 9 8 MNA908 MNA907 14 13 12 11 Fig.5 Functional diagram. Fig.6 State diagram. handbook, full pagewidth MR PE D0 D1 D2 D3 CP CEP CET Q0 Q1 Q2 Q3 TC 12 reset preset 13 14 15 0 1 count 2 inhibit MNA909 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit. Fig.7 Timing sequence. 2004 Mar 30 6 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset handbook, full pagewidth 74LVC161 D1 D0 D2 D3 CET CEP PE D FF0 Q D FF1 Q D CP CP Q FF2 Q CP Q RD D FF3 Q CP Q RD Q RD RD CP MR Q0 Q1 Q2 Q3 TC MNA910 Fig.8 Logic diagram. 2004 Mar 30 7 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage CONDITIONS MIN. MAX. UNIT for maximum speed performance 2.7 3.6 V for low voltage applications 1.2 3.6 V 0 5.5 V VI input voltage VO output voltage 0 VCC V Tamb operating temperature in free-air -40 +125 C tr, tf input rise and fall times VCC = 1.2 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V); note 1. SYMBOL PARAMETER CONDITIONS MIN. -0.5 TYP. - VCC supply voltage IIK input diode current VI < 0 V - VI input voltage note 2 -0.5 IOK output diode current VO > VCC or VO < 0 V - 50 MAX. UNIT +6.5 V -50 - mA - +6.5 V - mA VO output voltage note 2 -0.5 - VCC + 0.5 V IO output source of sink current VO = 0 V to VCC - 50 - mA ICC, IGND VCC or GND current - 100 - mA Tstg storage temperature -65 - +150 C Ptot power dissipation - 500 - mW Tamb = -40 C to +125 C; note 3 Notes 1. Stresses beyond those listed may cause permanent damage to the device. These are stress rating only and functional operation of the device at these or any other condition beyond those indicated under "Recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. For SO16 packages: above 70 C derate linearly with 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 C derate linearly with 4.5 mW/K. 2004 Mar 30 8 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER TYP.(1) MIN. OTHER MAX. UNIT VCC (V) Tamb = -40 C to +85 C HIGH-level input voltage 1.2 VCC - - V 2.7 to 3.6 2.0 - - V VIL LOW-level input voltage 1.2 - - GND V 2.7 to 3.6 - - 0.8 V VOH HIGH-level output voltage IO = -100 A 2.7 to 3.6 VCC - 0.2 VCC - V IO = -12 mA 2.7 VCC - 0.5 - - V IO = -18 mA 3.0 VCC - 0.6 - - V IO = -24 mA 3.0 VCC - 0.8 - - V IO = 100 A 2.7 to 3.6 - GND 0.2 V IO = 12 mA 2.7 - - 0.4 V IO = 24 mA 3.0 - - 0.55 V VIH VOL LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND 3.6 - 0.1 5 A ICC quiescent supply current VI = VCC or GND; IO = 0 A 3.6 - 0.1 10 A ICC additional quiescent VI =VCC - 0.6 V; supply current per IO = 0 A input pin 2.7 to 3.6 - 5 500 A 2004 Mar 30 9 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 TEST CONDITIONS SYMBOL PARAMETER TYP.(1) MIN. OTHER MAX. UNIT VCC (V) Tamb = -40 C to +125 C VIH VIL VOH VOL HIGH-level input voltage 1.2 VCC - - V 2.7 to 3.6 2.0 - - V LOW-level input voltage 1.2 - - GND V 2.7 to 3.6 - - 0.8 V HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = -100 A 2.7 to 3.6 VCC - 0.3 - - V IO = -12 mA 2.7 VCC - 0.65 - - V IO = -18 mA 3.0 VCC - 0.75 - - V IO = -24 mA 3.0 VCC - 1 - - V IO = 100 A 2.7 to 3.6 - - 0.3 V IO = 12 mA 2.7 - - 0.6 V IO = 24 mA 3.0 - - 0.8 V VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND 3.6 - - 20 A ICC quiescent supply current VI = VCC or GND; IO = 0 A 3.6 - - 40 A ICC additional quiescent VI =VCC - 0.6 V; supply current per IO = 0 A input pin 2.7 to 3.6 - - 5000 A Note 1. Typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2004 Mar 30 10 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 500 . CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = -40 C to +85 C; note 1 tPHL/tPLH propagation delay CP to Qn propagation delay CP to TC propagation delay CET to TC tPHL propagation delay MR to Qn propagation delay MR to TC tW trem tsu tsk(0) 2004 Mar 30 see Figs 10 and 14 see Figs 11 and 14 see Figs 11 and 14 see Fig.9 master reset width LOW see Fig.11 removal time MR to CP set-up time Dn to CP set-up time CEP, CET to CP fclk(max) see Figs 9 and 14 clock pulse width HIGH or LOW set-up time PE to CP th see Figs 9 and 14 - 17 - ns 2.7 1.5 - 7.2 ns 3.0 to 3.6 1.5 3.9(2) 7.3 ns 1.2 - 20 - ns 2.7 1.5 - 7.8 ns 3.0 to 3.6 1.5 4.5(2) 7.8 ns 1.2 - 16 - ns 2.7 1.5 - 6.5 ns 3.0 to 3.6 1.5 3.3(2) 6.0 ns 1.2 - 17 - ns 2.7 1.5 - 7.1 ns 3.0 to 3.6 1.5 3.5(2) 6.4 ns 1.2 - 18 - ns 2.7 1.5 - 8.6 ns 3.0 to 3.6 1.5 4.7(2) 8.0 ns 2.7 5.0 - - ns 4.0 1.2(2) - ns 3.0 to 3.6 see Fig.11 see Fig.12 see Fig.12 see Fig.13 hold time Dn, PE, CEP, CET to CP see Figs 12 and 13 maximum clock frequency see Fig.9 skew 1.2 note 3 11 2.7 4.0 - - ns 3.0 to 3.6 3.0 1.6(2) - ns 2.7 0.0 - - ns 3.0 to 3.6 0.5 0.0(2) - ns 2.7 3.0 - - ns 3.0 to 3.6 2.5 1.0(2) - ns 2.7 3.5 - - ns 3.0 to 3.6 3.0 1.2(2) - ns 2.7 5.5 - - ns 3.0 to 3.6 5.0 2.1(2) - ns 2.7 0.0 - - ns 3.0 to 3.6 0.5 0.0(2) - ns 2.7 150 - - MHz 3.0 to 3.6 150 200(2) - MHz 3.0 to 3.6 - - 1.0 ns Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = -40 C to +125 C tPHL/tPLH propagation delay CP to Qn propagation delay CP to TC propagation delay CET to TC tPHL propagation delay MR to Qn propagation delay MR to TC tW trem tsu th fclk(max) tsk(0) see Figs 9 and 14 see Figs 9 and 14 see Figs 10 and 14 see Figs 11 and 14 see Figs 11 and 14 clock pulse width HIGH or LOW see Fig.9 master reset width LOW see Fig.11 removal time MR to CP see Fig.11 set-up time Dn to CP see Fig.12 set-up time PE to CP see Fig.12 set-up time CEP, CET to CP see Fig.13 hold time Dn, PE, CEP, CET to CP see Figs 12 and 13 maximum clock frequency see Fig.9 skew note 3 1.2 - - - ns 2.7 1.5 - 9.0 ns 3.0 to 3.6 1.5 - 9.5 ns 1.2 - - - ns 2.7 1.5 - 10.0 ns 3.0 to 3.6 1.5 - 10.0 ns 1.2 - - - ns 2.7 1.5 - 8.5 ns 3.0 to 3.6 1.5 - 7.5 ns 1.2 - - - ns 2.7 1.5 - 9.0 ns 3.0 to 3.6 1.5 - 8.0 ns 1.2 - - - ns 2.7 1.5 - 11.0 ns 3.0 to 3.6 1.5 - 10.0 ns 2.7 5.0 - - ns 3.0 to 3.6 4.0 - - ns 2.7 4.0 - - ns 3.0 to 3.6 3.0 - - ns 2.7 0.0 - - ns 3.0 to 3.6 0.5 - - ns 2.7 3.0 - - ns 3.0 to 3.6 2.5 - - ns 2.7 3.5 - - ns 3.0 to 3.6 3.0 - - ns 2.7 5.5 - - ns 3.0 to 3.6 5.0 - - ns 2.7 0.0 - - ns 3.0 to 3.6 0.5 - - ns 2.7 150 - - MHz 3.0 to 3.6 150 - - MHz 3.0 to 3.6 - - 1.5 ns Notes 1. All typical values are measured at Tamb = 25 C. 2. Typical values are measured at VCC = 3.3 V. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2004 Mar 30 12 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 AC WAVEFORMS 1/fmax handbook, full pagewidth VI CP input VM GND tW t PHL t PLH VOH VM Qn, TC output VOL MNA911 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.9 Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock frequency. handbook, halfpage VI CET input VM GND tPLH tPHL VOH VM TC output VOL MNA912 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.10 Input (CET) to output (TC) propagation delays. 2004 Mar 30 13 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 VI handbook, full pagewidth VM MR input GND t rem tW VI CP input VM GND t PHL VOH VM Qn, TC output VOL MNA913 Fig.11 Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master reset to clock (CP) removal times. VI handbook, full pagewidth VM PE input GND t su t su th th VI VM CP input GND t su t su th th VI VM Dn input GND MNA914 The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.12 Set-up and hold times for the input (Dn) and parallel enable input (PE). 2004 Mar 30 14 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 VI handbook, full pagewidth VM CEP, CET input GND th th tsu tsu VI VM CP input GND MNA915 The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.13 CEP and CET set-up and hold times. VEXT VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL mna616 VCC VI CL RL (1) VEXT tPLH/tPHL tPZH/tPHZ tPZL/tPLZ 1.2 V VCC 50 pF 500 open GND 2 x VCC 2.7 V 2.7 V 50 pF 500 open GND 2 x VCC 3.0 V to 3.6 V 2.7 V 50 pF 500 open GND 2 x VCC Note 1. The circuit performs better when RL = 1000 . Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.14 Load circuitry for switching times. 2004 Mar 30 15 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 2004 Mar 30 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 16 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 2004 Mar 30 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 17 o Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 2004 Mar 30 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 18 o Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 16 9 Eh e 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- 2004 Mar 30 19 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Mar 30 20 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA76 (c) Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/03/pp21 Date of release: 2004 Mar 30 Document order number: 9397 750 10505