Camelia M1 8M LV_CL - Atmel Corporation

5319B–IMAGE–10/03

Main Features

•High Sensitivity Full Frame CCD Sensor

•2300 x 3500 Resolution with 10 µm Square Pixels

•100% Aperture Pixels

•12-bit Dynamic Range

•Very Low Noise: 65 dB SNR

•Binning and ROI Modes

•LVDS or CameraLink Data Fo rmat (Base Configuratio n)

•High Data Rate: 25 Mpixels/s

•Flexible and Easy to Operate via RS-232 Control

– Trigger Mode: Free Run or External Trigger Modes

– Binning 2 x 2 and 4 x 4, Up to 5 ROI

– Exposure Time

– Gain: -5 to 29 dB by Step of 0.04 dB

– Offset: 0 to 255 LSB

– 3-Shot Color Operation

– Test Pattern Generation

•Single Power Supply: 24VDC

•High Reliability – CE and FCC Compliant

•F (Nikon) Mount Adapter (Lens Not Supplied)

Description

This camera is designed to meet high performance and quality requiremen ts while

providin g ease of use. Atmel manages the entire process , f rom the sensor to th e cam-

era. The result is a camera able to work in 12 bits, with dedicated electronics that

provide excellent signal to noise ratio.Because of the 100% aperture pixel, the sensi-

tivity of the camera is fairly high even in near infrared.The programmable settings let

the user work with different integration times, gains and offsets. The external tr igger

allows the user to synchronize the camera on an exter nal event while the 3-shot color

mode allows very high resolution for color image acquisition.

Applications

The performance and reliability of this camera make it well suited for the most

demanding applications such as film and document scann ing, semiconductor and

PCB inspection, DNA analysis, metrology, X-ray imaging, etc...

B & W 8 Megapixels

LVDS and

CameraLink™

Digital Cameras

CAMELIA M1 LV 8M

CAMELIA M1 CL 8M

Preliminary

Rev. 5319B–IMAGE–10/0 3

2CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Improvements The Camelia 8M has been redesigned:

• To add new features:

– Gain: 928 steps from -5 to 29 dB

– Offset: 0 to 255 LSB

– Test pattern: ramps up from 0 to 2298 pixel values on each line

– Median filter: to remove 1 x 1 and column defe cts

• To improve the electro-optical performances, in particular by:

– Reducing power consumption from 8.5 W down to 5.5 W, using a new front

panel and internal heat sink. This lowers the CCD temperature by 5°C, t h u s

decreasing th e magnitude of “white pixels”.

– Decreasing the typical temporal noise from 2.7 to 2.4 LSB

• To interface with more standard and more cost effective cables

• To improve reliability

• Camelia M1 8M is CE and FCC compliant

What changes for the user?

• New additional commands for gain, offset and test pattern

• Interface connectors:

– DATA & SYNC is a 3M MDR connector with improved availability, the same

pinout but different mechanics

– RS-232 is a D-Sub 9 female for full-duplex transmission

– The power supply connector has a camera standard pinout

– TTL CONTROL is a new D-Sub 9 male connector avoiding the use of a Y

cable

• New rear panel (see position of connectors) Imaging Syst em Description

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

Figure 1. LVDS Imaging System

Figure 2. CameraLink Imaging System

4CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

The Camelia camera is powered by a single 24 V power supply. It is configurable via the

computer’s serial port (by using either CommCam software or a standard RS-232 com-

municator as TTY or Hyperterminal) for LSD cameras. Camelia is configurable via the

serial communication of CameraLink for CameraLink cameras. It also sends digital

video.

As Camelia's CCD is a full fr ame sensor , the user mu st use either pulsed light ing or a

chopper/shutter in front of the camera in order to have only incident lighting on the CCD

during integration time. The user must design an electro-optical interface to drive the

camera, the shutter/chop per or lighting by using the SHUTTER sig nal delivered by the

camera. If required, the system can send an external trigger or external ITC (integration

time control si gnal) to the camera.

The BG38 Filter is essential to have a correct white balance on Color Cameras and for

use with standard optics (for achromaticity purpose).

Note that the following Elements are not provided by Atmel:

• Shutter (LCD or Mechanical)

• BG38 (Anti-infra Red) Filter

• Control Box

•Lens

• Light Source

• +24V Power Supply

•Computer

For a complete explanation of the utility of the BG38 Filter and the Shutter, please con-

sult the associa ted FAQ and the sa mple images on the At mel’s "Camera Document ation

& Software" CD-Rom.

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

CCD Description

Image Format 35.0 mm (V) x 23.0 mm (H)

Figure 3. Sensor Organization

Note: The camera does not output to the 16 dark references.

Active Pixels

Readout Register The readout reg ister is along the small side of the image area (vertical image).

Pixel Geometry Pixels are 10 µm x 10 µm with an aperture ratio of 100%.

Antiblooming by

Clocking Antiblooming can be activated or inhibited (see “Serial Communication” on page 12):

• Antiblooming OFF: antiblooming inhibited. This posit ion is recommended if

antiblooming is not required for the application.

• Antiblooming ON: antiblooming a ctivated.

• When binning is disabled, the antib looming is typically efficient up to 8 times

saturation light.

MPP Photosensitive Zone

Output Register

16 Dark References

3500 Lines

2300 Columns - 100% aperture

- 10 µm square pixels

Table 1. Active Pixels

Mode (set vi a serial com ) Image Size (H x V) Timing Diagram Correspondence

No binning 2300 x 3500 H = M

V = N

2 x 2 pixel binning 1150 x 1750

4 x 4 pixel binning 574 x 875

6CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03
Camera 
Specifications LSB (Least Significant Bit): 12-bit corresponds to 4095 LSB.
Absolute Maximum 
Ratings Storage temperature: -20 to +70°C
Operating tem perature: 0 to +50°C
Operating humidity (non condensing): < 80% at +35°C
Vibration: 2 g sinusoidal, from 10 to 100 Hz
Power supply: +20 to +28V
Weight • Camera with F mount ring: 1400 g
• Camera without F mount ring: 1200 g
Electro-optical 
Performance Conditions:
• Camera operating at ambient temperature: 20°C.
• Camera operating in binning 1 x 1 mode, nominal gain 0 dB (G = 173) and no 
processing filter.
Notes: 1. Full scale value VPE: maximum digital video signal
2. Tempo ral noise VN: r ms value in darkness; measur ed by subtracting 2 images, pixel
to pixel, at 40 ms of integration time
3. This parameter depends on integration time and on the CCD temperature. Thermal
noise doubles with every increase of 16°C temperature. Dark signal doubles with
every increase of 8°C temperature. An inter nal clamp can correct the mean value of
this phenomena.
4. Dark signal non-uniformity: rms value; excludes b lemishes
5. Dynamic range DY = VPE/VN measured at 40 ms of integration time
6. Responsitivity conditions: 3200K, light source powered between 200 and 1100 nm,
measured on the sensor
7. Resolution conditions: VIDEO = 2000 LSB and red light source used
8. Antiblooming ON and integration time = 100 ms
9. Measured at 24V
Table 2.  Electro-optical Perfo rma nce
Parameter Symbol Typical 
Value Unit
Full scale value(1) VPE 4095 LSB
Temporal noise(2)(3) VN 2.4 LSB
Dark signal non-uniformity(3)(4) DSNU 2LSB.s
Dynamic range(5) DY 1700
64.6 dB
Responsivity(6) R51.43 LSB/(nJ/cm2)
Resolution(7)
Horizontal Transfer function at Nyquist
Vertical Contrast Transfer function at Nyquist CTFh
CTFv 20%
20% –
–
Antiblooming (over illumination capability)(8) –8x –
Electrons to LSB conversion –15 e-/LSB
Current consumption(9) I230 mA

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

Spectral Responsivity Figure 4. Spectral Responsivity

Image Grade

Specification • Defect Sizes

– Blemish: 1 x 1 defect

– Cluster: blemish grouping of not more than a given number of adjacent

defects:

1 x 1 < cluster 1 size ≤ 2 x 2

2 x 2 < cluster 2 size ≤ 5 x 5

– Column: one-pixel-wide column with more than 7 contiguous defective pixels

– Defect separation: defects are separated by no less than D min pixels in any

direction

• Defects in Darkness

– Blemish or cluster: pixel(s) whose signal deviate(s) more than 150 LSB

– Column: column whose signal deviates more than 15 LSB

• Defects under Illumination

– Blemish or cluster: pixel(s) that deviate(s) by more than +20% or -30% from

the average pixel

– Column: column which deviates by more than 10% from the average

column.

Defect Test Conditions • Room temperature = 20°C

• Integration time in darkness = 100 ms

• Camera operating in binning 1 x 1 mode

• Light source : Halo ge n 320 0K with BG3 8 (2 mm th ick) IR cut- off with f/11 ape rture

• Test under illumination at 50% saturation level

• No software correct ion performed

100

400 500 600 700 800 900 1000 1100

Responsivity LSB/(nJ/cm2)

Wavelength (nm)

Note: nJ/cm2 measured on the sensor

8CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Classifications

CCD Window

Specification • Thickness = 1.2 mm ± 0.05

• Glass index at 588 nm: n = 1.5255

• Admitted defects rate: 0 inclusions > 10 µm

• Transmittance > 98% in the range of 400-700 nm

• Transmittance > 82% in the range of 700-1000 nm

• Flatness of th e CCD Window < 100 um (concave)

• Flatness of the CCD chip must be within 30 µm

Table 3. Image Grade Classifications

Grade

Blemishes Cluster 1 Cluster 2 Column

Total D min Total D min Total D min Total D min

E≤ 500 3≤ 30 50 ≤ 6 100 ≤ 5 150

H≤ 300 3≤ 10 50 0 – 0 –

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

Camera Features

Regions Of Interest

(ROI ) Caution: This function has been available since October 2001 starting with Camera

S/N: 01321093. For older Cameras, these commands aren’t available and can corrupt

the EEPROM (see “Camera Identification” on page 14).

Camelia 8M can operate in multi ROI mode, allowing masking of regions of the image

and thus increasing frame r ate by a reduced readout time.

The user defines up to 5 windows to be masked. In addition the starting and ending

addresses for each window can be specified.

Time reduction: about 92 µs per masked line.

Two steps (under serial communication):

• Enter the list of starting and ending addresses with the command:

Y=ssss/eeee/ssss/eeee/…/eeee/

• Enter the number of regions masked with the command: F=X (X=0 to 5)

Rules The line addresses must be a multiple of 4 (to be compliant with the binning).

The Image starts at Line 0 and ends at Line 3499 and the smallest area consists

of 4 lines.

The commands must be send in the following order: “Y=…” then “F=…”.

For FGT software users, the user has to resize the number of lines in the FGT se ttings.

Example In order to mask 3 regions in the wafer image defined as follows:

• The first 304 lines at the top of the image (blue backgr ound)

• 748 lines in the center of the image (two center lines of the wafer)

• The last 304 lines of the image (blue background):

– "Y=0/304/1376/2124/3196/3499/"

–"F=3"

In this example readout time will be reduced by 1356 lines which are equivalent to

125 ms.

Figure 5. Readout Time

10 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Gain & Offset Video signal processing gain and off set can be adjusted by setting the Gain and the

Offset via serial communication:

• Gain adjusted from -5.1 to 28.9 d B: G = code 0 to 928

• Nominal gain (factory configuration) is 0 dB: G = code 1 73

• Offset adjusted from 0 to 255 LSB: O = code 0 to 255

• Gain is applied to the video signal before the addition of offset

Antiblooming by

Clocking Antiblooming can be activated or inhibited (set via serial communication):

• Antiblo oming OFF: this position is recommended if antiblooming is not re qu ire d for

the application.

• Antiblooming ON: antiblooming is activated and is effective up to 8 times the

saturation level of the sensor.

Test Pattern In normal mode, the digital video signal from the CCD sensor is available at the LVDS

output interface.

For test purpose a fixed digital pattern is generated and can be available instead of the

video signal at the LVDS output interface.

The digital pattern is ramped up from 0 to 2298 LSB code (line width); each line pre-

sents the same pattern:

This is useful to validate the connection to the acquisition system before adjustment

operations relative to image capt ure.

Selection is set by the Test Pattern Generation command:

• CCD sensor : M = 0

• Test Pattern : M = 1

Median Filter A median filter can be applied to sensor signals in order to remove 1 x 1 defect pixels or

1 pixel width columns avoiding subsequent software processing. This filter produces a

smoothing effect on the image.

• Median filter OFF: M = 0

• Median filter ON: M = 2

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

3-Shot Color Operation In 3-shot color mode, each image is made of 3 fram es: red, green, blue + 1 optional

additional frame (infra red for example):

• The camera must be operated either in external trigger mode or in Integration Tim e

Control (ITC) mode.

• F or each image, the user selects th e color of the next frame by se tting COLOUR_I1

and COLOUR_I2 input signals. COLOUR_I1, _I2 must be valid during both the

TRIG signal’s rising edge (or ITC signal falling edge) and the SHUTTER signal’s

falling edge (see Figure 6).

• Color definition is:

• Integration time can be adjusted differently for each color (set via serial

communication). This provides better signal to noise ratio for the colour with the

lowest sensitivity (i.e the blue).

• Each frame requires a TRIG_ITC signal.

• Camelia 8M camera synchronizes COLOUR_I1, _I2 with the rest of the timing and

sends COLOUR_O1, _O2 to:

– FGT frame grabber for LVDS cameras

– CameraLink frame grabber as the 2 most significant bit of data

PDATA(13,12)

Figure 6. Color Timing Diagram

COLOUR_I2 COLOUR_I1 Frame Color

0 0 Red

0 1 Green

1 0 Blue

1 1 User defined i.e. Infra Red

Frame 00

(red) Frame 01

(green) Frame 10

(blue)

00 01

COLOUR_I

COLOUR_O

FEN

> 0 > 0

SHUTTER

> 0

Red

integration

time

TRIG

Green

integration

time

> 0 > 0

> 0

Blue

integration

time

12 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Serial

Communication

Serial Configuration The camera configuration is set by an RS-232 or CameraLink serial interf ace.

The RS-232 configuration is:

• Full duplex/without handshaking (the camera is configured in DCE/Modem)

• 9600 baud, 8-bit data, no parity bit, 1 stop bit

The CameraLink configuration is:

• 9600 baud, 8-bit data, no parity bit, 1 stop bit

Serial Commands The following features are available:

Table 4. Serial Commands

Function Serial Configuration Comment Serial

Command

Timing mode

3 modes:

- continuous (free running)

- external trigger

- external ITC

T=0

T=1

T=2

Binning

3 modes:

- no binning

- 2 x 2 pixel binning

- 4 x 4 pixel binning

Image size: 2300 (H) x 3500 (V)

Image size: 1150 (H) x 1750 (V)

Image size: 574 (H) x 875 (V)

B=0

B=1

B=2

Gain Range from:

- G = 5.1 dB

- G = 28.9 dB

Steps of around 37 mdB (gain

curve is not fully linear) G=0

G=928

Offset Range from:

- 0 LSB

- 255 LSB Steps of 1 LSB O=0

O=255

Shutter

3 modes:

- inactive (always open)

- active

- inactive (always closed)

S=0

S=1

S=2

Shutter delay

4 positions:

- 1 ms

- 10 ms

- 20 ms

- 40 ms

D=0

D=1

D=2

D=3

Antiblooming

control

2 modes:

- active

- inactive A=0

A=1

Black & white or

3-shot color

mode

2 modes:

- black and white

- 3-shot color C=0

C=1

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

Note: ROI commands have been available since October 2001 starting with Camera

S/N: 01321093. For older Cameras, these commands aren’t available and can corrupt

the EEPROM. If in doubt, please contact our hotline before using ROI function (See

“Camera Identification” on page 14).

Black & white

integration time

or 4th color

integration time

Value: 1 to 2000

Unit: ms

Active modes: Monochrome

and 3-shot color

Must be an integer

Ex: 120 for 120 ms

120.4 not allowed

Ex:

I=120

Red integration

time

Value: 1 to 2000

Unit: ms

Active mode: 3-shot color

Must be an integer

Ex: 120 for 120 ms Ex:

J=120

Green

integration time

Value: 1 to 2000

Unit: ms

Active mode: 3-shot color

Must be an integer

Ex: 120 for 120 ms Ex:

K=120

Blue integration

time

Value: 1 to 2000

Unit: ms

Active mode: 3-shot color

Must be an integer

Ex: 120 for 120 ms Ex:

L=120

ROI: Number of

Windows 0 to 5 windows Ex:

F=2

ROI: Windows

Addresses Line start/Line Stop … Must be an integer divisible by 4

Line Stop >3

First Line = 0; Last Line = 3499

Ex:

Y=1824/2252/

3156/3499/

Test pattern

generation

medial filter

processing

M=0: Sensor image

M=1: Pattern image

M=2: Sensor image filtered To check pow er, transmission...

To remov e 1 x 1 pixel defects

M=0

M=1

M=2

Special

commands

Camera identification readout

User camera identification

readout

Software version readout

Camera configuration readout

Current camera configuration

record

Default camera configuration

restoration

!=0

!=1

!=2

!=3

!=4

!=5

User camera ID $= String of Char Writing and record of the user

camera identification $=

Table 4. Serial Commands (Continued)

Function Serial Configuration Comment Serial

Command

14 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Command Syntax • Valid syntax is: S=n(CR) where:

– S: command identification (S is a single character in upper case)

– n: setting value

– (CR): means "carriage return" (ASCII code = 13)

– No spaces, nor tabs may be inserted between S , =, n and (CR)

– For the Camelia 8M only, each address value is followed by “/”:

Y=ssss/eeee/….eeee/

• Example of a valid command: I=500(CR) (sets the integration time to 500 ms)

• Example of non valid commands:

– I=500(CR): no space

– i=500(CR): i instead of I

– I=3000(CR): 3000 is out of range

– Y=ssss/eeee/sssseeee/: a “/” is missing

Settings Validation New settings are clocked and become valid for the camera at the end of the readout

phase. This means that new settings written before the end of readout of image N will be

used for image N+1. New settings written after the readout of image N and before the

end of readout of image N+1 will be used for image N+2.

Camera Identification A character str ing sto re d in the EEPROM contai ns the product mode l, its ver sion and its

serial number.

Example: CAMEL_8M_01_9851002

stands for: CAMELIA 8M, version 01 , serial number 9851002

It is read by sending: !=0(CR)

The serial number is detailed as follows:

Figure 7. Serial Number

Customer Identification Customer identification is a character string (25 characters max).

• It is set and stored in the EEPROM by sending $=xx..xx

• It is read by sending !=1(CR)

Reading Firmware

Version When receiving !=2(CR) the camera returns the version of the firmware.

Reading Current Settings When receiving !=3(CR) the camera returns its current settings.

98 51 002

Year Number in the week

Week in the year

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

Storing the Current

Configuration When receiving !=4(CR) the camera stores the current configuration in the EEPROM.

Factory Configuration When receiving !=5(CR), the camer a sends back its factory configure d settings:

A=0(CR)

C=0(CR)

G=173(CR)

O=16(CR)

S=1(CR)

B=0(CR)

T=0(CR)

I=0100(CR)

J=0100(CR)

K=0100(CR)

L=0100(CR)

D=2(CR)

M=0(CR)

F=0(CR)

Y=(CR)(not set)

>OK(CR)

16 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Timing 2 x 2 and 4 x 4 pixel binning can be used to enable previewing modes. The preview

mode is only available in black and white, otherwise the user has to use Overlay mode

(correction and software LUT are not applicable on displayed image s).

LVDS Camera Timing Three timing modes are available: continuous, external triggered and Integration Time

Control (ITC).

The signals in the following drawings are described in Table 6:

Notes: 1. Signal present on both connectors.

2. Pixel is defined as valid (part of the Frame) when both LEN and FEN signals are at a

low level.

3. The maximum latency (called Td) after o f 1 reado ut line time defined below depends

on the binning mode. In binning 1 x 1 mode, this delay is around 104 µs.

4. Minimum time at high level of the LEN signal is 10 µs (transfer time between two

lines).

5. Minimum time at high level of the FEN signal is 4 lines readout time (around 416 µs).

6. Shutter delay is adjustable via Commcam or RS-232 commands (1, 5, 10 or 20 ms).

Table 5. Timing Mode

Mode Frame Readout Time Line Readout Time Max Frame Rate

No binning B=0 370 ms 104 µs 2.67 f/s

2 x 2 pixel binning B=1 200 ms 114 µs 4.91 f/s

4 x 4 pixel binning B=2 110 ms 134 µs 8.82 f/s

Table 6. LVDS Frame Timing

Signal Name Description Cam.

In/Out

DATA &

SYNC

Pins

TTL

CONTROL

Pins

LEN Line ENable Low state activ e when pix el

is part of line Out 26/27 –

FEN Frame

ENable Lo w state activ e when lines

are part of frame Out 3/4 –

SHUTTER SHUTTER

sync External shutter Trig output

Signal (high level active) Out 21/22(1) 1(1)

TRIG TRIGger External Trigger Input

Signal (Rising Edge) In 46/47(1) 2(1)

ITC Integration

Time Control Externa l ITC Input Signal

(Falling/Rising Edges) In 46/47(1) 2(1)

PCK Pixel ClocK Internal Master Data Clock

Signal at 25 MHz Out 1/2 –

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

Continuous: T=0 The camera delivers frames continuously:

• Frame N+1 integr ation starts as soon as frame N readout has been completed.

• Integration time is set by RS-232.

• Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1

for Binning 4 x 4).

Figure 8. LVDS Continuous Timin g Diagram

Operation with External

Trigger: T= 1 Integration start is controlled by the user by the external signal TRIG:

• The rising edge of TRIG activates the start of frame integration. This rising edge is

synchroniz ed b y the camer a with a latency o f Td (time delay equivalent to a readout

time for a line: see notes in Table 6 on page 16).

• Integration time is set by RS-232.

• Note: The TRIG signal period must be greater than the sum of the integration time

and frame readout time.

• Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1

for Binning 4 x 4).

Figure 9. LVDS External Trigger Timing Diagram

LEN

Frame

integration

Time set by RS-232

...

Video lines

Line 1

Line 2

Line N-1

Line N

Video lines

M Pixels

Shutter

delay 2 ms

FEN

SHUTTER

Frame readout

LEN

TRIG

Frame

integration

Time set by RS-232 Video lines

Line 1

Line 2

Line N-1

Line N

Video lines

M Pixels

Shutter

delay WaitingFrame readout

FEN

SHUTTER

...

18 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Operation with Integration

Time Control: T=2 Integration is fully controlled by the user by th e external signal ITC:

• The fa lling edge of ITC activates the start of frame integration. This falling edge is

synchroniz ed b y the camer a with a latency o f Td (time delay equivalent to a readout

time for a line: see notes in Table 6 on page 16).

• The rising edge of ITC activates the stop of frame integration. This rising edge is

synchronized by the camera with the same latency as Td.

• Note: The ITC signal period must be greater than the sum of the integration ti me

(defined by ITC low) and frame readout time.

• Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1

for Binning 4 x 4).

Figure 10. LVDS Integration Time Control Timing Diagram

Line Timing • Duty cycle of the PCK is 50%

• Rising and falling edges: 1.5 ns

• Pixel clock PCK and Data rate are: 25 MHz in binning mode 1 x 1, 12.5 MHz in

binning mode 2 x 2 and 6. 25 MHz in binning mode 4 x 4

• Minimum setup time of Data, LEN and FEN, to the rising edge of PCK: 10 ns

• Minimum hold time of Data, LEN and FEN, after the rising edge of PCK: 10 ns

Figure 11. LVDS Line Timing Diagram

LEN

ITC

Frame

integration

Time set by RS-232

...

Video lines

Line 1

Line 2

Line N-1

Line N

Video lines

M Pixels

Td Td

Shutter

delay WaitingFrame readout

FEN

SHUTTER

LEN

PCK

...

DATA

1st Valid Pixel Last Valid Pixel

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

CameraLink Camera

Timing Three timing modes are available: continuous, external triggered and Integration Time

Control (ITC).

The signals in the following drawings are described in Table 7:

Notes: 1. Signal present on both connectors.

2. Pixel is defined as valid (part of the Frame) when both LVAL and FVAL signals are at

a high level.

3. The maximum latency (Td) of 1 read out line time defined below depends on the bin-

ning mode. In binning 1 x 1 mode, this delay is around 104 µs.

4. Minimum time at low level of LVAL signal is 10 µs (transfer time between two lines).

5. Minimum time at low level of FVAL signal is 4 lines readout time (around 416 µs).

6. Shutter delay is adjustable via serial communication commands (1, 5, 10 or 20 ms).

Continuous: T=0 The camera delivers frames continuously:

• Frame N+1 integr ation starts as soon as frame N readout has been completed.

• Integration time is set by serial communication.

• Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1

for Binning 4 x 4).

Figure 12. CameraLink Continuous Timing Diagram

Table 7. CameraLink Frame Timing

Signal Name Description Cam.

In/Out

Camera

Link

Connector

TTL

CONTROL

Connector

LVAL Line VALid High state active when pixel

is part of line Out yes no

FVAL Frame VALid High state active when lines

are part of frame Out yes no

SHUTTER SHUTTER

sync Exter nal shutter Trig output

Sig. (high lev el active) Out no Pin 1(1)

TRIG TRIGger External Trigger Input

Signal (Rising Edge) In CC1+/

CC1-(1) Pin 2(1)

ITC Integration

Time Control External ITC Input Signal

(Falling/Rising Edges) In CC1+/

CC1-(1) Pin 2(1)

PCK Pixel ClocK Internal Master Data Clock

Signal at 25 MHz Out yes no

LEN

Frame

integration

Time set by RS-232 Video lines

Line 1

Line 2

Line N-1

Line N

Video lines

M Pixels

Shutter

delay 2 ms

FEN

SHUTTER

...

Frame readout

20 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Operation with External

Trigger: T= 1 Integration start is controlled by the user with the external signal TRIG:

• The rising edge of TRIG activates the start of frame integration. This rising edge is

synchroniz ed b y the camer a with a latency o f Td (time delay equivalent to a readout

time for a line: see notes in Table 7 on page 19).

• Integration time is set by serial communication.

• Note: The TRIG signal period must be greater than the sum of the integration time

and frame readout time.

• Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1

for Binning 4 x 4).

Figure 13. CameraLink External Trigger Timing Diagram

Operation with Integration

Time Control: T=2 Integration is fully controlled by the user with the external signal ITC:

• The fa lling edge of ITC activates the start of frame integration. This falling edge is

synchroniz ed b y the camer a with a latency o f Td (time delay equivalent to a readout

time for a line: see notes in Table 7 on page 19).

• The rising edge of ITC activates the stop of the frame integration. This rising edge is

synchronized by the camera with the same latency of Td.

• Note: The ITC signal period must be greater than the sum of the integration ti me

(defined by ITC low) and frame readout time.

• Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1

for Binning 4 x 4).

Figure 14. CameraLin k In te gr at ion Tim e Con tr ol Tim in g Dia gr am

LEN

TRIG

Frame

integration

Time set by RS-232 Video lines

Line 1

Line 2

Line N-1

Line N

Video lines

M Pixels

Shutter

delay WaitingFrame readout

FEN

SHUTTER

...

LEN

ITC

Frame

integration

Time set by RS-232 Video lines

Line 1

Line 2

Line N-1

Line N

Video lines

M Pixels

Td Td

Shutter

delay WaitingFrame readout

FEN

SHUTTER

...

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

Line Timing • Duty cycle of the PCK is 50%

• PCK clock rate is 25 MHz

• Data rate (Internal pixel clock) is 25 MHz in binning mode 1 x 1

• Mode binning 1 x 1:

– Data rate is 25 MHz

– DVAL is always in high state

Figure 15. CameraLink Line Timi ng Diagram for Binning 1 x 1

• Mode binning 2 x 2 (and 4 x 4):

– Data rate is 12.5 MHz (or 6.25 MHz)

Figure 16. CameraLink Line Timing Diagram for Binning 2 x 2 (and 4 x 4)

LEN ...

...

PCK

DATA

1st Valid Pixel Last Valid Pixel

LEN

PCK

DVAL

DATA ...

...

1st Valid Pixel Last Valid Pixel

22 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Electrical Interfaces

DATA & SYNC and TTL

CONTROL for LVDS

Camera

Note: 1. LVDS (Low Voltage differential Signal): EIA 644 standard.

All digital I/Os are differential: (signal+, signal-). Specifications are give n for signal +.

LVDS drivers/receivers:

• Manufacturer NS

• Driver: DS90LVO47ATMTC (SO16 package)

• Receiver: DS90LVO48ATMTC (SO16 package)

Table 8. Specifications

Symbol I/O Definition Level

TRIG_ITC I

Timing control:

- TRIG_ITC is either an external trigger or integration

time control (ITC) depending on the timing mode

configured via RS-232.

Operation with external trigger:

- TRIG_ITC = TRIG

Operation with ITC:

- TRIG_ITC = ITC

- TRIG_ITC is synchronized by the camera line clock

(jitter : 104 µs)

LVDS(1)

and TTL

PDATA(11..0) ODigital video output: 12-bit LVDS

FEN OFrame enab le:

- FEN = 0: frame data valid: active lines

- FEN = 1: frame data not valid LVDS

LEN OLine enable:

- LEN = 0: line data valid: active pixels

- LEN = 1: line data not valid LVDS

PCK OPixel clock LVDS

SHUTTER O

Shutter open/close:

- shutter open = 1

- shutter closed = 0

Delay between the falling edge of SHUTTER and the start

of readout:

- 4 positions: 1, 10, 20 or 40 m s (set vi a RS -23 2 )

LVDS

and TTL

COLOUR_I(1..0) I

Color selection of the next frame (in color mode):

- 00: red

- 01: green

- 10: blue

- 11: user defined

LVDS

and TTL

COLOUR_O(1..0) O

Color identification of the current frame (in color mode):

- 00: red

- 01: green

- 10: blue

- 11: user defined

LVDS

and TTL

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

DATA & SYNC Cabling 50-pin connector:

• Connector reference on camera : 3M 10250-6212JL (or 3M 10250-6212VC)

• Mating connector on cable side: 3M 10150-6000EL; shell: 3M 10350-A200-00

• We recommend using a twisted pair shielded cable.

Note: NC: not connected

Table 9. Pinout

Number Signal I/O Pin

Number Signal I/O

1PCK+ O26 LEN+ O

2PCK- O27 LEN- O

3FEN+ O28 COLOUR_O1+ O

4FEN- O29 COLOUR_O1- O

5COLOUR_O2+ O30 GROUND O

6COLOUR_O2- O31 GROUND O

7PDATA0+ O32 PDATA1+ O

8PDATA0- O33 PDATA1- O

9PDATA2+ O34 PDATA3+ O

10 PDATA2- O35 PDATA3- O

11 PDATA4+ O36 PDATA5+ O

12 PDATA4- O37 PDATA5- O

13 PDATA6+ O38 PDATA7+ O

14 PDATA6- O39 PDATA7- O

15 PDATA8+ O40 PDATA9+ O

16 PDATA8- O41 PDATA9- O

17 PDATA10+ O42 PDATA11+ O

18 PDATA10- O43 PDATA11- O

19 GROUND –44 NC –

20 GROUND –45 NC –

21 SHUTTER+ O46 TRIG_ITC+ I

22 SHUTTER- O47 TRIG_ITC- I

23 COLOUR_I1+ I48 COLOUR_I2+ I

24 COLOUR_I1- I49 COLOUR_I2- I

25 NC –50 NC –

24 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

TTL CONTROL Cabling The connector on the camera is D-sub 9 pins male.

Notes: 1. The following signals: TRIG-ITC, COLOUR-I1, COLOUR-I2 are provided by the

DATA & SYNC (MDR50) Connector in LVDS format or by the TTL CONTROL con-

nector; the two diff erent signals are logically “anded” as follows: TRIG-ITC from LVDS

and TRIG-ITC from TTL. The inputs left open are internally tied to a high level.

2. The SHUTTER, COLOUR-O1 and COLOUR-O2 Outputs are available on both DATA

& SYNC and TTL Output Connectors.

Table 10. Pinout

Pin Number

At Camera Output Signal Direction

1SHUTTER Out

2TRIG-ITC In

3COLOUR-I1 In

4COLOUR-I2 In

5NC –

6NC –

7COLOUR-O1 Out

8COLOUR-O2 Out

9 GROUND –

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

CAMERALINK and TTL

CONTROL for

CameraLink Camera

Notes: 1. TRIG_ITC signal is connected on CC1 differential inputs

2. COLOUR_I0 signal is connected on CC2 differential inputs

3. COLOUR_I1 signal is connected on CC3 differential inputs

4. COLOUR_O0 and COLOUR_O1 signals are coded as outputs PDATA(13,12)

5. LVDS (Low Voltage differential Signal): EIA 644 standard

Table 11. Specifications

Symbol I/O Definition Level

TRIG_ITC(1) I

Timing control:

- TRIG_ITC is either an external trigger or integration

time control (ITC) depending on the timing mode

configured via seria l communication.

Operation with external trigger:

- TRIG_ITC = TRIG

Operation with ITC:

- TRIG_ITC = ITC

- TRIG_ITC is synchronized by the camera line clock

(jitter: 104 µs)

LVDS(5)

and TTL

PDATA(11..0) ODigital video output: 12-bit LVDS

FVAL OFrame enable:

- FVAL = 1: frame data valid: active lines

- FVAL = 0: frame data not valid LVDS

LVAL OLine enable:

- LVAL = 1: line data valid: active pixels

- LVAL = 0: line data not valid LVDS

DVAL OData Strobe:

- DVAL = 1: pixel data valid

- DVAL = 0: pixel data not valid LVDS

PCK OPix el clock LVDS

SHUTTER O

Shutter open/close:

- shutter open = 1

- shutter closed = 0

Delay between the falling edge of SHUTTER and the start

of readout:

- 4 positions: 1, 10, 20 or 40 ms

(set via serial communication)

TTL

COLOUR_I(1..0)(2)(3) I

Color selection of the next frame (in 3-shot color mode):

- 00: red

- 01: green

- 10: blue

- 11: user defined

LVDS

and TTL

COLOUR_O(1..0)(4) O

Color identification of the current frame (in 3-shot color

mode):

- 00: red

- 01: green

- 10: blue

- 11: user defined

LVDS

and TTL

26 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

All digital I/Os are differential: (signal+, signal-). Specifications are give n for signal +.

CameraLink drivers/receivers:

• Driver: NS DS90CR285MTD (SO56 package)

• Receiver: NS DS90LVO48ATMTC (SO16 package)

CAMERALINK Cabling 26-pin connector:

• Connector reference on camera: 3M 10226-2210VE

• We recommend using a CameraLink Standard shielded cable such as the

3M 14X26-SZLB-XXX-0LC.

Note: NC: not connected

Table 12. Pinout

Number Signal I/O Pin

Number Signal I/O

1GROUND –14 GROUND –

2X0- O15 X0+ O

3X1- O16 X1+ O

4X2- O17 X2+ O

5XCLK- O18 XCLK+ O

6X3- O19 X3+ O

7SERTC+ I20 SERTC- I

8SERTFG- O21 SERTFG+ O

9CC1- I22 CC1+ I

10 CC2+ I23 CC2- I

11 CC3- I24 CC3+ I

12 CC4+ I25 CC4- I

13 GROUND –26 GROUND –

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

TTL CONTROL Cabling The connector on the camera is D-sub 9 pins male.

Notes: 1. The following signals: TRIG-ITC, COLOUR-I1, COLOUR-I2 are provided by the

DATA & SYNC (MDR26) connector in LVDS format or by the TTL CONTROL connec-

tor; the two different signals are logically “anded” as follows: TRIG-ITC from LVDS

and TRIG-ITC from TTL. The inputs left open are internally tied to a high level.

2. COLOUR-O1 and COLOUR-O2 Outputs are available on both CameraLink and TTL

Output Connectors.

RS-232 for LVDS Camera • On camera side: D-sub 9 pins female

• On computer: side Dsub9 male, pin out compatible with computer serial port

• Note: the cable to be used is a straight pin to pin male-female

Notes: 1. NC: not connecte d

2. Pin 7 and 8 are internally shorted.

Table 13. Pinout

Pin Number

At Camera Output Signal Direction

1SHUTTER Out

2TRIG-ITC In

3COLOUR-I1 In

4COLOUR-I2 In

5NC –

6NC –

7COLOUR-O1 Out

8COLOUR-O2 Out

9 GROUND –

Table 14. Pinout

Pin Number

At camera output Signal

1NC

2TX

3RX

4NC

5GROUND

6NC

7NC

8NC

9NC

28 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Power Supply

Specifications

Cabling • Camera co nnector type: Hir ose HR10A-7R-6PB (male)

• Cab le connector type: Hirose HR10A-7P-6S (female)

Note: NC: not connected

Figure 17. Receptacle Viewed fr om behind the Camera

Caution: Power supply cabling is fully compa tible with Atmel’s AviivA Linescan Cam-

eras. The cabling is NOT compatible with ol d Camelia 8M.

An internal 1A fuse protects the came ra aga in st hig h cu rr en ts.

An internal diode protects the camera against cabling inversion.

Kits of Cable • LVDS-FGT: FGT frame grabber B&W + DATA & SYNC for FGT frame grabber

(length 3 meters) + Power Supply (length 10 meters, open on power supply side)

• CameraLin k: CameraLink (length 5 mete rs) + P ow er Supply (length 10 meters , open

on power supply side)

• Connectors LVDS: 3M MDR 50 + HR10A-7P-6S

Table 15. Power Supply Specifications

Parameter Nominal Value Min Value Max V alue

Voltage +24V +20V +28V

Current 0.23A 0.26A 0.20A

Table 16. Pinout

Pin Number Signal Pin Number Signal

1PWR 4GND

2NC 5NC

3PWR 6GND

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

Mechanical Interface

LVDS Camera with F

Mount Ring

Figure 18. With F Mount Ring

FRONT PANEL

REAR PANEL

First pixel

First line

LVDS Data & Sync

DC 24V

110.5 mm

RS-232TTL Control

114 mm

144.5 mm

108 mm

2 x 1/4 − 20 UNC 2B 25.6 mm

74 ±0.1 mm

37 ± 0.2mm

5 ±0.3 mm 64 ±0.2 mm

26 ±0.3 mm

112 mm

64 ±0.2 mm

2 x ∅ 2h7 4 x M3 4 mm

46.5 mm

Factory adjusted

∅ 66 mm

6 ±0.2 mm

//0.3

30 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

LVDS Camera without F

Mount Ring

Figure 19. Without F Mount Ring

First pixel

First line

114 mm

108 mm

2 x 1/4 − 20 UNC 2B 25.6 mm

74 ±0.1 mm

37 ± 0.2 mm

5 ±0.3 mm 64 ±0.2 mm

8.9 ±0.45 mm

6.9 ±0.6 mm

26 ±0.3 mm

6 ±0.2 mm

2 x ∅ 2h7 4 x M3 4 mm

∅ 66 mm

∅ 56 ±0.1 mm

M 51 - 5 H pas 0.75

64 ±0.2 mm

//0.3

FRONT PANEL

REAR PANEL

LVDS Data & Sync

DC 24V

110.5 mm

RS-232TTL Control

112 mm

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

CameraLink Camera with

F Mount Ring

Figure 20. With F Mount Ring

FRONT PANEL

REAR PANEL

First pixel

First line

CameraLink

DC 24V

110.5 mm

TTL Control

114 mm

144.5 mm

108 mm

2 x 1/4 − 20 UNC 2B 25.6 mm

74 ±0.1 mm

37 ±0.2 mm

5 ±0.3 mm 64 ±0.2 mm

26 ±0.3 mm

112 mm

64 ±0.2 mm

2 x ∅ 2h7 4 x M3 4 mm

46.5 mm

Factory adjusted

∅ 66 mm

6 ±0.2 mm

//0.3

32 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

CameraLink Camera

without F Mount Ring

Figure 21. Without F Mount Ring

First pixel

First line

114 mm

108 mm

2 x 1/4 − 20 UNC 2B 25.6 mm

74 ± 0.1 mm

37 ± 0.2 mm

5 ±0.3 mm 64 ±0.2 mm

8.9 ±0.45 mm

6.9 ±0.6 mm

26 ±0.3 mm

6 ±0.2 mm

2 x ∅ 2h7 4 x M3 4 mm

∅ 66 mm

∅ 56 ±0.1 mm

M 51 - 5 H pas 0.75

64 ±0.2 mm

//0.3

FRONT PANEL

REAR PANEL

DC 24V

110.5 mm

TTL Control

112 mm

CameraLink

CAMELIA M1 8M LVDS and CameraLink Camera

5319B–IMAGE–10/03

Mechanical Mounting

References • Position in the X, Y plan:

– The center pixel of the CCD sensor is positioned within a circle centered on

the optical axis and with a diameter of 0.35 mm. The optical axis is defined

by the mechanical thread for the optical adapter.

– The center pixel of the CCD sensor is referenced to the two needles on the

front panel with a tolerance of ±0.125 mm.

• Position in the Z plan:

– For cameras delivered with an F mount ring, the distance from the CCD

sensor plan to the Nikon mount is adjusted in factory at 46.5 mm.

– For cameras delivered without the F mount ring, the distance from the CCD

sensor plan to the front plan of the thread is 8.9 ±0.45 mm.

• Tilt around the Z axis:

– All the pixels of the CCD sensor are located between two plans,

perpendicular to the optical axis and separated by a maximum distance of

0.26 mm.

34 CAMELIA M1 8M LVDS and CameraLink Camera 5319B–IMAGE–10/03

Standard Conformity The cameras have been tested in the following conditions:

• Camera with complete Atmel housing

• Shielded power supply cable

• Shielde d an d twiste d pa ir da ta transfer cable

• TTL CONTROL cable

• Linear AC-DC power supply

We recommend using the same configuration to ensure compliance with the following

standards.

CE conformity The Camelia Camera complies with the European directive 89/336/CEE (EN55022

B/CISPR22 B, EN55024).

Class A of EN55022 is obtained without condition. Class B of EN55022 is obtained with

ferrite beads on the DATA/SYNC and TTL CONTROL cables.

FCC conformity The Camelia Camera complies with Part 15 of FCC rules.

Operation is subject to the following two conditions:

1. This device may not cause harmful interference, and

2. This device must accept any interference received, including interference that

may cause undesired operation.

This equipment has been tested and found to comply with the limits for a Class A digital

device, pursuant to part 15 of the FCC Rules. These limits are designed to provide rea-

sonable protection against harmful interference when the equipment is operated in a

commercial environment. This equipment generates, uses, and can radiate radio fre-

quency energy and, if not installed and used in accordance with the instruction manual,

may cause harmfu l interference to radio commu nications. Op eration of t his equipment in

a residential area is likely to cause harmful interference in which case the user will be

required to correct the interference at his own expense.

Warning: Changes or modifications to this unit not expressly approved by the party

responsible for compliance could void the user' s authority to operate this equipment.

Ordering Information Table 17. Ordering Code

Part Number Description

AT71XM1LV8MFERCB0 CAMELIA 8M M1 LVDS Grade E with Housing and F-Mount

AT71XM1LV8MFERCA0 CAMELIA 8M M1 LVDS Grade E with Housing and no F-Mount

AT71XM1LV8MFERAA0 CAMELIA 8M M1 LVDS Grade E without Mechanics

AT71XM1CL8MFERCB0 CAMELIA 8M M1 CameraLink Grade E with Housing and F-Mount

AT71XM1CL8MFERCA0 CAMELIA 8M M1 CameraLink Grade E with Housing and no F-Mount

AT71XM1CL8MFERAA0 CAMELIA 8M M1 CameraLink Grade E without Mechanics

AT71-LV-P2C1D1B2 LVDS-FGT Kit (see “Kits of Cable” on page 28)

AT71-LV-P8C8D8A0 Set of LVDS connectors (see “Kits of Cable” on page 28)

AT71-CL-P2C0D3A0 CL Kit (see “Kits of Cable” on page 28)

Printed on recycled paper.

Disclaimer: Atmel Cor poration makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Ter ms and Conditions located on th e Company’s web site. The Company assumes no responsibility fo r any

errors which may appear in this document, reser ves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not author ized for use

as critical components in life suppor t devices or systems.

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5319B–IMAGE–10/03 0M

Camelia™ are the trademarks of Atmel Cor poration or its subsidiar ies. Other terms and product names may be

the trademarks of others.