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SEMICONDUCTOR TECHNICAL DATA Order this document

by Mc54HcT541A/D

–Advance Information I

–Octal 3=State Non=hwerting Mc54/’74HcT541 A

Buffer/Line Driver/Line Receiver

With LSTTL=CompatibIe Enputs 1~

High=Performance Silicon=Gate CMOS

The M(254/74HCT541A is identical in pinout to the LS541. This device

may be used as alevel converter for interfacing lTL or NM(3S outputs to

high speed CMOS inputs.

The HCT541 Ais an octal non-inverting buffer/line driver/line receiver

designed to be used with 3-state memory address drivers, clock drivers,

and other bus-oriented systems. This device features inputs and outputs

on opposite sides of the package and two ANDed active-low output

enables.

o

Q

e

o

e

●

a

—

—

Output Drive Capability 15 LSITL Loads

TWNMOS-Compatible Input Levels

Outputs Directly Interface to CMOS, NMOS and TTL ./>

@

Operating Voltage Range: 4.5 to 5.5V “‘!yi,i

~.+

,.<+

----m+

Jon-inverting

)Utputs

NSUFFIX

PLASTIC

CASE 733-03

e

DW SUFFIX

20 Sole

CASE 751 D-04

1

ORDERING INFORMATION

MC74HCTXXXAN Plastic

MC54HCTXXXAJ Ceramic

MC74HCTXXXADW Sole wide

TA =-55° to 125°C for all packages.

FUNCTION TABLE

Inputs output Y

OE1 0E2 A

L L L L

L L HH

Hx x z

xHxz

?=High Impedance

.

X=Don’t Care

This document contains information on a new product. Specifications and information hereinare subjecl to

—changewithout notice.

5/94

@MOTOROLA

@Matorole, Inc. 1994 REV0.1

MC54/74HCT541 A

Pinout: 20-Lead Packages (Top View)

Vrj-c OE2 Y1 Y2 ‘f3 Y4 WY6 Y? Y8 —

—

Symbol Characteristic Range Unit

Vcc DC Supply Voltage -0.5 to+7.0 v

~n DC Input Voltage Referen&~$@tiD -0.5 to Vcc +0.5 v

VCj”t DC Output Voltage Ref&&cec&o GND -0.5 to Vcc +0.5 v

-%,.,..,+“

Ii” DC Input Current, per Pin ii$..:~

‘ai~,:, *2O mA

{.. ,.!s.,

lout DC Output Current, per Pin ,$.;,).

<.+~+, *35

,>,. at~\a mA

Icc DC Supply Current, VCC and GND Pins ,,.. ..

‘*,

,\),\:$*:$,,#*75 mA

*::’

pD Power Dissipation in Still Air ~~;$~” Plasticor Ceramic DIP? 750 mW

‘+*<>>, SOIC Packagel’ 500 —

,.,,

Tstg Storage Temperature Range .. +,,

.:.\.$\?L.” -65 to +150

.,>4:?’ ‘c

TL Lead Temperature, 1mm from Case f~{~~~~nds Plastic DIP or SOIC pacl=ge 260 “c —

\\*

.X:t .Ceramic DIP 300

.>,,?.,<.%..,

~-w.+,,,,.

*Maximum Ratings are those values beyond wti@wage to the device may occur. Functional operation should be res~cted to the

Recommended Operating Conditions. ,.>,\,J... ,,.

t.,i.,..:...,~?.

%

~’:.,~e$,,

::}s.,,,.>:,,,~.

.

~Derating —Plastic DIP: -l OmW/°Cfrorm4i5~1 W?50C

Ceramic DIP: –lOmW/°C.@r#l@ to 125°C

SOIC Package: -7mW~~}~o$j 65° to 125°C

For high frequency or heavy load ~s/&a#ons, refer to Chapter 4in the High-Speed CMOS Data Book (DL129/D).

,*.‘“.:.S,*

‘:+<;“?,:,?)...,...

RE&MMENDED OPERATfNG CONDITIONS

[SvmboI IParameter IMin IMax IUnit I

IVcc IDC Supply Voltage Referenced to GND I4.5 ~5.5 IVI

Vin,Vout DC Input Voltage, Output Voltage Referenced to GND oVcc v

TA Operatiniemperature Range, All Package Types -55 +125 “c

~,tf Input Rise/Fall Time (Figure 1) o500 ns —

MOTOROLA

2

Mc54/741-lcT541A

—

—

DC CHAR

1

E

Symbol

VIH

VIL

VOH

IVOL

1. Informatia

2. Total SUPI

—

—AC CHAR

1-u

F

tpLf-f,

tpf+L

tp~,

tpHz

ItpzL,

tpzH

>TERISTICS (Voltages Referenced to GND)

I

Parameter Condition

Minimum High-Level input Voltage Vout=O.lV or VCC– O.lV

Iloljtl <2opA

Maximum Low-Level Input Voltage Vout=O.lV or VCC-O.lV

Iloutl ~20W

Minimum High-Level Output Vin =VIH or VIL

Voltage Ilo”tl <2opA

Vin =ViH or VIL IIoutl <6.OmA

Maximum Low-Level Output Vin =VIH OrvlL

Voltage Iloutl <2opA

IVin =VIH or VIL Iloutl -S6.OmA

Maximum Input Leakage Current IVin =VCC or GND

Maximum Three-State Leakage Output in High lmpedan~ State

Current Vin =VIL Or vlH

Vout. VCC or GND

Maximum Quiescent Supply ~n. VCC or GND ,j&

Current (per Package) lout =OJA tti

Jk.>:

1%

Additional Quiescent Supply I~n =2.4V, Any One In@t :.

.\}\>\

Currant ~n =VCC or GND,@$@puts

lout =Opi? ,,:...!..., ..

Q~

$$ ..),

mtypical parametric values can be found in Chapter}~.~~&#gh3p*d ZE+EELl

MOS Data Book (DL129/D).

#

$

,&;;.

*$’ ‘?~:},,:,,

:*,,, ,.,,,

>TERISTICS (Vcc =5.OV, CL =$w&@put tr =tf =6ns)

,$::,&:$“~’

,,;:.’

(~~y++,$ Guaranteed Limit

,~:*&*&ter -65 tO 25°C S85°C S125°C Unit

Maximum Propagation ~~afi:~~tAto Output Y23 28 32 ns

(Figures 1 and 3) ,l:W ,;s3.

Maximum Propa#~~w~ay, Output Enable to Output Y30 34 38

(R9ures 2a~~~~~,,,$ ns

,.,,,.

Maximum F%@$ation Delay,Output Enable to Output Y30 34 38

(Figur@~an&$) ns

~~’~~k@u@ut Transition Kme, Any Output 12 15 18

$~e 1~d 31 ns

Wl$$mum Input Capacitance 10 10 10 pF

‘Maximum Three-State Output Capacitance (Output in High Impedan@ 15 15 15

State) pF

‘x>,.

~~~@~:r#@J$~ wi~ loads other than 5fJPF,and information on typical parametric values, sea Chapter4 of the High-Speed CMOS

...

AC CHARACTERISTICS (CL= 50pF, Input tr =tf . Ens)

Symbol Parameter Typica! at 25”C, VCC =5.OV Unit

CpD Power Dissipation Capacitance (Per Buffer~

—55 pF

*Used to determine the no-load dynamic power mnsumption: PD =CpD VCC2f +ICC Vcc. For load considerations, see Chapter 4of the

—High-Speed CMOS Data Book (DL129/D).

MOTOROLA

3

MC54/74HCT541 A

SWITCHING WAVEFORMS

+

INPUTS

Figure 1.

DEWCE

UNDER

TEST

OUTPUT

TEST

POINT

iudes all probe and jig capacitance

Figure 3.

Al, A2, A3, A4, A5, A6, A7, A8 (PINS 2,3,

TEST

CONNECTTO Vcc WHEN

TESTINGtp~ ANDt’zL.

CONNECT TOGND WHEN

TESTING tp”zand ~~.

PlhR3ESCRlPTIONS

—

—

—

.<.

‘q,,,,

~~..~., .,,,. .

$Ji}~

..

+:$,’$ ?.ay.,. outputs are enabled and the device functions as a

.&’.&k$ 7,8, non-inverting buffer. When ahigh voltage is applied to either

9) —Data input pins. Data on “these ~~~~~$ear in input, the outputs assume the high impedance state.

non-inverted form on the corresponding Y@@k, ‘when the

,.,3.,*\*$,1~.

outputs are enabled. OUTPUTS

~~.>$,\\

~‘,;.t\,

.*;., ‘$ Yl, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18,17,16,15,14,

.,,.,p%<,,,

CONTROLS .J.y!..

.. -e?:s:-

{J, ~j 13, 12, 11)— Device outputs. Depending upon the state of

OE1, 0E2 (PINS 1, 19) —=~.sables (active-low). the output enable pins, these outputs are either non-invetting

When alow voltage is applied@,$oth of these pins, the outputs or high-impedance outputs.

.,*w\&..l,~<.

,.,,:‘.,,1,

,y\, ~t~:

,%1~,y$~

,..t~, ‘i,-

OUTPUTY

OEI

0E2 w

—

—

MOTOROLA

4

Mc54/74HcT541A

OUTLINE DIMENSIONS

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MOTOFIOIA

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MC54/74HCT541 A

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.,,,~\(..+&J-$ ,4,>

Motorolareservesthe nt.jQt~@ke changeswithout furthernoticetoanyproducs herein. Motorola makesnowarmnty. rePre$en@tionor9u~ant* re9ardin9

T

the suitability of its@’ ,.$,R fbr any particular purpme, nor does Motorola assume any liability arising out of the appli=tion or use of any product or circuit,

andspecificallyc@X@ yandallliability,includingwithout limitation consequential orincidenti damages. “TypiMl” Pammefers=n ~d doWY in~fferent

applications. $11w~ng parameters,including “lypicals” mustbe validated for each customer application by wstomer’s technical experts. Motorola does

3

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WRP$W claims) COStS.dama9es. ~d exPenses, and rea=nable a~omey f*s afisin9 out of! ~rec~Y or indirectly. ~Y clam of personal injuw or dea~

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@MOTOROLA 3PHX32197-O PRINTED IN USA (1994) MPS/ POD LOGIC YOAAAA Mc54HcT541A/D

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