ispLSI ® 5512VA
In-System Programmable
3.3V SuperWIDE™ High Density PLD
15512va_08
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Features
•SuperWIDE HIGH-DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
—3.3V Power Supply
—User Selectable 3.3V/2.5V I/O
—24000 PLD Gates / 512 Macrocells
—Up to 288 I/O Pins
—512 Registers
—High-Speed Global Interconnect
—SuperWIDE 32 Generic Logic Block (GLB) Size for
Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
—PCB Efficient Ball Grid Array (BGA) Package Options
—Interfaces with Standard 5V TTL Devices
•HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—fmax = 110 MHz Maximum Operating Frequency
—tpd = 8.5 ns Propagation Delay
— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,
tsu3 (CLK2/3) = 3.5ns
—TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
—Electrically Erasable and Reprogrammable
— Non-Volatile
—Programmable Speed/Power Logic Path Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
•100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
•ARCHITECTURE FEATURES
—Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWIDE GLBs
—Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
—Macrocells Support Concurrent Combinatorial and
Registered Functions
—Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
—Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
—Slew and Skew Programmable I/O (SASPI/O)
Supports Programmable Bus Hold, Pull-up, Open
Drain and Slew and Skew Rate Options
—Six Global Output Enable Terms, Two Global OE
Pins and One Product Term OE per Macrocell
Functional Block Diagram
Global Routing Pool
(GRP)
Boundary
Scan
Interface
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Input Bus
Input Bus Input Bus
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Input Bus
Input Bus Input Bus
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
ispLSI 5000V Description
The ispLSI 5000V Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and five extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
in both true and complement form for every product term.
The 160 product terms are grouped in 32 sets of five and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 35 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of five product terms or less. The
Specifications ispLSI 5512VA
2
Functional Block Diagram
Figure 1. ispLSI 5512VA Functional Block Diagram (388 BGA Option)
Global Routing Pool
(GRP)
Boundary
Scan
Interface
GOE0
GOE1
GSET/GRST
1.CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Which I/O is multiplexed is
determined by the package type used – see table below.
TDI
TCK
TMS
TDO
CLK 1
CLK 0
1CLK 3
1CLK 2
VCCIO
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Input Bus
Input Bus Input Bus
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Input Bus
Input Bus Input Bus
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block Generic
Logic Block
Package Type Multiplexed Signals
388 BGA I/O 179 / CLK2 I/O 197 / CLK3 I/O 0 / TOE
272 BGA I/O 119 / CLK2 I/O 131 / CLK 3 I/O 0 / TOE
208 PQFP I/O 89 / CLK2 I/O 98 / CLK 3 I/O 0 / TOE
I/O 161
I/O 160
I/O 159
I/O 158
I/O 147
I/O 146
I/O 145
I/O 144
I/O 72
I/O 73
I/O 74
I/O 75
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 104
I/O 105
I/O 106
I/O 107
I/O 233
I/O 232
I/O 231
I/O 230
I/O 219
I/O 218
I/O 217
I/O 216
I/O 251
I/O 250
I/O 249
I/O 248
I/O 237
I/O 236
I/O 235
I/O 234
I/O 269
I/O 268
I/O 267
I/O 266
I/O 255
I/O 254
I/O 253
I/O 252
1
I/O 0 / TOE
I/O 1
I/O 2
I/O 3
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 50
I/O 51
I/O 52
I/O 53
Input Bus
Generic
Logic Block
I/O 54
I/O 55
I/O 56
I/O 57
I/O 68
I/O 69
I/O 70
I/O 71
Input Bus
Generic
Logic Block
I/O 122
I/O 123
I/O 124
I/O 125
I/O 108
I/O 109
I/O 110
I/O 111
I/O 140
I/O 141
I/O 142
I/O 143
I/O 126
I/O 127
I/O 128
I/O 129
Input Bus
Generic
Logic Block
I/O 179/CLK2
I/O 178
I/O 177
I/O 176
I/O 165
I/O 164
I/O 163
I/O 162
I/O 197/CLK3
I/O 196
I/O 195
I/O 194
I/O 183
I/O 182
I/O 181
I/O 180
I/O 215
I/O 214
I/O 213
I/O 212
I/O 201
I/O 200
I/O 199
I/O 198
Input Bus
Generic
Logic Block
I/O 287
I/O 286
I/O 285
I/O 284
I/O 273
I/O 272
I/O 271
I/O 270
Specifications ispLSI 5512VA
3
ispLSI 5000V Description (Continued)
five extra product terms are used for shared GLB con-
trols, set, reset, clock, clock enable and output enable.
The 32 registered macrocells in the GLB are driven by the
32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a pro-
grammable register/latch/toggle flip-flop and the
necessary clocks and control logic to allow combinatorial
or registered operation. The macrocells each have two
outputs, which can be fed back through the Global
Routing Pool. This dual output capability from the
macrocell allows efficient use of the hardware resources.
One output can be a registered function for example,
while the other output can be an unrelated combinatorial
function. A direct register input from the I/O pad facilitates
efficient use of this feature to construct high-speed input
registers.
Macrocell registers can be clocked from one of several
global or product term clocks available on the device. A
global and product term clock enable is also provided,
eliminating the need to gate the clock to the macrocell
registers. Reset and preset for the macrocell register is
provided from both global and product term signals. The
macrocell register can be programmed to operate as a D-
type register, a D-type latch or a T-type flip flop.
The 32 outputs from the GLB can drive both the Global
Routing Pool and the device I/O cells. The Global Routing
Pool contains one line from each macrocell output and
one line from each I/O pin.
The input buffer threshold has programmable TTL/3.3V/
2.5V compatible levels. The output driver can source
4mA and sink 8mA in 3.3V mode. The output drivers have
a separate VCCIO reference input which is independent
of the main VCC supply for the device. This feature allows
the output drivers to drive either 3.3V or 2.5V output
levels while the device logic and the output current drive
is always powered from 3.3V. The output drivers also
provide individually programmable edge rates and open
drain capability. A programmable pullup resistor is pro-
vided to tie off unused inputs and a programmable
bus-hold latch is available to hold tristate outputs in their
last valid state until the bus is driven again by some
device.
The ispLSI 5000V Family features 3.3V, non-volatile in-
system programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface. Boundary Scan test is also
supported through the same interface.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
ispLSI 5000V Family Members
The ispLSI 5000V Family ranges from 256 macrocells to
512 macrocells and operates from a 3.3V power supply.
All family members will be available with multiple pack-
age options. The ispLSI 5000V Family device matrix
showing the various bondout options is shown in the table
below.
The interconnect structure (GRP) is very similar to Lattice's
existing ispLSI 1000, 2000 and 3000 families, but with an
enhanced interconnect structure for optimal pin locking
and logic routing. This eliminates the need for registered
I/O cells or an Output Routing Pool.
Table 1. ispLSI 5000VA Family
epyTegakcaP
eciveDsBLGsllecorcaMAGBpf802PFQP802AGB272AGB883
AV6525ISLpsi 8652O/I441O/I441O/I291—
AV4835ISLpsi 21483O/I441O/I441O/I291O/I882
AV2155ISLpsi 61215— O/I441O/I291O/I882
Specifications ispLSI 5512VA
4
Figure 2. ispLSI 5512VA Block Diagram (288 I/O Version)
32
18
I/O
160
160
PT
160
32
DQ
32
18
I/O
68
DQ
160
160
68
160
PT
32
32
18
I/O
160
160
PT
160
32
DQ
32
18
I/O
68
DQ
160
160
68
160
PT
32
32
18
I/O
160
160
PT
160
32
DQ
32
18
I/O
68
DQ
160
160
68
160
PT
32
32
18
I/O
160
160
PT
160
32
DQ
32
18
I/O
68
DQ
160
160
68
160
PT
32
5512_384
18
18
18
18
18
18
18
18
32
18
I/O
160
160
PT
160
32
DQ
32
18
I/O
68
DQ
160
160
68
160
PT
32
32 32
18 18
800
18 18
32 32
18 18
32 32
18 18
32 32
18 18
32 32
18 18
5
5
PT 5
PT
5
5
5
PT 5
PT
5
5
5
PT 5
PT
5
5
5
PT 5
PT
5
5
5
PT 5
PT
5
SET/RESET
GOE1
GOE0
TOE
CLK1
CLK0
Global
Routing
Pool
(GRP)
Generic
Logic
Block
(GLB)
Buffers/Pins
CLK3
CLK2
Specifications ispLSI 5512VA
5
Figure 3. ispLSI 5000V Generic Logic Block (GLB)
GLB_5K
0126667
Macrocell 0
PT 160
PT 161
PT 162
PT 163
Macrocell 1
Macrocell 15
Macrocell 31
PT 9
PT 8
PT 7
PT 6
PT 5
PT 0
PT 1
PT 2
PT 3
PT 4
PT 79
PT 78
PT 77
PT 76
PT 75
PT 159
PT 158
PT 157
PT 156
PT 155
To I/O Pad
To GRP
PTSA bypass
PT Clock
PT Reset
PT Preset
From PTSA
PTOE
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
Global PTOE 0 ... 5
6
To I/O Pad
To GRP
PTSA bypass
PT Clock
PT Reset
PT Preset
From PTSA
PTOE
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
Global PTOE 0 ... 5
6
To I/O Pad
To GRP
PTSA bypass
PT Clock
PT Reset
PT Preset
From PTSA
PTOE
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
Global PTOE 0 ... 5
6
To I/O Pad
To GRP
PTSA bypass
PT Clock
PT Reset
PT Preset
From PTSA
PTOE
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
Global PTOE 0 ... 5
6
From Global Routing Pool
PTSA
Programmable
AND Array
Global PTOE Bus
PT 164
Specifications ispLSI 5512VA
6
Figure 4. ispLSI 5000V Macrocell
Global PTOE 2
Global PTOE 3
Global PTOE 0
Global PTOE 1
Global PTOE 4
Global PTOE 5
PTSA
DQ
RP
PTSA bypass
PT Clock
PT Reset
Clk En
R/L
PTOE
Shared PT Clock 0
Shared PT Clock 1
D/T
GOE0
GOE1
DQD
D/T
Clk En
Clk
Register/
Latch
Q
RP
SET/RESET
PT Preset Shared PT (P)reset 0
Shared PT (P)reset 1
Programmable
Speed/Power
Option
TOE
CLK0
CLK1 Clk
CLK2
CLK3
VCCIOVCCIO VCC
Slew
rate
2.5V/3.3V
Output
Open
drain
I/O Pad
To GRP
Delay
Specifications ispLSI 5512VA
7
Global Clock Distribution
The ispLSI 5000V Family has four dedicated clock input
pins: CLK0 - CLK3. CLK0 input is used as the dedicated
master clock that has the lowest internal clock skew with
no clock inversion to maintain the fastest internal clock
speed. The clock inversion is available on the remaining
CLK1 - CLK3 signals. By sharing the pins with the I/O
pins, CLK2 and CLK3 can not only be inverted but also is
available for logic implementation through GRP signal
routing. Figure 5 shows these different clock distribution
options.
Figure 5. ispLSI 5000V Global Clock Structure
CLK0
CLK1
CLK 0
CLK 1
IO/CLK 2
IO/CLK 3
CLK2
CLK3
To GRP
To GRP
SET/RESET
GSET/GRST
Specifications ispLSI 5512VA
8
Figure 6. Boundary Scan Register Circuit for I/O Pins
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
Normal
Function
OE
EXTEST
Update DR
SCANOUT
(to next cell)
Clock DR
SCANIN
(from previous
cell)
Shift DR
Normal
Function
TOE
DQ
DQ
DQ
D
1
0
1
0
1
0
QDQ
I/O Pin
Reset
BSCAN
Registers BSCAN
Latches
HIGHZ
0
PROG_MODE
EXTEST
1
0
1
SCANOUT
(to next cell)
Clock DR
SCANIN
(from previous
cell)
Shift DR
DQ
Input Pin 0
1
Specifications ispLSI 5512VA
9
Figure 8. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
TCK
TDO
Data to be
captured
Data to be
driven out
Valid Data Valid Data
Valid Data Valid Data
Data Captured
btsu
T
bth
T
btcl
T
btch
T
btcp
T
btvo
T
btco
T
btoz
T
btcpsu
T
btcph
T
btuov
T
btuco
T
btuoz
T
SYMBOL PARAMETER MIN MAX UNITS
tbtcp TCK [BSCAN test] clock pulse width 125 – ns
tbtch TCK [BSCAN test] pulse width high 62.5 – ns
tbtcl TCK [BSCAN test] pulse width low 62.5 – ns
tbtsu TCK [BSCAN test] setup time 25 – ns
tbth TCK [BSCAN test] hold time 25 – ns
trf TCK [BSCAN test] rise and fall time 50 – mV/ns
tbtco TAP controller falling edge of clock to valid output –25ns
tbtoz TAP controller falling edge of clock to data output disable –25ns
tbtvo TAP controller falling edge of clock to data output enable –25ns
tbtcpsu BSCAN test Capture register setup time 25 – ns
tbtcph BSCAN test Capture register hold time 25 – ns
tbtuco BSCAN test Update reg, falling edge of clock to valid output –50ns
tbtuoz BSCAN test Update reg, falling edge of clock to output disable –50ns
tbtuov BSCAN test Update reg, falling edge of clock to output enable –50ns
Specifications ispLSI 5512VA
10
Absolute Maximum Ratings 1, 2
Supply Voltage Vcc .................................. -0.5 to +5.4V
Input Voltage Applied............................... -0.5 to +5.6V
Tri-Stated Output Voltage Applied........... -0.5 to +5.6V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Condition
SYMBOL
Table 2 - 0005/5000
VCC
VCCIO
PARAMETER
Supply Voltage
I/O Reference Voltage
Commercial T
A
= 0°C to +70°CMIN. MAX. UNITS
3.00
2.3
3.60
3.60
V
Industrial T
A
= -40°C to +85°C3.00 3.60 V
V
Capacitance (TA=25°C,f=1.0 MHz)
SYMBOL
Table 2 - 0006/5384
C
PARAMETER
Clock Capacitance 10
UNITSTYPICAL TEST CONDITIONS
2pf V = 3.3V, V = 2.0V
CC CK
C
I/O Capacitance 10
1pf V = 3.3V, V = 2.0V
CC I/O
C
Global Input Capacitance 10
3pf V = 3.3V, V = 2.0V
CC G
Erase Reprogram Specification
Table 2-0008/3320
PARAMETER MINIMUM MAXIMUM UNITS
ispLSI Erase/Reprogram Cycles 10000 – Cycles
Specifications ispLSI 5512VA
11
Switching Test Conditions
Input Pulse Levels
Table 2 - 0003/5384
Input Rise and Fall Time
Input Timing Reference Levels
Ouput Timing Reference Levels
Output Load
GND to V
CCIOmin
≤ 1.5ns 10% to 90%
1.5V
1.5V
See figure
3-state levels are measured 0.5V from steady-state
active level.
Output Load Conditions (See Figure 8)
TEST CONDITION R1
3.3V 2.5V
R2 CL
A35pF
D35pF
B35pF
35pF
Active High
Slow Slew
Active Low
C5pF
5pF
511Ω
∞
∞
511Ω
511Ω
∞
475Ω
∞
475Ω
∞
∞
475Ω
R1 R2
316Ω
∞
∞
316Ω
316Ω
∞
348Ω
∞
348Ω
∞
∞
348Ω
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2 - 0004A/5384
DC Electrical Characteristics for 3.3V Range1
Over Recommended Operating Conditions
Figure 9. Test Load
V
CCIO
R1
R2CL
*
Device
Output Test
Point
*
CL includes Test Fixture and Probe Capacitance.
0213D
VOL
SYMBOL
1. I/O voltage configuration must be set to VCC.
Table 2-0007/5512VA
VOH
VIH
VIL
PARAMETER
Output Low Voltage
Output High Voltage
Input High Voltage
Input Low Voltage
I
OL
= 8 mA
I
OH
= -4 mA
V
OH
≤ V
OUT
or V
OUT
≤ V
OL (max)
V
OH
≤ V
OUT
or V
OUT
≤ V
OL (max)
CONDITION MIN. TYP. MAX. UNITS
–
2.4
2.0
-0.3
–
–
–
–
0.4
–
5.25
0.8
V
V
VCCIO I/O Reference Voltage 3.0 – 3.6 V
V
V
Specifications ispLSI 5512VA
12
DC Electrical Characteristics
Over Recommended Operating Conditions
DC Electrical Characteristics for 2.5V Range1
Over Recommended Operating Conditions
VIH
SYMBOL
2.5V/5512VA
VOH
PARAMETER
Input High Voltage
Output High Voltage
V
OH(min)
≤ V
OUT
or V
OUT
≤ V
OL(max)
V
OH(min)
≤ V
OUT
or V
OUT
≤ V
OL(max)
V
CCIO=min
, V
IN
=V
IH
or V
IL
, I
OH
= -2mA
V
CCIO=min
, V
IN
=V
IH
or V
IL
, I
OL
= 2mA
CONDITION MIN. TYP. MAX. UNITS
1.7
1.7
–
–
5.25
–
V
VCCIO
VIL
I/O Reference Voltage
Input Low Voltage 2.3
-0.3 –
–2.7
0.7 V
V
V
V
CCIO=min
, V
IN
=V
IH
or V
IL
, I
OH
= -100µA2.1 – – V
––0.7V
V
CCIO=min
, V
IN
=V
IH
or V
IL
, I
OL
= 100µA––0.2V
VOL Output Low Voltage
1. I/O voltage configuration must be set to VCCIO.
SYMBOL
1. Pullup is capable of pulling to a minimum voltage of V
OH
under no-load conditions. DC Char_5512VA
IPU
IBHL
PARAMETER
IBHH
IBHLO
1I/O Active Pullup Current
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus Hold Low Overdrive Current
IIH
IIL Input or I/O High Leakage Current
Input or I/O Low Leakage Current 0V ≤ V ≤ V (Max.)
IN IL
CONDITION MIN. TYP. MAX. UNITS
–
–
–
–
40
-40
–
–
–
–
–
–
–
–
-10
10
-150
50
–
–
550
µA
µA
µA
µA
µA
µA
IBHLH
IBHT
Bus Hold High Overdrive Current
Bus Hold Trip Points –
VIL
–
–-550
VIH
µA
V
IVCCIO Current Needed for VCCIO Pin All I/Os Pulled-up, (Total I/Os * IPUmax)– – 45 mA
µA
(VCCIO-0.2)V ≤ VIN ≤ VCCIO
VCCIO ≤ VIN ≤ 5.25V
0V ≤ VIN ≤ VIL
0V ≤ VIN ≤ VCCIO
0V ≤ VIN ≤ VCCIO
VIN = VIL(max)
VIN = VIH(min)
Specifications ispLSI 5512VA
13
External Switching Characteristics
Over Recommended Operating Conditions
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1us —6 ssapybTP5,klCerofebemiTputeS.geRBLG6—8—21— sn
t
1oc
6
A7 yaleDtuptuOotkcolC.geRBLG—4—5.5—8 sn
t
1h —8 ssapybTP5,kcolCretfaemiTdloH.geRBLG0—0—0— sn
t
2us —9 kcolCerofebemiTputeS.geRBLG7—9—41— sn
t
2h —01kcolCretfaemiTdloH.geRBLG0—0—0— sn
t
)1/0KLC(3us —11.geRtupnI,kcolCerofebemiTputeS.geRBLG )1/0KLC(htaP 5.4—6—9— sn
t
)3/2KLC(3us —21.geRtupnI,kcolCerofebemiTputeS.geRBLG )3/2KLC(htaP 5.3—5—7— sn
t
)1/0KLC(3h —31htaP.geRtupnI,kcolCretfaemiTdloH.geRBLG )1/0KLC( 0—0—0— sn
t
)3/2KLC(3h —41htaP.geRtupnI,kcolCretfaemiTdloH.geRBLG )3/2KLC( 0—0—0— sn
t
1r A51yaleDtuptuOotniPteseR.txE—71—02—03sn
t
1wr —61noitaruDesluPteseR.txE5.7—9—41— sn
t
sid/eotp C/B71elbasiD/elbanEtuptuOmreTtcudorPlacoL—01—21—81sn
t
sid/eotpg C/B81elbasiD/elbanEtuptuOmreTtcudorPlabolG—02—42—03sn
t
sid/eog C/B91elbasiD/elbanEtuptuOottupnIEOlabolG—5.6—8—21sn
t
hw —02hgiH,noitaruDesluPkcolC.cnyS.txE5.3—4—6— sn
t
lw —12woL,noitaruDesluPkcolC.cnyS.txE5.3—4—6— sn
.kcabdeefPRGgnisuretnuoctib-23dradnatS.1 .%05nahtrehtofoelcycytudkcolcarofwollaotsisihT.)lwt+hwt(/1nahtsselebyam)elggoT(xamf.2 .noitcessnoitidnoCtseTgnihctiwSecnerefeR.3 .0KLCdna,BLG1fodaolPRGa,tuonafASTPesactsrowhtiwnekaterasrebmungnimitlla,esiwrehtodetonsselnU.4 .revirdtuptuoevitcalamrongnisuderusaemsretemarapgnimiT.5 sioiccVnehwderrucnisiyaledsn5.0lanoitiddanA.ecnereferegatlovO/IsaccVhtiwderusaemerasretemarapyaledehT.6 .ecnereferegatlovO/Isadesu
spe.0.4/AV2155.txEgnimiT
Specifications ispLSI 5512VA
14
Internal Timing Parameters1
Over Recommended Operating Conditions
I/O Buffer
tidcom 22 Input Pad and Buffer, Combinatorial Input – 0.7 – 0.9 – 1.4 ns
tidreg 23 Input Pad and Buffer, Registered Input – 4.7 – 6.6 – 9.7 ns
todcom 24 Output Pad and Buffer, Combinatorial Output – 2.4 – 1.7 – 2.6 ns
todreg 25 Output Pad and Buffer, Registered Output – 1.0 – 2.8 – 4.6 ns
todz 26 Output Buffer Enable/Disable – 1.7 – 1.7 – 2.6 ns
tslf 27 Slew Rate Adder, Fast Slew –0–0–0 ns
tsls 28 Slew Rate Adder, Slow Slew – 8.5 – 10 – 15 ns
tslfd 29 Programmable Delay Adder, Fast Slew – 0.5 – 0.7 – 1 ns
tslsd 30 Programmable Delay Adder, Slow Slew – 9.5 – 10.7 – 16 ns
GLB/Macrocell Delay Register
tmbp 31 Macrocell Register/Latch Bypass –0–0–0 ns
tmlat 32 Macrocell Latch Delay – 1 – 1.4 – 2 ns
tmco 33 Macrocell Register/Latch Clock to Output – 1.8 –1–1 ns
tmsu 34 Macrocell Register/Latch Setup Time 1 – 1.1 – 1.7 – ns
tmh 35 Macrocell Register/Latch Hold Time 2.5 – 3.9 – 5.3 – ns
tmsuce 36 Macrocell Register/Latch CLKEN Setup Time 1 – 1.4 – 2 – ns
tmhce 37 Macrocell Register/Latch CLKEN Hold Time 1 – 1.4 – 2 – ns
tmrst 38 Macrocell Register/Latch Set/Reset Time – 1.8 – 1.4 – 2 ns
tftog 39 Toggle Flip-Flop Feedback – 1 – 1.3 – 2 ns
AND Array
tandhs 40 AND Array, High Speed Mode –3–4–6 ns
tandlp 41 AND Array, Low Power Mode – 5 – 6.6 – 10 ns
PTSA
t5ptcom 42 5 Product Term Bypass, Combinatorial – 0.7 – 1.4 – 2 ns
t5ptreg 43 5 Product Term Bypass, Registered – 1 – 1.7 – 2.3 ns
t5ptxcom 44 5 Product Term XOR, Combinatorial – 2.5 – 3.6 – 5 ns
t5ptxreg 45 5 Product Term XOR, Registered – 2.3 – 2.2 – 3.3 ns
tptsacom 46 Product Term Sharing Array, Combinatorial – 3 – 4.1 – 6 ns
tptsareg 47 Product Term Sharing Array, Registered – 2 – 2.7 – 4.3 ns
PTSA Controls
tpck 48 Product Term Clock Delay – 0.5 – 0.7 – 1 ns
tpcken 49 Product Term CLKEN Delay – 1 – 1.4 – 2 ns
tscken 50 Shared Product Term CLKEN Delay – 1 – 1.4 – 2 ns
tsck 51 Shared Product Term Clock Delay – 0.5 – 0.7 – 1 ns
tptsacken 52 Product Term Sharing Array CLKEN Delay – 2.0 – 2.4 – 4 ns
tsrst 53 Shared Product Term Set/Reset Delay – 2.5 – 3.4 – 5 ns
tprst 54 Product Term Set/Reset Delay – 1.5 –2–3 ns
tpoe 55 Product Term Output Enable/Disable – 2.9 – 3.4 – 5 ns
tgpoe 56 Global PT Output Enable/Disable – 13.1 – 15.4 – 17 ns
-110 -100 -70
MIN MAX MIN MAX MIN MAX UNIT
PARAM #2 DESCRIPTION
1. Internal Timing Parameters are not tested and are for reference only. Timing Rev 4.0
Refer to Timing Model in this data sheet for further details.
Specifications ispLSI 5512VA
15
ispLSI 5512VA Timing Model
PT Controls
Register
Dedicated
Input Buffers
Output
Buffer
I/O
Pad
I/O
Pad
INPUT
OUTPUT
PTSA
GRP
t
grpi
GLB/Macrocell
t
andhs
t
goe
t
gclk01
t
grst
t
toe
t
andlp
t
5ptcom
t
5ptreg
t
5ptxreg
t
5ptxcom
t
ptsacom
t
ptsareg
t
sck
t
pck
t
ptsacken
t
srst
t
poe
t
gpoe
t
idcom
t
grpm
t
t
Slew
Input
Pad
t
prst
t
idreg
Buffer Delays
AND Array
t
gclken1
t
gclken0
Input
Buffer
#22
#23
#58
#40
#41
#42
#46
#44
#45
#47
#43
#51
#48
#31 t
mbp
#39 t
ftog
t
odcom
#24
t
slf
t
sls
#27
#28
t
slsd
t
slfd
#30
#29
t
odreg
#25 t
odz
#26
#32 t
mlat
#34 t
msu
#35 t
mh
#33 t
mco
#37 t
mhce
#36 t
msuce
#38 t
mrst
#52
#49
#50
#53
#54
#55
#56
#59 t
gclk23
#60
#61
#62
#63
#64
#65
#57
pcken
scken
Internal Timing Parameters1
Over Recommended Operating Conditions
-110 -100 -70
MIN MAX MIN MAX MIN MAX UNIT
PARAM #2 DESCRIPTION
GRP
tgrpi 57 GRP Delay from I/O Pad – 1.5 –2–3 ns
tgrpm 58 GRP Delay from Macrocell – 1.2 – 1.2 – 1.2 ns
Global Control Delays
tgclk01 59 Global Clock 0 or 1 Delay – 1.2 – 1.7 – 2.4 ns
tgclk23 60 Global Clock 2 or 3 Delay – 2.2 – 2.7 – 4.4 ns
tgclken0 61 Global CLKEN 0 Delay – 1.7 – 2.4 – 3.4 ns
tgclken1 62 Global CLKEN 1 Delay – 2.7 – 3.4 – 5.4 ns
tgrst 63 Global Set/Reset Delay – 14.2 – 15.8 – 23.4 ns
tgoe 64 Global OE Delay – 4.8 – 6.3 – 9.4 ns
ttoe 65 Test OE Delay – 4.7 – 6.2 – 9.4 ns
1. Internal Timing Parameters are not tested and are for reference only. Timing Rev 4.0
Refer to Timing Model in this data sheet for further details.
Specifications ispLSI 5512VA
16
Power Consumption
setting operates product terms at their normal full power
consumption. For portions of the logic that can tolerate
longer propagation delays, selecting the slower “low-
power” setting will significantly reduce the power
dissipation for these product terms. Figure 10 shows the
relationship between power and operating speed.
Power consumption in the ispLSI 5512VA device de-
pends on two primary factors: the speed at which the
device is operating and the number of product terms
used. The product terms have a fuse-selectable speed/
power tradeoff setting. Each group of four product terms
has a single speed/power tradeoff control fuse that acts
on the complete group of four. The fast “high-speed”
200020 40 60 80 100 120
fmax (MHz)
ICC (mA)
Notes: Configuration of 32 16-bit Counters
Typical Current at 3.3V, 25° C
ispLSI 5512VA
High Speed Mode
ispLSI 5512VA
Low Power Mode
0127/5512va
ICC can be estimated for the ispLSI 5512VA using the following equation:
High Speed Mode: ICC = 70 + (# of PTs * 0.4592) + (# of nets * Max. freq * 0.00391)
Low Power Mode: ICC = 70 + (# of PTs * 0.160) + (# of nets * Max. freq * 0.00391)
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of 2 GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
300
400
500
550
450
350
250
600
700
750
650
800
Figure 10. Typical Device Power Consumption vs fmax
Specifications ispLSI 5512VA
17
TMS Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine.
TCK Input - This pin is the Test Clock input pin used to clock through the JTAG state machine.
TDI Input - This pin is the JTAG Test Data In pin used to load data.
TDO Output - This pin is the JTAG Test Data Out pin used to shift data out.
TOE / I/O0 Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon customer's
design. TOE tristates all I/O pins when a logic low is driven.
GOE0, GOE1 Input - These two pins are the Global Output Enable input pins.
GSET/GRST Dedicated Set/Reset Input - This pin is available to all registers in the device and can independently be
configured as preset, reset or no effect on each register. The global polarity (active high or low input)
for this pin is also selectable.
I/O Input/Output – These are the general purpose I/O used by the logic array.
GND Ground
NC1No connect.
VCC Vcc
CLK0, CLK1 Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock
input to all registers in the device.
CLK2 / I/O, Input/Output - These pins function as either dedicated clock inputs for all registers or an I/O
CLK3 / I/O pin based upon customer's design. Both clocks are muxed before being used as the clock input
to all registers in the device.
VCCIO Input - This pin is used if an optional 2.5V output is to be used. Every I/O can independently select either
3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must
be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches only draw current
from this supply.
Signal Descriptions
Signal Name Description
1. NC pins are not to be connected to any active signals, VCC or GND.
Specifications ispLSI 5512VA
18
GOE0, GOE1 78, 79
TOE / I/O0 32
GSET/GRST 138
TCK 29
TDI 30
TDO 136
TMS 28
CLK0, CLK1 184,185
CLK2 / I/O89 162
CLK3 / I/O98 173
VCCIO 137
GND 3, 12, 19, 27, 39, 48, 58, 69, 77, 88, 99, 113, 121, 128, 135, 150, 164, 170, 179, 191, 199
VCC 7, 14, 22, 31, 41, 61, 80, 90, 110, 123, 139, 152, 156, 177, 186, 201
NC 49, 50, 51, 52, 101, 102, 103, 104, 105, 106, 107, 108, 109, 157, 158, 207, 208
208-Pin PQFP Signal Locations
Signal Pin
1. NCs are not to be connected to any active signals, VCC or GND.
208-Pin PQFP I/O Locations
I/O # Pin I/O # Pin I/O # Pin I/O # Pin I/O # Pin I/O # Pin
* I/O 89 is multiplexed with CLK2, I/O 98 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE.
0* 32
133
234
335
436
537
638
740
842
943
10 44
11 45
12 46
13 47
14 53
15 54
16 55
17 56
18 57
19 59
20 60
21 62
22 63
23 64
24 65
25 66
26 67
27 68
28 70
29 71
30 72
31 73
32 74
33 75
34 76
35 81
36 82
37 83
38 84
39 85
40 86
41 87
42 89
43 91
44 92
45 93
46 94
47 95
48 96
49 97
50 98
51 100
52 111
53 112
54 114
55 115
56 116
57 117
58 118
59 119
60 120
61 122
62 124
63 125
64 126
65 127
66 129
67 130
68 131
69 132
70 133
71 134
72 140
73 141
74 142
75 143
76 144
77 145
78 146
79 147
80 148
81 149
82 151
83 153
84 154
85 155
86 159
87 160
88 161
89* 162
90 163
91 165
92 166
93 167
94 168
95 169
96 171
97 172
98* 173
99 174
100 175
101 176
102 178
103 180
104 181
105 182
106 183
107 187
108 188
109 189
110 190
111 192
112 193
113 194
114 195
115 196
116 197
117 198
118 200
119 202
120 203
121 204
122 205
123 206
124 1
125 2
126 4
127 5
128 6
129 8
130 9
131 10
132 11
133 13
134 15
135 16
136 17
137 18
138 20
139 21
140 23
141 24
142 25
143 26
Specifications ispLSI 5512VA
19
GOE0, GOE1 AF14, AD13
TOE / I/O0 T1
GSET/GRST L25
TCK T2
TDI R3
TDO N24
TMS R1
CLK0, CLK1 A13, C14
CLK2 / I/O179 A23
CLK3 / I/O197 B17
VCCIO M26
GND A1, A2, A26, B2, B25, B26, C3, C24, D4, D9, D14, D19, D23, H4, J23, L11, L12, L13, L14, L15, L16,
M11, M12, M13, M14, M15, M16, N4, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16,
P23, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16, V4, W23, AC4, AC8, AC13, AC18,
AC23, AD3, AD24, AE1, AE2, AE25, AF1, AF25, AF26
VCC D6, D11, D16, D21, F4, F23, L4, L23, T4, T23, AA4, AA23, AC6, AC11, AC16, AC21
NC1C9, D2, E24, L1, AC25, AF19
388-Ball BGA Signal Locations
Signal Ball
1. NCs are not to be connected to any active signals, VCC or GND.
Specifications ispLSI 5512VA
20
388-Ball BGA I/O Locations (Sorted by I/O)
0* T1
1R4
2U2
3T3
4U1
5U4
6V2
7U3
8V1
9W2
10 W1
11 V3
12 Y2
13 W4
14 Y1
15 W3
16 AA2
17 Y4
18 AA1
19 Y3
20 AB2
21 AB1
22 AA3
23 AC2
24 AB4
25 AC1
26 AB3
27 AD2
28 AC3
29 AD1
30 AF2
31 AE3
32 AF3
33 AE4
34 AD4
35 AF4
36 AE5
37 AC5
38 AD5
39 AF5
40 AE6
41 AC7
42 AD6
43 AF6
44 AE7
45 AF7
46 AD7
47 AE8
48 AC9
49 AF8
50 AD8
51 AE9
52 AF9
53 AE10
54 AD9
55 AF10
56 AC10
57 AE11
58 AD10
59 AF11
60 AE12
61 AF12
62 AD11
63 AE13
64 AC12
65 AF13
66 AD12
67 AE14
68 AC14
69 AE15
70 AD14
71 AF15
72 AE16
73 AD15
74 AF16
75 AC15
76 AE17
77 AD16
78 AF17
79 AC17
80 AE18
81 AD17
82 AF18
83 AE19
84 AD18
85 AE20
86 AC19
87 AF20
88 AD19
89 AE21
90 AC20
91 AF21
92 AD20
93 AE22
94 AF22
95 AD21
96 AE23
97 AC22
98 AF23
99 AD22
100 AE24
101 AD23
102 AF24
103 AE26
104 AD25
105 AD26
106 AC24
107 AC26
108 AB25
109 AB23
110 AB24
111 AB26
112 AA25
113 Y23
114 AA24
115 AA26
116 Y25
117 Y26
118 Y24
119 W25
120 V23
121 W26
122 W24
123 V25
124 V26
125 U25
126 V24
127 U26
128 U23
129 T25
130 U24
131 T26
132 R25
133 R26
134 T24
135 P25
136 R23
137 P26
138 R24
139 N25
140 N23
141 N26
142 P24
143 M25
144 M24
145 L26
146 M23
147 K25
148 L24
149 K26
150 K23
151 J25
152 K24
153 J26
154 H25
155 H26
156 J24
157 G25
158 H23
159 G26
160 H24
161 F25
162 G23
163 F26
164 G24
165 E25
166 E26
167 F24
168 D25
169 E23
170 D26
171 C25
172 D24
173 C26
174 A25
175 B24
176 A24
177 B23
178 C23
179* A23
180 B22
181 D22
182 C22
183 A22
184 B21
185 D20
186 C21
187 A21
188 B20
189 A20
190 C20
191 B19
192 D18
193 A19
194 C19
195 B18
196 A18
197* B17
198 C18
199 A17
200 D17
201 B16
202 C17
203 A16
204 B15
205 A15
206 C16
207 B14
208 D15
209 A14
210 C15
211 B13
212 D13
213 B12
214 C13
215 A12
216 B11
217 C12
218 A11
219 D12
220 B10
221 C11
222 A10
223 D10
224 B9
225 C10
226 A9
227 B8
228 A8
229 B7
230 D8
231 A7
232 C8
233 B6
234 D7
235 A6
236 C7
237 B5
238 A5
239 C6
240 B4
241 D5
242 A4
243 C5
244 B3
245 C4
246 A3
247 B1
248 C2
249 C1
250 D3
251 D1
252 E2
253 E4
254 E3
255 E1
256 F2
257 G4
258 F3
259 F1
260 G2
261 G1
262 G3
263 H2
264 J4
265 H1
266 H3
267 J2
268 J1
269 K2
270 J3
271 K1
272 K4
273 L2
274 K3
275 M2
276 M1
277 L3
278 N2
279 M4
280 N1
281 M3
282 P2
283 P4
284 P1
285 N3
286 R2
287 P3
I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball
* I/O 179 is multiplexed with CLK2, I/O 197 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE.
Specifications ispLSI 5512VA
21
388-Ball BGA I/O Locations (Sorted by Ball)
246 A03
242 A04
238 A05
235 A06
231 A07
228 A08
226 A09
222 A10
218 A11
215 A12
209 A14
205 A15
203 A16
199 A17
196 A18
193 A19
189 A20
187 A21
183 A22
179* A23
176 A24
174 A25
247 B01
244 B03
240 B04
237 B05
233 B06
229 B07
227 B08
224 B09
220 B10
216 B11
213 B12
211 B13
207 B14
204 B15
201 B16
197* B17
195 B18
191 B19
188 B20
184 B21
180 B22
177 B23
175 B24
249 C01
248 C02
245 C04
243 C05
239 C06
236 C07
232 C08
225 C10
221 C11
217 C12
214 C13
210 C15
206 C16
202 C17
198 C18
194 C19
190 C20
186 C21
182 C22
178 C23
171 C25
173 C26
251 D01
250 D03
241 D05
234 D07
230 D08
223 D10
219 D12
212 D13
208 D15
200 D17
192 D18
185 D20
181 D22
172 D24
168 D25
170 D26
255 E01
252 E02
254 E03
253 E04
169 E23
165 E25
166 E26
259 F01
256 F02
258 F03
167 F24
161 F25
163 F26
261 G01
260 G02
262 G03
257 G04
162 G23
164 G24
157 G25
159 G26
265 H01
263 H02
266 H03
158 H23
160 H24
154 H25
155 H26
268 J01
267 J02
270 J03
264 J04
156 J24
151 J25
153 J26
271 K01
269 K02
274 K03
272 K04
150 K23
152 K24
147 K25
149 K26
273 L02
277 L03
148 L24
145 L26
276 M01
275 M02
281 M03
279 M04
146 M23
144 M24
143 M25
280 N01
278 N02
285 N03
140 N23
139 N25
141 N26
284 P01
282 P02
287 P03
283 P04
142 P24
135 P25
137 P26
286 R02
1R04
136 R23
138 R24
132 R25
133 R26
0* T01
3T03
134 T24
129 T25
131 T26
4U01
2U02
7U03
5U04
128 U23
130 U24
125 U25
127 U26
8V01
6V02
11 V03
120 V23
126 V24
123 V25
124 V26
10 W01
9W02
15 W03
13 W04
122 W24
119 W25
121 W26
14 Y01
12 Y02
19 Y03
17 Y04
113 Y23
118 Y24
116 Y25
117 Y26
18 AA01
I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball
* I/O 179 is multiplexed with CLK2, I/O 197 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE.
16 AA02
22 AA03
114 AA24
112 AA25
115 AA26
21 AB01
20 AB02
26 AB03
24 AB04
109 AB23
110 AB24
108 AB25
111 AB26
25 AC01
23 AC02
28 AC03
37 AC05
41 AC07
48 AC09
56 AC10
64 AC12
68 AC14
75 AC15
79 AC17
86 AC19
90 AC20
97 AC22
106 AC24
107 AC26
29 AD01
27 AD02
34 AD04
38 AD05
42 AD06
46 AD07
50 AD08
54 AD09
58 AD10
62 AD11
66 AD12
70 AD14
73 AD15
77 AD16
81 AD17
84 AD18
88 AD19
92 AD20
95 AD21
99 AD22
101 AD23
104 AD25
105 AD26
31 AE03
33 AE04
36 AE05
40 AE06
44 AE07
47 AE08
51 AE09
53 AE10
57 AE11
60 AE12
63 AE13
67 AE14
69 AE15
72 AE16
76 AE17
80 AE18
83 AE19
85 AE20
89 AE21
93 AE22
96 AE23
100 AE24
103 AE26
30 AF02
32 AF03
35 AF04
39 AF05
43 AF06
45 AF07
49 AF08
52 AF09
55 AF10
59 AF11
61 AF12
65 AF13
71 AF15
74 AF16
78 AF17
82 AF18
87 AF20
91 AF21
94 AF22
98 AF23
102 AF24
Specifications ispLSI 5512VA
22
GOE0, GOE1 V11, U11
TOE / I/O 0 M2
GSET/GRST J18
TCK L4
TDI M1
TDO J20
TMS L3
CLK0, CLK1 C10, D10
CLK2 / I/O 119 A18
CLK3 / I/O 131 B13
VCCIO J19
GND A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10,
M11, M12, N4, N17, U4, U8, U13, U17
VCC D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15
NC1A17, B3, B18, B19, B20, C3, C5, C18, C19, D3, D19, E2, P19, R3, T4, T17, T20, U1, U2, U3, W1, W2,
W4, W17, W19, W20, Y2, Y12, Y20
Signal Locations (272-Ball BGA)
Signal Ball
1. NCs are not to be connected to any active signals, VCC or GND.
Specifications ispLSI 5512VA
23
272-Ball BGA I/O Locations (Sorted by I/O)
* I/O 119 is multiplexed with CLK2, I/O 131 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE.
0* M2
1M3
2M4
3N1
4N2
5N3
6P1
7P2
8R1
9P3
10 R2
11 T1
12 P4
13 T2
14 T3
15 V1
16 V2
17 V3
18 Y1
19 W3
20 V4
21 U5
22 Y3
23 Y4
24 V5
25 W5
26 Y5
27 V6
28 U7
29 W6
30 Y6
31 V7
32 W7
33 Y7
34 V8
35 W8
36 Y8
37 U9
38 V9
39 W9
40 Y9
41 W10
42 V10
43 Y10
44 Y11
45 W11
46 W12
47 V12
48 U12
49 Y13
50 W13
51 V13
52 Y14
53 W14
54 Y15
55 V14
56 W15
57 Y16
58 U14
59 V15
60 W16
61 Y17
62 V16
63 Y18
64 U16
65 V17
66 W18
67 Y19
68 V18
69 V19
70 U19
71 U18
72 V20
73 U20
74 T18
75 T19
76 R18
77 P17
78 R19
79 R20
80 P18
81 P20
82 N18
83 N19
84 N20
85 M17
86 M18
87 M19
88 M20
89 L19
90 L18
91 L20
92 K20
93 K19
94 K18
95 K17
96 J17
97 H20
98 H19
99 H18
100 G20
101 G19
102 F20
103 G18
104 F19
105 E20
106 G17
107 F18
108 E19
109 D20
110 E18
111 C20
112 E17
113 D18
114 A20
115 A19
116 B17
117 C17
118 D16
119* A18
120 C16
121 B16
122 A16
123 C15
124 D14
125 B15
126 A15
127 C14
I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball
128 B14
129 A14
130 C13
131* B13
132 A13
133 D12
134 C12
135 B12
136 A12
137 B11
138 C11
139 A11
140 A10
141 B10
142 A9
143 B9
144 C9
145 D9
146 A8
147 B8
148 C8
149 A7
150 B7
151 A6
152 C7
153 B6
154 A5
155 D7
156 C6
157 B5
158 A4
159 B4
160 A3
161 D5
162 C4
163 B2
164 A2
165 B1
166 C2
167 D2
168 E4
169 C1
170 D1
171 E3
172 E1
173 F3
174 G4
175 F2
176 F1
177 G3
178 G2
179 G1
180 H3
181 H2
182 H1
183 J4
184 J3
185 J2
186 J1
187 K2
188 K3
189 K1
190 L1
191 L2
Specifications ispLSI 5512VA
24
272-Ball BGA I/O Locations (Sorted by Ball)
* I/O 119 is multiplexed with CLK2, I/O 131 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE.
I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball
164 A2
160 A3
158 A4
154 A5
151 A6
149 A7
146 A8
142 A9
140 A10
139 A11
136 A12
132 A13
129 A14
126 A15
122 A16
119* A18
115 A19
114 A20
165 B1
163 B2
159 B4
157 B5
153 B6
150 B7
147 B8
143 B9
141 B10
137 B11
135 B12
131* B13
128 B14
125 B15
121 B16
116 B17
169 C1
166 C2
162 C4
156 C6
152 C7
148 C8
144 C9
138 C11
134 C12
130 C13
127 C14
123 C15
120 C16
117 C17
111 C20
170 D1
167 D2
161 D5
155 D7
145 D9
133 D12
124 D14
118 D16
113 D18
109 D20
172 E1
171 E3
168 E4
112 E17
110 E18
108 E19
105 E20
176 F1
175 F2
173 F3
107 F18
104 F19
102 F20
179 G1
178 G2
177 G3
174 G4
106 G17
103 G18
101 G19
100 G20
182 H1
181 H2
180 H3
99 H18
98 H19
97 H20
186 J1
185 J2
184 J3
183 J4
96 J17
189 K1
187 K2
188 K3
95 K17
94 K18
93 K19
92 K20
190 L1
191 L2
90 L18
89 L19
91 L20
0* M2
1M3
2M4
85 M17
86 M18
87 M19
88 M20
3N1
4N2
5N3
82 N18
83 N19
84 N20
6P1
7P2
9P3
12 P4
77 P17
80 P18
81 P20
8R1
10 R2
76 R18
78 R19
79 R20
11 T1
13 T2
14 T3
74 T18
75 T19
21 U5
28 U7
37 U9
48 U12
58 U14
64 U16
71 U18
70 U19
73 U20
15 V1
16 V2
17 V3
20 V4
24 V5
27 V6
31 V7
34 V8
38 V9
42 V10
47 V12
51 V13
55 V14
59 V15
62 V16
65 V17
68 V18
69 V19
72 V20
19 W3
25 W5
29 W6
32 W7
35 W8
39 W9
41 W10
45 W11
46 W12
50 W13
53 W14
56 W15
60 W16
66 W18
18 Y1
22 Y3
23 Y4
26 Y5
30 Y6
33 Y7
36 Y8
40 Y9
43 Y10
44 Y11
49 Y13
52 Y14
54 Y15
57 Y16
61 Y17
63 Y18
67 Y19
Specifications ispLSI 5512VA
25
Signal Configuration
ispLSI 5512VA 272-ball BGA
20 19 18 17 16 15 14 13 12 11 10 987654321
AA
B B
C C
D
GNDNC1
NC1
NC1
NC1
NC1
NC1
NC1
NC1
NC1
NC1
NC1
NC1
NC1
NC1
NC1
GNDGNDGNDGND VCCVCCVCC GOE1
GOE0
NC1
NC1
NC1
NC1
NC1
VCCVCC
NC1
NC1
NC1
GND
GND
GNDGND
GND
GNDGNDGND CLK1 VCC
VCC
VCC
TMSTCK
TDI
VCC
VCCVCC
CLK0 NC1
NC1
NC1
NC1
NC1
NC1
GNDTDO
VCCIO
GND GND GND
GND GND GND GND
GNDVCC GND GND GND
GND GND GND GND
D
EE
F
ispLSI 5512VA
F
GBottom View G
H H
J J
KK
LL
M M
NN
P P
RR
TT
UU
VV
WW
YY
20 19 18 17 16 15 14 13 12 11 10 987654321
1. NCs are not to be connected to any active signals, Vcc or GND.
Note: Ball A1 indicator dot on top side of package.
I/O
164 I/O
165
I/O
169
I/O
170
I/O
166
I/O
162
I/O
172
I/O
176
I/O
179
I/O
178
I/O
190
I/O
191
I/O
90
I/O
89
I/O
91
I/O
187
I/O
188
I/O
94 I/O
95
I/O
93
I/O
92
I/O
185 I/O
186
I/O
189
I/O
184
I/O
183
I/O
96
SET/
RST
I/O
181 I/O
182
I/O
180
I/O
98 I/O
99
I/O
97
I/O
177
I/O
174
I/O
106
I/O
103
I/O
101
I/O
100
I/O
175
I/O
173
I/O
171
I/O
168
I/O
104 I/O
107
I/O
102
I/O
108 I/O
110 I/O
112
I/O
105
I/O
167
I/O
155
I/O
145
I/O
133
I/O
124
I/O
118
I/O
113
I/O
109 I/O
161
I/O
156
I/O
152
I/O
148
I/O
144
I/O
138
I/O
134
I/O
130
I/O
127
I/O
123
I/O
120
I/O
117
I/O
111
I/O
163
I/O
159
I/O
157
I/O
153
I/O
150
I/O
147
I/O
143
I/O
141
I/O
137
I/O
135
I/O
128
I/O
125
I/O
121
I/O
116
I/O
160
I/O
158
I/O
154
I/O
151
I/O
149
I/O
146
I/O
142
I/O
140
I/O
139
I/O
136
I/O
132
I/O
129
I/O
126
I/O
122
I/O
115
I/O
114
CLK2/
I/O 119
CLK3/
I/O 131
TOE
I/O 0
I/O
1
I/O
2
I/O
6
I/O
7
I/O
3
I/O
8
I/O
10 I/O
11
I/O
16 I/O
15
I/O
22
I/O
23 I/O
18
I/O
26
I/O
30
I/O
33
I/O
36
I/O
40
I/O
43
I/O
44
I/O
49
I/O
52
I/O
54
I/O
57
I/O
61
I/O
63
I/O
67
I/O
25 I/O
19
I/O
29
I/O
32
I/O
35
I/O
39
I/O
41
I/O
45
I/O
46
I/O
50
I/O
53
I/O
56
I/O
60
I/O
66
I/O
17
I/O
20
I/O
24
I/O
27
I/O
31
I/O
34
I/O
38
I/O
42
I/O
47
I/O
51
I/O
55
I/O
59
I/O
62
I/O
65
I/O
68
I/O
69
I/O
72
I/O
13
I/O
14
I/O
21
I/O
37
I/O
48
I/O
58
I/O
70
I/O
73 I/O
64
I/O
71 I/O
28
I/O
74
I/O
75
I/O
76
I/O
78
I/O
79
I/O
9
I/O
12
I/O
77
I/O
80
I/O
81
I/O
4
I/O
5
I/O
82
I/O
84 I/O
83
I/O
85
I/O
86
I/O
88 I/O
87
272 BGA/5512VA
Specifications ispLSI 5512VA
26
Signal Configuration
ispLSI 5512VA 388-ball BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
234567891011121314151617181920212223242526
1234567891011121314151617181920212223242526
I/O
238
I/O
235
I/O
231
I/O
228
I/O
226
I/O
222
I/O
218
I/O
215
I/O
209
I/O
205
I/O
203
I/O
199
I/O
196
I/O
193
I/O
189
I/O
187
I/O
183
I/O
176
I/O
174 I/O 179/
CLK2
I/O197/
CLK3
I/O
242 I/O
246
I/O
247
I/O
244
I/O
237
I/O
233
I/O
229
I/O
227
I/O
224
I/O
220
I/O
216
I/O
213
I/O
211
I/O
207
I/O
204
I/O
201
I/O
195
I/O
191
I/O
188
I/O
184
I/O
180
I/O
177
I/O
175
I/O
173 I/O
171 I/O
178 I/O
182 I/O
186 I/O
190 I/O
194 I/O
198 I/O
202 I/O
206 I/O
210 I/O
214 I/O
217 I/O
221 I/O
225 I/O
232 I/O
236 I/O
239 I/O
243
I/O
253 I/O
254 I/O
252 I/O
255
I/O
264 I/O
270 I/O
267 I/O
268
I/O
272 I/O
274 I/O
269 I/O
271
I/O
279 I/O
281 I/O
275 I/O
276
I/O
283 I/O
287 I/O
282 I/O
284
I/O
13 I/O
15 I/O
9I/O
10
I/O
17 I/O
19 I/O
12 I/O
14
I/O
24 I/O
26 I/O
20 I/O
21
I/O
5I/O
7I/O
2I/O
4
I/O
1I/O
286
I/O
257 I/O
262 I/O
260 I/O
261
I/O
258 I/O
256 I/O
259
I/O
245 I/O
248 I/O
249
I/O
251
I/O
250
I/O
240
CLK0
CLK1
GND GND
GND
GND
GND
VCC
I/O
266 I/O
263 I/O
265
GND
I/O
285 I/O
278 I/O
280
GND
I/O
11 I/O
6I/O
8
GND
I/O
22 I/O
16 I/O
18
VCC
I/O
3I/O 0/
TOE
VCC TCK
TDI TMS
I/O
277 I/O
273
VCC
I/O
241
I/O
234
I/O
230
I/O
223
I/O
219
I/O
212 VCCGNDVCC
I/O
208 GND
I/O
200
I/O
192
GND VCC
I/O
185
I/O
181
I/O
172
I/O
168
I/O
170
I/O
165 I/O
169
I/O
166
VCC
GND
GND GND
GND
GND
I/O
167
I/O
161
I/O
163
I/O
164 I/O
162
I/O
157
I/O
159
I/O
160 I/O
158
I/O
154
I/O
155
I/O
152 I/O
150
I/O
147
I/O
144 I/O
146
I/O
143
I/O
149
I/O
130 I/O
128
I/O
125
I/O
127
I/O
126 I/O
120
I/O
123
I/O
124
I/O
118 I/O
113
I/O
116
I/O
117
I/O
110 I/O
109
I/O
108
I/O
111
I/O
107 I/O
106 I/O
97 I/O
90 I/O
86 I/O
79
I/O
138 I/O
136
I/O
132
I/O
133
I/O
140
I/O
139
I/O
141
VCC
I/O
148
SET/
RST
I/O
145 VCC
I/O
134
I/O
129
I/O
131 VCC
I/O
114
I/O
112
I/O
115 VCC
I/O
122
I/O
119
I/O
121 GND
GND VCC VCC I/O
64 VCCGND I/O
75 I/O
68 GND I/O
56 I/O
41 VCC I/O
37 I/O
28 I/O
23 I/O
25
I/O
27
I/O
34
I/O
38
I/O
42
I/O
46
I/O
50
I/O
54
I/O
58
I/O
62
I/O
66
I/O
70
I/O
73
I/O
77
I/O
81
I/O
84
I/O
88
I/O
92
I/O
95
I/O
99
I/O
101
I/O
104
I/O
105
I/O
103 I/O
100 I/O
96 I/O
93 I/O
89 I/O
85 I/O
83 I/O
80 I/O
76 I/O
72 I/O
69 I/O
67 I/O
63 I/O
60 I/O
57 I/O
53 I/O
51 I/O
47 I/O
44 I/O
40 I/O
36 I/O
33 I/O
31
I/O
30
I/O
32
I/O
35
I/O
39
I/O
43
I/O
45
I/O
49
I/O
52
I/O
55
I/O
59
I/O
61
I/O
65
I/O
71
I/O
74
I/O
78
I/O
82
I/O
87
I/O
91
I/O
94
I/O
98
I/O
102
I/O
29
I/O
48 GND GND
GNDGOE1
GND GND
GND
GND
GND
GND GND GOE0
I/O
142
I/O
135
I/O
137 GND
TDO
VCCIO
I/O
156
I/O
151
I/O
153 GND
NC
1
NC
1
NC
1
GND GND GND GND GND GND
GND GND GND GND GND GND
GND GND GND GND GND GND
GND GND GND GND GND GND
GND GND GND GND GND GND
GND GND GND GND GND GND
NC
1
NC
1
NC
1
ispLSI 5512VA
Bottom View
388 BGA/5512VA
1. NC pins are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
Specifications ispLSI 5512VA
27
ispLSI 5512VA
Top View
208-PQFP/5512VA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
1. NC pins are not to be connected to any active signal, Vcc or GND.
2. Pins have dual function capability.
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
GND
I/O 19
I/O 20
VCC
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
GND
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
GND
GOE0
GOE1
VCC
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
GND
I/O 42
VCC
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
I/O 50
GND
I/O 51
1NC
1NC
1NC
1NC
NC1
NC1
I/O 123
I/O 122
I/O 121
I/O 120
I/O 119
VCC
I/O 118
GND
I/O 117
I/O 116
I/O 115
I/O 114
I/O 113
I/O 112
I/O 111
GND
I/O 110
I/O 109
I/O 108
I/O 107
VCC
CLK1
CLK0
I/O 106
I/O 105
I/O 104
I/O 103
GND
I/O 102
VCC
I/O 101
I/O 100
I/O 99
I/O 98 / CLK32
I/O 97
I/O 96
GND
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
GND
I/O 90
I/O 89 / CLK22
I/O 88
I/O 87
I/O 86
NC1
NC1
VCC
I/O 85
I/O 84
I/O 83
VCC
I/O 82
GND
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
VCC
GSET/GRST
VCCIO
TDO
GND
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
GND
I/O 65
I/O 64
I/O 63
I/O 62
VCC
I/O 61
GND
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
GND
I/O 53
I/O 52
VCC
NC1
NC1
NC1
NC1
NC1
I/O 124
I/O 125
GND
I/O 126
I/O 127
I/O 128
VCC
I/O 129
I/O 130
I/O 131
I/O 132
GND
I/O 133
VCC
I/O 134
I/O 135
I/O 136
I/O 137
GND
I/O 138
I/O 139
VCC
I/O 140
I/O 141
I/O 142
I/O 143
GND
TMS
TCK
TDI
VCC
2I/O 0 / TOE
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
GND
I/O 7
VCC
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
GND
1NC
1NC
1NC
1NC
Pin Configuration
ispLSI 5512VA 208-pin PQFP (with Heat Spreader)
Specifications ispLSI 5512VA
28
Part Number Description
Ordering Information
COMMERCIAL
Device Number
Grade
Blank = Commercial
I = Industrial
ispLSI 5512VA XXX X XXXX
Speed
110 = 110 MHz fmax
100 = 100 MHz fmax
70 = 70 MHz fmax
Power
L = Low
Package
B388 = 388-Ball BGA
(Thermally Enhanced)
B272 = 272-Ball BGA
(Thermally Enhanced)
Q208 = 208-Pin PQFP
(with Heat Spreader)
–
Device Family
X
0212/5512va
ylimaFfxam tdp rebmuNgniredrOegakcaP
ISLpsi
0115.8272BL011-AV2155ISLpsiAGBllaB-272
0115.8883BL011-AV2155ISLpsiAGBllaB-883
0115.8802QL011-AV2155ISLpsiPFQPniP-802
00101272BL001-AV2155ISLpsiAGBllaB-272
00101883BL001-AV2155ISLpsiAGBllaB-883
00101802QL001-AV2155ISLpsiPFQPniP-802
0751272BL07-AV2155ISLpsiAGBllaB-272
0751883BL07-AV2155ISLpsiAGBllaB-883
0751802QL07-AV2155ISLpsiPFQPniP-802
INDUSTRIAL
ylimaFfxam tdp rebmuNgniredrOegakcaP
ISLpsi 0751I883BL07-AV2155ISLpsiAGBllaB-883
